mwl8k.c 90 KB

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  1. /*
  2. * drivers/net/wireless/mwl8k.c
  3. * Driver for Marvell TOPDOG 802.11 Wireless cards
  4. *
  5. * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/init.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/sched.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/list.h>
  17. #include <linux/pci.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <linux/etherdevice.h>
  21. #include <net/mac80211.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/firmware.h>
  24. #include <linux/workqueue.h>
  25. #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
  26. #define MWL8K_NAME KBUILD_MODNAME
  27. #define MWL8K_VERSION "0.11"
  28. /* Register definitions */
  29. #define MWL8K_HIU_GEN_PTR 0x00000c10
  30. #define MWL8K_MODE_STA 0x0000005a
  31. #define MWL8K_MODE_AP 0x000000a5
  32. #define MWL8K_HIU_INT_CODE 0x00000c14
  33. #define MWL8K_FWSTA_READY 0xf0f1f2f4
  34. #define MWL8K_FWAP_READY 0xf1f2f4a5
  35. #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
  36. #define MWL8K_HIU_SCRATCH 0x00000c40
  37. /* Host->device communications */
  38. #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
  39. #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
  40. #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
  41. #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
  42. #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
  43. #define MWL8K_H2A_INT_DUMMY (1 << 20)
  44. #define MWL8K_H2A_INT_RESET (1 << 15)
  45. #define MWL8K_H2A_INT_DOORBELL (1 << 1)
  46. #define MWL8K_H2A_INT_PPA_READY (1 << 0)
  47. /* Device->host communications */
  48. #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
  49. #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
  50. #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
  51. #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
  52. #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
  53. #define MWL8K_A2H_INT_DUMMY (1 << 20)
  54. #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
  55. #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
  56. #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
  57. #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
  58. #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
  59. #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
  60. #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
  61. #define MWL8K_A2H_INT_RX_READY (1 << 1)
  62. #define MWL8K_A2H_INT_TX_DONE (1 << 0)
  63. #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
  64. MWL8K_A2H_INT_CHNL_SWITCHED | \
  65. MWL8K_A2H_INT_QUEUE_EMPTY | \
  66. MWL8K_A2H_INT_RADAR_DETECT | \
  67. MWL8K_A2H_INT_RADIO_ON | \
  68. MWL8K_A2H_INT_RADIO_OFF | \
  69. MWL8K_A2H_INT_MAC_EVENT | \
  70. MWL8K_A2H_INT_OPC_DONE | \
  71. MWL8K_A2H_INT_RX_READY | \
  72. MWL8K_A2H_INT_TX_DONE)
  73. #define MWL8K_RX_QUEUES 1
  74. #define MWL8K_TX_QUEUES 4
  75. struct rxd_ops {
  76. int rxd_size;
  77. void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
  78. void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
  79. int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
  80. __le16 *qos);
  81. };
  82. struct mwl8k_device_info {
  83. char *part_name;
  84. char *helper_image;
  85. char *fw_image;
  86. struct rxd_ops *ap_rxd_ops;
  87. };
  88. struct mwl8k_rx_queue {
  89. int rxd_count;
  90. /* hw receives here */
  91. int head;
  92. /* refill descs here */
  93. int tail;
  94. void *rxd;
  95. dma_addr_t rxd_dma;
  96. struct {
  97. struct sk_buff *skb;
  98. DECLARE_PCI_UNMAP_ADDR(dma)
  99. } *buf;
  100. };
  101. struct mwl8k_tx_queue {
  102. /* hw transmits here */
  103. int head;
  104. /* sw appends here */
  105. int tail;
  106. struct ieee80211_tx_queue_stats stats;
  107. struct mwl8k_tx_desc *txd;
  108. dma_addr_t txd_dma;
  109. struct sk_buff **skb;
  110. };
  111. struct mwl8k_priv {
  112. struct ieee80211_hw *hw;
  113. struct pci_dev *pdev;
  114. struct mwl8k_device_info *device_info;
  115. void __iomem *sram;
  116. void __iomem *regs;
  117. /* firmware */
  118. struct firmware *fw_helper;
  119. struct firmware *fw_ucode;
  120. /* hardware/firmware parameters */
  121. bool ap_fw;
  122. struct rxd_ops *rxd_ops;
  123. /* firmware access */
  124. struct mutex fw_mutex;
  125. struct task_struct *fw_mutex_owner;
  126. int fw_mutex_depth;
  127. struct completion *hostcmd_wait;
  128. /* lock held over TX and TX reap */
  129. spinlock_t tx_lock;
  130. /* TX quiesce completion, protected by fw_mutex and tx_lock */
  131. struct completion *tx_wait;
  132. struct ieee80211_vif *vif;
  133. struct ieee80211_channel *current_channel;
  134. /* power management status cookie from firmware */
  135. u32 *cookie;
  136. dma_addr_t cookie_dma;
  137. u16 num_mcaddrs;
  138. u8 hw_rev;
  139. u32 fw_rev;
  140. /*
  141. * Running count of TX packets in flight, to avoid
  142. * iterating over the transmit rings each time.
  143. */
  144. int pending_tx_pkts;
  145. struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
  146. struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
  147. /* PHY parameters */
  148. struct ieee80211_supported_band band;
  149. struct ieee80211_channel channels[14];
  150. struct ieee80211_rate rates[14];
  151. bool radio_on;
  152. bool radio_short_preamble;
  153. bool sniffer_enabled;
  154. bool wmm_enabled;
  155. struct work_struct sta_notify_worker;
  156. spinlock_t sta_notify_list_lock;
  157. struct list_head sta_notify_list;
  158. /* XXX need to convert this to handle multiple interfaces */
  159. bool capture_beacon;
  160. u8 capture_bssid[ETH_ALEN];
  161. struct sk_buff *beacon_skb;
  162. /*
  163. * This FJ worker has to be global as it is scheduled from the
  164. * RX handler. At this point we don't know which interface it
  165. * belongs to until the list of bssids waiting to complete join
  166. * is checked.
  167. */
  168. struct work_struct finalize_join_worker;
  169. /* Tasklet to reclaim TX descriptors and buffers after tx */
  170. struct tasklet_struct tx_reclaim_task;
  171. };
  172. /* Per interface specific private data */
  173. struct mwl8k_vif {
  174. /* Local MAC address. */
  175. u8 mac_addr[ETH_ALEN];
  176. /* Non AMPDU sequence number assigned by driver */
  177. u16 seqno;
  178. };
  179. #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
  180. struct mwl8k_sta {
  181. /* Index into station database. Returned by UPDATE_STADB. */
  182. u8 peer_id;
  183. };
  184. #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
  185. static const struct ieee80211_channel mwl8k_channels[] = {
  186. { .center_freq = 2412, .hw_value = 1, },
  187. { .center_freq = 2417, .hw_value = 2, },
  188. { .center_freq = 2422, .hw_value = 3, },
  189. { .center_freq = 2427, .hw_value = 4, },
  190. { .center_freq = 2432, .hw_value = 5, },
  191. { .center_freq = 2437, .hw_value = 6, },
  192. { .center_freq = 2442, .hw_value = 7, },
  193. { .center_freq = 2447, .hw_value = 8, },
  194. { .center_freq = 2452, .hw_value = 9, },
  195. { .center_freq = 2457, .hw_value = 10, },
  196. { .center_freq = 2462, .hw_value = 11, },
  197. { .center_freq = 2467, .hw_value = 12, },
  198. { .center_freq = 2472, .hw_value = 13, },
  199. { .center_freq = 2484, .hw_value = 14, },
  200. };
  201. static const struct ieee80211_rate mwl8k_rates[] = {
  202. { .bitrate = 10, .hw_value = 2, },
  203. { .bitrate = 20, .hw_value = 4, },
  204. { .bitrate = 55, .hw_value = 11, },
  205. { .bitrate = 110, .hw_value = 22, },
  206. { .bitrate = 220, .hw_value = 44, },
  207. { .bitrate = 60, .hw_value = 12, },
  208. { .bitrate = 90, .hw_value = 18, },
  209. { .bitrate = 120, .hw_value = 24, },
  210. { .bitrate = 180, .hw_value = 36, },
  211. { .bitrate = 240, .hw_value = 48, },
  212. { .bitrate = 360, .hw_value = 72, },
  213. { .bitrate = 480, .hw_value = 96, },
  214. { .bitrate = 540, .hw_value = 108, },
  215. { .bitrate = 720, .hw_value = 144, },
  216. };
  217. /* Set or get info from Firmware */
  218. #define MWL8K_CMD_SET 0x0001
  219. #define MWL8K_CMD_GET 0x0000
  220. /* Firmware command codes */
  221. #define MWL8K_CMD_CODE_DNLD 0x0001
  222. #define MWL8K_CMD_GET_HW_SPEC 0x0003
  223. #define MWL8K_CMD_SET_HW_SPEC 0x0004
  224. #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
  225. #define MWL8K_CMD_GET_STAT 0x0014
  226. #define MWL8K_CMD_RADIO_CONTROL 0x001c
  227. #define MWL8K_CMD_RF_TX_POWER 0x001e
  228. #define MWL8K_CMD_RF_ANTENNA 0x0020
  229. #define MWL8K_CMD_SET_PRE_SCAN 0x0107
  230. #define MWL8K_CMD_SET_POST_SCAN 0x0108
  231. #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
  232. #define MWL8K_CMD_SET_AID 0x010d
  233. #define MWL8K_CMD_SET_RATE 0x0110
  234. #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
  235. #define MWL8K_CMD_RTS_THRESHOLD 0x0113
  236. #define MWL8K_CMD_SET_SLOT 0x0114
  237. #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
  238. #define MWL8K_CMD_SET_WMM_MODE 0x0123
  239. #define MWL8K_CMD_MIMO_CONFIG 0x0125
  240. #define MWL8K_CMD_USE_FIXED_RATE 0x0126
  241. #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
  242. #define MWL8K_CMD_SET_MAC_ADDR 0x0202
  243. #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
  244. #define MWL8K_CMD_UPDATE_STADB 0x1123
  245. static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
  246. {
  247. #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
  248. snprintf(buf, bufsize, "%s", #x);\
  249. return buf;\
  250. } while (0)
  251. switch (cmd & ~0x8000) {
  252. MWL8K_CMDNAME(CODE_DNLD);
  253. MWL8K_CMDNAME(GET_HW_SPEC);
  254. MWL8K_CMDNAME(SET_HW_SPEC);
  255. MWL8K_CMDNAME(MAC_MULTICAST_ADR);
  256. MWL8K_CMDNAME(GET_STAT);
  257. MWL8K_CMDNAME(RADIO_CONTROL);
  258. MWL8K_CMDNAME(RF_TX_POWER);
  259. MWL8K_CMDNAME(RF_ANTENNA);
  260. MWL8K_CMDNAME(SET_PRE_SCAN);
  261. MWL8K_CMDNAME(SET_POST_SCAN);
  262. MWL8K_CMDNAME(SET_RF_CHANNEL);
  263. MWL8K_CMDNAME(SET_AID);
  264. MWL8K_CMDNAME(SET_RATE);
  265. MWL8K_CMDNAME(SET_FINALIZE_JOIN);
  266. MWL8K_CMDNAME(RTS_THRESHOLD);
  267. MWL8K_CMDNAME(SET_SLOT);
  268. MWL8K_CMDNAME(SET_EDCA_PARAMS);
  269. MWL8K_CMDNAME(SET_WMM_MODE);
  270. MWL8K_CMDNAME(MIMO_CONFIG);
  271. MWL8K_CMDNAME(USE_FIXED_RATE);
  272. MWL8K_CMDNAME(ENABLE_SNIFFER);
  273. MWL8K_CMDNAME(SET_MAC_ADDR);
  274. MWL8K_CMDNAME(SET_RATEADAPT_MODE);
  275. MWL8K_CMDNAME(UPDATE_STADB);
  276. default:
  277. snprintf(buf, bufsize, "0x%x", cmd);
  278. }
  279. #undef MWL8K_CMDNAME
  280. return buf;
  281. }
  282. /* Hardware and firmware reset */
  283. static void mwl8k_hw_reset(struct mwl8k_priv *priv)
  284. {
  285. iowrite32(MWL8K_H2A_INT_RESET,
  286. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  287. iowrite32(MWL8K_H2A_INT_RESET,
  288. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  289. msleep(20);
  290. }
  291. /* Release fw image */
  292. static void mwl8k_release_fw(struct firmware **fw)
  293. {
  294. if (*fw == NULL)
  295. return;
  296. release_firmware(*fw);
  297. *fw = NULL;
  298. }
  299. static void mwl8k_release_firmware(struct mwl8k_priv *priv)
  300. {
  301. mwl8k_release_fw(&priv->fw_ucode);
  302. mwl8k_release_fw(&priv->fw_helper);
  303. }
  304. /* Request fw image */
  305. static int mwl8k_request_fw(struct mwl8k_priv *priv,
  306. const char *fname, struct firmware **fw)
  307. {
  308. /* release current image */
  309. if (*fw != NULL)
  310. mwl8k_release_fw(fw);
  311. return request_firmware((const struct firmware **)fw,
  312. fname, &priv->pdev->dev);
  313. }
  314. static int mwl8k_request_firmware(struct mwl8k_priv *priv)
  315. {
  316. struct mwl8k_device_info *di = priv->device_info;
  317. int rc;
  318. if (di->helper_image != NULL) {
  319. rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
  320. if (rc) {
  321. printk(KERN_ERR "%s: Error requesting helper "
  322. "firmware file %s\n", pci_name(priv->pdev),
  323. di->helper_image);
  324. return rc;
  325. }
  326. }
  327. rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
  328. if (rc) {
  329. printk(KERN_ERR "%s: Error requesting firmware file %s\n",
  330. pci_name(priv->pdev), di->fw_image);
  331. mwl8k_release_fw(&priv->fw_helper);
  332. return rc;
  333. }
  334. return 0;
  335. }
  336. MODULE_FIRMWARE("mwl8k/helper_8687.fw");
  337. MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
  338. struct mwl8k_cmd_pkt {
  339. __le16 code;
  340. __le16 length;
  341. __le16 seq_num;
  342. __le16 result;
  343. char payload[0];
  344. } __attribute__((packed));
  345. /*
  346. * Firmware loading.
  347. */
  348. static int
  349. mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
  350. {
  351. void __iomem *regs = priv->regs;
  352. dma_addr_t dma_addr;
  353. int loops;
  354. dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
  355. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  356. return -ENOMEM;
  357. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  358. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  359. iowrite32(MWL8K_H2A_INT_DOORBELL,
  360. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  361. iowrite32(MWL8K_H2A_INT_DUMMY,
  362. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  363. loops = 1000;
  364. do {
  365. u32 int_code;
  366. int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
  367. if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
  368. iowrite32(0, regs + MWL8K_HIU_INT_CODE);
  369. break;
  370. }
  371. cond_resched();
  372. udelay(1);
  373. } while (--loops);
  374. pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
  375. return loops ? 0 : -ETIMEDOUT;
  376. }
  377. static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
  378. const u8 *data, size_t length)
  379. {
  380. struct mwl8k_cmd_pkt *cmd;
  381. int done;
  382. int rc = 0;
  383. cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
  384. if (cmd == NULL)
  385. return -ENOMEM;
  386. cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
  387. cmd->seq_num = 0;
  388. cmd->result = 0;
  389. done = 0;
  390. while (length) {
  391. int block_size = length > 256 ? 256 : length;
  392. memcpy(cmd->payload, data + done, block_size);
  393. cmd->length = cpu_to_le16(block_size);
  394. rc = mwl8k_send_fw_load_cmd(priv, cmd,
  395. sizeof(*cmd) + block_size);
  396. if (rc)
  397. break;
  398. done += block_size;
  399. length -= block_size;
  400. }
  401. if (!rc) {
  402. cmd->length = 0;
  403. rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
  404. }
  405. kfree(cmd);
  406. return rc;
  407. }
  408. static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
  409. const u8 *data, size_t length)
  410. {
  411. unsigned char *buffer;
  412. int may_continue, rc = 0;
  413. u32 done, prev_block_size;
  414. buffer = kmalloc(1024, GFP_KERNEL);
  415. if (buffer == NULL)
  416. return -ENOMEM;
  417. done = 0;
  418. prev_block_size = 0;
  419. may_continue = 1000;
  420. while (may_continue > 0) {
  421. u32 block_size;
  422. block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
  423. if (block_size & 1) {
  424. block_size &= ~1;
  425. may_continue--;
  426. } else {
  427. done += prev_block_size;
  428. length -= prev_block_size;
  429. }
  430. if (block_size > 1024 || block_size > length) {
  431. rc = -EOVERFLOW;
  432. break;
  433. }
  434. if (length == 0) {
  435. rc = 0;
  436. break;
  437. }
  438. if (block_size == 0) {
  439. rc = -EPROTO;
  440. may_continue--;
  441. udelay(1);
  442. continue;
  443. }
  444. prev_block_size = block_size;
  445. memcpy(buffer, data + done, block_size);
  446. rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
  447. if (rc)
  448. break;
  449. }
  450. if (!rc && length != 0)
  451. rc = -EREMOTEIO;
  452. kfree(buffer);
  453. return rc;
  454. }
  455. static int mwl8k_load_firmware(struct ieee80211_hw *hw)
  456. {
  457. struct mwl8k_priv *priv = hw->priv;
  458. struct firmware *fw = priv->fw_ucode;
  459. int rc;
  460. int loops;
  461. if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
  462. struct firmware *helper = priv->fw_helper;
  463. if (helper == NULL) {
  464. printk(KERN_ERR "%s: helper image needed but none "
  465. "given\n", pci_name(priv->pdev));
  466. return -EINVAL;
  467. }
  468. rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
  469. if (rc) {
  470. printk(KERN_ERR "%s: unable to load firmware "
  471. "helper image\n", pci_name(priv->pdev));
  472. return rc;
  473. }
  474. msleep(5);
  475. rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
  476. } else {
  477. rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
  478. }
  479. if (rc) {
  480. printk(KERN_ERR "%s: unable to load firmware image\n",
  481. pci_name(priv->pdev));
  482. return rc;
  483. }
  484. iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
  485. loops = 500000;
  486. do {
  487. u32 ready_code;
  488. ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  489. if (ready_code == MWL8K_FWAP_READY) {
  490. priv->ap_fw = 1;
  491. break;
  492. } else if (ready_code == MWL8K_FWSTA_READY) {
  493. priv->ap_fw = 0;
  494. break;
  495. }
  496. cond_resched();
  497. udelay(1);
  498. } while (--loops);
  499. return loops ? 0 : -ETIMEDOUT;
  500. }
  501. /* DMA header used by firmware and hardware. */
  502. struct mwl8k_dma_data {
  503. __le16 fwlen;
  504. struct ieee80211_hdr wh;
  505. char data[0];
  506. } __attribute__((packed));
  507. /* Routines to add/remove DMA header from skb. */
  508. static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
  509. {
  510. struct mwl8k_dma_data *tr;
  511. int hdrlen;
  512. tr = (struct mwl8k_dma_data *)skb->data;
  513. hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
  514. if (hdrlen != sizeof(tr->wh)) {
  515. if (ieee80211_is_data_qos(tr->wh.frame_control)) {
  516. memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
  517. *((__le16 *)(tr->data - 2)) = qos;
  518. } else {
  519. memmove(tr->data - hdrlen, &tr->wh, hdrlen);
  520. }
  521. }
  522. if (hdrlen != sizeof(*tr))
  523. skb_pull(skb, sizeof(*tr) - hdrlen);
  524. }
  525. static inline void mwl8k_add_dma_header(struct sk_buff *skb)
  526. {
  527. struct ieee80211_hdr *wh;
  528. int hdrlen;
  529. struct mwl8k_dma_data *tr;
  530. /*
  531. * Add a firmware DMA header; the firmware requires that we
  532. * present a 2-byte payload length followed by a 4-address
  533. * header (without QoS field), followed (optionally) by any
  534. * WEP/ExtIV header (but only filled in for CCMP).
  535. */
  536. wh = (struct ieee80211_hdr *)skb->data;
  537. hdrlen = ieee80211_hdrlen(wh->frame_control);
  538. if (hdrlen != sizeof(*tr))
  539. skb_push(skb, sizeof(*tr) - hdrlen);
  540. if (ieee80211_is_data_qos(wh->frame_control))
  541. hdrlen -= 2;
  542. tr = (struct mwl8k_dma_data *)skb->data;
  543. if (wh != &tr->wh)
  544. memmove(&tr->wh, wh, hdrlen);
  545. if (hdrlen != sizeof(tr->wh))
  546. memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
  547. /*
  548. * Firmware length is the length of the fully formed "802.11
  549. * payload". That is, everything except for the 802.11 header.
  550. * This includes all crypto material including the MIC.
  551. */
  552. tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
  553. }
  554. /*
  555. * Packet reception for 88w8366 AP firmware.
  556. */
  557. struct mwl8k_rxd_8366_ap {
  558. __le16 pkt_len;
  559. __u8 sq2;
  560. __u8 rate;
  561. __le32 pkt_phys_addr;
  562. __le32 next_rxd_phys_addr;
  563. __le16 qos_control;
  564. __le16 htsig2;
  565. __le32 hw_rssi_info;
  566. __le32 hw_noise_floor_info;
  567. __u8 noise_floor;
  568. __u8 pad0[3];
  569. __u8 rssi;
  570. __u8 rx_status;
  571. __u8 channel;
  572. __u8 rx_ctrl;
  573. } __attribute__((packed));
  574. #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
  575. #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
  576. #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
  577. #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
  578. static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
  579. {
  580. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  581. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  582. rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
  583. }
  584. static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
  585. {
  586. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  587. rxd->pkt_len = cpu_to_le16(len);
  588. rxd->pkt_phys_addr = cpu_to_le32(addr);
  589. wmb();
  590. rxd->rx_ctrl = 0;
  591. }
  592. static int
  593. mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
  594. __le16 *qos)
  595. {
  596. struct mwl8k_rxd_8366_ap *rxd = _rxd;
  597. if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
  598. return -1;
  599. rmb();
  600. memset(status, 0, sizeof(*status));
  601. status->signal = -rxd->rssi;
  602. status->noise = -rxd->noise_floor;
  603. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
  604. status->flag |= RX_FLAG_HT;
  605. if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
  606. status->flag |= RX_FLAG_40MHZ;
  607. status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
  608. } else {
  609. int i;
  610. for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
  611. if (mwl8k_rates[i].hw_value == rxd->rate) {
  612. status->rate_idx = i;
  613. break;
  614. }
  615. }
  616. }
  617. status->band = IEEE80211_BAND_2GHZ;
  618. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  619. *qos = rxd->qos_control;
  620. return le16_to_cpu(rxd->pkt_len);
  621. }
  622. static struct rxd_ops rxd_8366_ap_ops = {
  623. .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
  624. .rxd_init = mwl8k_rxd_8366_ap_init,
  625. .rxd_refill = mwl8k_rxd_8366_ap_refill,
  626. .rxd_process = mwl8k_rxd_8366_ap_process,
  627. };
  628. /*
  629. * Packet reception for STA firmware.
  630. */
  631. struct mwl8k_rxd_sta {
  632. __le16 pkt_len;
  633. __u8 link_quality;
  634. __u8 noise_level;
  635. __le32 pkt_phys_addr;
  636. __le32 next_rxd_phys_addr;
  637. __le16 qos_control;
  638. __le16 rate_info;
  639. __le32 pad0[4];
  640. __u8 rssi;
  641. __u8 channel;
  642. __le16 pad1;
  643. __u8 rx_ctrl;
  644. __u8 rx_status;
  645. __u8 pad2[2];
  646. } __attribute__((packed));
  647. #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
  648. #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
  649. #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
  650. #define MWL8K_STA_RATE_INFO_40MHZ 0x0004
  651. #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
  652. #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
  653. #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
  654. static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
  655. {
  656. struct mwl8k_rxd_sta *rxd = _rxd;
  657. rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
  658. rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
  659. }
  660. static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
  661. {
  662. struct mwl8k_rxd_sta *rxd = _rxd;
  663. rxd->pkt_len = cpu_to_le16(len);
  664. rxd->pkt_phys_addr = cpu_to_le32(addr);
  665. wmb();
  666. rxd->rx_ctrl = 0;
  667. }
  668. static int
  669. mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
  670. __le16 *qos)
  671. {
  672. struct mwl8k_rxd_sta *rxd = _rxd;
  673. u16 rate_info;
  674. if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
  675. return -1;
  676. rmb();
  677. rate_info = le16_to_cpu(rxd->rate_info);
  678. memset(status, 0, sizeof(*status));
  679. status->signal = -rxd->rssi;
  680. status->noise = -rxd->noise_level;
  681. status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
  682. status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
  683. if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
  684. status->flag |= RX_FLAG_SHORTPRE;
  685. if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
  686. status->flag |= RX_FLAG_40MHZ;
  687. if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
  688. status->flag |= RX_FLAG_SHORT_GI;
  689. if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
  690. status->flag |= RX_FLAG_HT;
  691. status->band = IEEE80211_BAND_2GHZ;
  692. status->freq = ieee80211_channel_to_frequency(rxd->channel);
  693. *qos = rxd->qos_control;
  694. return le16_to_cpu(rxd->pkt_len);
  695. }
  696. static struct rxd_ops rxd_sta_ops = {
  697. .rxd_size = sizeof(struct mwl8k_rxd_sta),
  698. .rxd_init = mwl8k_rxd_sta_init,
  699. .rxd_refill = mwl8k_rxd_sta_refill,
  700. .rxd_process = mwl8k_rxd_sta_process,
  701. };
  702. #define MWL8K_RX_DESCS 256
  703. #define MWL8K_RX_MAXSZ 3800
  704. static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
  705. {
  706. struct mwl8k_priv *priv = hw->priv;
  707. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  708. int size;
  709. int i;
  710. rxq->rxd_count = 0;
  711. rxq->head = 0;
  712. rxq->tail = 0;
  713. size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
  714. rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
  715. if (rxq->rxd == NULL) {
  716. printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
  717. wiphy_name(hw->wiphy));
  718. return -ENOMEM;
  719. }
  720. memset(rxq->rxd, 0, size);
  721. rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
  722. if (rxq->buf == NULL) {
  723. printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
  724. wiphy_name(hw->wiphy));
  725. pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
  726. return -ENOMEM;
  727. }
  728. memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
  729. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  730. int desc_size;
  731. void *rxd;
  732. int nexti;
  733. dma_addr_t next_dma_addr;
  734. desc_size = priv->rxd_ops->rxd_size;
  735. rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
  736. nexti = i + 1;
  737. if (nexti == MWL8K_RX_DESCS)
  738. nexti = 0;
  739. next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
  740. priv->rxd_ops->rxd_init(rxd, next_dma_addr);
  741. }
  742. return 0;
  743. }
  744. static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
  745. {
  746. struct mwl8k_priv *priv = hw->priv;
  747. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  748. int refilled;
  749. refilled = 0;
  750. while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
  751. struct sk_buff *skb;
  752. dma_addr_t addr;
  753. int rx;
  754. void *rxd;
  755. skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
  756. if (skb == NULL)
  757. break;
  758. addr = pci_map_single(priv->pdev, skb->data,
  759. MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
  760. rxq->rxd_count++;
  761. rx = rxq->tail++;
  762. if (rxq->tail == MWL8K_RX_DESCS)
  763. rxq->tail = 0;
  764. rxq->buf[rx].skb = skb;
  765. pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
  766. rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
  767. priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
  768. refilled++;
  769. }
  770. return refilled;
  771. }
  772. /* Must be called only when the card's reception is completely halted */
  773. static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
  774. {
  775. struct mwl8k_priv *priv = hw->priv;
  776. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  777. int i;
  778. for (i = 0; i < MWL8K_RX_DESCS; i++) {
  779. if (rxq->buf[i].skb != NULL) {
  780. pci_unmap_single(priv->pdev,
  781. pci_unmap_addr(&rxq->buf[i], dma),
  782. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  783. pci_unmap_addr_set(&rxq->buf[i], dma, 0);
  784. kfree_skb(rxq->buf[i].skb);
  785. rxq->buf[i].skb = NULL;
  786. }
  787. }
  788. kfree(rxq->buf);
  789. rxq->buf = NULL;
  790. pci_free_consistent(priv->pdev,
  791. MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
  792. rxq->rxd, rxq->rxd_dma);
  793. rxq->rxd = NULL;
  794. }
  795. /*
  796. * Scan a list of BSSIDs to process for finalize join.
  797. * Allows for extension to process multiple BSSIDs.
  798. */
  799. static inline int
  800. mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
  801. {
  802. return priv->capture_beacon &&
  803. ieee80211_is_beacon(wh->frame_control) &&
  804. !compare_ether_addr(wh->addr3, priv->capture_bssid);
  805. }
  806. static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
  807. struct sk_buff *skb)
  808. {
  809. struct mwl8k_priv *priv = hw->priv;
  810. priv->capture_beacon = false;
  811. memset(priv->capture_bssid, 0, ETH_ALEN);
  812. /*
  813. * Use GFP_ATOMIC as rxq_process is called from
  814. * the primary interrupt handler, memory allocation call
  815. * must not sleep.
  816. */
  817. priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
  818. if (priv->beacon_skb != NULL)
  819. ieee80211_queue_work(hw, &priv->finalize_join_worker);
  820. }
  821. static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
  822. {
  823. struct mwl8k_priv *priv = hw->priv;
  824. struct mwl8k_rx_queue *rxq = priv->rxq + index;
  825. int processed;
  826. processed = 0;
  827. while (rxq->rxd_count && limit--) {
  828. struct sk_buff *skb;
  829. void *rxd;
  830. int pkt_len;
  831. struct ieee80211_rx_status status;
  832. __le16 qos;
  833. skb = rxq->buf[rxq->head].skb;
  834. if (skb == NULL)
  835. break;
  836. rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
  837. pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
  838. if (pkt_len < 0)
  839. break;
  840. rxq->buf[rxq->head].skb = NULL;
  841. pci_unmap_single(priv->pdev,
  842. pci_unmap_addr(&rxq->buf[rxq->head], dma),
  843. MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
  844. pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
  845. rxq->head++;
  846. if (rxq->head == MWL8K_RX_DESCS)
  847. rxq->head = 0;
  848. rxq->rxd_count--;
  849. skb_put(skb, pkt_len);
  850. mwl8k_remove_dma_header(skb, qos);
  851. /*
  852. * Check for a pending join operation. Save a
  853. * copy of the beacon and schedule a tasklet to
  854. * send a FINALIZE_JOIN command to the firmware.
  855. */
  856. if (mwl8k_capture_bssid(priv, (void *)skb->data))
  857. mwl8k_save_beacon(hw, skb);
  858. memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
  859. ieee80211_rx_irqsafe(hw, skb);
  860. processed++;
  861. }
  862. return processed;
  863. }
  864. /*
  865. * Packet transmission.
  866. */
  867. #define MWL8K_TXD_STATUS_OK 0x00000001
  868. #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
  869. #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
  870. #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
  871. #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
  872. #define MWL8K_QOS_QLEN_UNSPEC 0xff00
  873. #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
  874. #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
  875. #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
  876. #define MWL8K_QOS_EOSP 0x0010
  877. struct mwl8k_tx_desc {
  878. __le32 status;
  879. __u8 data_rate;
  880. __u8 tx_priority;
  881. __le16 qos_control;
  882. __le32 pkt_phys_addr;
  883. __le16 pkt_len;
  884. __u8 dest_MAC_addr[ETH_ALEN];
  885. __le32 next_txd_phys_addr;
  886. __le32 reserved;
  887. __le16 rate_info;
  888. __u8 peer_id;
  889. __u8 tx_frag_cnt;
  890. } __attribute__((packed));
  891. #define MWL8K_TX_DESCS 128
  892. static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
  893. {
  894. struct mwl8k_priv *priv = hw->priv;
  895. struct mwl8k_tx_queue *txq = priv->txq + index;
  896. int size;
  897. int i;
  898. memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
  899. txq->stats.limit = MWL8K_TX_DESCS;
  900. txq->head = 0;
  901. txq->tail = 0;
  902. size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
  903. txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
  904. if (txq->txd == NULL) {
  905. printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
  906. wiphy_name(hw->wiphy));
  907. return -ENOMEM;
  908. }
  909. memset(txq->txd, 0, size);
  910. txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
  911. if (txq->skb == NULL) {
  912. printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
  913. wiphy_name(hw->wiphy));
  914. pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
  915. return -ENOMEM;
  916. }
  917. memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
  918. for (i = 0; i < MWL8K_TX_DESCS; i++) {
  919. struct mwl8k_tx_desc *tx_desc;
  920. int nexti;
  921. tx_desc = txq->txd + i;
  922. nexti = (i + 1) % MWL8K_TX_DESCS;
  923. tx_desc->status = 0;
  924. tx_desc->next_txd_phys_addr =
  925. cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
  926. }
  927. return 0;
  928. }
  929. static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
  930. {
  931. iowrite32(MWL8K_H2A_INT_PPA_READY,
  932. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  933. iowrite32(MWL8K_H2A_INT_DUMMY,
  934. priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  935. ioread32(priv->regs + MWL8K_HIU_INT_CODE);
  936. }
  937. static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
  938. {
  939. struct mwl8k_priv *priv = hw->priv;
  940. int i;
  941. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  942. struct mwl8k_tx_queue *txq = priv->txq + i;
  943. int fw_owned = 0;
  944. int drv_owned = 0;
  945. int unused = 0;
  946. int desc;
  947. for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
  948. struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
  949. u32 status;
  950. status = le32_to_cpu(tx_desc->status);
  951. if (status & MWL8K_TXD_STATUS_FW_OWNED)
  952. fw_owned++;
  953. else
  954. drv_owned++;
  955. if (tx_desc->pkt_len == 0)
  956. unused++;
  957. }
  958. printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
  959. "fw_owned=%d drv_owned=%d unused=%d\n",
  960. wiphy_name(hw->wiphy), i,
  961. txq->stats.len, txq->head, txq->tail,
  962. fw_owned, drv_owned, unused);
  963. }
  964. }
  965. /*
  966. * Must be called with priv->fw_mutex held and tx queues stopped.
  967. */
  968. #define MWL8K_TX_WAIT_TIMEOUT_MS 1000
  969. static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
  970. {
  971. struct mwl8k_priv *priv = hw->priv;
  972. DECLARE_COMPLETION_ONSTACK(tx_wait);
  973. int retry;
  974. int rc;
  975. might_sleep();
  976. /*
  977. * The TX queues are stopped at this point, so this test
  978. * doesn't need to take ->tx_lock.
  979. */
  980. if (!priv->pending_tx_pkts)
  981. return 0;
  982. retry = 0;
  983. rc = 0;
  984. spin_lock_bh(&priv->tx_lock);
  985. priv->tx_wait = &tx_wait;
  986. while (!rc) {
  987. int oldcount;
  988. unsigned long timeout;
  989. oldcount = priv->pending_tx_pkts;
  990. spin_unlock_bh(&priv->tx_lock);
  991. timeout = wait_for_completion_timeout(&tx_wait,
  992. msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
  993. spin_lock_bh(&priv->tx_lock);
  994. if (timeout) {
  995. WARN_ON(priv->pending_tx_pkts);
  996. if (retry) {
  997. printk(KERN_NOTICE "%s: tx rings drained\n",
  998. wiphy_name(hw->wiphy));
  999. }
  1000. break;
  1001. }
  1002. if (priv->pending_tx_pkts < oldcount) {
  1003. printk(KERN_NOTICE "%s: waiting for tx rings "
  1004. "to drain (%d -> %d pkts)\n",
  1005. wiphy_name(hw->wiphy), oldcount,
  1006. priv->pending_tx_pkts);
  1007. retry = 1;
  1008. continue;
  1009. }
  1010. priv->tx_wait = NULL;
  1011. printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
  1012. wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
  1013. mwl8k_dump_tx_rings(hw);
  1014. rc = -ETIMEDOUT;
  1015. }
  1016. spin_unlock_bh(&priv->tx_lock);
  1017. return rc;
  1018. }
  1019. #define MWL8K_TXD_SUCCESS(status) \
  1020. ((status) & (MWL8K_TXD_STATUS_OK | \
  1021. MWL8K_TXD_STATUS_OK_RETRY | \
  1022. MWL8K_TXD_STATUS_OK_MORE_RETRY))
  1023. static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
  1024. {
  1025. struct mwl8k_priv *priv = hw->priv;
  1026. struct mwl8k_tx_queue *txq = priv->txq + index;
  1027. int wake = 0;
  1028. while (txq->stats.len > 0) {
  1029. int tx;
  1030. struct mwl8k_tx_desc *tx_desc;
  1031. unsigned long addr;
  1032. int size;
  1033. struct sk_buff *skb;
  1034. struct ieee80211_tx_info *info;
  1035. u32 status;
  1036. tx = txq->head;
  1037. tx_desc = txq->txd + tx;
  1038. status = le32_to_cpu(tx_desc->status);
  1039. if (status & MWL8K_TXD_STATUS_FW_OWNED) {
  1040. if (!force)
  1041. break;
  1042. tx_desc->status &=
  1043. ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
  1044. }
  1045. txq->head = (tx + 1) % MWL8K_TX_DESCS;
  1046. BUG_ON(txq->stats.len == 0);
  1047. txq->stats.len--;
  1048. priv->pending_tx_pkts--;
  1049. addr = le32_to_cpu(tx_desc->pkt_phys_addr);
  1050. size = le16_to_cpu(tx_desc->pkt_len);
  1051. skb = txq->skb[tx];
  1052. txq->skb[tx] = NULL;
  1053. BUG_ON(skb == NULL);
  1054. pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
  1055. mwl8k_remove_dma_header(skb, tx_desc->qos_control);
  1056. /* Mark descriptor as unused */
  1057. tx_desc->pkt_phys_addr = 0;
  1058. tx_desc->pkt_len = 0;
  1059. info = IEEE80211_SKB_CB(skb);
  1060. ieee80211_tx_info_clear_status(info);
  1061. if (MWL8K_TXD_SUCCESS(status))
  1062. info->flags |= IEEE80211_TX_STAT_ACK;
  1063. ieee80211_tx_status_irqsafe(hw, skb);
  1064. wake = 1;
  1065. }
  1066. if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
  1067. ieee80211_wake_queue(hw, index);
  1068. }
  1069. /* must be called only when the card's transmit is completely halted */
  1070. static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
  1071. {
  1072. struct mwl8k_priv *priv = hw->priv;
  1073. struct mwl8k_tx_queue *txq = priv->txq + index;
  1074. mwl8k_txq_reclaim(hw, index, 1);
  1075. kfree(txq->skb);
  1076. txq->skb = NULL;
  1077. pci_free_consistent(priv->pdev,
  1078. MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
  1079. txq->txd, txq->txd_dma);
  1080. txq->txd = NULL;
  1081. }
  1082. static int
  1083. mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
  1084. {
  1085. struct mwl8k_priv *priv = hw->priv;
  1086. struct ieee80211_tx_info *tx_info;
  1087. struct mwl8k_vif *mwl8k_vif;
  1088. struct ieee80211_hdr *wh;
  1089. struct mwl8k_tx_queue *txq;
  1090. struct mwl8k_tx_desc *tx;
  1091. dma_addr_t dma;
  1092. u32 txstatus;
  1093. u8 txdatarate;
  1094. u16 qos;
  1095. wh = (struct ieee80211_hdr *)skb->data;
  1096. if (ieee80211_is_data_qos(wh->frame_control))
  1097. qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
  1098. else
  1099. qos = 0;
  1100. mwl8k_add_dma_header(skb);
  1101. wh = &((struct mwl8k_dma_data *)skb->data)->wh;
  1102. tx_info = IEEE80211_SKB_CB(skb);
  1103. mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
  1104. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1105. u16 seqno = mwl8k_vif->seqno;
  1106. wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1107. wh->seq_ctrl |= cpu_to_le16(seqno << 4);
  1108. mwl8k_vif->seqno = seqno++ % 4096;
  1109. }
  1110. /* Setup firmware control bit fields for each frame type. */
  1111. txstatus = 0;
  1112. txdatarate = 0;
  1113. if (ieee80211_is_mgmt(wh->frame_control) ||
  1114. ieee80211_is_ctl(wh->frame_control)) {
  1115. txdatarate = 0;
  1116. qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
  1117. } else if (ieee80211_is_data(wh->frame_control)) {
  1118. txdatarate = 1;
  1119. if (is_multicast_ether_addr(wh->addr1))
  1120. txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
  1121. qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
  1122. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
  1123. qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
  1124. else
  1125. qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
  1126. }
  1127. dma = pci_map_single(priv->pdev, skb->data,
  1128. skb->len, PCI_DMA_TODEVICE);
  1129. if (pci_dma_mapping_error(priv->pdev, dma)) {
  1130. printk(KERN_DEBUG "%s: failed to dma map skb, "
  1131. "dropping TX frame.\n", wiphy_name(hw->wiphy));
  1132. dev_kfree_skb(skb);
  1133. return NETDEV_TX_OK;
  1134. }
  1135. spin_lock_bh(&priv->tx_lock);
  1136. txq = priv->txq + index;
  1137. BUG_ON(txq->skb[txq->tail] != NULL);
  1138. txq->skb[txq->tail] = skb;
  1139. tx = txq->txd + txq->tail;
  1140. tx->data_rate = txdatarate;
  1141. tx->tx_priority = index;
  1142. tx->qos_control = cpu_to_le16(qos);
  1143. tx->pkt_phys_addr = cpu_to_le32(dma);
  1144. tx->pkt_len = cpu_to_le16(skb->len);
  1145. tx->rate_info = 0;
  1146. if (!priv->ap_fw && tx_info->control.sta != NULL)
  1147. tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
  1148. else
  1149. tx->peer_id = 0;
  1150. wmb();
  1151. tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
  1152. txq->stats.count++;
  1153. txq->stats.len++;
  1154. priv->pending_tx_pkts++;
  1155. txq->tail++;
  1156. if (txq->tail == MWL8K_TX_DESCS)
  1157. txq->tail = 0;
  1158. if (txq->head == txq->tail)
  1159. ieee80211_stop_queue(hw, index);
  1160. mwl8k_tx_start(priv);
  1161. spin_unlock_bh(&priv->tx_lock);
  1162. return NETDEV_TX_OK;
  1163. }
  1164. /*
  1165. * Firmware access.
  1166. *
  1167. * We have the following requirements for issuing firmware commands:
  1168. * - Some commands require that the packet transmit path is idle when
  1169. * the command is issued. (For simplicity, we'll just quiesce the
  1170. * transmit path for every command.)
  1171. * - There are certain sequences of commands that need to be issued to
  1172. * the hardware sequentially, with no other intervening commands.
  1173. *
  1174. * This leads to an implementation of a "firmware lock" as a mutex that
  1175. * can be taken recursively, and which is taken by both the low-level
  1176. * command submission function (mwl8k_post_cmd) as well as any users of
  1177. * that function that require issuing of an atomic sequence of commands,
  1178. * and quiesces the transmit path whenever it's taken.
  1179. */
  1180. static int mwl8k_fw_lock(struct ieee80211_hw *hw)
  1181. {
  1182. struct mwl8k_priv *priv = hw->priv;
  1183. if (priv->fw_mutex_owner != current) {
  1184. int rc;
  1185. mutex_lock(&priv->fw_mutex);
  1186. ieee80211_stop_queues(hw);
  1187. rc = mwl8k_tx_wait_empty(hw);
  1188. if (rc) {
  1189. ieee80211_wake_queues(hw);
  1190. mutex_unlock(&priv->fw_mutex);
  1191. return rc;
  1192. }
  1193. priv->fw_mutex_owner = current;
  1194. }
  1195. priv->fw_mutex_depth++;
  1196. return 0;
  1197. }
  1198. static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
  1199. {
  1200. struct mwl8k_priv *priv = hw->priv;
  1201. if (!--priv->fw_mutex_depth) {
  1202. ieee80211_wake_queues(hw);
  1203. priv->fw_mutex_owner = NULL;
  1204. mutex_unlock(&priv->fw_mutex);
  1205. }
  1206. }
  1207. /*
  1208. * Command processing.
  1209. */
  1210. /* Timeout firmware commands after 10s */
  1211. #define MWL8K_CMD_TIMEOUT_MS 10000
  1212. static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
  1213. {
  1214. DECLARE_COMPLETION_ONSTACK(cmd_wait);
  1215. struct mwl8k_priv *priv = hw->priv;
  1216. void __iomem *regs = priv->regs;
  1217. dma_addr_t dma_addr;
  1218. unsigned int dma_size;
  1219. int rc;
  1220. unsigned long timeout = 0;
  1221. u8 buf[32];
  1222. cmd->result = 0xffff;
  1223. dma_size = le16_to_cpu(cmd->length);
  1224. dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
  1225. PCI_DMA_BIDIRECTIONAL);
  1226. if (pci_dma_mapping_error(priv->pdev, dma_addr))
  1227. return -ENOMEM;
  1228. rc = mwl8k_fw_lock(hw);
  1229. if (rc) {
  1230. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1231. PCI_DMA_BIDIRECTIONAL);
  1232. return rc;
  1233. }
  1234. priv->hostcmd_wait = &cmd_wait;
  1235. iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
  1236. iowrite32(MWL8K_H2A_INT_DOORBELL,
  1237. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1238. iowrite32(MWL8K_H2A_INT_DUMMY,
  1239. regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
  1240. timeout = wait_for_completion_timeout(&cmd_wait,
  1241. msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
  1242. priv->hostcmd_wait = NULL;
  1243. mwl8k_fw_unlock(hw);
  1244. pci_unmap_single(priv->pdev, dma_addr, dma_size,
  1245. PCI_DMA_BIDIRECTIONAL);
  1246. if (!timeout) {
  1247. printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
  1248. wiphy_name(hw->wiphy),
  1249. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1250. MWL8K_CMD_TIMEOUT_MS);
  1251. rc = -ETIMEDOUT;
  1252. } else {
  1253. int ms;
  1254. ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
  1255. rc = cmd->result ? -EINVAL : 0;
  1256. if (rc)
  1257. printk(KERN_ERR "%s: Command %s error 0x%x\n",
  1258. wiphy_name(hw->wiphy),
  1259. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1260. le16_to_cpu(cmd->result));
  1261. else if (ms > 2000)
  1262. printk(KERN_NOTICE "%s: Command %s took %d ms\n",
  1263. wiphy_name(hw->wiphy),
  1264. mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
  1265. ms);
  1266. }
  1267. return rc;
  1268. }
  1269. /*
  1270. * CMD_GET_HW_SPEC (STA version).
  1271. */
  1272. struct mwl8k_cmd_get_hw_spec_sta {
  1273. struct mwl8k_cmd_pkt header;
  1274. __u8 hw_rev;
  1275. __u8 host_interface;
  1276. __le16 num_mcaddrs;
  1277. __u8 perm_addr[ETH_ALEN];
  1278. __le16 region_code;
  1279. __le32 fw_rev;
  1280. __le32 ps_cookie;
  1281. __le32 caps;
  1282. __u8 mcs_bitmap[16];
  1283. __le32 rx_queue_ptr;
  1284. __le32 num_tx_queues;
  1285. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1286. __le32 caps2;
  1287. __le32 num_tx_desc_per_queue;
  1288. __le32 total_rxd;
  1289. } __attribute__((packed));
  1290. #define MWL8K_CAP_MAX_AMSDU 0x20000000
  1291. #define MWL8K_CAP_GREENFIELD 0x08000000
  1292. #define MWL8K_CAP_AMPDU 0x04000000
  1293. #define MWL8K_CAP_RX_STBC 0x01000000
  1294. #define MWL8K_CAP_TX_STBC 0x00800000
  1295. #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
  1296. #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
  1297. #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
  1298. #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
  1299. #define MWL8K_CAP_DELAY_BA 0x00003000
  1300. #define MWL8K_CAP_MIMO 0x00000200
  1301. #define MWL8K_CAP_40MHZ 0x00000100
  1302. static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
  1303. {
  1304. struct mwl8k_priv *priv = hw->priv;
  1305. int rx_streams;
  1306. int tx_streams;
  1307. priv->band.ht_cap.ht_supported = 1;
  1308. if (cap & MWL8K_CAP_MAX_AMSDU)
  1309. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  1310. if (cap & MWL8K_CAP_GREENFIELD)
  1311. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
  1312. if (cap & MWL8K_CAP_AMPDU) {
  1313. hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
  1314. priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  1315. priv->band.ht_cap.ampdu_density =
  1316. IEEE80211_HT_MPDU_DENSITY_NONE;
  1317. }
  1318. if (cap & MWL8K_CAP_RX_STBC)
  1319. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
  1320. if (cap & MWL8K_CAP_TX_STBC)
  1321. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
  1322. if (cap & MWL8K_CAP_SHORTGI_40MHZ)
  1323. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
  1324. if (cap & MWL8K_CAP_SHORTGI_20MHZ)
  1325. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
  1326. if (cap & MWL8K_CAP_DELAY_BA)
  1327. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
  1328. if (cap & MWL8K_CAP_40MHZ)
  1329. priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  1330. rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
  1331. tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
  1332. priv->band.ht_cap.mcs.rx_mask[0] = 0xff;
  1333. if (rx_streams >= 2)
  1334. priv->band.ht_cap.mcs.rx_mask[1] = 0xff;
  1335. if (rx_streams >= 3)
  1336. priv->band.ht_cap.mcs.rx_mask[2] = 0xff;
  1337. priv->band.ht_cap.mcs.rx_mask[4] = 0x01;
  1338. priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  1339. if (rx_streams != tx_streams) {
  1340. priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  1341. priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) <<
  1342. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1343. }
  1344. }
  1345. static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
  1346. {
  1347. struct mwl8k_priv *priv = hw->priv;
  1348. struct mwl8k_cmd_get_hw_spec_sta *cmd;
  1349. int rc;
  1350. int i;
  1351. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1352. if (cmd == NULL)
  1353. return -ENOMEM;
  1354. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1355. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1356. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1357. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1358. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1359. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1360. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1361. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1362. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1363. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1364. rc = mwl8k_post_cmd(hw, &cmd->header);
  1365. if (!rc) {
  1366. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1367. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1368. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1369. priv->hw_rev = cmd->hw_rev;
  1370. if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
  1371. mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
  1372. }
  1373. kfree(cmd);
  1374. return rc;
  1375. }
  1376. /*
  1377. * CMD_GET_HW_SPEC (AP version).
  1378. */
  1379. struct mwl8k_cmd_get_hw_spec_ap {
  1380. struct mwl8k_cmd_pkt header;
  1381. __u8 hw_rev;
  1382. __u8 host_interface;
  1383. __le16 num_wcb;
  1384. __le16 num_mcaddrs;
  1385. __u8 perm_addr[ETH_ALEN];
  1386. __le16 region_code;
  1387. __le16 num_antenna;
  1388. __le32 fw_rev;
  1389. __le32 wcbbase0;
  1390. __le32 rxwrptr;
  1391. __le32 rxrdptr;
  1392. __le32 ps_cookie;
  1393. __le32 wcbbase1;
  1394. __le32 wcbbase2;
  1395. __le32 wcbbase3;
  1396. } __attribute__((packed));
  1397. static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
  1398. {
  1399. struct mwl8k_priv *priv = hw->priv;
  1400. struct mwl8k_cmd_get_hw_spec_ap *cmd;
  1401. int rc;
  1402. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1403. if (cmd == NULL)
  1404. return -ENOMEM;
  1405. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
  1406. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1407. memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
  1408. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1409. rc = mwl8k_post_cmd(hw, &cmd->header);
  1410. if (!rc) {
  1411. int off;
  1412. SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
  1413. priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
  1414. priv->fw_rev = le32_to_cpu(cmd->fw_rev);
  1415. priv->hw_rev = cmd->hw_rev;
  1416. off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
  1417. iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
  1418. off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
  1419. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1420. off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
  1421. iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
  1422. off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
  1423. iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
  1424. off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
  1425. iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
  1426. off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
  1427. iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
  1428. }
  1429. kfree(cmd);
  1430. return rc;
  1431. }
  1432. /*
  1433. * CMD_SET_HW_SPEC.
  1434. */
  1435. struct mwl8k_cmd_set_hw_spec {
  1436. struct mwl8k_cmd_pkt header;
  1437. __u8 hw_rev;
  1438. __u8 host_interface;
  1439. __le16 num_mcaddrs;
  1440. __u8 perm_addr[ETH_ALEN];
  1441. __le16 region_code;
  1442. __le32 fw_rev;
  1443. __le32 ps_cookie;
  1444. __le32 caps;
  1445. __le32 rx_queue_ptr;
  1446. __le32 num_tx_queues;
  1447. __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
  1448. __le32 flags;
  1449. __le32 num_tx_desc_per_queue;
  1450. __le32 total_rxd;
  1451. } __attribute__((packed));
  1452. #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
  1453. static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
  1454. {
  1455. struct mwl8k_priv *priv = hw->priv;
  1456. struct mwl8k_cmd_set_hw_spec *cmd;
  1457. int rc;
  1458. int i;
  1459. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1460. if (cmd == NULL)
  1461. return -ENOMEM;
  1462. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
  1463. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1464. cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
  1465. cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
  1466. cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
  1467. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  1468. cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
  1469. cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
  1470. cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
  1471. cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
  1472. rc = mwl8k_post_cmd(hw, &cmd->header);
  1473. kfree(cmd);
  1474. return rc;
  1475. }
  1476. /*
  1477. * CMD_MAC_MULTICAST_ADR.
  1478. */
  1479. struct mwl8k_cmd_mac_multicast_adr {
  1480. struct mwl8k_cmd_pkt header;
  1481. __le16 action;
  1482. __le16 numaddr;
  1483. __u8 addr[0][ETH_ALEN];
  1484. };
  1485. #define MWL8K_ENABLE_RX_DIRECTED 0x0001
  1486. #define MWL8K_ENABLE_RX_MULTICAST 0x0002
  1487. #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
  1488. #define MWL8K_ENABLE_RX_BROADCAST 0x0008
  1489. static struct mwl8k_cmd_pkt *
  1490. __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
  1491. int mc_count, struct dev_addr_list *mclist)
  1492. {
  1493. struct mwl8k_priv *priv = hw->priv;
  1494. struct mwl8k_cmd_mac_multicast_adr *cmd;
  1495. int size;
  1496. if (allmulti || mc_count > priv->num_mcaddrs) {
  1497. allmulti = 1;
  1498. mc_count = 0;
  1499. }
  1500. size = sizeof(*cmd) + mc_count * ETH_ALEN;
  1501. cmd = kzalloc(size, GFP_ATOMIC);
  1502. if (cmd == NULL)
  1503. return NULL;
  1504. cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
  1505. cmd->header.length = cpu_to_le16(size);
  1506. cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
  1507. MWL8K_ENABLE_RX_BROADCAST);
  1508. if (allmulti) {
  1509. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
  1510. } else if (mc_count) {
  1511. int i;
  1512. cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
  1513. cmd->numaddr = cpu_to_le16(mc_count);
  1514. for (i = 0; i < mc_count && mclist; i++) {
  1515. if (mclist->da_addrlen != ETH_ALEN) {
  1516. kfree(cmd);
  1517. return NULL;
  1518. }
  1519. memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
  1520. mclist = mclist->next;
  1521. }
  1522. }
  1523. return &cmd->header;
  1524. }
  1525. /*
  1526. * CMD_GET_STAT.
  1527. */
  1528. struct mwl8k_cmd_get_stat {
  1529. struct mwl8k_cmd_pkt header;
  1530. __le32 stats[64];
  1531. } __attribute__((packed));
  1532. #define MWL8K_STAT_ACK_FAILURE 9
  1533. #define MWL8K_STAT_RTS_FAILURE 12
  1534. #define MWL8K_STAT_FCS_ERROR 24
  1535. #define MWL8K_STAT_RTS_SUCCESS 11
  1536. static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
  1537. struct ieee80211_low_level_stats *stats)
  1538. {
  1539. struct mwl8k_cmd_get_stat *cmd;
  1540. int rc;
  1541. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1542. if (cmd == NULL)
  1543. return -ENOMEM;
  1544. cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
  1545. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1546. rc = mwl8k_post_cmd(hw, &cmd->header);
  1547. if (!rc) {
  1548. stats->dot11ACKFailureCount =
  1549. le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
  1550. stats->dot11RTSFailureCount =
  1551. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
  1552. stats->dot11FCSErrorCount =
  1553. le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
  1554. stats->dot11RTSSuccessCount =
  1555. le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
  1556. }
  1557. kfree(cmd);
  1558. return rc;
  1559. }
  1560. /*
  1561. * CMD_RADIO_CONTROL.
  1562. */
  1563. struct mwl8k_cmd_radio_control {
  1564. struct mwl8k_cmd_pkt header;
  1565. __le16 action;
  1566. __le16 control;
  1567. __le16 radio_on;
  1568. } __attribute__((packed));
  1569. static int
  1570. mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
  1571. {
  1572. struct mwl8k_priv *priv = hw->priv;
  1573. struct mwl8k_cmd_radio_control *cmd;
  1574. int rc;
  1575. if (enable == priv->radio_on && !force)
  1576. return 0;
  1577. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1578. if (cmd == NULL)
  1579. return -ENOMEM;
  1580. cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
  1581. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1582. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1583. cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
  1584. cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
  1585. rc = mwl8k_post_cmd(hw, &cmd->header);
  1586. kfree(cmd);
  1587. if (!rc)
  1588. priv->radio_on = enable;
  1589. return rc;
  1590. }
  1591. static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
  1592. {
  1593. return mwl8k_cmd_radio_control(hw, 0, 0);
  1594. }
  1595. static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
  1596. {
  1597. return mwl8k_cmd_radio_control(hw, 1, 0);
  1598. }
  1599. static int
  1600. mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
  1601. {
  1602. struct mwl8k_priv *priv = hw->priv;
  1603. priv->radio_short_preamble = short_preamble;
  1604. return mwl8k_cmd_radio_control(hw, 1, 1);
  1605. }
  1606. /*
  1607. * CMD_RF_TX_POWER.
  1608. */
  1609. #define MWL8K_TX_POWER_LEVEL_TOTAL 8
  1610. struct mwl8k_cmd_rf_tx_power {
  1611. struct mwl8k_cmd_pkt header;
  1612. __le16 action;
  1613. __le16 support_level;
  1614. __le16 current_level;
  1615. __le16 reserved;
  1616. __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
  1617. } __attribute__((packed));
  1618. static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
  1619. {
  1620. struct mwl8k_cmd_rf_tx_power *cmd;
  1621. int rc;
  1622. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1623. if (cmd == NULL)
  1624. return -ENOMEM;
  1625. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
  1626. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1627. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1628. cmd->support_level = cpu_to_le16(dBm);
  1629. rc = mwl8k_post_cmd(hw, &cmd->header);
  1630. kfree(cmd);
  1631. return rc;
  1632. }
  1633. /*
  1634. * CMD_RF_ANTENNA.
  1635. */
  1636. struct mwl8k_cmd_rf_antenna {
  1637. struct mwl8k_cmd_pkt header;
  1638. __le16 antenna;
  1639. __le16 mode;
  1640. } __attribute__((packed));
  1641. #define MWL8K_RF_ANTENNA_RX 1
  1642. #define MWL8K_RF_ANTENNA_TX 2
  1643. static int
  1644. mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
  1645. {
  1646. struct mwl8k_cmd_rf_antenna *cmd;
  1647. int rc;
  1648. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1649. if (cmd == NULL)
  1650. return -ENOMEM;
  1651. cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
  1652. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1653. cmd->antenna = cpu_to_le16(antenna);
  1654. cmd->mode = cpu_to_le16(mask);
  1655. rc = mwl8k_post_cmd(hw, &cmd->header);
  1656. kfree(cmd);
  1657. return rc;
  1658. }
  1659. /*
  1660. * CMD_SET_PRE_SCAN.
  1661. */
  1662. struct mwl8k_cmd_set_pre_scan {
  1663. struct mwl8k_cmd_pkt header;
  1664. } __attribute__((packed));
  1665. static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
  1666. {
  1667. struct mwl8k_cmd_set_pre_scan *cmd;
  1668. int rc;
  1669. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1670. if (cmd == NULL)
  1671. return -ENOMEM;
  1672. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
  1673. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1674. rc = mwl8k_post_cmd(hw, &cmd->header);
  1675. kfree(cmd);
  1676. return rc;
  1677. }
  1678. /*
  1679. * CMD_SET_POST_SCAN.
  1680. */
  1681. struct mwl8k_cmd_set_post_scan {
  1682. struct mwl8k_cmd_pkt header;
  1683. __le32 isibss;
  1684. __u8 bssid[ETH_ALEN];
  1685. } __attribute__((packed));
  1686. static int
  1687. mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
  1688. {
  1689. struct mwl8k_cmd_set_post_scan *cmd;
  1690. int rc;
  1691. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1692. if (cmd == NULL)
  1693. return -ENOMEM;
  1694. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
  1695. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1696. cmd->isibss = 0;
  1697. memcpy(cmd->bssid, mac, ETH_ALEN);
  1698. rc = mwl8k_post_cmd(hw, &cmd->header);
  1699. kfree(cmd);
  1700. return rc;
  1701. }
  1702. /*
  1703. * CMD_SET_RF_CHANNEL.
  1704. */
  1705. struct mwl8k_cmd_set_rf_channel {
  1706. struct mwl8k_cmd_pkt header;
  1707. __le16 action;
  1708. __u8 current_channel;
  1709. __le32 channel_flags;
  1710. } __attribute__((packed));
  1711. static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
  1712. struct ieee80211_conf *conf)
  1713. {
  1714. struct ieee80211_channel *channel = conf->channel;
  1715. struct mwl8k_cmd_set_rf_channel *cmd;
  1716. int rc;
  1717. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1718. if (cmd == NULL)
  1719. return -ENOMEM;
  1720. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
  1721. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1722. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1723. cmd->current_channel = channel->hw_value;
  1724. if (channel->band == IEEE80211_BAND_2GHZ)
  1725. cmd->channel_flags |= cpu_to_le32(0x00000001);
  1726. if (conf->channel_type == NL80211_CHAN_NO_HT ||
  1727. conf->channel_type == NL80211_CHAN_HT20)
  1728. cmd->channel_flags |= cpu_to_le32(0x00000080);
  1729. else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
  1730. cmd->channel_flags |= cpu_to_le32(0x000001900);
  1731. else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
  1732. cmd->channel_flags |= cpu_to_le32(0x000000900);
  1733. rc = mwl8k_post_cmd(hw, &cmd->header);
  1734. kfree(cmd);
  1735. return rc;
  1736. }
  1737. /*
  1738. * CMD_SET_AID.
  1739. */
  1740. #define MWL8K_FRAME_PROT_DISABLED 0x00
  1741. #define MWL8K_FRAME_PROT_11G 0x07
  1742. #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
  1743. #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
  1744. struct mwl8k_cmd_update_set_aid {
  1745. struct mwl8k_cmd_pkt header;
  1746. __le16 aid;
  1747. /* AP's MAC address (BSSID) */
  1748. __u8 bssid[ETH_ALEN];
  1749. __le16 protection_mode;
  1750. __u8 supp_rates[14];
  1751. } __attribute__((packed));
  1752. static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
  1753. {
  1754. int i;
  1755. int j;
  1756. /*
  1757. * Clear nonstandard rates 4 and 13.
  1758. */
  1759. mask &= 0x1fef;
  1760. for (i = 0, j = 0; i < 14; i++) {
  1761. if (mask & (1 << i))
  1762. rates[j++] = mwl8k_rates[i].hw_value;
  1763. }
  1764. }
  1765. static int
  1766. mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
  1767. struct ieee80211_vif *vif, u32 legacy_rate_mask)
  1768. {
  1769. struct mwl8k_cmd_update_set_aid *cmd;
  1770. u16 prot_mode;
  1771. int rc;
  1772. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1773. if (cmd == NULL)
  1774. return -ENOMEM;
  1775. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
  1776. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1777. cmd->aid = cpu_to_le16(vif->bss_conf.aid);
  1778. memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
  1779. if (vif->bss_conf.use_cts_prot) {
  1780. prot_mode = MWL8K_FRAME_PROT_11G;
  1781. } else {
  1782. switch (vif->bss_conf.ht_operation_mode &
  1783. IEEE80211_HT_OP_MODE_PROTECTION) {
  1784. case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
  1785. prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
  1786. break;
  1787. case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
  1788. prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
  1789. break;
  1790. default:
  1791. prot_mode = MWL8K_FRAME_PROT_DISABLED;
  1792. break;
  1793. }
  1794. }
  1795. cmd->protection_mode = cpu_to_le16(prot_mode);
  1796. legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
  1797. rc = mwl8k_post_cmd(hw, &cmd->header);
  1798. kfree(cmd);
  1799. return rc;
  1800. }
  1801. /*
  1802. * CMD_SET_RATE.
  1803. */
  1804. struct mwl8k_cmd_set_rate {
  1805. struct mwl8k_cmd_pkt header;
  1806. __u8 legacy_rates[14];
  1807. /* Bitmap for supported MCS codes. */
  1808. __u8 mcs_set[16];
  1809. __u8 reserved[16];
  1810. } __attribute__((packed));
  1811. static int
  1812. mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  1813. u32 legacy_rate_mask, u8 *mcs_rates)
  1814. {
  1815. struct mwl8k_cmd_set_rate *cmd;
  1816. int rc;
  1817. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1818. if (cmd == NULL)
  1819. return -ENOMEM;
  1820. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
  1821. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1822. legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
  1823. memcpy(cmd->mcs_set, mcs_rates, 16);
  1824. rc = mwl8k_post_cmd(hw, &cmd->header);
  1825. kfree(cmd);
  1826. return rc;
  1827. }
  1828. /*
  1829. * CMD_FINALIZE_JOIN.
  1830. */
  1831. #define MWL8K_FJ_BEACON_MAXLEN 128
  1832. struct mwl8k_cmd_finalize_join {
  1833. struct mwl8k_cmd_pkt header;
  1834. __le32 sleep_interval; /* Number of beacon periods to sleep */
  1835. __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
  1836. } __attribute__((packed));
  1837. static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
  1838. int framelen, int dtim)
  1839. {
  1840. struct mwl8k_cmd_finalize_join *cmd;
  1841. struct ieee80211_mgmt *payload = frame;
  1842. int payload_len;
  1843. int rc;
  1844. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1845. if (cmd == NULL)
  1846. return -ENOMEM;
  1847. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
  1848. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1849. cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
  1850. payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
  1851. if (payload_len < 0)
  1852. payload_len = 0;
  1853. else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
  1854. payload_len = MWL8K_FJ_BEACON_MAXLEN;
  1855. memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
  1856. rc = mwl8k_post_cmd(hw, &cmd->header);
  1857. kfree(cmd);
  1858. return rc;
  1859. }
  1860. /*
  1861. * CMD_SET_RTS_THRESHOLD.
  1862. */
  1863. struct mwl8k_cmd_set_rts_threshold {
  1864. struct mwl8k_cmd_pkt header;
  1865. __le16 action;
  1866. __le16 threshold;
  1867. } __attribute__((packed));
  1868. static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw,
  1869. u16 action, u16 threshold)
  1870. {
  1871. struct mwl8k_cmd_set_rts_threshold *cmd;
  1872. int rc;
  1873. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1874. if (cmd == NULL)
  1875. return -ENOMEM;
  1876. cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
  1877. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1878. cmd->action = cpu_to_le16(action);
  1879. cmd->threshold = cpu_to_le16(threshold);
  1880. rc = mwl8k_post_cmd(hw, &cmd->header);
  1881. kfree(cmd);
  1882. return rc;
  1883. }
  1884. /*
  1885. * CMD_SET_SLOT.
  1886. */
  1887. struct mwl8k_cmd_set_slot {
  1888. struct mwl8k_cmd_pkt header;
  1889. __le16 action;
  1890. __u8 short_slot;
  1891. } __attribute__((packed));
  1892. static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
  1893. {
  1894. struct mwl8k_cmd_set_slot *cmd;
  1895. int rc;
  1896. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1897. if (cmd == NULL)
  1898. return -ENOMEM;
  1899. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
  1900. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1901. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  1902. cmd->short_slot = short_slot_time;
  1903. rc = mwl8k_post_cmd(hw, &cmd->header);
  1904. kfree(cmd);
  1905. return rc;
  1906. }
  1907. /*
  1908. * CMD_SET_EDCA_PARAMS.
  1909. */
  1910. struct mwl8k_cmd_set_edca_params {
  1911. struct mwl8k_cmd_pkt header;
  1912. /* See MWL8K_SET_EDCA_XXX below */
  1913. __le16 action;
  1914. /* TX opportunity in units of 32 us */
  1915. __le16 txop;
  1916. union {
  1917. struct {
  1918. /* Log exponent of max contention period: 0...15 */
  1919. __le32 log_cw_max;
  1920. /* Log exponent of min contention period: 0...15 */
  1921. __le32 log_cw_min;
  1922. /* Adaptive interframe spacing in units of 32us */
  1923. __u8 aifs;
  1924. /* TX queue to configure */
  1925. __u8 txq;
  1926. } ap;
  1927. struct {
  1928. /* Log exponent of max contention period: 0...15 */
  1929. __u8 log_cw_max;
  1930. /* Log exponent of min contention period: 0...15 */
  1931. __u8 log_cw_min;
  1932. /* Adaptive interframe spacing in units of 32us */
  1933. __u8 aifs;
  1934. /* TX queue to configure */
  1935. __u8 txq;
  1936. } sta;
  1937. };
  1938. } __attribute__((packed));
  1939. #define MWL8K_SET_EDCA_CW 0x01
  1940. #define MWL8K_SET_EDCA_TXOP 0x02
  1941. #define MWL8K_SET_EDCA_AIFS 0x04
  1942. #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
  1943. MWL8K_SET_EDCA_TXOP | \
  1944. MWL8K_SET_EDCA_AIFS)
  1945. static int
  1946. mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
  1947. __u16 cw_min, __u16 cw_max,
  1948. __u8 aifs, __u16 txop)
  1949. {
  1950. struct mwl8k_priv *priv = hw->priv;
  1951. struct mwl8k_cmd_set_edca_params *cmd;
  1952. int rc;
  1953. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1954. if (cmd == NULL)
  1955. return -ENOMEM;
  1956. /*
  1957. * Queues 0 (BE) and 1 (BK) are swapped in hardware for
  1958. * this call.
  1959. */
  1960. qnum ^= !(qnum >> 1);
  1961. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
  1962. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1963. cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
  1964. cmd->txop = cpu_to_le16(txop);
  1965. if (priv->ap_fw) {
  1966. cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
  1967. cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
  1968. cmd->ap.aifs = aifs;
  1969. cmd->ap.txq = qnum;
  1970. } else {
  1971. cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
  1972. cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
  1973. cmd->sta.aifs = aifs;
  1974. cmd->sta.txq = qnum;
  1975. }
  1976. rc = mwl8k_post_cmd(hw, &cmd->header);
  1977. kfree(cmd);
  1978. return rc;
  1979. }
  1980. /*
  1981. * CMD_SET_WMM_MODE.
  1982. */
  1983. struct mwl8k_cmd_set_wmm_mode {
  1984. struct mwl8k_cmd_pkt header;
  1985. __le16 action;
  1986. } __attribute__((packed));
  1987. static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
  1988. {
  1989. struct mwl8k_priv *priv = hw->priv;
  1990. struct mwl8k_cmd_set_wmm_mode *cmd;
  1991. int rc;
  1992. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  1993. if (cmd == NULL)
  1994. return -ENOMEM;
  1995. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
  1996. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  1997. cmd->action = cpu_to_le16(!!enable);
  1998. rc = mwl8k_post_cmd(hw, &cmd->header);
  1999. kfree(cmd);
  2000. if (!rc)
  2001. priv->wmm_enabled = enable;
  2002. return rc;
  2003. }
  2004. /*
  2005. * CMD_MIMO_CONFIG.
  2006. */
  2007. struct mwl8k_cmd_mimo_config {
  2008. struct mwl8k_cmd_pkt header;
  2009. __le32 action;
  2010. __u8 rx_antenna_map;
  2011. __u8 tx_antenna_map;
  2012. } __attribute__((packed));
  2013. static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
  2014. {
  2015. struct mwl8k_cmd_mimo_config *cmd;
  2016. int rc;
  2017. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2018. if (cmd == NULL)
  2019. return -ENOMEM;
  2020. cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
  2021. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2022. cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
  2023. cmd->rx_antenna_map = rx;
  2024. cmd->tx_antenna_map = tx;
  2025. rc = mwl8k_post_cmd(hw, &cmd->header);
  2026. kfree(cmd);
  2027. return rc;
  2028. }
  2029. /*
  2030. * CMD_USE_FIXED_RATE.
  2031. */
  2032. #define MWL8K_RATE_TABLE_SIZE 8
  2033. #define MWL8K_UCAST_RATE 0
  2034. #define MWL8K_USE_AUTO_RATE 0x0002
  2035. struct mwl8k_rate_entry {
  2036. /* Set to 1 if HT rate, 0 if legacy. */
  2037. __le32 is_ht_rate;
  2038. /* Set to 1 to use retry_count field. */
  2039. __le32 enable_retry;
  2040. /* Specified legacy rate or MCS. */
  2041. __le32 rate;
  2042. /* Number of allowed retries. */
  2043. __le32 retry_count;
  2044. } __attribute__((packed));
  2045. struct mwl8k_rate_table {
  2046. /* 1 to allow specified rate and below */
  2047. __le32 allow_rate_drop;
  2048. __le32 num_rates;
  2049. struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
  2050. } __attribute__((packed));
  2051. struct mwl8k_cmd_use_fixed_rate {
  2052. struct mwl8k_cmd_pkt header;
  2053. __le32 action;
  2054. struct mwl8k_rate_table rate_table;
  2055. /* Unicast, Broadcast or Multicast */
  2056. __le32 rate_type;
  2057. __le32 reserved1;
  2058. __le32 reserved2;
  2059. } __attribute__((packed));
  2060. static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
  2061. u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
  2062. {
  2063. struct mwl8k_cmd_use_fixed_rate *cmd;
  2064. int count;
  2065. int rc;
  2066. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2067. if (cmd == NULL)
  2068. return -ENOMEM;
  2069. cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
  2070. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2071. cmd->action = cpu_to_le32(action);
  2072. cmd->rate_type = cpu_to_le32(rate_type);
  2073. if (rate_table != NULL) {
  2074. /*
  2075. * Copy over each field manually so that endian
  2076. * conversion can be done.
  2077. */
  2078. cmd->rate_table.allow_rate_drop =
  2079. cpu_to_le32(rate_table->allow_rate_drop);
  2080. cmd->rate_table.num_rates =
  2081. cpu_to_le32(rate_table->num_rates);
  2082. for (count = 0; count < rate_table->num_rates; count++) {
  2083. struct mwl8k_rate_entry *dst =
  2084. &cmd->rate_table.rate_entry[count];
  2085. struct mwl8k_rate_entry *src =
  2086. &rate_table->rate_entry[count];
  2087. dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
  2088. dst->enable_retry = cpu_to_le32(src->enable_retry);
  2089. dst->rate = cpu_to_le32(src->rate);
  2090. dst->retry_count = cpu_to_le32(src->retry_count);
  2091. }
  2092. }
  2093. rc = mwl8k_post_cmd(hw, &cmd->header);
  2094. kfree(cmd);
  2095. return rc;
  2096. }
  2097. /*
  2098. * CMD_ENABLE_SNIFFER.
  2099. */
  2100. struct mwl8k_cmd_enable_sniffer {
  2101. struct mwl8k_cmd_pkt header;
  2102. __le32 action;
  2103. } __attribute__((packed));
  2104. static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
  2105. {
  2106. struct mwl8k_cmd_enable_sniffer *cmd;
  2107. int rc;
  2108. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2109. if (cmd == NULL)
  2110. return -ENOMEM;
  2111. cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
  2112. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2113. cmd->action = cpu_to_le32(!!enable);
  2114. rc = mwl8k_post_cmd(hw, &cmd->header);
  2115. kfree(cmd);
  2116. return rc;
  2117. }
  2118. /*
  2119. * CMD_SET_MAC_ADDR.
  2120. */
  2121. struct mwl8k_cmd_set_mac_addr {
  2122. struct mwl8k_cmd_pkt header;
  2123. union {
  2124. struct {
  2125. __le16 mac_type;
  2126. __u8 mac_addr[ETH_ALEN];
  2127. } mbss;
  2128. __u8 mac_addr[ETH_ALEN];
  2129. };
  2130. } __attribute__((packed));
  2131. static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
  2132. {
  2133. struct mwl8k_priv *priv = hw->priv;
  2134. struct mwl8k_cmd_set_mac_addr *cmd;
  2135. int rc;
  2136. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2137. if (cmd == NULL)
  2138. return -ENOMEM;
  2139. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
  2140. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2141. if (priv->ap_fw) {
  2142. cmd->mbss.mac_type = 0;
  2143. memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
  2144. } else {
  2145. memcpy(cmd->mac_addr, mac, ETH_ALEN);
  2146. }
  2147. rc = mwl8k_post_cmd(hw, &cmd->header);
  2148. kfree(cmd);
  2149. return rc;
  2150. }
  2151. /*
  2152. * CMD_SET_RATEADAPT_MODE.
  2153. */
  2154. struct mwl8k_cmd_set_rate_adapt_mode {
  2155. struct mwl8k_cmd_pkt header;
  2156. __le16 action;
  2157. __le16 mode;
  2158. } __attribute__((packed));
  2159. static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
  2160. {
  2161. struct mwl8k_cmd_set_rate_adapt_mode *cmd;
  2162. int rc;
  2163. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2164. if (cmd == NULL)
  2165. return -ENOMEM;
  2166. cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
  2167. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2168. cmd->action = cpu_to_le16(MWL8K_CMD_SET);
  2169. cmd->mode = cpu_to_le16(mode);
  2170. rc = mwl8k_post_cmd(hw, &cmd->header);
  2171. kfree(cmd);
  2172. return rc;
  2173. }
  2174. /*
  2175. * CMD_UPDATE_STADB.
  2176. */
  2177. struct ewc_ht_info {
  2178. __le16 control1;
  2179. __le16 control2;
  2180. __le16 control3;
  2181. } __attribute__((packed));
  2182. struct peer_capability_info {
  2183. /* Peer type - AP vs. STA. */
  2184. __u8 peer_type;
  2185. /* Basic 802.11 capabilities from assoc resp. */
  2186. __le16 basic_caps;
  2187. /* Set if peer supports 802.11n high throughput (HT). */
  2188. __u8 ht_support;
  2189. /* Valid if HT is supported. */
  2190. __le16 ht_caps;
  2191. __u8 extended_ht_caps;
  2192. struct ewc_ht_info ewc_info;
  2193. /* Legacy rate table. Intersection of our rates and peer rates. */
  2194. __u8 legacy_rates[12];
  2195. /* HT rate table. Intersection of our rates and peer rates. */
  2196. __u8 ht_rates[16];
  2197. __u8 pad[16];
  2198. /* If set, interoperability mode, no proprietary extensions. */
  2199. __u8 interop;
  2200. __u8 pad2;
  2201. __u8 station_id;
  2202. __le16 amsdu_enabled;
  2203. } __attribute__((packed));
  2204. struct mwl8k_cmd_update_stadb {
  2205. struct mwl8k_cmd_pkt header;
  2206. /* See STADB_ACTION_TYPE */
  2207. __le32 action;
  2208. /* Peer MAC address */
  2209. __u8 peer_addr[ETH_ALEN];
  2210. __le32 reserved;
  2211. /* Peer info - valid during add/update. */
  2212. struct peer_capability_info peer_info;
  2213. } __attribute__((packed));
  2214. #define MWL8K_STA_DB_MODIFY_ENTRY 1
  2215. #define MWL8K_STA_DB_DEL_ENTRY 2
  2216. /* Peer Entry flags - used to define the type of the peer node */
  2217. #define MWL8K_PEER_TYPE_ACCESSPOINT 2
  2218. static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
  2219. struct ieee80211_vif *vif,
  2220. struct ieee80211_sta *sta)
  2221. {
  2222. struct mwl8k_cmd_update_stadb *cmd;
  2223. struct peer_capability_info *p;
  2224. int rc;
  2225. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2226. if (cmd == NULL)
  2227. return -ENOMEM;
  2228. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2229. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2230. cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
  2231. memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
  2232. p = &cmd->peer_info;
  2233. p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
  2234. p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
  2235. p->ht_support = sta->ht_cap.ht_supported;
  2236. p->ht_caps = sta->ht_cap.cap;
  2237. p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
  2238. ((sta->ht_cap.ampdu_density & 7) << 2);
  2239. legacy_rate_mask_to_array(p->legacy_rates,
  2240. sta->supp_rates[IEEE80211_BAND_2GHZ]);
  2241. memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
  2242. p->interop = 1;
  2243. p->amsdu_enabled = 0;
  2244. rc = mwl8k_post_cmd(hw, &cmd->header);
  2245. kfree(cmd);
  2246. return rc ? rc : p->station_id;
  2247. }
  2248. static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
  2249. struct ieee80211_vif *vif, u8 *addr)
  2250. {
  2251. struct mwl8k_cmd_update_stadb *cmd;
  2252. int rc;
  2253. cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
  2254. if (cmd == NULL)
  2255. return -ENOMEM;
  2256. cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
  2257. cmd->header.length = cpu_to_le16(sizeof(*cmd));
  2258. cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
  2259. memcpy(cmd->peer_addr, addr, ETH_ALEN);
  2260. rc = mwl8k_post_cmd(hw, &cmd->header);
  2261. kfree(cmd);
  2262. return rc;
  2263. }
  2264. /*
  2265. * Interrupt handling.
  2266. */
  2267. static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
  2268. {
  2269. struct ieee80211_hw *hw = dev_id;
  2270. struct mwl8k_priv *priv = hw->priv;
  2271. u32 status;
  2272. status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2273. iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2274. if (!status)
  2275. return IRQ_NONE;
  2276. if (status & MWL8K_A2H_INT_TX_DONE)
  2277. tasklet_schedule(&priv->tx_reclaim_task);
  2278. if (status & MWL8K_A2H_INT_RX_READY) {
  2279. while (rxq_process(hw, 0, 1))
  2280. rxq_refill(hw, 0, 1);
  2281. }
  2282. if (status & MWL8K_A2H_INT_OPC_DONE) {
  2283. if (priv->hostcmd_wait != NULL)
  2284. complete(priv->hostcmd_wait);
  2285. }
  2286. if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
  2287. if (!mutex_is_locked(&priv->fw_mutex) &&
  2288. priv->radio_on && priv->pending_tx_pkts)
  2289. mwl8k_tx_start(priv);
  2290. }
  2291. return IRQ_HANDLED;
  2292. }
  2293. /*
  2294. * Core driver operations.
  2295. */
  2296. static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2297. {
  2298. struct mwl8k_priv *priv = hw->priv;
  2299. int index = skb_get_queue_mapping(skb);
  2300. int rc;
  2301. if (priv->current_channel == NULL) {
  2302. printk(KERN_DEBUG "%s: dropped TX frame since radio "
  2303. "disabled\n", wiphy_name(hw->wiphy));
  2304. dev_kfree_skb(skb);
  2305. return NETDEV_TX_OK;
  2306. }
  2307. rc = mwl8k_txq_xmit(hw, index, skb);
  2308. return rc;
  2309. }
  2310. static int mwl8k_start(struct ieee80211_hw *hw)
  2311. {
  2312. struct mwl8k_priv *priv = hw->priv;
  2313. int rc;
  2314. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  2315. IRQF_SHARED, MWL8K_NAME, hw);
  2316. if (rc) {
  2317. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  2318. wiphy_name(hw->wiphy));
  2319. return -EIO;
  2320. }
  2321. /* Enable tx reclaim tasklet */
  2322. tasklet_enable(&priv->tx_reclaim_task);
  2323. /* Enable interrupts */
  2324. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2325. rc = mwl8k_fw_lock(hw);
  2326. if (!rc) {
  2327. rc = mwl8k_cmd_radio_enable(hw);
  2328. if (!priv->ap_fw) {
  2329. if (!rc)
  2330. rc = mwl8k_cmd_enable_sniffer(hw, 0);
  2331. if (!rc)
  2332. rc = mwl8k_cmd_set_pre_scan(hw);
  2333. if (!rc)
  2334. rc = mwl8k_cmd_set_post_scan(hw,
  2335. "\x00\x00\x00\x00\x00\x00");
  2336. }
  2337. if (!rc)
  2338. rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
  2339. if (!rc)
  2340. rc = mwl8k_cmd_set_wmm_mode(hw, 0);
  2341. mwl8k_fw_unlock(hw);
  2342. }
  2343. if (rc) {
  2344. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2345. free_irq(priv->pdev->irq, hw);
  2346. tasklet_disable(&priv->tx_reclaim_task);
  2347. }
  2348. return rc;
  2349. }
  2350. static void mwl8k_stop(struct ieee80211_hw *hw)
  2351. {
  2352. struct mwl8k_priv *priv = hw->priv;
  2353. int i;
  2354. mwl8k_cmd_radio_disable(hw);
  2355. ieee80211_stop_queues(hw);
  2356. /* Disable interrupts */
  2357. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2358. free_irq(priv->pdev->irq, hw);
  2359. /* Stop finalize join worker */
  2360. cancel_work_sync(&priv->finalize_join_worker);
  2361. if (priv->beacon_skb != NULL)
  2362. dev_kfree_skb(priv->beacon_skb);
  2363. /* Stop tx reclaim tasklet */
  2364. tasklet_disable(&priv->tx_reclaim_task);
  2365. /* Return all skbs to mac80211 */
  2366. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2367. mwl8k_txq_reclaim(hw, i, 1);
  2368. }
  2369. static int mwl8k_add_interface(struct ieee80211_hw *hw,
  2370. struct ieee80211_vif *vif)
  2371. {
  2372. struct mwl8k_priv *priv = hw->priv;
  2373. struct mwl8k_vif *mwl8k_vif;
  2374. /*
  2375. * We only support one active interface at a time.
  2376. */
  2377. if (priv->vif != NULL)
  2378. return -EBUSY;
  2379. /*
  2380. * We only support managed interfaces for now.
  2381. */
  2382. if (vif->type != NL80211_IFTYPE_STATION)
  2383. return -EINVAL;
  2384. /*
  2385. * Reject interface creation if sniffer mode is active, as
  2386. * STA operation is mutually exclusive with hardware sniffer
  2387. * mode.
  2388. */
  2389. if (priv->sniffer_enabled) {
  2390. printk(KERN_INFO "%s: unable to create STA "
  2391. "interface due to sniffer mode being enabled\n",
  2392. wiphy_name(hw->wiphy));
  2393. return -EINVAL;
  2394. }
  2395. /* Clean out driver private area */
  2396. mwl8k_vif = MWL8K_VIF(vif);
  2397. memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
  2398. /* Set and save the mac address */
  2399. mwl8k_cmd_set_mac_addr(hw, vif->addr);
  2400. memcpy(mwl8k_vif->mac_addr, vif->addr, ETH_ALEN);
  2401. /* Set Initial sequence number to zero */
  2402. mwl8k_vif->seqno = 0;
  2403. priv->vif = vif;
  2404. priv->current_channel = NULL;
  2405. return 0;
  2406. }
  2407. static void mwl8k_remove_interface(struct ieee80211_hw *hw,
  2408. struct ieee80211_vif *vif)
  2409. {
  2410. struct mwl8k_priv *priv = hw->priv;
  2411. if (priv->vif == NULL)
  2412. return;
  2413. mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  2414. priv->vif = NULL;
  2415. }
  2416. static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
  2417. {
  2418. struct ieee80211_conf *conf = &hw->conf;
  2419. struct mwl8k_priv *priv = hw->priv;
  2420. int rc;
  2421. if (conf->flags & IEEE80211_CONF_IDLE) {
  2422. mwl8k_cmd_radio_disable(hw);
  2423. priv->current_channel = NULL;
  2424. return 0;
  2425. }
  2426. rc = mwl8k_fw_lock(hw);
  2427. if (rc)
  2428. return rc;
  2429. rc = mwl8k_cmd_radio_enable(hw);
  2430. if (rc)
  2431. goto out;
  2432. rc = mwl8k_cmd_set_rf_channel(hw, conf);
  2433. if (rc)
  2434. goto out;
  2435. priv->current_channel = conf->channel;
  2436. if (conf->power_level > 18)
  2437. conf->power_level = 18;
  2438. rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
  2439. if (rc)
  2440. goto out;
  2441. if (priv->ap_fw) {
  2442. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
  2443. if (!rc)
  2444. rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
  2445. } else {
  2446. rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
  2447. }
  2448. out:
  2449. mwl8k_fw_unlock(hw);
  2450. return rc;
  2451. }
  2452. static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
  2453. struct ieee80211_vif *vif,
  2454. struct ieee80211_bss_conf *info,
  2455. u32 changed)
  2456. {
  2457. struct mwl8k_priv *priv = hw->priv;
  2458. u32 ap_legacy_rates;
  2459. u8 ap_mcs_rates[16];
  2460. int rc;
  2461. if (mwl8k_fw_lock(hw))
  2462. return;
  2463. /*
  2464. * No need to capture a beacon if we're no longer associated.
  2465. */
  2466. if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
  2467. priv->capture_beacon = false;
  2468. /*
  2469. * Get the AP's legacy and MCS rates.
  2470. */
  2471. ap_legacy_rates = 0;
  2472. if (vif->bss_conf.assoc) {
  2473. struct ieee80211_sta *ap;
  2474. rcu_read_lock();
  2475. ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
  2476. if (ap == NULL) {
  2477. rcu_read_unlock();
  2478. goto out;
  2479. }
  2480. ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
  2481. memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
  2482. rcu_read_unlock();
  2483. }
  2484. if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
  2485. rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
  2486. if (rc)
  2487. goto out;
  2488. rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
  2489. MWL8K_UCAST_RATE, NULL);
  2490. if (rc)
  2491. goto out;
  2492. }
  2493. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  2494. rc = mwl8k_set_radio_preamble(hw,
  2495. vif->bss_conf.use_short_preamble);
  2496. if (rc)
  2497. goto out;
  2498. }
  2499. if (changed & BSS_CHANGED_ERP_SLOT) {
  2500. rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
  2501. if (rc)
  2502. goto out;
  2503. }
  2504. if (((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) ||
  2505. (changed & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT))) {
  2506. rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
  2507. if (rc)
  2508. goto out;
  2509. }
  2510. if (vif->bss_conf.assoc &&
  2511. (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
  2512. /*
  2513. * Finalize the join. Tell rx handler to process
  2514. * next beacon from our BSSID.
  2515. */
  2516. memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
  2517. priv->capture_beacon = true;
  2518. }
  2519. out:
  2520. mwl8k_fw_unlock(hw);
  2521. }
  2522. static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
  2523. int mc_count, struct dev_addr_list *mclist)
  2524. {
  2525. struct mwl8k_cmd_pkt *cmd;
  2526. /*
  2527. * Synthesize and return a command packet that programs the
  2528. * hardware multicast address filter. At this point we don't
  2529. * know whether FIF_ALLMULTI is being requested, but if it is,
  2530. * we'll end up throwing this packet away and creating a new
  2531. * one in mwl8k_configure_filter().
  2532. */
  2533. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
  2534. return (unsigned long)cmd;
  2535. }
  2536. static int
  2537. mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
  2538. unsigned int changed_flags,
  2539. unsigned int *total_flags)
  2540. {
  2541. struct mwl8k_priv *priv = hw->priv;
  2542. /*
  2543. * Hardware sniffer mode is mutually exclusive with STA
  2544. * operation, so refuse to enable sniffer mode if a STA
  2545. * interface is active.
  2546. */
  2547. if (priv->vif != NULL) {
  2548. if (net_ratelimit())
  2549. printk(KERN_INFO "%s: not enabling sniffer "
  2550. "mode because STA interface is active\n",
  2551. wiphy_name(hw->wiphy));
  2552. return 0;
  2553. }
  2554. if (!priv->sniffer_enabled) {
  2555. if (mwl8k_cmd_enable_sniffer(hw, 1))
  2556. return 0;
  2557. priv->sniffer_enabled = true;
  2558. }
  2559. *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
  2560. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
  2561. FIF_OTHER_BSS;
  2562. return 1;
  2563. }
  2564. static void mwl8k_configure_filter(struct ieee80211_hw *hw,
  2565. unsigned int changed_flags,
  2566. unsigned int *total_flags,
  2567. u64 multicast)
  2568. {
  2569. struct mwl8k_priv *priv = hw->priv;
  2570. struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
  2571. /*
  2572. * AP firmware doesn't allow fine-grained control over
  2573. * the receive filter.
  2574. */
  2575. if (priv->ap_fw) {
  2576. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2577. kfree(cmd);
  2578. return;
  2579. }
  2580. /*
  2581. * Enable hardware sniffer mode if FIF_CONTROL or
  2582. * FIF_OTHER_BSS is requested.
  2583. */
  2584. if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
  2585. mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
  2586. kfree(cmd);
  2587. return;
  2588. }
  2589. /* Clear unsupported feature flags */
  2590. *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
  2591. if (mwl8k_fw_lock(hw))
  2592. return;
  2593. if (priv->sniffer_enabled) {
  2594. mwl8k_cmd_enable_sniffer(hw, 0);
  2595. priv->sniffer_enabled = false;
  2596. }
  2597. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  2598. if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
  2599. /*
  2600. * Disable the BSS filter.
  2601. */
  2602. mwl8k_cmd_set_pre_scan(hw);
  2603. } else {
  2604. const u8 *bssid;
  2605. /*
  2606. * Enable the BSS filter.
  2607. *
  2608. * If there is an active STA interface, use that
  2609. * interface's BSSID, otherwise use a dummy one
  2610. * (where the OUI part needs to be nonzero for
  2611. * the BSSID to be accepted by POST_SCAN).
  2612. */
  2613. bssid = "\x01\x00\x00\x00\x00\x00";
  2614. if (priv->vif != NULL)
  2615. bssid = priv->vif->bss_conf.bssid;
  2616. mwl8k_cmd_set_post_scan(hw, bssid);
  2617. }
  2618. }
  2619. /*
  2620. * If FIF_ALLMULTI is being requested, throw away the command
  2621. * packet that ->prepare_multicast() built and replace it with
  2622. * a command packet that enables reception of all multicast
  2623. * packets.
  2624. */
  2625. if (*total_flags & FIF_ALLMULTI) {
  2626. kfree(cmd);
  2627. cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
  2628. }
  2629. if (cmd != NULL) {
  2630. mwl8k_post_cmd(hw, cmd);
  2631. kfree(cmd);
  2632. }
  2633. mwl8k_fw_unlock(hw);
  2634. }
  2635. static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  2636. {
  2637. return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value);
  2638. }
  2639. struct mwl8k_sta_notify_item
  2640. {
  2641. struct list_head list;
  2642. struct ieee80211_vif *vif;
  2643. enum sta_notify_cmd cmd;
  2644. struct ieee80211_sta sta;
  2645. };
  2646. static void mwl8k_sta_notify_worker(struct work_struct *work)
  2647. {
  2648. struct mwl8k_priv *priv =
  2649. container_of(work, struct mwl8k_priv, sta_notify_worker);
  2650. struct ieee80211_hw *hw = priv->hw;
  2651. spin_lock_bh(&priv->sta_notify_list_lock);
  2652. while (!list_empty(&priv->sta_notify_list)) {
  2653. struct mwl8k_sta_notify_item *s;
  2654. s = list_entry(priv->sta_notify_list.next,
  2655. struct mwl8k_sta_notify_item, list);
  2656. list_del(&s->list);
  2657. spin_unlock_bh(&priv->sta_notify_list_lock);
  2658. if (s->cmd == STA_NOTIFY_ADD) {
  2659. int rc;
  2660. rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
  2661. if (rc >= 0) {
  2662. struct ieee80211_sta *sta;
  2663. rcu_read_lock();
  2664. sta = ieee80211_find_sta(s->vif, s->sta.addr);
  2665. if (sta != NULL)
  2666. MWL8K_STA(sta)->peer_id = rc;
  2667. rcu_read_unlock();
  2668. }
  2669. } else {
  2670. mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
  2671. }
  2672. kfree(s);
  2673. spin_lock_bh(&priv->sta_notify_list_lock);
  2674. }
  2675. spin_unlock_bh(&priv->sta_notify_list_lock);
  2676. }
  2677. static void
  2678. mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2679. enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
  2680. {
  2681. struct mwl8k_priv *priv = hw->priv;
  2682. struct mwl8k_sta_notify_item *s;
  2683. if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
  2684. return;
  2685. s = kmalloc(sizeof(*s), GFP_ATOMIC);
  2686. if (s != NULL) {
  2687. s->vif = vif;
  2688. s->cmd = cmd;
  2689. s->sta = *sta;
  2690. spin_lock(&priv->sta_notify_list_lock);
  2691. list_add_tail(&s->list, &priv->sta_notify_list);
  2692. spin_unlock(&priv->sta_notify_list_lock);
  2693. ieee80211_queue_work(hw, &priv->sta_notify_worker);
  2694. }
  2695. }
  2696. static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  2697. const struct ieee80211_tx_queue_params *params)
  2698. {
  2699. struct mwl8k_priv *priv = hw->priv;
  2700. int rc;
  2701. rc = mwl8k_fw_lock(hw);
  2702. if (!rc) {
  2703. if (!priv->wmm_enabled)
  2704. rc = mwl8k_cmd_set_wmm_mode(hw, 1);
  2705. if (!rc)
  2706. rc = mwl8k_cmd_set_edca_params(hw, queue,
  2707. params->cw_min,
  2708. params->cw_max,
  2709. params->aifs,
  2710. params->txop);
  2711. mwl8k_fw_unlock(hw);
  2712. }
  2713. return rc;
  2714. }
  2715. static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
  2716. struct ieee80211_tx_queue_stats *stats)
  2717. {
  2718. struct mwl8k_priv *priv = hw->priv;
  2719. struct mwl8k_tx_queue *txq;
  2720. int index;
  2721. spin_lock_bh(&priv->tx_lock);
  2722. for (index = 0; index < MWL8K_TX_QUEUES; index++) {
  2723. txq = priv->txq + index;
  2724. memcpy(&stats[index], &txq->stats,
  2725. sizeof(struct ieee80211_tx_queue_stats));
  2726. }
  2727. spin_unlock_bh(&priv->tx_lock);
  2728. return 0;
  2729. }
  2730. static int mwl8k_get_stats(struct ieee80211_hw *hw,
  2731. struct ieee80211_low_level_stats *stats)
  2732. {
  2733. return mwl8k_cmd_get_stat(hw, stats);
  2734. }
  2735. static int
  2736. mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  2737. enum ieee80211_ampdu_mlme_action action,
  2738. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2739. {
  2740. switch (action) {
  2741. case IEEE80211_AMPDU_RX_START:
  2742. case IEEE80211_AMPDU_RX_STOP:
  2743. if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
  2744. return -ENOTSUPP;
  2745. return 0;
  2746. default:
  2747. return -ENOTSUPP;
  2748. }
  2749. }
  2750. static const struct ieee80211_ops mwl8k_ops = {
  2751. .tx = mwl8k_tx,
  2752. .start = mwl8k_start,
  2753. .stop = mwl8k_stop,
  2754. .add_interface = mwl8k_add_interface,
  2755. .remove_interface = mwl8k_remove_interface,
  2756. .config = mwl8k_config,
  2757. .bss_info_changed = mwl8k_bss_info_changed,
  2758. .prepare_multicast = mwl8k_prepare_multicast,
  2759. .configure_filter = mwl8k_configure_filter,
  2760. .set_rts_threshold = mwl8k_set_rts_threshold,
  2761. .sta_notify = mwl8k_sta_notify,
  2762. .conf_tx = mwl8k_conf_tx,
  2763. .get_tx_stats = mwl8k_get_tx_stats,
  2764. .get_stats = mwl8k_get_stats,
  2765. .ampdu_action = mwl8k_ampdu_action,
  2766. };
  2767. static void mwl8k_tx_reclaim_handler(unsigned long data)
  2768. {
  2769. int i;
  2770. struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
  2771. struct mwl8k_priv *priv = hw->priv;
  2772. spin_lock_bh(&priv->tx_lock);
  2773. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  2774. mwl8k_txq_reclaim(hw, i, 0);
  2775. if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
  2776. complete(priv->tx_wait);
  2777. priv->tx_wait = NULL;
  2778. }
  2779. spin_unlock_bh(&priv->tx_lock);
  2780. }
  2781. static void mwl8k_finalize_join_worker(struct work_struct *work)
  2782. {
  2783. struct mwl8k_priv *priv =
  2784. container_of(work, struct mwl8k_priv, finalize_join_worker);
  2785. struct sk_buff *skb = priv->beacon_skb;
  2786. mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
  2787. priv->vif->bss_conf.dtim_period);
  2788. dev_kfree_skb(skb);
  2789. priv->beacon_skb = NULL;
  2790. }
  2791. enum {
  2792. MWL8363 = 0,
  2793. MWL8687,
  2794. MWL8366,
  2795. };
  2796. static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
  2797. [MWL8363] = {
  2798. .part_name = "88w8363",
  2799. .helper_image = "mwl8k/helper_8363.fw",
  2800. .fw_image = "mwl8k/fmimage_8363.fw",
  2801. },
  2802. [MWL8687] = {
  2803. .part_name = "88w8687",
  2804. .helper_image = "mwl8k/helper_8687.fw",
  2805. .fw_image = "mwl8k/fmimage_8687.fw",
  2806. },
  2807. [MWL8366] = {
  2808. .part_name = "88w8366",
  2809. .helper_image = "mwl8k/helper_8366.fw",
  2810. .fw_image = "mwl8k/fmimage_8366.fw",
  2811. .ap_rxd_ops = &rxd_8366_ap_ops,
  2812. },
  2813. };
  2814. static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
  2815. { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
  2816. { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
  2817. { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
  2818. { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
  2819. { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
  2820. { },
  2821. };
  2822. MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
  2823. static int __devinit mwl8k_probe(struct pci_dev *pdev,
  2824. const struct pci_device_id *id)
  2825. {
  2826. static int printed_version = 0;
  2827. struct ieee80211_hw *hw;
  2828. struct mwl8k_priv *priv;
  2829. int rc;
  2830. int i;
  2831. if (!printed_version) {
  2832. printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
  2833. printed_version = 1;
  2834. }
  2835. rc = pci_enable_device(pdev);
  2836. if (rc) {
  2837. printk(KERN_ERR "%s: Cannot enable new PCI device\n",
  2838. MWL8K_NAME);
  2839. return rc;
  2840. }
  2841. rc = pci_request_regions(pdev, MWL8K_NAME);
  2842. if (rc) {
  2843. printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
  2844. MWL8K_NAME);
  2845. goto err_disable_device;
  2846. }
  2847. pci_set_master(pdev);
  2848. hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
  2849. if (hw == NULL) {
  2850. printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
  2851. rc = -ENOMEM;
  2852. goto err_free_reg;
  2853. }
  2854. SET_IEEE80211_DEV(hw, &pdev->dev);
  2855. pci_set_drvdata(pdev, hw);
  2856. priv = hw->priv;
  2857. priv->hw = hw;
  2858. priv->pdev = pdev;
  2859. priv->device_info = &mwl8k_info_tbl[id->driver_data];
  2860. priv->sram = pci_iomap(pdev, 0, 0x10000);
  2861. if (priv->sram == NULL) {
  2862. printk(KERN_ERR "%s: Cannot map device SRAM\n",
  2863. wiphy_name(hw->wiphy));
  2864. goto err_iounmap;
  2865. }
  2866. /*
  2867. * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
  2868. * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
  2869. */
  2870. priv->regs = pci_iomap(pdev, 1, 0x10000);
  2871. if (priv->regs == NULL) {
  2872. priv->regs = pci_iomap(pdev, 2, 0x10000);
  2873. if (priv->regs == NULL) {
  2874. printk(KERN_ERR "%s: Cannot map device registers\n",
  2875. wiphy_name(hw->wiphy));
  2876. goto err_iounmap;
  2877. }
  2878. }
  2879. /* Reset firmware and hardware */
  2880. mwl8k_hw_reset(priv);
  2881. /* Ask userland hotplug daemon for the device firmware */
  2882. rc = mwl8k_request_firmware(priv);
  2883. if (rc) {
  2884. printk(KERN_ERR "%s: Firmware files not found\n",
  2885. wiphy_name(hw->wiphy));
  2886. goto err_stop_firmware;
  2887. }
  2888. /* Load firmware into hardware */
  2889. rc = mwl8k_load_firmware(hw);
  2890. if (rc) {
  2891. printk(KERN_ERR "%s: Cannot start firmware\n",
  2892. wiphy_name(hw->wiphy));
  2893. goto err_stop_firmware;
  2894. }
  2895. /* Reclaim memory once firmware is successfully loaded */
  2896. mwl8k_release_firmware(priv);
  2897. if (priv->ap_fw) {
  2898. priv->rxd_ops = priv->device_info->ap_rxd_ops;
  2899. if (priv->rxd_ops == NULL) {
  2900. printk(KERN_ERR "%s: Driver does not have AP "
  2901. "firmware image support for this hardware\n",
  2902. wiphy_name(hw->wiphy));
  2903. goto err_stop_firmware;
  2904. }
  2905. } else {
  2906. priv->rxd_ops = &rxd_sta_ops;
  2907. }
  2908. priv->sniffer_enabled = false;
  2909. priv->wmm_enabled = false;
  2910. priv->pending_tx_pkts = 0;
  2911. memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
  2912. priv->band.band = IEEE80211_BAND_2GHZ;
  2913. priv->band.channels = priv->channels;
  2914. priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
  2915. priv->band.bitrates = priv->rates;
  2916. priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
  2917. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
  2918. BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
  2919. memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
  2920. /*
  2921. * Extra headroom is the size of the required DMA header
  2922. * minus the size of the smallest 802.11 frame (CTS frame).
  2923. */
  2924. hw->extra_tx_headroom =
  2925. sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
  2926. hw->channel_change_time = 10;
  2927. hw->queues = MWL8K_TX_QUEUES;
  2928. /* Set rssi and noise values to dBm */
  2929. hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
  2930. hw->vif_data_size = sizeof(struct mwl8k_vif);
  2931. hw->sta_data_size = sizeof(struct mwl8k_sta);
  2932. priv->vif = NULL;
  2933. /* Set default radio state and preamble */
  2934. priv->radio_on = 0;
  2935. priv->radio_short_preamble = 0;
  2936. /* Station database handling */
  2937. INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
  2938. spin_lock_init(&priv->sta_notify_list_lock);
  2939. INIT_LIST_HEAD(&priv->sta_notify_list);
  2940. /* Finalize join worker */
  2941. INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
  2942. /* TX reclaim tasklet */
  2943. tasklet_init(&priv->tx_reclaim_task,
  2944. mwl8k_tx_reclaim_handler, (unsigned long)hw);
  2945. tasklet_disable(&priv->tx_reclaim_task);
  2946. /* Power management cookie */
  2947. priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
  2948. if (priv->cookie == NULL)
  2949. goto err_stop_firmware;
  2950. rc = mwl8k_rxq_init(hw, 0);
  2951. if (rc)
  2952. goto err_free_cookie;
  2953. rxq_refill(hw, 0, INT_MAX);
  2954. mutex_init(&priv->fw_mutex);
  2955. priv->fw_mutex_owner = NULL;
  2956. priv->fw_mutex_depth = 0;
  2957. priv->hostcmd_wait = NULL;
  2958. spin_lock_init(&priv->tx_lock);
  2959. priv->tx_wait = NULL;
  2960. for (i = 0; i < MWL8K_TX_QUEUES; i++) {
  2961. rc = mwl8k_txq_init(hw, i);
  2962. if (rc)
  2963. goto err_free_queues;
  2964. }
  2965. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
  2966. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2967. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
  2968. iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
  2969. rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
  2970. IRQF_SHARED, MWL8K_NAME, hw);
  2971. if (rc) {
  2972. printk(KERN_ERR "%s: failed to register IRQ handler\n",
  2973. wiphy_name(hw->wiphy));
  2974. goto err_free_queues;
  2975. }
  2976. /*
  2977. * Temporarily enable interrupts. Initial firmware host
  2978. * commands use interrupts and avoids polling. Disable
  2979. * interrupts when done.
  2980. */
  2981. iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  2982. /* Get config data, mac addrs etc */
  2983. if (priv->ap_fw) {
  2984. rc = mwl8k_cmd_get_hw_spec_ap(hw);
  2985. if (!rc)
  2986. rc = mwl8k_cmd_set_hw_spec(hw);
  2987. } else {
  2988. rc = mwl8k_cmd_get_hw_spec_sta(hw);
  2989. hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
  2990. }
  2991. if (rc) {
  2992. printk(KERN_ERR "%s: Cannot initialise firmware\n",
  2993. wiphy_name(hw->wiphy));
  2994. goto err_free_irq;
  2995. }
  2996. /* Turn radio off */
  2997. rc = mwl8k_cmd_radio_disable(hw);
  2998. if (rc) {
  2999. printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
  3000. goto err_free_irq;
  3001. }
  3002. /* Clear MAC address */
  3003. rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
  3004. if (rc) {
  3005. printk(KERN_ERR "%s: Cannot clear MAC address\n",
  3006. wiphy_name(hw->wiphy));
  3007. goto err_free_irq;
  3008. }
  3009. /* Disable interrupts */
  3010. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3011. free_irq(priv->pdev->irq, hw);
  3012. rc = ieee80211_register_hw(hw);
  3013. if (rc) {
  3014. printk(KERN_ERR "%s: Cannot register device\n",
  3015. wiphy_name(hw->wiphy));
  3016. goto err_free_queues;
  3017. }
  3018. printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
  3019. wiphy_name(hw->wiphy), priv->device_info->part_name,
  3020. priv->hw_rev, hw->wiphy->perm_addr,
  3021. priv->ap_fw ? "AP" : "STA",
  3022. (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
  3023. (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
  3024. return 0;
  3025. err_free_irq:
  3026. iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
  3027. free_irq(priv->pdev->irq, hw);
  3028. err_free_queues:
  3029. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3030. mwl8k_txq_deinit(hw, i);
  3031. mwl8k_rxq_deinit(hw, 0);
  3032. err_free_cookie:
  3033. if (priv->cookie != NULL)
  3034. pci_free_consistent(priv->pdev, 4,
  3035. priv->cookie, priv->cookie_dma);
  3036. err_stop_firmware:
  3037. mwl8k_hw_reset(priv);
  3038. mwl8k_release_firmware(priv);
  3039. err_iounmap:
  3040. if (priv->regs != NULL)
  3041. pci_iounmap(pdev, priv->regs);
  3042. if (priv->sram != NULL)
  3043. pci_iounmap(pdev, priv->sram);
  3044. pci_set_drvdata(pdev, NULL);
  3045. ieee80211_free_hw(hw);
  3046. err_free_reg:
  3047. pci_release_regions(pdev);
  3048. err_disable_device:
  3049. pci_disable_device(pdev);
  3050. return rc;
  3051. }
  3052. static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
  3053. {
  3054. printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
  3055. }
  3056. static void __devexit mwl8k_remove(struct pci_dev *pdev)
  3057. {
  3058. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  3059. struct mwl8k_priv *priv;
  3060. int i;
  3061. if (hw == NULL)
  3062. return;
  3063. priv = hw->priv;
  3064. ieee80211_stop_queues(hw);
  3065. ieee80211_unregister_hw(hw);
  3066. /* Remove tx reclaim tasklet */
  3067. tasklet_kill(&priv->tx_reclaim_task);
  3068. /* Stop hardware */
  3069. mwl8k_hw_reset(priv);
  3070. /* Return all skbs to mac80211 */
  3071. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3072. mwl8k_txq_reclaim(hw, i, 1);
  3073. for (i = 0; i < MWL8K_TX_QUEUES; i++)
  3074. mwl8k_txq_deinit(hw, i);
  3075. mwl8k_rxq_deinit(hw, 0);
  3076. pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
  3077. pci_iounmap(pdev, priv->regs);
  3078. pci_iounmap(pdev, priv->sram);
  3079. pci_set_drvdata(pdev, NULL);
  3080. ieee80211_free_hw(hw);
  3081. pci_release_regions(pdev);
  3082. pci_disable_device(pdev);
  3083. }
  3084. static struct pci_driver mwl8k_driver = {
  3085. .name = MWL8K_NAME,
  3086. .id_table = mwl8k_pci_id_table,
  3087. .probe = mwl8k_probe,
  3088. .remove = __devexit_p(mwl8k_remove),
  3089. .shutdown = __devexit_p(mwl8k_shutdown),
  3090. };
  3091. static int __init mwl8k_init(void)
  3092. {
  3093. return pci_register_driver(&mwl8k_driver);
  3094. }
  3095. static void __exit mwl8k_exit(void)
  3096. {
  3097. pci_unregister_driver(&mwl8k_driver);
  3098. }
  3099. module_init(mwl8k_init);
  3100. module_exit(mwl8k_exit);
  3101. MODULE_DESCRIPTION(MWL8K_DESC);
  3102. MODULE_VERSION(MWL8K_VERSION);
  3103. MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
  3104. MODULE_LICENSE("GPL");