wm8804.c 19 KB

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  1. /*
  2. * wm8804.c -- WM8804 S/PDIF transceiver driver
  3. *
  4. * Copyright 2010 Wolfson Microelectronics plc
  5. *
  6. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/regulator/consumer.h>
  20. #include <linux/slab.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include "wm8804.h"
  29. #define WM8804_NUM_SUPPLIES 2
  30. static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
  31. "PVDD",
  32. "DVDD"
  33. };
  34. static const u8 wm8804_reg_defs[] = {
  35. 0x05, /* R0 - RST/DEVID1 */
  36. 0x88, /* R1 - DEVID2 */
  37. 0x04, /* R2 - DEVREV */
  38. 0x21, /* R3 - PLL1 */
  39. 0xFD, /* R4 - PLL2 */
  40. 0x36, /* R5 - PLL3 */
  41. 0x07, /* R6 - PLL4 */
  42. 0x16, /* R7 - PLL5 */
  43. 0x18, /* R8 - PLL6 */
  44. 0xFF, /* R9 - SPDMODE */
  45. 0x00, /* R10 - INTMASK */
  46. 0x00, /* R11 - INTSTAT */
  47. 0x00, /* R12 - SPDSTAT */
  48. 0x00, /* R13 - RXCHAN1 */
  49. 0x00, /* R14 - RXCHAN2 */
  50. 0x00, /* R15 - RXCHAN3 */
  51. 0x00, /* R16 - RXCHAN4 */
  52. 0x00, /* R17 - RXCHAN5 */
  53. 0x00, /* R18 - SPDTX1 */
  54. 0x00, /* R19 - SPDTX2 */
  55. 0x00, /* R20 - SPDTX3 */
  56. 0x71, /* R21 - SPDTX4 */
  57. 0x0B, /* R22 - SPDTX5 */
  58. 0x70, /* R23 - GPO0 */
  59. 0x57, /* R24 - GPO1 */
  60. 0x00, /* R25 */
  61. 0x42, /* R26 - GPO2 */
  62. 0x06, /* R27 - AIFTX */
  63. 0x06, /* R28 - AIFRX */
  64. 0x80, /* R29 - SPDRX1 */
  65. 0x07, /* R30 - PWRDN */
  66. };
  67. struct wm8804_priv {
  68. enum snd_soc_control_type control_type;
  69. struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
  70. struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
  71. struct snd_soc_codec *codec;
  72. };
  73. static int txsrc_get(struct snd_kcontrol *kcontrol,
  74. struct snd_ctl_elem_value *ucontrol);
  75. static int txsrc_put(struct snd_kcontrol *kcontrol,
  76. struct snd_ctl_elem_value *ucontrol);
  77. /*
  78. * We can't use the same notifier block for more than one supply and
  79. * there's no way I can see to get from a callback to the caller
  80. * except container_of().
  81. */
  82. #define WM8804_REGULATOR_EVENT(n) \
  83. static int wm8804_regulator_event_##n(struct notifier_block *nb, \
  84. unsigned long event, void *data) \
  85. { \
  86. struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
  87. disable_nb[n]); \
  88. if (event & REGULATOR_EVENT_DISABLE) { \
  89. wm8804->codec->cache_sync = 1; \
  90. } \
  91. return 0; \
  92. }
  93. WM8804_REGULATOR_EVENT(0)
  94. WM8804_REGULATOR_EVENT(1)
  95. static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
  96. static const SOC_ENUM_SINGLE_EXT_DECL(txsrc, txsrc_text);
  97. static const struct snd_kcontrol_new wm8804_snd_controls[] = {
  98. SOC_ENUM_EXT("Input Source", txsrc, txsrc_get, txsrc_put),
  99. SOC_SINGLE("TX Playback Switch", WM8804_PWRDN, 2, 1, 1),
  100. SOC_SINGLE("AIF Playback Switch", WM8804_PWRDN, 4, 1, 1)
  101. };
  102. static int txsrc_get(struct snd_kcontrol *kcontrol,
  103. struct snd_ctl_elem_value *ucontrol)
  104. {
  105. struct snd_soc_codec *codec;
  106. unsigned int src;
  107. codec = snd_kcontrol_chip(kcontrol);
  108. src = snd_soc_read(codec, WM8804_SPDTX4);
  109. if (src & 0x40)
  110. ucontrol->value.integer.value[0] = 1;
  111. else
  112. ucontrol->value.integer.value[0] = 0;
  113. return 0;
  114. }
  115. static int txsrc_put(struct snd_kcontrol *kcontrol,
  116. struct snd_ctl_elem_value *ucontrol)
  117. {
  118. struct snd_soc_codec *codec;
  119. unsigned int src, txpwr;
  120. codec = snd_kcontrol_chip(kcontrol);
  121. if (ucontrol->value.integer.value[0] != 0
  122. && ucontrol->value.integer.value[0] != 1)
  123. return -EINVAL;
  124. src = snd_soc_read(codec, WM8804_SPDTX4);
  125. switch ((src & 0x40) >> 6) {
  126. case 0:
  127. if (!ucontrol->value.integer.value[0])
  128. return 0;
  129. break;
  130. case 1:
  131. if (ucontrol->value.integer.value[1])
  132. return 0;
  133. break;
  134. }
  135. /* save the current power state of the transmitter */
  136. txpwr = snd_soc_read(codec, WM8804_PWRDN) & 0x4;
  137. /* power down the transmitter */
  138. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x4);
  139. /* set the tx source */
  140. snd_soc_update_bits(codec, WM8804_SPDTX4, 0x40,
  141. ucontrol->value.integer.value[0] << 6);
  142. if (ucontrol->value.integer.value[0]) {
  143. /* power down the receiver */
  144. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0x2);
  145. /* power up the AIF */
  146. snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0);
  147. } else {
  148. /* don't power down the AIF -- may be used as an output */
  149. /* power up the receiver */
  150. snd_soc_update_bits(codec, WM8804_PWRDN, 0x2, 0);
  151. }
  152. /* restore the transmitter's configuration */
  153. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, txpwr);
  154. return 0;
  155. }
  156. static int wm8804_volatile(unsigned int reg)
  157. {
  158. switch (reg) {
  159. case WM8804_RST_DEVID1:
  160. case WM8804_DEVID2:
  161. case WM8804_DEVREV:
  162. case WM8804_INTSTAT:
  163. case WM8804_SPDSTAT:
  164. case WM8804_RXCHAN1:
  165. case WM8804_RXCHAN2:
  166. case WM8804_RXCHAN3:
  167. case WM8804_RXCHAN4:
  168. case WM8804_RXCHAN5:
  169. return 1;
  170. default:
  171. break;
  172. }
  173. return 0;
  174. }
  175. static int wm8804_reset(struct snd_soc_codec *codec)
  176. {
  177. return snd_soc_write(codec, WM8804_RST_DEVID1, 0x0);
  178. }
  179. static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  180. {
  181. struct snd_soc_codec *codec;
  182. u16 format, master, bcp, lrp;
  183. codec = dai->codec;
  184. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  185. case SND_SOC_DAIFMT_I2S:
  186. format = 0x2;
  187. break;
  188. case SND_SOC_DAIFMT_RIGHT_J:
  189. format = 0x0;
  190. break;
  191. case SND_SOC_DAIFMT_LEFT_J:
  192. format = 0x1;
  193. break;
  194. case SND_SOC_DAIFMT_DSP_A:
  195. case SND_SOC_DAIFMT_DSP_B:
  196. format = 0x3;
  197. break;
  198. default:
  199. dev_err(dai->dev, "Unknown dai format\n");
  200. return -EINVAL;
  201. }
  202. /* set data format */
  203. snd_soc_update_bits(codec, WM8804_AIFTX, 0x3, format);
  204. snd_soc_update_bits(codec, WM8804_AIFRX, 0x3, format);
  205. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  206. case SND_SOC_DAIFMT_CBM_CFM:
  207. master = 1;
  208. break;
  209. case SND_SOC_DAIFMT_CBS_CFS:
  210. master = 0;
  211. break;
  212. default:
  213. dev_err(dai->dev, "Unknown master/slave configuration\n");
  214. return -EINVAL;
  215. }
  216. /* set master/slave mode */
  217. snd_soc_update_bits(codec, WM8804_AIFRX, 0x40, master << 6);
  218. bcp = lrp = 0;
  219. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  220. case SND_SOC_DAIFMT_NB_NF:
  221. break;
  222. case SND_SOC_DAIFMT_IB_IF:
  223. bcp = lrp = 1;
  224. break;
  225. case SND_SOC_DAIFMT_IB_NF:
  226. bcp = 1;
  227. break;
  228. case SND_SOC_DAIFMT_NB_IF:
  229. lrp = 1;
  230. break;
  231. default:
  232. dev_err(dai->dev, "Unknown polarity configuration\n");
  233. return -EINVAL;
  234. }
  235. /* set frame inversion */
  236. snd_soc_update_bits(codec, WM8804_AIFTX, 0x10 | 0x20,
  237. (bcp << 4) | (lrp << 5));
  238. snd_soc_update_bits(codec, WM8804_AIFRX, 0x10 | 0x20,
  239. (bcp << 4) | (lrp << 5));
  240. return 0;
  241. }
  242. static int wm8804_hw_params(struct snd_pcm_substream *substream,
  243. struct snd_pcm_hw_params *params,
  244. struct snd_soc_dai *dai)
  245. {
  246. struct snd_soc_codec *codec;
  247. u16 blen;
  248. codec = dai->codec;
  249. switch (params_format(params)) {
  250. case SNDRV_PCM_FORMAT_S16_LE:
  251. blen = 0x0;
  252. break;
  253. case SNDRV_PCM_FORMAT_S20_3LE:
  254. blen = 0x1;
  255. break;
  256. case SNDRV_PCM_FORMAT_S24_LE:
  257. blen = 0x2;
  258. break;
  259. default:
  260. dev_err(dai->dev, "Unsupported word length: %u\n",
  261. params_format(params));
  262. return -EINVAL;
  263. }
  264. /* set word length */
  265. snd_soc_update_bits(codec, WM8804_AIFTX, 0xc, blen << 2);
  266. snd_soc_update_bits(codec, WM8804_AIFRX, 0xc, blen << 2);
  267. return 0;
  268. }
  269. struct pll_div {
  270. u32 prescale:1;
  271. u32 mclkdiv:1;
  272. u32 freqmode:2;
  273. u32 n:4;
  274. u32 k:22;
  275. };
  276. /* PLL rate to output rate divisions */
  277. static struct {
  278. unsigned int div;
  279. unsigned int freqmode;
  280. unsigned int mclkdiv;
  281. } post_table[] = {
  282. { 2, 0, 0 },
  283. { 4, 0, 1 },
  284. { 4, 1, 0 },
  285. { 8, 1, 1 },
  286. { 8, 2, 0 },
  287. { 16, 2, 1 },
  288. { 12, 3, 0 },
  289. { 24, 3, 1 }
  290. };
  291. #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
  292. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  293. unsigned int source)
  294. {
  295. u64 Kpart;
  296. unsigned long int K, Ndiv, Nmod, tmp;
  297. int i;
  298. /*
  299. * Scale the output frequency up; the PLL should run in the
  300. * region of 90-100MHz.
  301. */
  302. for (i = 0; i < ARRAY_SIZE(post_table); i++) {
  303. tmp = target * post_table[i].div;
  304. if (tmp >= 90000000 && tmp <= 100000000) {
  305. pll_div->freqmode = post_table[i].freqmode;
  306. pll_div->mclkdiv = post_table[i].mclkdiv;
  307. target *= post_table[i].div;
  308. break;
  309. }
  310. }
  311. if (i == ARRAY_SIZE(post_table)) {
  312. pr_err("%s: Unable to scale output frequency: %uHz\n",
  313. __func__, target);
  314. return -EINVAL;
  315. }
  316. pll_div->prescale = 0;
  317. Ndiv = target / source;
  318. if (Ndiv < 5) {
  319. source >>= 1;
  320. pll_div->prescale = 1;
  321. Ndiv = target / source;
  322. }
  323. if (Ndiv < 5 || Ndiv > 13) {
  324. pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
  325. __func__, Ndiv);
  326. return -EINVAL;
  327. }
  328. pll_div->n = Ndiv;
  329. Nmod = target % source;
  330. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  331. do_div(Kpart, source);
  332. K = Kpart & 0xffffffff;
  333. if ((K % 10) >= 5)
  334. K += 5;
  335. K /= 10;
  336. pll_div->k = K;
  337. return 0;
  338. }
  339. static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
  340. int source, unsigned int freq_in,
  341. unsigned int freq_out)
  342. {
  343. int ret;
  344. struct snd_soc_codec *codec;
  345. struct pll_div pll_div = { 0 };
  346. codec = dai->codec;
  347. if (freq_in && freq_out) {
  348. ret = pll_factors(&pll_div, freq_out, freq_in);
  349. if (ret)
  350. return ret;
  351. }
  352. /* power down the PLL before reprogramming it */
  353. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0);
  354. if (!freq_in || !freq_out)
  355. return 0;
  356. /* set PLLN and PRESCALE */
  357. snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
  358. pll_div.n | (pll_div.prescale << 4));
  359. /* set mclkdiv and freqmode */
  360. snd_soc_update_bits(codec, WM8804_PLL5, 0x3 | 0x8,
  361. pll_div.freqmode | (pll_div.mclkdiv << 3));
  362. /* set PLLK */
  363. snd_soc_write(codec, WM8804_PLL1, pll_div.k & 0xff);
  364. snd_soc_write(codec, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
  365. snd_soc_write(codec, WM8804_PLL3, pll_div.k >> 16);
  366. /* power up the PLL */
  367. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0x1);
  368. return 0;
  369. }
  370. static int wm8804_set_sysclk(struct snd_soc_dai *dai,
  371. int clk_id, unsigned int freq, int dir)
  372. {
  373. struct snd_soc_codec *codec;
  374. codec = dai->codec;
  375. switch (clk_id) {
  376. case WM8804_TX_CLKSRC_MCLK:
  377. if ((freq >= 10000000 && freq <= 14400000)
  378. || (freq >= 16280000 && freq <= 27000000))
  379. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0x80);
  380. else {
  381. dev_err(dai->dev, "OSCCLOCK is not within the "
  382. "recommended range: %uHz\n", freq);
  383. return -EINVAL;
  384. }
  385. break;
  386. case WM8804_TX_CLKSRC_PLL:
  387. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0);
  388. break;
  389. case WM8804_CLKOUT_SRC_CLK1:
  390. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0);
  391. break;
  392. case WM8804_CLKOUT_SRC_OSCCLK:
  393. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0x8);
  394. break;
  395. default:
  396. dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
  397. return -EINVAL;
  398. }
  399. return 0;
  400. }
  401. static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
  402. int div_id, int div)
  403. {
  404. struct snd_soc_codec *codec;
  405. codec = dai->codec;
  406. switch (div_id) {
  407. case WM8804_CLKOUT_DIV:
  408. snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
  409. (div & 0x3) << 4);
  410. break;
  411. default:
  412. dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
  413. return -EINVAL;
  414. }
  415. return 0;
  416. }
  417. static void wm8804_sync_cache(struct snd_soc_codec *codec)
  418. {
  419. short i;
  420. u8 *cache;
  421. if (!codec->cache_sync)
  422. return;
  423. codec->cache_only = 0;
  424. cache = codec->reg_cache;
  425. for (i = 0; i < codec->driver->reg_cache_size; i++) {
  426. if (i == WM8804_RST_DEVID1 || cache[i] == wm8804_reg_defs[i])
  427. continue;
  428. snd_soc_write(codec, i, cache[i]);
  429. }
  430. codec->cache_sync = 0;
  431. }
  432. static int wm8804_set_bias_level(struct snd_soc_codec *codec,
  433. enum snd_soc_bias_level level)
  434. {
  435. int ret;
  436. struct wm8804_priv *wm8804;
  437. wm8804 = snd_soc_codec_get_drvdata(codec);
  438. switch (level) {
  439. case SND_SOC_BIAS_ON:
  440. break;
  441. case SND_SOC_BIAS_PREPARE:
  442. /* power up the OSC and the PLL */
  443. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0);
  444. break;
  445. case SND_SOC_BIAS_STANDBY:
  446. if (codec->bias_level == SND_SOC_BIAS_OFF) {
  447. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  448. wm8804->supplies);
  449. if (ret) {
  450. dev_err(codec->dev,
  451. "Failed to enable supplies: %d\n",
  452. ret);
  453. return ret;
  454. }
  455. wm8804_sync_cache(codec);
  456. }
  457. /* power down the OSC and the PLL */
  458. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  459. break;
  460. case SND_SOC_BIAS_OFF:
  461. /* power down the OSC and the PLL */
  462. snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0x9);
  463. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
  464. wm8804->supplies);
  465. break;
  466. }
  467. codec->bias_level = level;
  468. return 0;
  469. }
  470. #ifdef CONFIG_PM
  471. static int wm8804_suspend(struct snd_soc_codec *codec, pm_message_t state)
  472. {
  473. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  474. return 0;
  475. }
  476. static int wm8804_resume(struct snd_soc_codec *codec)
  477. {
  478. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  479. return 0;
  480. }
  481. #else
  482. #define wm8804_suspend NULL
  483. #define wm8804_resume NULL
  484. #endif
  485. static int wm8804_remove(struct snd_soc_codec *codec)
  486. {
  487. struct wm8804_priv *wm8804;
  488. int i;
  489. wm8804 = snd_soc_codec_get_drvdata(codec);
  490. wm8804_set_bias_level(codec, SND_SOC_BIAS_OFF);
  491. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); ++i)
  492. regulator_unregister_notifier(wm8804->supplies[i].consumer,
  493. &wm8804->disable_nb[i]);
  494. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  495. return 0;
  496. }
  497. static int wm8804_probe(struct snd_soc_codec *codec)
  498. {
  499. struct wm8804_priv *wm8804;
  500. int i, id1, id2, ret;
  501. wm8804 = snd_soc_codec_get_drvdata(codec);
  502. wm8804->codec = codec;
  503. codec->idle_bias_off = 1;
  504. ret = snd_soc_codec_set_cache_io(codec, 8, 8, wm8804->control_type);
  505. if (ret < 0) {
  506. dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
  507. return ret;
  508. }
  509. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
  510. wm8804->supplies[i].supply = wm8804_supply_names[i];
  511. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8804->supplies),
  512. wm8804->supplies);
  513. if (ret) {
  514. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  515. return ret;
  516. }
  517. wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
  518. wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
  519. /* This should really be moved into the regulator core */
  520. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
  521. ret = regulator_register_notifier(wm8804->supplies[i].consumer,
  522. &wm8804->disable_nb[i]);
  523. if (ret != 0) {
  524. dev_err(codec->dev,
  525. "Failed to register regulator notifier: %d\n",
  526. ret);
  527. }
  528. }
  529. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  530. wm8804->supplies);
  531. if (ret) {
  532. dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
  533. goto err_reg_get;
  534. }
  535. id1 = snd_soc_read(codec, WM8804_RST_DEVID1);
  536. if (id1 < 0) {
  537. dev_err(codec->dev, "Failed to read device ID: %d\n", id1);
  538. ret = id1;
  539. goto err_reg_enable;
  540. }
  541. id2 = snd_soc_read(codec, WM8804_DEVID2);
  542. if (id2 < 0) {
  543. dev_err(codec->dev, "Failed to read device ID: %d\n", id2);
  544. ret = id2;
  545. goto err_reg_enable;
  546. }
  547. id2 = (id2 << 8) | id1;
  548. if (id2 != ((wm8804_reg_defs[WM8804_DEVID2] << 8)
  549. | wm8804_reg_defs[WM8804_RST_DEVID1])) {
  550. dev_err(codec->dev, "Invalid device ID: %#x\n", id2);
  551. ret = -EINVAL;
  552. goto err_reg_enable;
  553. }
  554. ret = wm8804_reset(codec);
  555. if (ret < 0) {
  556. dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
  557. goto err_reg_enable;
  558. }
  559. wm8804_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  560. snd_soc_add_controls(codec, wm8804_snd_controls,
  561. ARRAY_SIZE(wm8804_snd_controls));
  562. return 0;
  563. err_reg_enable:
  564. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  565. err_reg_get:
  566. regulator_bulk_free(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  567. return ret;
  568. }
  569. static struct snd_soc_dai_ops wm8804_dai_ops = {
  570. .hw_params = wm8804_hw_params,
  571. .set_fmt = wm8804_set_fmt,
  572. .set_sysclk = wm8804_set_sysclk,
  573. .set_clkdiv = wm8804_set_clkdiv,
  574. .set_pll = wm8804_set_pll
  575. };
  576. #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  577. SNDRV_PCM_FMTBIT_S24_LE)
  578. static struct snd_soc_dai_driver wm8804_dai = {
  579. .name = "wm8804-s/pdif",
  580. .playback = {
  581. .stream_name = "Playback",
  582. .channels_min = 2,
  583. .channels_max = 2,
  584. .rates = SNDRV_PCM_RATE_8000_192000,
  585. .formats = WM8804_FORMATS,
  586. },
  587. .capture = {
  588. .stream_name = "Capture",
  589. .channels_min = 2,
  590. .channels_max = 2,
  591. .rates = SNDRV_PCM_RATE_8000_192000,
  592. .formats = WM8804_FORMATS,
  593. },
  594. .ops = &wm8804_dai_ops,
  595. .symmetric_rates = 1
  596. };
  597. static struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
  598. .probe = wm8804_probe,
  599. .remove = wm8804_remove,
  600. .suspend = wm8804_suspend,
  601. .resume = wm8804_resume,
  602. .set_bias_level = wm8804_set_bias_level,
  603. .reg_cache_size = ARRAY_SIZE(wm8804_reg_defs),
  604. .reg_word_size = sizeof(u8),
  605. .reg_cache_default = wm8804_reg_defs,
  606. .volatile_register = wm8804_volatile
  607. };
  608. #if defined(CONFIG_SPI_MASTER)
  609. static int __devinit wm8804_spi_probe(struct spi_device *spi)
  610. {
  611. struct wm8804_priv *wm8804;
  612. int ret;
  613. wm8804 = kzalloc(sizeof *wm8804, GFP_KERNEL);
  614. if (IS_ERR(wm8804))
  615. return PTR_ERR(wm8804);
  616. wm8804->control_type = SND_SOC_SPI;
  617. spi_set_drvdata(spi, wm8804);
  618. ret = snd_soc_register_codec(&spi->dev,
  619. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  620. if (ret < 0)
  621. kfree(wm8804);
  622. return ret;
  623. }
  624. static int __devexit wm8804_spi_remove(struct spi_device *spi)
  625. {
  626. snd_soc_unregister_codec(&spi->dev);
  627. kfree(spi_get_drvdata(spi));
  628. return 0;
  629. }
  630. static struct spi_driver wm8804_spi_driver = {
  631. .driver = {
  632. .name = "wm8804",
  633. .owner = THIS_MODULE,
  634. },
  635. .probe = wm8804_spi_probe,
  636. .remove = __devexit_p(wm8804_spi_remove)
  637. };
  638. #endif
  639. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  640. static __devinit int wm8804_i2c_probe(struct i2c_client *i2c,
  641. const struct i2c_device_id *id)
  642. {
  643. struct wm8804_priv *wm8804;
  644. int ret;
  645. wm8804 = kzalloc(sizeof *wm8804, GFP_KERNEL);
  646. if (IS_ERR(wm8804))
  647. return PTR_ERR(wm8804);
  648. wm8804->control_type = SND_SOC_I2C;
  649. i2c_set_clientdata(i2c, wm8804);
  650. ret = snd_soc_register_codec(&i2c->dev,
  651. &soc_codec_dev_wm8804, &wm8804_dai, 1);
  652. if (ret < 0)
  653. kfree(wm8804);
  654. return ret;
  655. }
  656. static __devexit int wm8804_i2c_remove(struct i2c_client *client)
  657. {
  658. snd_soc_unregister_codec(&client->dev);
  659. kfree(i2c_get_clientdata(client));
  660. return 0;
  661. }
  662. static const struct i2c_device_id wm8804_i2c_id[] = {
  663. { "wm8804", 0 },
  664. { }
  665. };
  666. MODULE_DEVICE_TABLE(i2c, wm8804_i2c_id);
  667. static struct i2c_driver wm8804_i2c_driver = {
  668. .driver = {
  669. .name = "wm8804",
  670. .owner = THIS_MODULE,
  671. },
  672. .probe = wm8804_i2c_probe,
  673. .remove = __devexit_p(wm8804_i2c_remove),
  674. .id_table = wm8804_i2c_id
  675. };
  676. #endif
  677. static int __init wm8804_modinit(void)
  678. {
  679. int ret = 0;
  680. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  681. ret = i2c_add_driver(&wm8804_i2c_driver);
  682. if (ret) {
  683. printk(KERN_ERR "Failed to register wm8804 I2C driver: %d\n",
  684. ret);
  685. }
  686. #endif
  687. #if defined(CONFIG_SPI_MASTER)
  688. ret = spi_register_driver(&wm8804_spi_driver);
  689. if (ret != 0) {
  690. printk(KERN_ERR "Failed to register wm8804 SPI driver: %d\n",
  691. ret);
  692. }
  693. #endif
  694. return ret;
  695. }
  696. module_init(wm8804_modinit);
  697. static void __exit wm8804_exit(void)
  698. {
  699. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  700. i2c_del_driver(&wm8804_i2c_driver);
  701. #endif
  702. #if defined(CONFIG_SPI_MASTER)
  703. spi_unregister_driver(&wm8804_spi_driver);
  704. #endif
  705. }
  706. module_exit(wm8804_exit);
  707. MODULE_DESCRIPTION("ASoC WM8804 driver");
  708. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  709. MODULE_LICENSE("GPL");