cs5520.c 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243
  1. /*
  2. * IDE tuning and bus mastering support for the CS5510/CS5520
  3. * chipsets
  4. *
  5. * The CS5510/CS5520 are slightly unusual devices. Unlike the
  6. * typical IDE controllers they do bus mastering with the drive in
  7. * PIO mode and smarter silicon.
  8. *
  9. * The practical upshot of this is that we must always tune the
  10. * drive for the right PIO mode. We must also ignore all the blacklists
  11. * and the drive bus mastering DMA information.
  12. *
  13. * *** This driver is strictly experimental ***
  14. *
  15. * (c) Copyright Red Hat Inc 2002
  16. *
  17. * This program is free software; you can redistribute it and/or modify it
  18. * under the terms of the GNU General Public License as published by the
  19. * Free Software Foundation; either version 2, or (at your option) any
  20. * later version.
  21. *
  22. * This program is distributed in the hope that it will be useful, but
  23. * WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  25. * General Public License for more details.
  26. *
  27. * For the avoidance of doubt the "preferred form" of this code is one which
  28. * is in an open non patent encumbered format. Where cryptographic key signing
  29. * forms part of the process of creating an executable the information
  30. * including keys needed to generate an equivalently functional executable
  31. * are deemed to be part of the source code.
  32. *
  33. */
  34. #include <linux/module.h>
  35. #include <linux/types.h>
  36. #include <linux/kernel.h>
  37. #include <linux/delay.h>
  38. #include <linux/timer.h>
  39. #include <linux/mm.h>
  40. #include <linux/ioport.h>
  41. #include <linux/blkdev.h>
  42. #include <linux/hdreg.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/init.h>
  45. #include <linux/pci.h>
  46. #include <linux/ide.h>
  47. #include <linux/dma-mapping.h>
  48. #include <asm/io.h>
  49. #include <asm/irq.h>
  50. struct pio_clocks
  51. {
  52. int address;
  53. int assert;
  54. int recovery;
  55. };
  56. static struct pio_clocks cs5520_pio_clocks[]={
  57. {3, 6, 11},
  58. {2, 5, 6},
  59. {1, 4, 3},
  60. {1, 3, 2},
  61. {1, 2, 1}
  62. };
  63. static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
  64. {
  65. ide_hwif_t *hwif = HWIF(drive);
  66. struct pci_dev *pdev = hwif->pci_dev;
  67. int controller = drive->dn > 1 ? 1 : 0;
  68. u8 reg;
  69. /* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
  70. /* 8bit CAT/CRT - 8bit command timing for channel */
  71. pci_write_config_byte(pdev, 0x62 + controller,
  72. (cs5520_pio_clocks[pio].recovery << 4) |
  73. (cs5520_pio_clocks[pio].assert));
  74. /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
  75. /* FIXME: should these use address ? */
  76. /* Data read timing */
  77. pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
  78. (cs5520_pio_clocks[pio].recovery << 4) |
  79. (cs5520_pio_clocks[pio].assert));
  80. /* Write command timing */
  81. pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
  82. (cs5520_pio_clocks[pio].recovery << 4) |
  83. (cs5520_pio_clocks[pio].assert));
  84. /* Set the DMA enable/disable flag */
  85. reg = inb(hwif->dma_base + 0x02 + 8*controller);
  86. reg |= 1<<((drive->dn&1)+5);
  87. outb(reg, hwif->dma_base + 0x02 + 8*controller);
  88. }
  89. static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed)
  90. {
  91. printk(KERN_ERR "cs55x0: bad ide timing.\n");
  92. cs5520_set_pio_mode(drive, 0);
  93. }
  94. /*
  95. * We provide a callback for our nonstandard DMA location
  96. */
  97. static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
  98. {
  99. unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
  100. if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
  101. bmide += 8;
  102. ide_setup_dma(hwif, bmide, 8);
  103. }
  104. /*
  105. * We wrap the DMA activate to set the vdma flag. This is needed
  106. * so that the IDE DMA layer issues PIO not DMA commands over the
  107. * DMA channel
  108. */
  109. static int cs5520_dma_on(ide_drive_t *drive)
  110. {
  111. /* ATAPI is harder so leave it for now */
  112. drive->vdma = 1;
  113. return 0;
  114. }
  115. static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
  116. {
  117. hwif->set_pio_mode = &cs5520_set_pio_mode;
  118. hwif->set_dma_mode = &cs5520_set_dma_mode;
  119. if (hwif->dma_base == 0) {
  120. hwif->drives[1].autotune = hwif->drives[0].autotune = 1;
  121. return;
  122. }
  123. hwif->ide_dma_on = &cs5520_dma_on;
  124. hwif->ultra_mask = 0;
  125. hwif->swdma_mask = 0;
  126. hwif->mwdma_mask = 0;
  127. }
  128. #define DECLARE_CS_DEV(name_str) \
  129. { \
  130. .name = name_str, \
  131. .init_setup_dma = cs5520_init_setup_dma, \
  132. .init_hwif = init_hwif_cs5520, \
  133. .autodma = AUTODMA, \
  134. .bootable = ON_BOARD, \
  135. .host_flags = IDE_HFLAG_ISA_PORTS | \
  136. IDE_HFLAG_VDMA | \
  137. IDE_HFLAG_NO_ATAPI_DMA, \
  138. .pio_mask = ATA_PIO4, \
  139. }
  140. static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
  141. /* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
  142. /* 1 */ DECLARE_CS_DEV("Cyrix 5520")
  143. };
  144. /*
  145. * The 5510/5520 are a bit weird. They don't quite set up the way
  146. * the PCI helper layer expects so we must do much of the set up
  147. * work longhand.
  148. */
  149. static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  150. {
  151. ide_hwif_t *hwif = NULL, *mate = NULL;
  152. ata_index_t index;
  153. ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
  154. ide_setup_pci_noise(dev, d);
  155. /* We must not grab the entire device, it has 'ISA' space in its
  156. BARS too and we will freak out other bits of the kernel */
  157. if (pci_enable_device_bars(dev, 1<<2)) {
  158. printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
  159. return -ENODEV;
  160. }
  161. pci_set_master(dev);
  162. if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
  163. printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
  164. return -ENODEV;
  165. }
  166. index.all = 0xf0f0;
  167. /*
  168. * Now the chipset is configured we can let the core
  169. * do all the device setup for us
  170. */
  171. ide_pci_setup_ports(dev, d, 14, &index);
  172. if ((index.b.low & 0xf0) != 0xf0)
  173. hwif = &ide_hwifs[index.b.low];
  174. if ((index.b.high & 0xf0) != 0xf0)
  175. mate = &ide_hwifs[index.b.high];
  176. if (hwif)
  177. probe_hwif_init(hwif);
  178. if (mate)
  179. probe_hwif_init(mate);
  180. if (hwif)
  181. ide_proc_register_port(hwif);
  182. if (mate)
  183. ide_proc_register_port(mate);
  184. return 0;
  185. }
  186. static const struct pci_device_id cs5520_pci_tbl[] = {
  187. { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), 0 },
  188. { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), 1 },
  189. { 0, },
  190. };
  191. MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
  192. static struct pci_driver driver = {
  193. .name = "Cyrix_IDE",
  194. .id_table = cs5520_pci_tbl,
  195. .probe = cs5520_init_one,
  196. };
  197. static int __init cs5520_ide_init(void)
  198. {
  199. return ide_pci_register_driver(&driver);
  200. }
  201. module_init(cs5520_ide_init);
  202. MODULE_AUTHOR("Alan Cox");
  203. MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
  204. MODULE_LICENSE("GPL");