nouveau_bo.c 20 KB

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  1. /*
  2. * Copyright 2007 Dave Airlied
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. /*
  25. * Authors: Dave Airlied <airlied@linux.ie>
  26. * Ben Skeggs <darktama@iinet.net.au>
  27. * Jeremy Kolb <jkolb@brandeis.edu>
  28. */
  29. #include "drmP.h"
  30. #include "nouveau_drm.h"
  31. #include "nouveau_drv.h"
  32. #include "nouveau_dma.h"
  33. #include <linux/log2.h>
  34. #include <linux/slab.h>
  35. static void
  36. nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  37. {
  38. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  39. struct drm_device *dev = dev_priv->dev;
  40. struct nouveau_bo *nvbo = nouveau_bo(bo);
  41. ttm_bo_kunmap(&nvbo->kmap);
  42. if (unlikely(nvbo->gem))
  43. DRM_ERROR("bo %p still attached to GEM object\n", bo);
  44. if (nvbo->tile)
  45. nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
  46. spin_lock(&dev_priv->ttm.bo_list_lock);
  47. list_del(&nvbo->head);
  48. spin_unlock(&dev_priv->ttm.bo_list_lock);
  49. kfree(nvbo);
  50. }
  51. static void
  52. nouveau_bo_fixup_align(struct drm_device *dev,
  53. uint32_t tile_mode, uint32_t tile_flags,
  54. int *align, int *size)
  55. {
  56. struct drm_nouveau_private *dev_priv = dev->dev_private;
  57. /*
  58. * Some of the tile_flags have a periodic structure of N*4096 bytes,
  59. * align to to that as well as the page size. Align the size to the
  60. * appropriate boundaries. This does imply that sizes are rounded up
  61. * 3-7 pages, so be aware of this and do not waste memory by allocating
  62. * many small buffers.
  63. */
  64. if (dev_priv->card_type == NV_50) {
  65. uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15;
  66. int i;
  67. switch (tile_flags) {
  68. case 0x1800:
  69. case 0x2800:
  70. case 0x4800:
  71. case 0x7a00:
  72. if (is_power_of_2(block_size)) {
  73. for (i = 1; i < 10; i++) {
  74. *align = 12 * i * block_size;
  75. if (!(*align % 65536))
  76. break;
  77. }
  78. } else {
  79. for (i = 1; i < 10; i++) {
  80. *align = 8 * i * block_size;
  81. if (!(*align % 65536))
  82. break;
  83. }
  84. }
  85. *size = roundup(*size, *align);
  86. break;
  87. default:
  88. break;
  89. }
  90. } else {
  91. if (tile_mode) {
  92. if (dev_priv->chipset >= 0x40) {
  93. *align = 65536;
  94. *size = roundup(*size, 64 * tile_mode);
  95. } else if (dev_priv->chipset >= 0x30) {
  96. *align = 32768;
  97. *size = roundup(*size, 64 * tile_mode);
  98. } else if (dev_priv->chipset >= 0x20) {
  99. *align = 16384;
  100. *size = roundup(*size, 64 * tile_mode);
  101. } else if (dev_priv->chipset >= 0x10) {
  102. *align = 16384;
  103. *size = roundup(*size, 32 * tile_mode);
  104. }
  105. }
  106. }
  107. /* ALIGN works only on powers of two. */
  108. *size = roundup(*size, PAGE_SIZE);
  109. if (dev_priv->card_type == NV_50) {
  110. *size = roundup(*size, 65536);
  111. *align = max(65536, *align);
  112. }
  113. }
  114. int
  115. nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
  116. int size, int align, uint32_t flags, uint32_t tile_mode,
  117. uint32_t tile_flags, bool no_vm, bool mappable,
  118. struct nouveau_bo **pnvbo)
  119. {
  120. struct drm_nouveau_private *dev_priv = dev->dev_private;
  121. struct nouveau_bo *nvbo;
  122. int ret = 0;
  123. nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
  124. if (!nvbo)
  125. return -ENOMEM;
  126. INIT_LIST_HEAD(&nvbo->head);
  127. INIT_LIST_HEAD(&nvbo->entry);
  128. nvbo->mappable = mappable;
  129. nvbo->no_vm = no_vm;
  130. nvbo->tile_mode = tile_mode;
  131. nvbo->tile_flags = tile_flags;
  132. nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
  133. align >>= PAGE_SHIFT;
  134. nvbo->placement.fpfn = 0;
  135. nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
  136. nouveau_bo_placement_set(nvbo, flags);
  137. nvbo->channel = chan;
  138. ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
  139. ttm_bo_type_device, &nvbo->placement, align, 0,
  140. false, NULL, size, nouveau_bo_del_ttm);
  141. nvbo->channel = NULL;
  142. if (ret) {
  143. /* ttm will call nouveau_bo_del_ttm if it fails.. */
  144. return ret;
  145. }
  146. spin_lock(&dev_priv->ttm.bo_list_lock);
  147. list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);
  148. spin_unlock(&dev_priv->ttm.bo_list_lock);
  149. *pnvbo = nvbo;
  150. return 0;
  151. }
  152. void
  153. nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype)
  154. {
  155. int n = 0;
  156. if (memtype & TTM_PL_FLAG_VRAM)
  157. nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING;
  158. if (memtype & TTM_PL_FLAG_TT)
  159. nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  160. if (memtype & TTM_PL_FLAG_SYSTEM)
  161. nvbo->placements[n++] = TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
  162. nvbo->placement.placement = nvbo->placements;
  163. nvbo->placement.busy_placement = nvbo->placements;
  164. nvbo->placement.num_placement = n;
  165. nvbo->placement.num_busy_placement = n;
  166. if (nvbo->pin_refcnt) {
  167. while (n--)
  168. nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT;
  169. }
  170. }
  171. int
  172. nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
  173. {
  174. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  175. struct ttm_buffer_object *bo = &nvbo->bo;
  176. int ret, i;
  177. if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
  178. NV_ERROR(nouveau_bdev(bo->bdev)->dev,
  179. "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
  180. 1 << bo->mem.mem_type, memtype);
  181. return -EINVAL;
  182. }
  183. if (nvbo->pin_refcnt++)
  184. return 0;
  185. ret = ttm_bo_reserve(bo, false, false, false, 0);
  186. if (ret)
  187. goto out;
  188. nouveau_bo_placement_set(nvbo, memtype);
  189. for (i = 0; i < nvbo->placement.num_placement; i++)
  190. nvbo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
  191. ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
  192. if (ret == 0) {
  193. switch (bo->mem.mem_type) {
  194. case TTM_PL_VRAM:
  195. dev_priv->fb_aper_free -= bo->mem.size;
  196. break;
  197. case TTM_PL_TT:
  198. dev_priv->gart_info.aper_free -= bo->mem.size;
  199. break;
  200. default:
  201. break;
  202. }
  203. }
  204. ttm_bo_unreserve(bo);
  205. out:
  206. if (unlikely(ret))
  207. nvbo->pin_refcnt--;
  208. return ret;
  209. }
  210. int
  211. nouveau_bo_unpin(struct nouveau_bo *nvbo)
  212. {
  213. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  214. struct ttm_buffer_object *bo = &nvbo->bo;
  215. int ret, i;
  216. if (--nvbo->pin_refcnt)
  217. return 0;
  218. ret = ttm_bo_reserve(bo, false, false, false, 0);
  219. if (ret)
  220. return ret;
  221. for (i = 0; i < nvbo->placement.num_placement; i++)
  222. nvbo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
  223. ret = ttm_bo_validate(bo, &nvbo->placement, false, false);
  224. if (ret == 0) {
  225. switch (bo->mem.mem_type) {
  226. case TTM_PL_VRAM:
  227. dev_priv->fb_aper_free += bo->mem.size;
  228. break;
  229. case TTM_PL_TT:
  230. dev_priv->gart_info.aper_free += bo->mem.size;
  231. break;
  232. default:
  233. break;
  234. }
  235. }
  236. ttm_bo_unreserve(bo);
  237. return ret;
  238. }
  239. int
  240. nouveau_bo_map(struct nouveau_bo *nvbo)
  241. {
  242. int ret;
  243. ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
  244. if (ret)
  245. return ret;
  246. ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
  247. ttm_bo_unreserve(&nvbo->bo);
  248. return ret;
  249. }
  250. void
  251. nouveau_bo_unmap(struct nouveau_bo *nvbo)
  252. {
  253. ttm_bo_kunmap(&nvbo->kmap);
  254. }
  255. u16
  256. nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
  257. {
  258. bool is_iomem;
  259. u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  260. mem = &mem[index];
  261. if (is_iomem)
  262. return ioread16_native((void __force __iomem *)mem);
  263. else
  264. return *mem;
  265. }
  266. void
  267. nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
  268. {
  269. bool is_iomem;
  270. u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  271. mem = &mem[index];
  272. if (is_iomem)
  273. iowrite16_native(val, (void __force __iomem *)mem);
  274. else
  275. *mem = val;
  276. }
  277. u32
  278. nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
  279. {
  280. bool is_iomem;
  281. u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  282. mem = &mem[index];
  283. if (is_iomem)
  284. return ioread32_native((void __force __iomem *)mem);
  285. else
  286. return *mem;
  287. }
  288. void
  289. nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
  290. {
  291. bool is_iomem;
  292. u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  293. mem = &mem[index];
  294. if (is_iomem)
  295. iowrite32_native(val, (void __force __iomem *)mem);
  296. else
  297. *mem = val;
  298. }
  299. static struct ttm_backend *
  300. nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
  301. {
  302. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  303. struct drm_device *dev = dev_priv->dev;
  304. switch (dev_priv->gart_info.type) {
  305. #if __OS_HAS_AGP
  306. case NOUVEAU_GART_AGP:
  307. return ttm_agp_backend_init(bdev, dev->agp->bridge);
  308. #endif
  309. case NOUVEAU_GART_SGDMA:
  310. return nouveau_sgdma_init_ttm(dev);
  311. default:
  312. NV_ERROR(dev, "Unknown GART type %d\n",
  313. dev_priv->gart_info.type);
  314. break;
  315. }
  316. return NULL;
  317. }
  318. static int
  319. nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  320. {
  321. /* We'll do this from user space. */
  322. return 0;
  323. }
  324. static int
  325. nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  326. struct ttm_mem_type_manager *man)
  327. {
  328. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  329. struct drm_device *dev = dev_priv->dev;
  330. switch (type) {
  331. case TTM_PL_SYSTEM:
  332. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  333. man->available_caching = TTM_PL_MASK_CACHING;
  334. man->default_caching = TTM_PL_FLAG_CACHED;
  335. break;
  336. case TTM_PL_VRAM:
  337. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  338. TTM_MEMTYPE_FLAG_MAPPABLE |
  339. TTM_MEMTYPE_FLAG_NEEDS_IOREMAP;
  340. man->available_caching = TTM_PL_FLAG_UNCACHED |
  341. TTM_PL_FLAG_WC;
  342. man->default_caching = TTM_PL_FLAG_WC;
  343. man->io_addr = NULL;
  344. man->io_offset = drm_get_resource_start(dev, 1);
  345. man->io_size = drm_get_resource_len(dev, 1);
  346. if (man->io_size > nouveau_mem_fb_amount(dev))
  347. man->io_size = nouveau_mem_fb_amount(dev);
  348. man->gpu_offset = dev_priv->vm_vram_base;
  349. break;
  350. case TTM_PL_TT:
  351. switch (dev_priv->gart_info.type) {
  352. case NOUVEAU_GART_AGP:
  353. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
  354. TTM_MEMTYPE_FLAG_NEEDS_IOREMAP;
  355. man->available_caching = TTM_PL_FLAG_UNCACHED;
  356. man->default_caching = TTM_PL_FLAG_UNCACHED;
  357. break;
  358. case NOUVEAU_GART_SGDMA:
  359. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
  360. TTM_MEMTYPE_FLAG_CMA;
  361. man->available_caching = TTM_PL_MASK_CACHING;
  362. man->default_caching = TTM_PL_FLAG_CACHED;
  363. break;
  364. default:
  365. NV_ERROR(dev, "Unknown GART type: %d\n",
  366. dev_priv->gart_info.type);
  367. return -EINVAL;
  368. }
  369. man->io_offset = dev_priv->gart_info.aper_base;
  370. man->io_size = dev_priv->gart_info.aper_size;
  371. man->io_addr = NULL;
  372. man->gpu_offset = dev_priv->vm_gart_base;
  373. break;
  374. default:
  375. NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
  376. return -EINVAL;
  377. }
  378. return 0;
  379. }
  380. static void
  381. nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
  382. {
  383. struct nouveau_bo *nvbo = nouveau_bo(bo);
  384. switch (bo->mem.mem_type) {
  385. case TTM_PL_VRAM:
  386. nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT);
  387. break;
  388. default:
  389. nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM);
  390. break;
  391. }
  392. *pl = nvbo->placement;
  393. }
  394. /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
  395. * TTM_PL_{VRAM,TT} directly.
  396. */
  397. static int
  398. nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
  399. struct nouveau_bo *nvbo, bool evict, bool no_wait,
  400. struct ttm_mem_reg *new_mem)
  401. {
  402. struct nouveau_fence *fence = NULL;
  403. int ret;
  404. ret = nouveau_fence_new(chan, &fence, true);
  405. if (ret)
  406. return ret;
  407. ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
  408. evict, no_wait, new_mem);
  409. if (nvbo->channel && nvbo->channel != chan)
  410. ret = nouveau_fence_wait(fence, NULL, false, false);
  411. nouveau_fence_unref((void *)&fence);
  412. return ret;
  413. }
  414. static inline uint32_t
  415. nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
  416. struct ttm_mem_reg *mem)
  417. {
  418. if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) {
  419. if (mem->mem_type == TTM_PL_TT)
  420. return NvDmaGART;
  421. return NvDmaVRAM;
  422. }
  423. if (mem->mem_type == TTM_PL_TT)
  424. return chan->gart_handle;
  425. return chan->vram_handle;
  426. }
  427. static int
  428. nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
  429. int no_wait, struct ttm_mem_reg *new_mem)
  430. {
  431. struct nouveau_bo *nvbo = nouveau_bo(bo);
  432. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  433. struct ttm_mem_reg *old_mem = &bo->mem;
  434. struct nouveau_channel *chan;
  435. uint64_t src_offset, dst_offset;
  436. uint32_t page_count;
  437. int ret;
  438. chan = nvbo->channel;
  439. if (!chan || nvbo->tile_flags || nvbo->no_vm)
  440. chan = dev_priv->channel;
  441. src_offset = old_mem->mm_node->start << PAGE_SHIFT;
  442. dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
  443. if (chan != dev_priv->channel) {
  444. if (old_mem->mem_type == TTM_PL_TT)
  445. src_offset += dev_priv->vm_gart_base;
  446. else
  447. src_offset += dev_priv->vm_vram_base;
  448. if (new_mem->mem_type == TTM_PL_TT)
  449. dst_offset += dev_priv->vm_gart_base;
  450. else
  451. dst_offset += dev_priv->vm_vram_base;
  452. }
  453. ret = RING_SPACE(chan, 3);
  454. if (ret)
  455. return ret;
  456. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
  457. OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem));
  458. OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem));
  459. if (dev_priv->card_type >= NV_50) {
  460. ret = RING_SPACE(chan, 4);
  461. if (ret)
  462. return ret;
  463. BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
  464. OUT_RING(chan, 1);
  465. BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
  466. OUT_RING(chan, 1);
  467. }
  468. page_count = new_mem->num_pages;
  469. while (page_count) {
  470. int line_count = (page_count > 2047) ? 2047 : page_count;
  471. if (dev_priv->card_type >= NV_50) {
  472. ret = RING_SPACE(chan, 3);
  473. if (ret)
  474. return ret;
  475. BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
  476. OUT_RING(chan, upper_32_bits(src_offset));
  477. OUT_RING(chan, upper_32_bits(dst_offset));
  478. }
  479. ret = RING_SPACE(chan, 11);
  480. if (ret)
  481. return ret;
  482. BEGIN_RING(chan, NvSubM2MF,
  483. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  484. OUT_RING(chan, lower_32_bits(src_offset));
  485. OUT_RING(chan, lower_32_bits(dst_offset));
  486. OUT_RING(chan, PAGE_SIZE); /* src_pitch */
  487. OUT_RING(chan, PAGE_SIZE); /* dst_pitch */
  488. OUT_RING(chan, PAGE_SIZE); /* line_length */
  489. OUT_RING(chan, line_count);
  490. OUT_RING(chan, (1<<8)|(1<<0));
  491. OUT_RING(chan, 0);
  492. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
  493. OUT_RING(chan, 0);
  494. page_count -= line_count;
  495. src_offset += (PAGE_SIZE * line_count);
  496. dst_offset += (PAGE_SIZE * line_count);
  497. }
  498. return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait, new_mem);
  499. }
  500. static int
  501. nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
  502. bool no_wait, struct ttm_mem_reg *new_mem)
  503. {
  504. u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  505. struct ttm_placement placement;
  506. struct ttm_mem_reg tmp_mem;
  507. int ret;
  508. placement.fpfn = placement.lpfn = 0;
  509. placement.num_placement = placement.num_busy_placement = 1;
  510. placement.placement = placement.busy_placement = &placement_memtype;
  511. tmp_mem = *new_mem;
  512. tmp_mem.mm_node = NULL;
  513. ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait);
  514. if (ret)
  515. return ret;
  516. ret = ttm_tt_bind(bo->ttm, &tmp_mem);
  517. if (ret)
  518. goto out;
  519. ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem);
  520. if (ret)
  521. goto out;
  522. ret = ttm_bo_move_ttm(bo, evict, no_wait, new_mem);
  523. out:
  524. if (tmp_mem.mm_node) {
  525. spin_lock(&bo->bdev->glob->lru_lock);
  526. drm_mm_put_block(tmp_mem.mm_node);
  527. spin_unlock(&bo->bdev->glob->lru_lock);
  528. }
  529. return ret;
  530. }
  531. static int
  532. nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
  533. bool no_wait, struct ttm_mem_reg *new_mem)
  534. {
  535. u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  536. struct ttm_placement placement;
  537. struct ttm_mem_reg tmp_mem;
  538. int ret;
  539. placement.fpfn = placement.lpfn = 0;
  540. placement.num_placement = placement.num_busy_placement = 1;
  541. placement.placement = placement.busy_placement = &placement_memtype;
  542. tmp_mem = *new_mem;
  543. tmp_mem.mm_node = NULL;
  544. ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait);
  545. if (ret)
  546. return ret;
  547. ret = ttm_bo_move_ttm(bo, evict, no_wait, &tmp_mem);
  548. if (ret)
  549. goto out;
  550. ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
  551. if (ret)
  552. goto out;
  553. out:
  554. if (tmp_mem.mm_node) {
  555. spin_lock(&bo->bdev->glob->lru_lock);
  556. drm_mm_put_block(tmp_mem.mm_node);
  557. spin_unlock(&bo->bdev->glob->lru_lock);
  558. }
  559. return ret;
  560. }
  561. static int
  562. nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
  563. struct nouveau_tile_reg **new_tile)
  564. {
  565. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  566. struct drm_device *dev = dev_priv->dev;
  567. struct nouveau_bo *nvbo = nouveau_bo(bo);
  568. uint64_t offset;
  569. int ret;
  570. if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
  571. /* Nothing to do. */
  572. *new_tile = NULL;
  573. return 0;
  574. }
  575. offset = new_mem->mm_node->start << PAGE_SHIFT;
  576. if (dev_priv->card_type == NV_50) {
  577. ret = nv50_mem_vm_bind_linear(dev,
  578. offset + dev_priv->vm_vram_base,
  579. new_mem->size, nvbo->tile_flags,
  580. offset);
  581. if (ret)
  582. return ret;
  583. } else if (dev_priv->card_type >= NV_10) {
  584. *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
  585. nvbo->tile_mode);
  586. }
  587. return 0;
  588. }
  589. static void
  590. nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
  591. struct nouveau_tile_reg *new_tile,
  592. struct nouveau_tile_reg **old_tile)
  593. {
  594. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  595. struct drm_device *dev = dev_priv->dev;
  596. if (dev_priv->card_type >= NV_10 &&
  597. dev_priv->card_type < NV_50) {
  598. if (*old_tile)
  599. nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
  600. *old_tile = new_tile;
  601. }
  602. }
  603. static int
  604. nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
  605. bool no_wait, struct ttm_mem_reg *new_mem)
  606. {
  607. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  608. struct nouveau_bo *nvbo = nouveau_bo(bo);
  609. struct ttm_mem_reg *old_mem = &bo->mem;
  610. struct nouveau_tile_reg *new_tile = NULL;
  611. int ret = 0;
  612. ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
  613. if (ret)
  614. return ret;
  615. /* Software copy if the card isn't up and running yet. */
  616. if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
  617. !dev_priv->channel) {
  618. ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
  619. goto out;
  620. }
  621. /* Fake bo copy. */
  622. if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
  623. BUG_ON(bo->mem.mm_node != NULL);
  624. bo->mem = *new_mem;
  625. new_mem->mm_node = NULL;
  626. goto out;
  627. }
  628. /* Hardware assisted copy. */
  629. if (new_mem->mem_type == TTM_PL_SYSTEM)
  630. ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem);
  631. else if (old_mem->mem_type == TTM_PL_SYSTEM)
  632. ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem);
  633. else
  634. ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem);
  635. if (!ret)
  636. goto out;
  637. /* Fallback to software copy. */
  638. ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
  639. out:
  640. if (ret)
  641. nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
  642. else
  643. nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
  644. return ret;
  645. }
  646. static int
  647. nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  648. {
  649. return 0;
  650. }
  651. struct ttm_bo_driver nouveau_bo_driver = {
  652. .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
  653. .invalidate_caches = nouveau_bo_invalidate_caches,
  654. .init_mem_type = nouveau_bo_init_mem_type,
  655. .evict_flags = nouveau_bo_evict_flags,
  656. .move = nouveau_bo_move,
  657. .verify_access = nouveau_bo_verify_access,
  658. .sync_obj_signaled = nouveau_fence_signalled,
  659. .sync_obj_wait = nouveau_fence_wait,
  660. .sync_obj_flush = nouveau_fence_flush,
  661. .sync_obj_unref = nouveau_fence_unref,
  662. .sync_obj_ref = nouveau_fence_ref,
  663. };