ql4_mbx.c 56 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2010 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  12. int in_count)
  13. {
  14. int i;
  15. /* Load all mailbox registers, except mailbox 0. */
  16. for (i = 1; i < in_count; i++)
  17. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  18. /* Wakeup firmware */
  19. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  20. readl(&ha->reg->mailbox[0]);
  21. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  22. readl(&ha->reg->ctrl_status);
  23. }
  24. void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
  25. {
  26. int intr_status;
  27. intr_status = readl(&ha->reg->ctrl_status);
  28. if (intr_status & INTR_PENDING) {
  29. /*
  30. * Service the interrupt.
  31. * The ISR will save the mailbox status registers
  32. * to a temporary storage location in the adapter structure.
  33. */
  34. ha->mbox_status_count = out_count;
  35. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  36. }
  37. }
  38. /**
  39. * qla4xxx_mailbox_command - issues mailbox commands
  40. * @ha: Pointer to host adapter structure.
  41. * @inCount: number of mailbox registers to load.
  42. * @outCount: number of mailbox registers to return.
  43. * @mbx_cmd: data pointer for mailbox in registers.
  44. * @mbx_sts: data pointer for mailbox out registers.
  45. *
  46. * This routine issue mailbox commands and waits for completion.
  47. * If outCount is 0, this routine completes successfully WITHOUT waiting
  48. * for the mailbox command to complete.
  49. **/
  50. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  51. uint8_t outCount, uint32_t *mbx_cmd,
  52. uint32_t *mbx_sts)
  53. {
  54. int status = QLA_ERROR;
  55. uint8_t i;
  56. u_long wait_count;
  57. unsigned long flags = 0;
  58. uint32_t dev_state;
  59. /* Make sure that pointers are valid */
  60. if (!mbx_cmd || !mbx_sts) {
  61. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  62. "pointer\n", ha->host_no, __func__));
  63. return status;
  64. }
  65. if (is_qla40XX(ha)) {
  66. if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
  67. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  68. "prematurely completing mbx cmd as "
  69. "adapter removal detected\n",
  70. ha->host_no, __func__));
  71. return status;
  72. }
  73. }
  74. if ((is_aer_supported(ha)) &&
  75. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  76. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  77. "timeout MBX Exiting.\n", ha->host_no, __func__));
  78. return status;
  79. }
  80. /* Mailbox code active */
  81. wait_count = MBOX_TOV * 100;
  82. while (wait_count--) {
  83. mutex_lock(&ha->mbox_sem);
  84. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  85. set_bit(AF_MBOX_COMMAND, &ha->flags);
  86. mutex_unlock(&ha->mbox_sem);
  87. break;
  88. }
  89. mutex_unlock(&ha->mbox_sem);
  90. if (!wait_count) {
  91. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  92. ha->host_no, __func__));
  93. return status;
  94. }
  95. msleep(10);
  96. }
  97. if (is_qla8022(ha)) {
  98. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  99. DEBUG2(ql4_printk(KERN_WARNING, ha,
  100. "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
  101. ha->host_no, __func__));
  102. goto mbox_exit;
  103. }
  104. /* Do not send any mbx cmd if h/w is in failed state*/
  105. ha->isp_ops->idc_lock(ha);
  106. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  107. ha->isp_ops->idc_unlock(ha);
  108. if (dev_state == QLA8XXX_DEV_FAILED) {
  109. ql4_printk(KERN_WARNING, ha,
  110. "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
  111. ha->host_no, __func__);
  112. goto mbox_exit;
  113. }
  114. }
  115. spin_lock_irqsave(&ha->hardware_lock, flags);
  116. ha->mbox_status_count = outCount;
  117. for (i = 0; i < outCount; i++)
  118. ha->mbox_status[i] = 0;
  119. /* Queue the mailbox command to the firmware */
  120. ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
  121. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  122. /* Wait for completion */
  123. /*
  124. * If we don't want status, don't wait for the mailbox command to
  125. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  126. * you must poll the inbound Interrupt Mask for completion.
  127. */
  128. if (outCount == 0) {
  129. status = QLA_SUCCESS;
  130. goto mbox_exit;
  131. }
  132. /*
  133. * Wait for completion: Poll or completion queue
  134. */
  135. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  136. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  137. test_bit(AF_ONLINE, &ha->flags) &&
  138. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  139. /* Do not poll for completion. Use completion queue */
  140. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  141. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  142. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  143. } else {
  144. /* Poll for command to complete */
  145. wait_count = jiffies + MBOX_TOV * HZ;
  146. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  147. if (time_after_eq(jiffies, wait_count))
  148. break;
  149. /*
  150. * Service the interrupt.
  151. * The ISR will save the mailbox status registers
  152. * to a temporary storage location in the adapter
  153. * structure.
  154. */
  155. spin_lock_irqsave(&ha->hardware_lock, flags);
  156. ha->isp_ops->process_mailbox_interrupt(ha, outCount);
  157. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  158. msleep(10);
  159. }
  160. }
  161. /* Check for mailbox timeout. */
  162. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  163. if (is_qla8022(ha) &&
  164. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  165. DEBUG2(ql4_printk(KERN_INFO, ha,
  166. "scsi%ld: %s: prematurely completing mbx cmd as "
  167. "firmware recovery detected\n",
  168. ha->host_no, __func__));
  169. goto mbox_exit;
  170. }
  171. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  172. " Scheduling Adapter Reset\n", ha->host_no,
  173. mbx_cmd[0]));
  174. ha->mailbox_timeout_count++;
  175. mbx_sts[0] = (-1);
  176. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  177. if (is_qla8022(ha)) {
  178. ql4_printk(KERN_INFO, ha,
  179. "disabling pause transmit on port 0 & 1.\n");
  180. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
  181. CRB_NIU_XG_PAUSE_CTL_P0 |
  182. CRB_NIU_XG_PAUSE_CTL_P1);
  183. }
  184. goto mbox_exit;
  185. }
  186. /*
  187. * Copy the mailbox out registers to the caller's mailbox in/out
  188. * structure.
  189. */
  190. spin_lock_irqsave(&ha->hardware_lock, flags);
  191. for (i = 0; i < outCount; i++)
  192. mbx_sts[i] = ha->mbox_status[i];
  193. /* Set return status and error flags (if applicable). */
  194. switch (ha->mbox_status[0]) {
  195. case MBOX_STS_COMMAND_COMPLETE:
  196. status = QLA_SUCCESS;
  197. break;
  198. case MBOX_STS_INTERMEDIATE_COMPLETION:
  199. status = QLA_SUCCESS;
  200. break;
  201. case MBOX_STS_BUSY:
  202. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  203. ha->host_no, __func__, mbx_cmd[0]));
  204. ha->mailbox_timeout_count++;
  205. break;
  206. default:
  207. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  208. "sts = %08X ****\n", ha->host_no, __func__,
  209. mbx_cmd[0], mbx_sts[0]));
  210. break;
  211. }
  212. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  213. mbox_exit:
  214. mutex_lock(&ha->mbox_sem);
  215. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  216. mutex_unlock(&ha->mbox_sem);
  217. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  218. return status;
  219. }
  220. /**
  221. * qla4xxx_get_minidump_template - Get the firmware template
  222. * @ha: Pointer to host adapter structure.
  223. * @phys_addr: dma address for template
  224. *
  225. * Obtain the minidump template from firmware during initialization
  226. * as it may not be available when minidump is desired.
  227. **/
  228. int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
  229. dma_addr_t phys_addr)
  230. {
  231. uint32_t mbox_cmd[MBOX_REG_COUNT];
  232. uint32_t mbox_sts[MBOX_REG_COUNT];
  233. int status;
  234. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  235. memset(&mbox_sts, 0, sizeof(mbox_sts));
  236. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  237. mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
  238. mbox_cmd[2] = LSDW(phys_addr);
  239. mbox_cmd[3] = MSDW(phys_addr);
  240. mbox_cmd[4] = ha->fw_dump_tmplt_size;
  241. mbox_cmd[5] = 0;
  242. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  243. &mbox_sts[0]);
  244. if (status != QLA_SUCCESS) {
  245. DEBUG2(ql4_printk(KERN_INFO, ha,
  246. "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
  247. ha->host_no, __func__, mbox_cmd[0],
  248. mbox_sts[0], mbox_sts[1]));
  249. }
  250. return status;
  251. }
  252. /**
  253. * qla4xxx_req_template_size - Get minidump template size from firmware.
  254. * @ha: Pointer to host adapter structure.
  255. **/
  256. int qla4xxx_req_template_size(struct scsi_qla_host *ha)
  257. {
  258. uint32_t mbox_cmd[MBOX_REG_COUNT];
  259. uint32_t mbox_sts[MBOX_REG_COUNT];
  260. int status;
  261. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  262. memset(&mbox_sts, 0, sizeof(mbox_sts));
  263. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  264. mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
  265. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
  266. &mbox_sts[0]);
  267. if (status == QLA_SUCCESS) {
  268. ha->fw_dump_tmplt_size = mbox_sts[1];
  269. DEBUG2(ql4_printk(KERN_INFO, ha,
  270. "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
  271. __func__, mbox_sts[0], mbox_sts[1],
  272. mbox_sts[2], mbox_sts[3], mbox_sts[4],
  273. mbox_sts[5], mbox_sts[6], mbox_sts[7]));
  274. if (ha->fw_dump_tmplt_size == 0)
  275. status = QLA_ERROR;
  276. } else {
  277. ql4_printk(KERN_WARNING, ha,
  278. "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
  279. __func__, mbox_sts[0], mbox_sts[1]);
  280. status = QLA_ERROR;
  281. }
  282. return status;
  283. }
  284. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  285. {
  286. set_bit(AF_FW_RECOVERY, &ha->flags);
  287. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  288. ha->host_no, __func__);
  289. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  290. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  291. complete(&ha->mbx_intr_comp);
  292. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  293. "recovery, doing premature completion of "
  294. "mbx cmd\n", ha->host_no, __func__);
  295. } else {
  296. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  297. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  298. "recovery, doing premature completion of "
  299. "polling mbx cmd\n", ha->host_no, __func__);
  300. }
  301. }
  302. }
  303. static uint8_t
  304. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  305. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  306. {
  307. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  308. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  309. if (is_qla8022(ha))
  310. qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  311. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  312. mbox_cmd[1] = 0;
  313. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  314. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  315. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  316. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  317. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  318. QLA_SUCCESS) {
  319. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  320. "MBOX_CMD_INITIALIZE_FIRMWARE"
  321. " failed w/ status %04X\n",
  322. ha->host_no, __func__, mbox_sts[0]));
  323. return QLA_ERROR;
  324. }
  325. return QLA_SUCCESS;
  326. }
  327. uint8_t
  328. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  329. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  330. {
  331. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  332. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  333. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  334. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  335. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  336. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  337. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  338. QLA_SUCCESS) {
  339. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  340. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  341. " failed w/ status %04X\n",
  342. ha->host_no, __func__, mbox_sts[0]));
  343. return QLA_ERROR;
  344. }
  345. return QLA_SUCCESS;
  346. }
  347. static void
  348. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  349. struct addr_ctrl_blk *init_fw_cb)
  350. {
  351. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  352. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  353. ha->ip_config.ipv4_addr_state =
  354. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  355. ha->ip_config.eth_mtu_size =
  356. le16_to_cpu(init_fw_cb->eth_mtu_size);
  357. ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
  358. if (ha->acb_version == ACB_SUPPORTED) {
  359. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  360. ha->ip_config.ipv6_addl_options =
  361. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  362. }
  363. /* Save IPv4 Address Info */
  364. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  365. min(sizeof(ha->ip_config.ip_address),
  366. sizeof(init_fw_cb->ipv4_addr)));
  367. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  368. min(sizeof(ha->ip_config.subnet_mask),
  369. sizeof(init_fw_cb->ipv4_subnet)));
  370. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  371. min(sizeof(ha->ip_config.gateway),
  372. sizeof(init_fw_cb->ipv4_gw_addr)));
  373. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  374. if (is_ipv6_enabled(ha)) {
  375. /* Save IPv6 Address */
  376. ha->ip_config.ipv6_link_local_state =
  377. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  378. ha->ip_config.ipv6_addr0_state =
  379. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  380. ha->ip_config.ipv6_addr1_state =
  381. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  382. ha->ip_config.ipv6_default_router_state =
  383. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  384. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  385. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  386. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  387. init_fw_cb->ipv6_if_id,
  388. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  389. sizeof(init_fw_cb->ipv6_if_id)));
  390. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  391. min(sizeof(ha->ip_config.ipv6_addr0),
  392. sizeof(init_fw_cb->ipv6_addr0)));
  393. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  394. min(sizeof(ha->ip_config.ipv6_addr1),
  395. sizeof(init_fw_cb->ipv6_addr1)));
  396. memcpy(&ha->ip_config.ipv6_default_router_addr,
  397. init_fw_cb->ipv6_dflt_rtr_addr,
  398. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  399. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  400. ha->ip_config.ipv6_vlan_tag =
  401. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  402. ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
  403. }
  404. }
  405. uint8_t
  406. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  407. uint32_t *mbox_cmd,
  408. uint32_t *mbox_sts,
  409. struct addr_ctrl_blk *init_fw_cb,
  410. dma_addr_t init_fw_cb_dma)
  411. {
  412. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  413. != QLA_SUCCESS) {
  414. DEBUG2(printk(KERN_WARNING
  415. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  416. ha->host_no, __func__));
  417. return QLA_ERROR;
  418. }
  419. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  420. /* Save some info in adapter structure. */
  421. ha->acb_version = init_fw_cb->acb_version;
  422. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  423. ha->heartbeat_interval = init_fw_cb->hb_interval;
  424. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  425. min(sizeof(ha->name_string),
  426. sizeof(init_fw_cb->iscsi_name)));
  427. ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
  428. /*memcpy(ha->alias, init_fw_cb->Alias,
  429. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  430. qla4xxx_update_local_ip(ha, init_fw_cb);
  431. return QLA_SUCCESS;
  432. }
  433. /**
  434. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  435. * @ha: Pointer to host adapter structure.
  436. **/
  437. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  438. {
  439. struct addr_ctrl_blk *init_fw_cb;
  440. dma_addr_t init_fw_cb_dma;
  441. uint32_t mbox_cmd[MBOX_REG_COUNT];
  442. uint32_t mbox_sts[MBOX_REG_COUNT];
  443. int status = QLA_ERROR;
  444. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  445. sizeof(struct addr_ctrl_blk),
  446. &init_fw_cb_dma, GFP_KERNEL);
  447. if (init_fw_cb == NULL) {
  448. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  449. ha->host_no, __func__));
  450. goto exit_init_fw_cb_no_free;
  451. }
  452. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  453. /* Get Initialize Firmware Control Block. */
  454. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  455. memset(&mbox_sts, 0, sizeof(mbox_sts));
  456. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  457. QLA_SUCCESS) {
  458. dma_free_coherent(&ha->pdev->dev,
  459. sizeof(struct addr_ctrl_blk),
  460. init_fw_cb, init_fw_cb_dma);
  461. goto exit_init_fw_cb;
  462. }
  463. /* Initialize request and response queues. */
  464. qla4xxx_init_rings(ha);
  465. /* Fill in the request and response queue information. */
  466. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  467. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  468. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  469. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  470. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  471. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  472. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  473. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  474. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  475. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  476. /* Set up required options. */
  477. init_fw_cb->fw_options |=
  478. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  479. FWOPT_INITIATOR_MODE);
  480. if (is_qla8022(ha))
  481. init_fw_cb->fw_options |=
  482. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  483. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  484. init_fw_cb->add_fw_options = 0;
  485. init_fw_cb->add_fw_options |=
  486. __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
  487. init_fw_cb->add_fw_options |=
  488. __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
  489. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  490. != QLA_SUCCESS) {
  491. DEBUG2(printk(KERN_WARNING
  492. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  493. ha->host_no, __func__));
  494. goto exit_init_fw_cb;
  495. }
  496. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  497. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  498. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  499. ha->host_no, __func__));
  500. goto exit_init_fw_cb;
  501. }
  502. status = QLA_SUCCESS;
  503. exit_init_fw_cb:
  504. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  505. init_fw_cb, init_fw_cb_dma);
  506. exit_init_fw_cb_no_free:
  507. return status;
  508. }
  509. /**
  510. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  511. * @ha: Pointer to host adapter structure.
  512. **/
  513. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  514. {
  515. struct addr_ctrl_blk *init_fw_cb;
  516. dma_addr_t init_fw_cb_dma;
  517. uint32_t mbox_cmd[MBOX_REG_COUNT];
  518. uint32_t mbox_sts[MBOX_REG_COUNT];
  519. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  520. sizeof(struct addr_ctrl_blk),
  521. &init_fw_cb_dma, GFP_KERNEL);
  522. if (init_fw_cb == NULL) {
  523. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  524. __func__);
  525. return QLA_ERROR;
  526. }
  527. /* Get Initialize Firmware Control Block. */
  528. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  529. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  530. QLA_SUCCESS) {
  531. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  532. ha->host_no, __func__));
  533. dma_free_coherent(&ha->pdev->dev,
  534. sizeof(struct addr_ctrl_blk),
  535. init_fw_cb, init_fw_cb_dma);
  536. return QLA_ERROR;
  537. }
  538. /* Save IP Address. */
  539. qla4xxx_update_local_ip(ha, init_fw_cb);
  540. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  541. init_fw_cb, init_fw_cb_dma);
  542. return QLA_SUCCESS;
  543. }
  544. /**
  545. * qla4xxx_get_firmware_state - gets firmware state of HBA
  546. * @ha: Pointer to host adapter structure.
  547. **/
  548. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  549. {
  550. uint32_t mbox_cmd[MBOX_REG_COUNT];
  551. uint32_t mbox_sts[MBOX_REG_COUNT];
  552. /* Get firmware version */
  553. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  554. memset(&mbox_sts, 0, sizeof(mbox_sts));
  555. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  556. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  557. QLA_SUCCESS) {
  558. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  559. "status %04X\n", ha->host_no, __func__,
  560. mbox_sts[0]));
  561. return QLA_ERROR;
  562. }
  563. ha->firmware_state = mbox_sts[1];
  564. ha->board_id = mbox_sts[2];
  565. ha->addl_fw_state = mbox_sts[3];
  566. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  567. ha->host_no, __func__, ha->firmware_state);)
  568. return QLA_SUCCESS;
  569. }
  570. /**
  571. * qla4xxx_get_firmware_status - retrieves firmware status
  572. * @ha: Pointer to host adapter structure.
  573. **/
  574. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  575. {
  576. uint32_t mbox_cmd[MBOX_REG_COUNT];
  577. uint32_t mbox_sts[MBOX_REG_COUNT];
  578. /* Get firmware version */
  579. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  580. memset(&mbox_sts, 0, sizeof(mbox_sts));
  581. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  582. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  583. QLA_SUCCESS) {
  584. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  585. "status %04X\n", ha->host_no, __func__,
  586. mbox_sts[0]));
  587. return QLA_ERROR;
  588. }
  589. ql4_printk(KERN_INFO, ha, "%ld firmware IOCBs available (%d).\n",
  590. ha->host_no, mbox_sts[2]);
  591. return QLA_SUCCESS;
  592. }
  593. /**
  594. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  595. * @ha: Pointer to host adapter structure.
  596. * @fw_ddb_index: Firmware's device database index
  597. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  598. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  599. * @next_ddb_index: Pointer to next valid device database index
  600. * @fw_ddb_device_state: Pointer to device state
  601. **/
  602. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  603. uint16_t fw_ddb_index,
  604. struct dev_db_entry *fw_ddb_entry,
  605. dma_addr_t fw_ddb_entry_dma,
  606. uint32_t *num_valid_ddb_entries,
  607. uint32_t *next_ddb_index,
  608. uint32_t *fw_ddb_device_state,
  609. uint32_t *conn_err_detail,
  610. uint16_t *tcp_source_port_num,
  611. uint16_t *connection_id)
  612. {
  613. int status = QLA_ERROR;
  614. uint16_t options;
  615. uint32_t mbox_cmd[MBOX_REG_COUNT];
  616. uint32_t mbox_sts[MBOX_REG_COUNT];
  617. /* Make sure the device index is valid */
  618. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  619. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  620. ha->host_no, __func__, fw_ddb_index));
  621. goto exit_get_fwddb;
  622. }
  623. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  624. memset(&mbox_sts, 0, sizeof(mbox_sts));
  625. if (fw_ddb_entry)
  626. memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
  627. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  628. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  629. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  630. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  631. mbox_cmd[4] = sizeof(struct dev_db_entry);
  632. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  633. QLA_ERROR) {
  634. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  635. " with status 0x%04X\n", ha->host_no, __func__,
  636. mbox_sts[0]));
  637. goto exit_get_fwddb;
  638. }
  639. if (fw_ddb_index != mbox_sts[1]) {
  640. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  641. ha->host_no, __func__, fw_ddb_index,
  642. mbox_sts[1]));
  643. goto exit_get_fwddb;
  644. }
  645. if (fw_ddb_entry) {
  646. options = le16_to_cpu(fw_ddb_entry->options);
  647. if (options & DDB_OPT_IPV6_DEVICE) {
  648. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  649. "Next %d State %04x ConnErr %08x %pI6 "
  650. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  651. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  652. mbox_sts[4], mbox_sts[5],
  653. fw_ddb_entry->ip_addr,
  654. le16_to_cpu(fw_ddb_entry->port),
  655. fw_ddb_entry->iscsi_name);
  656. } else {
  657. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  658. "Next %d State %04x ConnErr %08x %pI4 "
  659. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  660. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  661. mbox_sts[4], mbox_sts[5],
  662. fw_ddb_entry->ip_addr,
  663. le16_to_cpu(fw_ddb_entry->port),
  664. fw_ddb_entry->iscsi_name);
  665. }
  666. }
  667. if (num_valid_ddb_entries)
  668. *num_valid_ddb_entries = mbox_sts[2];
  669. if (next_ddb_index)
  670. *next_ddb_index = mbox_sts[3];
  671. if (fw_ddb_device_state)
  672. *fw_ddb_device_state = mbox_sts[4];
  673. /*
  674. * RA: This mailbox has been changed to pass connection error and
  675. * details. Its true for ISP4010 as per Version E - Not sure when it
  676. * was changed. Get the time2wait from the fw_dd_entry field :
  677. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  678. * struct.
  679. */
  680. if (conn_err_detail)
  681. *conn_err_detail = mbox_sts[5];
  682. if (tcp_source_port_num)
  683. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  684. if (connection_id)
  685. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  686. status = QLA_SUCCESS;
  687. exit_get_fwddb:
  688. return status;
  689. }
  690. int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
  691. {
  692. uint32_t mbox_cmd[MBOX_REG_COUNT];
  693. uint32_t mbox_sts[MBOX_REG_COUNT];
  694. int status;
  695. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  696. memset(&mbox_sts, 0, sizeof(mbox_sts));
  697. mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
  698. mbox_cmd[1] = fw_ddb_index;
  699. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  700. &mbox_sts[0]);
  701. DEBUG2(ql4_printk(KERN_INFO, ha,
  702. "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
  703. __func__, status, mbox_sts[0], mbox_sts[1]));
  704. return status;
  705. }
  706. /**
  707. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  708. * @ha: Pointer to host adapter structure.
  709. * @fw_ddb_index: Firmware's device database index
  710. * @fw_ddb_entry_dma: dma address of ddb entry
  711. * @mbx_sts: mailbox 0 to be returned or NULL
  712. *
  713. * This routine initializes or updates the adapter's device database
  714. * entry for the specified device.
  715. **/
  716. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  717. dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
  718. {
  719. uint32_t mbox_cmd[MBOX_REG_COUNT];
  720. uint32_t mbox_sts[MBOX_REG_COUNT];
  721. int status;
  722. /* Do not wait for completion. The firmware will send us an
  723. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  724. */
  725. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  726. memset(&mbox_sts, 0, sizeof(mbox_sts));
  727. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  728. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  729. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  730. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  731. mbox_cmd[4] = sizeof(struct dev_db_entry);
  732. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  733. &mbox_sts[0]);
  734. if (mbx_sts)
  735. *mbx_sts = mbox_sts[0];
  736. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  737. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  738. return status;
  739. }
  740. int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
  741. struct ddb_entry *ddb_entry, int options)
  742. {
  743. int status;
  744. uint32_t mbox_cmd[MBOX_REG_COUNT];
  745. uint32_t mbox_sts[MBOX_REG_COUNT];
  746. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  747. memset(&mbox_sts, 0, sizeof(mbox_sts));
  748. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  749. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  750. mbox_cmd[3] = options;
  751. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  752. &mbox_sts[0]);
  753. if (status != QLA_SUCCESS) {
  754. DEBUG2(ql4_printk(KERN_INFO, ha,
  755. "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
  756. "failed sts %04X %04X", __func__,
  757. mbox_sts[0], mbox_sts[1]));
  758. }
  759. return status;
  760. }
  761. /**
  762. * qla4xxx_get_crash_record - retrieves crash record.
  763. * @ha: Pointer to host adapter structure.
  764. *
  765. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  766. **/
  767. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  768. {
  769. uint32_t mbox_cmd[MBOX_REG_COUNT];
  770. uint32_t mbox_sts[MBOX_REG_COUNT];
  771. struct crash_record *crash_record = NULL;
  772. dma_addr_t crash_record_dma = 0;
  773. uint32_t crash_record_size = 0;
  774. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  775. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  776. /* Get size of crash record. */
  777. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  778. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  779. QLA_SUCCESS) {
  780. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  781. ha->host_no, __func__));
  782. goto exit_get_crash_record;
  783. }
  784. crash_record_size = mbox_sts[4];
  785. if (crash_record_size == 0) {
  786. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  787. ha->host_no, __func__));
  788. goto exit_get_crash_record;
  789. }
  790. /* Alloc Memory for Crash Record. */
  791. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  792. &crash_record_dma, GFP_KERNEL);
  793. if (crash_record == NULL)
  794. goto exit_get_crash_record;
  795. /* Get Crash Record. */
  796. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  797. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  798. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  799. mbox_cmd[2] = LSDW(crash_record_dma);
  800. mbox_cmd[3] = MSDW(crash_record_dma);
  801. mbox_cmd[4] = crash_record_size;
  802. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  803. QLA_SUCCESS)
  804. goto exit_get_crash_record;
  805. /* Dump Crash Record. */
  806. exit_get_crash_record:
  807. if (crash_record)
  808. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  809. crash_record, crash_record_dma);
  810. }
  811. /**
  812. * qla4xxx_get_conn_event_log - retrieves connection event log
  813. * @ha: Pointer to host adapter structure.
  814. **/
  815. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  816. {
  817. uint32_t mbox_cmd[MBOX_REG_COUNT];
  818. uint32_t mbox_sts[MBOX_REG_COUNT];
  819. struct conn_event_log_entry *event_log = NULL;
  820. dma_addr_t event_log_dma = 0;
  821. uint32_t event_log_size = 0;
  822. uint32_t num_valid_entries;
  823. uint32_t oldest_entry = 0;
  824. uint32_t max_event_log_entries;
  825. uint8_t i;
  826. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  827. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  828. /* Get size of crash record. */
  829. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  830. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  831. QLA_SUCCESS)
  832. goto exit_get_event_log;
  833. event_log_size = mbox_sts[4];
  834. if (event_log_size == 0)
  835. goto exit_get_event_log;
  836. /* Alloc Memory for Crash Record. */
  837. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  838. &event_log_dma, GFP_KERNEL);
  839. if (event_log == NULL)
  840. goto exit_get_event_log;
  841. /* Get Crash Record. */
  842. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  843. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  844. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  845. mbox_cmd[2] = LSDW(event_log_dma);
  846. mbox_cmd[3] = MSDW(event_log_dma);
  847. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  848. QLA_SUCCESS) {
  849. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  850. "log!\n", ha->host_no, __func__));
  851. goto exit_get_event_log;
  852. }
  853. /* Dump Event Log. */
  854. num_valid_entries = mbox_sts[1];
  855. max_event_log_entries = event_log_size /
  856. sizeof(struct conn_event_log_entry);
  857. if (num_valid_entries > max_event_log_entries)
  858. oldest_entry = num_valid_entries % max_event_log_entries;
  859. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  860. ha->host_no, num_valid_entries));
  861. if (ql4xextended_error_logging == 3) {
  862. if (oldest_entry == 0) {
  863. /* Circular Buffer has not wrapped around */
  864. for (i=0; i < num_valid_entries; i++) {
  865. qla4xxx_dump_buffer((uint8_t *)event_log+
  866. (i*sizeof(*event_log)),
  867. sizeof(*event_log));
  868. }
  869. }
  870. else {
  871. /* Circular Buffer has wrapped around -
  872. * display accordingly*/
  873. for (i=oldest_entry; i < max_event_log_entries; i++) {
  874. qla4xxx_dump_buffer((uint8_t *)event_log+
  875. (i*sizeof(*event_log)),
  876. sizeof(*event_log));
  877. }
  878. for (i=0; i < oldest_entry; i++) {
  879. qla4xxx_dump_buffer((uint8_t *)event_log+
  880. (i*sizeof(*event_log)),
  881. sizeof(*event_log));
  882. }
  883. }
  884. }
  885. exit_get_event_log:
  886. if (event_log)
  887. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  888. event_log_dma);
  889. }
  890. /**
  891. * qla4xxx_abort_task - issues Abort Task
  892. * @ha: Pointer to host adapter structure.
  893. * @srb: Pointer to srb entry
  894. *
  895. * This routine performs a LUN RESET on the specified target/lun.
  896. * The caller must ensure that the ddb_entry and lun_entry pointers
  897. * are valid before calling this routine.
  898. **/
  899. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  900. {
  901. uint32_t mbox_cmd[MBOX_REG_COUNT];
  902. uint32_t mbox_sts[MBOX_REG_COUNT];
  903. struct scsi_cmnd *cmd = srb->cmd;
  904. int status = QLA_SUCCESS;
  905. unsigned long flags = 0;
  906. uint32_t index;
  907. /*
  908. * Send abort task command to ISP, so that the ISP will return
  909. * request with ABORT status
  910. */
  911. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  912. memset(&mbox_sts, 0, sizeof(mbox_sts));
  913. spin_lock_irqsave(&ha->hardware_lock, flags);
  914. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  915. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  916. /* Firmware already posted completion on response queue */
  917. if (index == MAX_SRBS)
  918. return status;
  919. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  920. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  921. mbox_cmd[2] = index;
  922. /* Immediate Command Enable */
  923. mbox_cmd[5] = 0x01;
  924. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  925. &mbox_sts[0]);
  926. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  927. status = QLA_ERROR;
  928. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  929. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  930. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  931. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  932. }
  933. return status;
  934. }
  935. /**
  936. * qla4xxx_reset_lun - issues LUN Reset
  937. * @ha: Pointer to host adapter structure.
  938. * @ddb_entry: Pointer to device database entry
  939. * @lun: lun number
  940. *
  941. * This routine performs a LUN RESET on the specified target/lun.
  942. * The caller must ensure that the ddb_entry and lun_entry pointers
  943. * are valid before calling this routine.
  944. **/
  945. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  946. int lun)
  947. {
  948. uint32_t mbox_cmd[MBOX_REG_COUNT];
  949. uint32_t mbox_sts[MBOX_REG_COUNT];
  950. int status = QLA_SUCCESS;
  951. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  952. ddb_entry->fw_ddb_index, lun));
  953. /*
  954. * Send lun reset command to ISP, so that the ISP will return all
  955. * outstanding requests with RESET status
  956. */
  957. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  958. memset(&mbox_sts, 0, sizeof(mbox_sts));
  959. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  960. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  961. mbox_cmd[2] = lun << 8;
  962. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  963. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  964. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  965. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  966. status = QLA_ERROR;
  967. return status;
  968. }
  969. /**
  970. * qla4xxx_reset_target - issues target Reset
  971. * @ha: Pointer to host adapter structure.
  972. * @db_entry: Pointer to device database entry
  973. * @un_entry: Pointer to lun entry structure
  974. *
  975. * This routine performs a TARGET RESET on the specified target.
  976. * The caller must ensure that the ddb_entry pointers
  977. * are valid before calling this routine.
  978. **/
  979. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  980. struct ddb_entry *ddb_entry)
  981. {
  982. uint32_t mbox_cmd[MBOX_REG_COUNT];
  983. uint32_t mbox_sts[MBOX_REG_COUNT];
  984. int status = QLA_SUCCESS;
  985. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  986. ddb_entry->fw_ddb_index));
  987. /*
  988. * Send target reset command to ISP, so that the ISP will return all
  989. * outstanding requests with RESET status
  990. */
  991. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  992. memset(&mbox_sts, 0, sizeof(mbox_sts));
  993. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  994. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  995. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  996. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  997. &mbox_sts[0]);
  998. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  999. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  1000. status = QLA_ERROR;
  1001. return status;
  1002. }
  1003. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  1004. uint32_t offset, uint32_t len)
  1005. {
  1006. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1007. uint32_t mbox_sts[MBOX_REG_COUNT];
  1008. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1009. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1010. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  1011. mbox_cmd[1] = LSDW(dma_addr);
  1012. mbox_cmd[2] = MSDW(dma_addr);
  1013. mbox_cmd[3] = offset;
  1014. mbox_cmd[4] = len;
  1015. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  1016. QLA_SUCCESS) {
  1017. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  1018. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  1019. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  1020. return QLA_ERROR;
  1021. }
  1022. return QLA_SUCCESS;
  1023. }
  1024. /**
  1025. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  1026. * @ha: Pointer to host adapter structure.
  1027. *
  1028. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  1029. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  1030. * those mailboxes, if unused.
  1031. **/
  1032. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  1033. {
  1034. struct about_fw_info *about_fw = NULL;
  1035. dma_addr_t about_fw_dma;
  1036. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1037. uint32_t mbox_sts[MBOX_REG_COUNT];
  1038. int status = QLA_ERROR;
  1039. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  1040. sizeof(struct about_fw_info),
  1041. &about_fw_dma, GFP_KERNEL);
  1042. if (!about_fw) {
  1043. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  1044. "for about_fw\n", __func__));
  1045. return status;
  1046. }
  1047. memset(about_fw, 0, sizeof(struct about_fw_info));
  1048. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1049. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1050. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  1051. mbox_cmd[2] = LSDW(about_fw_dma);
  1052. mbox_cmd[3] = MSDW(about_fw_dma);
  1053. mbox_cmd[4] = sizeof(struct about_fw_info);
  1054. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1055. &mbox_cmd[0], &mbox_sts[0]);
  1056. if (status != QLA_SUCCESS) {
  1057. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  1058. "failed w/ status %04X\n", __func__,
  1059. mbox_sts[0]));
  1060. goto exit_about_fw;
  1061. }
  1062. /* Save version information. */
  1063. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  1064. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  1065. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  1066. ha->build_number = le16_to_cpu(about_fw->fw_build);
  1067. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  1068. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  1069. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  1070. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  1071. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  1072. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  1073. status = QLA_SUCCESS;
  1074. exit_about_fw:
  1075. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  1076. about_fw, about_fw_dma);
  1077. return status;
  1078. }
  1079. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
  1080. dma_addr_t dma_addr)
  1081. {
  1082. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1083. uint32_t mbox_sts[MBOX_REG_COUNT];
  1084. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1085. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1086. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  1087. mbox_cmd[1] = options;
  1088. mbox_cmd[2] = LSDW(dma_addr);
  1089. mbox_cmd[3] = MSDW(dma_addr);
  1090. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  1091. QLA_SUCCESS) {
  1092. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1093. ha->host_no, __func__, mbox_sts[0]));
  1094. return QLA_ERROR;
  1095. }
  1096. return QLA_SUCCESS;
  1097. }
  1098. int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
  1099. uint32_t *mbx_sts)
  1100. {
  1101. int status;
  1102. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1103. uint32_t mbox_sts[MBOX_REG_COUNT];
  1104. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1105. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1106. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1107. mbox_cmd[1] = ddb_index;
  1108. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1109. &mbox_sts[0]);
  1110. if (status != QLA_SUCCESS) {
  1111. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1112. __func__, mbox_sts[0]));
  1113. }
  1114. *mbx_sts = mbox_sts[0];
  1115. return status;
  1116. }
  1117. int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
  1118. {
  1119. int status;
  1120. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1121. uint32_t mbox_sts[MBOX_REG_COUNT];
  1122. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1123. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1124. mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
  1125. mbox_cmd[1] = ddb_index;
  1126. status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
  1127. &mbox_sts[0]);
  1128. if (status != QLA_SUCCESS) {
  1129. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1130. __func__, mbox_sts[0]));
  1131. }
  1132. return status;
  1133. }
  1134. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1135. uint32_t offset, uint32_t length, uint32_t options)
  1136. {
  1137. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1138. uint32_t mbox_sts[MBOX_REG_COUNT];
  1139. int status = QLA_SUCCESS;
  1140. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1141. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1142. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1143. mbox_cmd[1] = LSDW(dma_addr);
  1144. mbox_cmd[2] = MSDW(dma_addr);
  1145. mbox_cmd[3] = offset;
  1146. mbox_cmd[4] = length;
  1147. mbox_cmd[5] = options;
  1148. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1149. if (status != QLA_SUCCESS) {
  1150. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1151. "failed w/ status %04X, mbx1 %04X\n",
  1152. __func__, mbox_sts[0], mbox_sts[1]));
  1153. }
  1154. return status;
  1155. }
  1156. int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
  1157. struct dev_db_entry *fw_ddb_entry,
  1158. dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
  1159. {
  1160. uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
  1161. uint32_t dev_db_end_offset;
  1162. int status = QLA_ERROR;
  1163. memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
  1164. dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
  1165. dev_db_end_offset = FLASH_OFFSET_DB_END;
  1166. if (dev_db_start_offset > dev_db_end_offset) {
  1167. DEBUG2(ql4_printk(KERN_ERR, ha,
  1168. "%s:Invalid DDB index %d", __func__,
  1169. ddb_index));
  1170. goto exit_bootdb_failed;
  1171. }
  1172. if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
  1173. sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
  1174. ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
  1175. "failed\n", ha->host_no, __func__);
  1176. goto exit_bootdb_failed;
  1177. }
  1178. if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
  1179. status = QLA_SUCCESS;
  1180. exit_bootdb_failed:
  1181. return status;
  1182. }
  1183. int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
  1184. uint16_t idx)
  1185. {
  1186. int ret = 0;
  1187. int rval = QLA_ERROR;
  1188. uint32_t offset = 0, chap_size;
  1189. struct ql4_chap_table *chap_table;
  1190. dma_addr_t chap_dma;
  1191. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1192. if (chap_table == NULL) {
  1193. ret = -ENOMEM;
  1194. goto exit_get_chap;
  1195. }
  1196. chap_size = sizeof(struct ql4_chap_table);
  1197. memset(chap_table, 0, chap_size);
  1198. if (is_qla40XX(ha))
  1199. offset = FLASH_CHAP_OFFSET | (idx * chap_size);
  1200. else {
  1201. offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
  1202. /* flt_chap_size is CHAP table size for both ports
  1203. * so divide it by 2 to calculate the offset for second port
  1204. */
  1205. if (ha->port_num == 1)
  1206. offset += (ha->hw.flt_chap_size / 2);
  1207. offset += (idx * chap_size);
  1208. }
  1209. rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
  1210. if (rval != QLA_SUCCESS) {
  1211. ret = -EINVAL;
  1212. goto exit_get_chap;
  1213. }
  1214. DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
  1215. __le16_to_cpu(chap_table->cookie)));
  1216. if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
  1217. ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
  1218. goto exit_get_chap;
  1219. }
  1220. strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
  1221. strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
  1222. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1223. exit_get_chap:
  1224. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1225. return ret;
  1226. }
  1227. static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
  1228. char *password, uint16_t idx, int bidi)
  1229. {
  1230. int ret = 0;
  1231. int rval = QLA_ERROR;
  1232. uint32_t offset = 0;
  1233. struct ql4_chap_table *chap_table;
  1234. dma_addr_t chap_dma;
  1235. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1236. if (chap_table == NULL) {
  1237. ret = -ENOMEM;
  1238. goto exit_set_chap;
  1239. }
  1240. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1241. if (bidi)
  1242. chap_table->flags |= BIT_6; /* peer */
  1243. else
  1244. chap_table->flags |= BIT_7; /* local */
  1245. chap_table->secret_len = strlen(password);
  1246. strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
  1247. strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
  1248. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1249. offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
  1250. rval = qla4xxx_set_flash(ha, chap_dma, offset,
  1251. sizeof(struct ql4_chap_table),
  1252. FLASH_OPT_RMW_COMMIT);
  1253. if (rval == QLA_SUCCESS && ha->chap_list) {
  1254. /* Update ha chap_list cache */
  1255. memcpy((struct ql4_chap_table *)ha->chap_list + idx,
  1256. chap_table, sizeof(struct ql4_chap_table));
  1257. }
  1258. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1259. if (rval != QLA_SUCCESS)
  1260. ret = -EINVAL;
  1261. exit_set_chap:
  1262. return ret;
  1263. }
  1264. /**
  1265. * qla4xxx_get_chap_index - Get chap index given username and secret
  1266. * @ha: pointer to adapter structure
  1267. * @username: CHAP username to be searched
  1268. * @password: CHAP password to be searched
  1269. * @bidi: Is this a BIDI CHAP
  1270. * @chap_index: CHAP index to be returned
  1271. *
  1272. * Match the username and password in the chap_list, return the index if a
  1273. * match is found. If a match is not found then add the entry in FLASH and
  1274. * return the index at which entry is written in the FLASH.
  1275. **/
  1276. int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
  1277. char *password, int bidi, uint16_t *chap_index)
  1278. {
  1279. int i, rval;
  1280. int free_index = -1;
  1281. int found_index = 0;
  1282. int max_chap_entries = 0;
  1283. struct ql4_chap_table *chap_table;
  1284. if (is_qla8022(ha))
  1285. max_chap_entries = (ha->hw.flt_chap_size / 2) /
  1286. sizeof(struct ql4_chap_table);
  1287. else
  1288. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1289. if (!ha->chap_list) {
  1290. ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
  1291. return QLA_ERROR;
  1292. }
  1293. if (!username || !password) {
  1294. ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
  1295. return QLA_ERROR;
  1296. }
  1297. mutex_lock(&ha->chap_sem);
  1298. for (i = 0; i < max_chap_entries; i++) {
  1299. chap_table = (struct ql4_chap_table *)ha->chap_list + i;
  1300. if (chap_table->cookie !=
  1301. __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
  1302. if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
  1303. free_index = i;
  1304. continue;
  1305. }
  1306. if (bidi) {
  1307. if (chap_table->flags & BIT_7)
  1308. continue;
  1309. } else {
  1310. if (chap_table->flags & BIT_6)
  1311. continue;
  1312. }
  1313. if (!strncmp(chap_table->secret, password,
  1314. MAX_CHAP_SECRET_LEN) &&
  1315. !strncmp(chap_table->name, username,
  1316. MAX_CHAP_NAME_LEN)) {
  1317. *chap_index = i;
  1318. found_index = 1;
  1319. break;
  1320. }
  1321. }
  1322. /* If chap entry is not present and a free index is available then
  1323. * write the entry in flash
  1324. */
  1325. if (!found_index && free_index != -1) {
  1326. rval = qla4xxx_set_chap(ha, username, password,
  1327. free_index, bidi);
  1328. if (!rval) {
  1329. *chap_index = free_index;
  1330. found_index = 1;
  1331. }
  1332. }
  1333. mutex_unlock(&ha->chap_sem);
  1334. if (found_index)
  1335. return QLA_SUCCESS;
  1336. return QLA_ERROR;
  1337. }
  1338. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1339. uint16_t fw_ddb_index,
  1340. uint16_t connection_id,
  1341. uint16_t option)
  1342. {
  1343. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1344. uint32_t mbox_sts[MBOX_REG_COUNT];
  1345. int status = QLA_SUCCESS;
  1346. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1347. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1348. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1349. mbox_cmd[1] = fw_ddb_index;
  1350. mbox_cmd[2] = connection_id;
  1351. mbox_cmd[3] = option;
  1352. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1353. if (status != QLA_SUCCESS) {
  1354. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1355. "option %04x failed w/ status %04X %04X\n",
  1356. __func__, option, mbox_sts[0], mbox_sts[1]));
  1357. }
  1358. return status;
  1359. }
  1360. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1361. {
  1362. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1363. uint32_t mbox_sts[MBOX_REG_COUNT];
  1364. int status = QLA_SUCCESS;
  1365. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1366. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1367. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1368. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1369. if (status != QLA_SUCCESS) {
  1370. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1371. "failed w/ status %04X %04X %04X", __func__,
  1372. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1373. }
  1374. return status;
  1375. }
  1376. int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
  1377. uint32_t acb_type, uint32_t len)
  1378. {
  1379. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1380. uint32_t mbox_sts[MBOX_REG_COUNT];
  1381. int status = QLA_SUCCESS;
  1382. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1383. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1384. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1385. mbox_cmd[1] = acb_type;
  1386. mbox_cmd[2] = LSDW(acb_dma);
  1387. mbox_cmd[3] = MSDW(acb_dma);
  1388. mbox_cmd[4] = len;
  1389. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1390. if (status != QLA_SUCCESS) {
  1391. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1392. "failed w/ status %04X\n", __func__,
  1393. mbox_sts[0]));
  1394. }
  1395. return status;
  1396. }
  1397. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1398. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1399. {
  1400. int status = QLA_SUCCESS;
  1401. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1402. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1403. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1404. mbox_cmd[1] = 0; /* Primary ACB */
  1405. mbox_cmd[2] = LSDW(acb_dma);
  1406. mbox_cmd[3] = MSDW(acb_dma);
  1407. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1408. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1409. if (status != QLA_SUCCESS) {
  1410. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1411. "failed w/ status %04X\n", __func__,
  1412. mbox_sts[0]));
  1413. }
  1414. return status;
  1415. }
  1416. int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
  1417. struct ddb_entry *ddb_entry,
  1418. struct iscsi_cls_conn *cls_conn,
  1419. uint32_t *mbx_sts)
  1420. {
  1421. struct dev_db_entry *fw_ddb_entry;
  1422. struct iscsi_conn *conn;
  1423. struct iscsi_session *sess;
  1424. struct qla_conn *qla_conn;
  1425. struct sockaddr *dst_addr;
  1426. dma_addr_t fw_ddb_entry_dma;
  1427. int status = QLA_SUCCESS;
  1428. int rval = 0;
  1429. struct sockaddr_in *addr;
  1430. struct sockaddr_in6 *addr6;
  1431. char *ip;
  1432. uint16_t iscsi_opts = 0;
  1433. uint32_t options = 0;
  1434. uint16_t idx, *ptid;
  1435. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1436. &fw_ddb_entry_dma, GFP_KERNEL);
  1437. if (!fw_ddb_entry) {
  1438. DEBUG2(ql4_printk(KERN_ERR, ha,
  1439. "%s: Unable to allocate dma buffer.\n",
  1440. __func__));
  1441. rval = -ENOMEM;
  1442. goto exit_set_param_no_free;
  1443. }
  1444. conn = cls_conn->dd_data;
  1445. qla_conn = conn->dd_data;
  1446. sess = conn->session;
  1447. dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
  1448. if (dst_addr->sa_family == AF_INET6)
  1449. options |= IPV6_DEFAULT_DDB_ENTRY;
  1450. status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1451. if (status == QLA_ERROR) {
  1452. rval = -EINVAL;
  1453. goto exit_set_param;
  1454. }
  1455. ptid = (uint16_t *)&fw_ddb_entry->isid[1];
  1456. *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
  1457. DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n",
  1458. fw_ddb_entry->isid[5], fw_ddb_entry->isid[4],
  1459. fw_ddb_entry->isid[3], fw_ddb_entry->isid[2],
  1460. fw_ddb_entry->isid[1], fw_ddb_entry->isid[0]));
  1461. iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
  1462. memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
  1463. memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
  1464. if (sess->targetname != NULL) {
  1465. memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
  1466. min(strlen(sess->targetname),
  1467. sizeof(fw_ddb_entry->iscsi_name)));
  1468. }
  1469. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1470. memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
  1471. fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
  1472. if (dst_addr->sa_family == AF_INET) {
  1473. addr = (struct sockaddr_in *)dst_addr;
  1474. ip = (char *)&addr->sin_addr;
  1475. memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
  1476. fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
  1477. DEBUG2(ql4_printk(KERN_INFO, ha,
  1478. "%s: Destination Address [%pI4]: index [%d]\n",
  1479. __func__, fw_ddb_entry->ip_addr,
  1480. ddb_entry->fw_ddb_index));
  1481. } else if (dst_addr->sa_family == AF_INET6) {
  1482. addr6 = (struct sockaddr_in6 *)dst_addr;
  1483. ip = (char *)&addr6->sin6_addr;
  1484. memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
  1485. fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
  1486. fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
  1487. DEBUG2(ql4_printk(KERN_INFO, ha,
  1488. "%s: Destination Address [%pI6]: index [%d]\n",
  1489. __func__, fw_ddb_entry->ip_addr,
  1490. ddb_entry->fw_ddb_index));
  1491. } else {
  1492. ql4_printk(KERN_ERR, ha,
  1493. "%s: Failed to get IP Address\n",
  1494. __func__);
  1495. rval = -EINVAL;
  1496. goto exit_set_param;
  1497. }
  1498. /* CHAP */
  1499. if (sess->username != NULL && sess->password != NULL) {
  1500. if (strlen(sess->username) && strlen(sess->password)) {
  1501. iscsi_opts |= BIT_7;
  1502. rval = qla4xxx_get_chap_index(ha, sess->username,
  1503. sess->password,
  1504. LOCAL_CHAP, &idx);
  1505. if (rval)
  1506. goto exit_set_param;
  1507. fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
  1508. }
  1509. }
  1510. if (sess->username_in != NULL && sess->password_in != NULL) {
  1511. /* Check if BIDI CHAP */
  1512. if (strlen(sess->username_in) && strlen(sess->password_in)) {
  1513. iscsi_opts |= BIT_4;
  1514. rval = qla4xxx_get_chap_index(ha, sess->username_in,
  1515. sess->password_in,
  1516. BIDI_CHAP, &idx);
  1517. if (rval)
  1518. goto exit_set_param;
  1519. }
  1520. }
  1521. if (sess->initial_r2t_en)
  1522. iscsi_opts |= BIT_10;
  1523. if (sess->imm_data_en)
  1524. iscsi_opts |= BIT_11;
  1525. fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
  1526. if (conn->max_recv_dlength)
  1527. fw_ddb_entry->iscsi_max_rcv_data_seg_len =
  1528. __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
  1529. if (sess->max_r2t)
  1530. fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
  1531. if (sess->first_burst)
  1532. fw_ddb_entry->iscsi_first_burst_len =
  1533. __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
  1534. if (sess->max_burst)
  1535. fw_ddb_entry->iscsi_max_burst_len =
  1536. __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
  1537. if (sess->time2wait)
  1538. fw_ddb_entry->iscsi_def_time2wait =
  1539. cpu_to_le16(sess->time2wait);
  1540. if (sess->time2retain)
  1541. fw_ddb_entry->iscsi_def_time2retain =
  1542. cpu_to_le16(sess->time2retain);
  1543. status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
  1544. fw_ddb_entry_dma, mbx_sts);
  1545. if (status != QLA_SUCCESS)
  1546. rval = -EINVAL;
  1547. exit_set_param:
  1548. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1549. fw_ddb_entry, fw_ddb_entry_dma);
  1550. exit_set_param_no_free:
  1551. return rval;
  1552. }
  1553. int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
  1554. uint16_t stats_size, dma_addr_t stats_dma)
  1555. {
  1556. int status = QLA_SUCCESS;
  1557. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1558. uint32_t mbox_sts[MBOX_REG_COUNT];
  1559. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1560. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1561. mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
  1562. mbox_cmd[1] = fw_ddb_index;
  1563. mbox_cmd[2] = LSDW(stats_dma);
  1564. mbox_cmd[3] = MSDW(stats_dma);
  1565. mbox_cmd[4] = stats_size;
  1566. status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
  1567. if (status != QLA_SUCCESS) {
  1568. DEBUG2(ql4_printk(KERN_WARNING, ha,
  1569. "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
  1570. "failed w/ status %04X\n", __func__,
  1571. mbox_sts[0]));
  1572. }
  1573. return status;
  1574. }
  1575. int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
  1576. uint32_t ip_idx, uint32_t *sts)
  1577. {
  1578. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1579. uint32_t mbox_sts[MBOX_REG_COUNT];
  1580. int status = QLA_SUCCESS;
  1581. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1582. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1583. mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
  1584. mbox_cmd[1] = acb_idx;
  1585. mbox_cmd[2] = ip_idx;
  1586. status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
  1587. if (status != QLA_SUCCESS) {
  1588. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
  1589. "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
  1590. "status %04X\n", __func__, mbox_sts[0]));
  1591. }
  1592. memcpy(sts, mbox_sts, sizeof(mbox_sts));
  1593. return status;
  1594. }
  1595. int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1596. uint32_t offset, uint32_t size)
  1597. {
  1598. int status = QLA_SUCCESS;
  1599. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1600. uint32_t mbox_sts[MBOX_REG_COUNT];
  1601. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1602. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1603. mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
  1604. mbox_cmd[1] = LSDW(nvram_dma);
  1605. mbox_cmd[2] = MSDW(nvram_dma);
  1606. mbox_cmd[3] = offset;
  1607. mbox_cmd[4] = size;
  1608. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1609. &mbox_sts[0]);
  1610. if (status != QLA_SUCCESS) {
  1611. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1612. "status %04X\n", ha->host_no, __func__,
  1613. mbox_sts[0]));
  1614. }
  1615. return status;
  1616. }
  1617. int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1618. uint32_t offset, uint32_t size)
  1619. {
  1620. int status = QLA_SUCCESS;
  1621. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1622. uint32_t mbox_sts[MBOX_REG_COUNT];
  1623. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1624. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1625. mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
  1626. mbox_cmd[1] = LSDW(nvram_dma);
  1627. mbox_cmd[2] = MSDW(nvram_dma);
  1628. mbox_cmd[3] = offset;
  1629. mbox_cmd[4] = size;
  1630. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1631. &mbox_sts[0]);
  1632. if (status != QLA_SUCCESS) {
  1633. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1634. "status %04X\n", ha->host_no, __func__,
  1635. mbox_sts[0]));
  1636. }
  1637. return status;
  1638. }
  1639. int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
  1640. uint32_t region, uint32_t field0,
  1641. uint32_t field1)
  1642. {
  1643. int status = QLA_SUCCESS;
  1644. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1645. uint32_t mbox_sts[MBOX_REG_COUNT];
  1646. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1647. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1648. mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
  1649. mbox_cmd[3] = region;
  1650. mbox_cmd[4] = field0;
  1651. mbox_cmd[5] = field1;
  1652. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
  1653. &mbox_sts[0]);
  1654. if (status != QLA_SUCCESS) {
  1655. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1656. "status %04X\n", ha->host_no, __func__,
  1657. mbox_sts[0]));
  1658. }
  1659. return status;
  1660. }