pm-debug.c 15 KB

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  1. /*
  2. * OMAP Power Management debug routines
  3. *
  4. * Copyright (C) 2005 Texas Instruments, Inc.
  5. * Copyright (C) 2006-2008 Nokia Corporation
  6. *
  7. * Written by:
  8. * Richard Woodruff <r-woodruff2@ti.com>
  9. * Tony Lindgren
  10. * Juha Yrjola
  11. * Amit Kucheria <amit.kucheria@nokia.com>
  12. * Igor Stoppa <igor.stoppa@nokia.com>
  13. * Jouni Hogander
  14. *
  15. * Based on pm.c for omap2
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License version 2 as
  19. * published by the Free Software Foundation.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/sched.h>
  23. #include <linux/clk.h>
  24. #include <linux/err.h>
  25. #include <linux/io.h>
  26. #include <linux/module.h>
  27. #include <linux/slab.h>
  28. #include <plat/clock.h>
  29. #include <plat/board.h>
  30. #include "powerdomain.h"
  31. #include "clockdomain.h"
  32. #include <plat/omap-pm.h>
  33. #include "cm2xxx_3xxx.h"
  34. #include "prm2xxx_3xxx.h"
  35. #include "pm.h"
  36. int omap2_pm_debug;
  37. u32 enable_off_mode;
  38. u32 sleep_while_idle;
  39. #define DUMP_PRM_MOD_REG(mod, reg) \
  40. regs[reg_count].name = #mod "." #reg; \
  41. regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
  42. #define DUMP_CM_MOD_REG(mod, reg) \
  43. regs[reg_count].name = #mod "." #reg; \
  44. regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
  45. #define DUMP_PRM_REG(reg) \
  46. regs[reg_count].name = #reg; \
  47. regs[reg_count++].val = __raw_readl(reg)
  48. #define DUMP_CM_REG(reg) \
  49. regs[reg_count].name = #reg; \
  50. regs[reg_count++].val = __raw_readl(reg)
  51. #define DUMP_INTC_REG(reg, off) \
  52. regs[reg_count].name = #reg; \
  53. regs[reg_count++].val = \
  54. __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
  55. void omap2_pm_dump(int mode, int resume, unsigned int us)
  56. {
  57. struct reg {
  58. const char *name;
  59. u32 val;
  60. } regs[32];
  61. int reg_count = 0, i;
  62. const char *s1 = NULL, *s2 = NULL;
  63. if (!resume) {
  64. #if 0
  65. /* MPU */
  66. DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
  67. DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
  68. DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
  69. DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
  70. DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
  71. #endif
  72. #if 0
  73. /* INTC */
  74. DUMP_INTC_REG(INTC_MIR0, 0x0084);
  75. DUMP_INTC_REG(INTC_MIR1, 0x00a4);
  76. DUMP_INTC_REG(INTC_MIR2, 0x00c4);
  77. #endif
  78. #if 0
  79. DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
  80. if (cpu_is_omap24xx()) {
  81. DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  82. DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  83. OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
  84. DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
  85. OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
  86. }
  87. DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
  88. DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
  89. DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
  90. DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
  91. DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
  92. DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
  93. DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
  94. #endif
  95. #if 0
  96. /* DSP */
  97. if (cpu_is_omap24xx()) {
  98. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
  99. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
  100. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
  101. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
  102. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
  103. DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
  104. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
  105. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
  106. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
  107. DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
  108. }
  109. #endif
  110. } else {
  111. DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
  112. if (cpu_is_omap24xx())
  113. DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
  114. DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
  115. DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
  116. #if 1
  117. DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
  118. DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
  119. DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
  120. #endif
  121. }
  122. switch (mode) {
  123. case 0:
  124. s1 = "full";
  125. s2 = "retention";
  126. break;
  127. case 1:
  128. s1 = "MPU";
  129. s2 = "retention";
  130. break;
  131. case 2:
  132. s1 = "MPU";
  133. s2 = "idle";
  134. break;
  135. }
  136. if (!resume)
  137. #ifdef CONFIG_NO_HZ
  138. printk(KERN_INFO
  139. "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
  140. jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
  141. jiffies));
  142. #else
  143. printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
  144. #endif
  145. else
  146. printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
  147. us / 1000, us % 1000);
  148. for (i = 0; i < reg_count; i++)
  149. printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
  150. }
  151. #ifdef CONFIG_DEBUG_FS
  152. #include <linux/debugfs.h>
  153. #include <linux/seq_file.h>
  154. static void pm_dbg_regset_store(u32 *ptr);
  155. static struct dentry *pm_dbg_dir;
  156. static int pm_dbg_init_done;
  157. static int __init pm_dbg_init(void);
  158. enum {
  159. DEBUG_FILE_COUNTERS = 0,
  160. DEBUG_FILE_TIMERS,
  161. };
  162. struct pm_module_def {
  163. char name[8]; /* Name of the module */
  164. short type; /* CM or PRM */
  165. unsigned short offset;
  166. int low; /* First register address on this module */
  167. int high; /* Last register address on this module */
  168. };
  169. #define MOD_CM 0
  170. #define MOD_PRM 1
  171. static const struct pm_module_def *pm_dbg_reg_modules;
  172. static const struct pm_module_def omap3_pm_reg_modules[] = {
  173. { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
  174. { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
  175. { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
  176. { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
  177. { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
  178. { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
  179. { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
  180. { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
  181. { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
  182. { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
  183. { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
  184. { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
  185. { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
  186. { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
  187. { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
  188. { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
  189. { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
  190. { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
  191. { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
  192. { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
  193. { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
  194. { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
  195. { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
  196. { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
  197. { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
  198. { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
  199. { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
  200. { "", 0, 0, 0, 0 },
  201. };
  202. #define PM_DBG_MAX_REG_SETS 4
  203. static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
  204. static int pm_dbg_get_regset_size(void)
  205. {
  206. static int regset_size;
  207. if (regset_size == 0) {
  208. int i = 0;
  209. while (pm_dbg_reg_modules[i].name[0] != 0) {
  210. regset_size += pm_dbg_reg_modules[i].high +
  211. 4 - pm_dbg_reg_modules[i].low;
  212. i++;
  213. }
  214. }
  215. return regset_size;
  216. }
  217. static int pm_dbg_show_regs(struct seq_file *s, void *unused)
  218. {
  219. int i, j;
  220. unsigned long val;
  221. int reg_set = (int)s->private;
  222. u32 *ptr;
  223. void *store = NULL;
  224. int regs;
  225. int linefeed;
  226. if (reg_set == 0) {
  227. store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
  228. ptr = store;
  229. pm_dbg_regset_store(ptr);
  230. } else {
  231. ptr = pm_dbg_reg_set[reg_set - 1];
  232. }
  233. i = 0;
  234. while (pm_dbg_reg_modules[i].name[0] != 0) {
  235. regs = 0;
  236. linefeed = 0;
  237. if (pm_dbg_reg_modules[i].type == MOD_CM)
  238. seq_printf(s, "MOD: CM_%s (%08x)\n",
  239. pm_dbg_reg_modules[i].name,
  240. (u32)(OMAP3430_CM_BASE +
  241. pm_dbg_reg_modules[i].offset));
  242. else
  243. seq_printf(s, "MOD: PRM_%s (%08x)\n",
  244. pm_dbg_reg_modules[i].name,
  245. (u32)(OMAP3430_PRM_BASE +
  246. pm_dbg_reg_modules[i].offset));
  247. for (j = pm_dbg_reg_modules[i].low;
  248. j <= pm_dbg_reg_modules[i].high; j += 4) {
  249. val = *(ptr++);
  250. if (val != 0) {
  251. regs++;
  252. if (linefeed) {
  253. seq_printf(s, "\n");
  254. linefeed = 0;
  255. }
  256. seq_printf(s, " %02x => %08lx", j, val);
  257. if (regs % 4 == 0)
  258. linefeed = 1;
  259. }
  260. }
  261. seq_printf(s, "\n");
  262. i++;
  263. }
  264. if (store != NULL)
  265. kfree(store);
  266. return 0;
  267. }
  268. static void pm_dbg_regset_store(u32 *ptr)
  269. {
  270. int i, j;
  271. u32 val;
  272. i = 0;
  273. while (pm_dbg_reg_modules[i].name[0] != 0) {
  274. for (j = pm_dbg_reg_modules[i].low;
  275. j <= pm_dbg_reg_modules[i].high; j += 4) {
  276. if (pm_dbg_reg_modules[i].type == MOD_CM)
  277. val = omap2_cm_read_mod_reg(
  278. pm_dbg_reg_modules[i].offset, j);
  279. else
  280. val = omap2_prm_read_mod_reg(
  281. pm_dbg_reg_modules[i].offset, j);
  282. *(ptr++) = val;
  283. }
  284. i++;
  285. }
  286. }
  287. int pm_dbg_regset_save(int reg_set)
  288. {
  289. if (pm_dbg_reg_set[reg_set-1] == NULL)
  290. return -EINVAL;
  291. pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
  292. return 0;
  293. }
  294. static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
  295. "OFF",
  296. "RET",
  297. "INA",
  298. "ON"
  299. };
  300. void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
  301. {
  302. s64 t;
  303. if (!pm_dbg_init_done)
  304. return ;
  305. /* Update timer for previous state */
  306. t = sched_clock();
  307. pwrdm->state_timer[prev] += t - pwrdm->timer;
  308. pwrdm->timer = t;
  309. }
  310. static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
  311. {
  312. struct seq_file *s = (struct seq_file *)user;
  313. if (strcmp(clkdm->name, "emu_clkdm") == 0 ||
  314. strcmp(clkdm->name, "wkup_clkdm") == 0 ||
  315. strncmp(clkdm->name, "dpll", 4) == 0)
  316. return 0;
  317. seq_printf(s, "%s->%s (%d)", clkdm->name,
  318. clkdm->pwrdm.ptr->name,
  319. atomic_read(&clkdm->usecount));
  320. seq_printf(s, "\n");
  321. return 0;
  322. }
  323. static int pwrdm_dbg_show_counter(struct powerdomain *pwrdm, void *user)
  324. {
  325. struct seq_file *s = (struct seq_file *)user;
  326. int i;
  327. if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
  328. strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
  329. strncmp(pwrdm->name, "dpll", 4) == 0)
  330. return 0;
  331. if (pwrdm->state != pwrdm_read_pwrst(pwrdm))
  332. printk(KERN_ERR "pwrdm state mismatch(%s) %d != %d\n",
  333. pwrdm->name, pwrdm->state, pwrdm_read_pwrst(pwrdm));
  334. seq_printf(s, "%s (%s)", pwrdm->name,
  335. pwrdm_state_names[pwrdm->state]);
  336. for (i = 0; i < PWRDM_MAX_PWRSTS; i++)
  337. seq_printf(s, ",%s:%d", pwrdm_state_names[i],
  338. pwrdm->state_counter[i]);
  339. seq_printf(s, ",RET-LOGIC-OFF:%d", pwrdm->ret_logic_off_counter);
  340. for (i = 0; i < pwrdm->banks; i++)
  341. seq_printf(s, ",RET-MEMBANK%d-OFF:%d", i + 1,
  342. pwrdm->ret_mem_off_counter[i]);
  343. seq_printf(s, "\n");
  344. return 0;
  345. }
  346. static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
  347. {
  348. struct seq_file *s = (struct seq_file *)user;
  349. int i;
  350. if (strcmp(pwrdm->name, "emu_pwrdm") == 0 ||
  351. strcmp(pwrdm->name, "wkup_pwrdm") == 0 ||
  352. strncmp(pwrdm->name, "dpll", 4) == 0)
  353. return 0;
  354. pwrdm_state_switch(pwrdm);
  355. seq_printf(s, "%s (%s)", pwrdm->name,
  356. pwrdm_state_names[pwrdm->state]);
  357. for (i = 0; i < 4; i++)
  358. seq_printf(s, ",%s:%lld", pwrdm_state_names[i],
  359. pwrdm->state_timer[i]);
  360. seq_printf(s, "\n");
  361. return 0;
  362. }
  363. static int pm_dbg_show_counters(struct seq_file *s, void *unused)
  364. {
  365. pwrdm_for_each(pwrdm_dbg_show_counter, s);
  366. clkdm_for_each(clkdm_dbg_show_counter, s);
  367. return 0;
  368. }
  369. static int pm_dbg_show_timers(struct seq_file *s, void *unused)
  370. {
  371. pwrdm_for_each(pwrdm_dbg_show_timer, s);
  372. return 0;
  373. }
  374. static int pm_dbg_open(struct inode *inode, struct file *file)
  375. {
  376. switch ((int)inode->i_private) {
  377. case DEBUG_FILE_COUNTERS:
  378. return single_open(file, pm_dbg_show_counters,
  379. &inode->i_private);
  380. case DEBUG_FILE_TIMERS:
  381. default:
  382. return single_open(file, pm_dbg_show_timers,
  383. &inode->i_private);
  384. };
  385. }
  386. static int pm_dbg_reg_open(struct inode *inode, struct file *file)
  387. {
  388. return single_open(file, pm_dbg_show_regs, inode->i_private);
  389. }
  390. static const struct file_operations debug_fops = {
  391. .open = pm_dbg_open,
  392. .read = seq_read,
  393. .llseek = seq_lseek,
  394. .release = single_release,
  395. };
  396. static const struct file_operations debug_reg_fops = {
  397. .open = pm_dbg_reg_open,
  398. .read = seq_read,
  399. .llseek = seq_lseek,
  400. .release = single_release,
  401. };
  402. int pm_dbg_regset_init(int reg_set)
  403. {
  404. char name[2];
  405. if (!pm_dbg_init_done)
  406. pm_dbg_init();
  407. if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
  408. pm_dbg_reg_set[reg_set-1] != NULL)
  409. return -EINVAL;
  410. pm_dbg_reg_set[reg_set-1] =
  411. kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
  412. if (pm_dbg_reg_set[reg_set-1] == NULL)
  413. return -ENOMEM;
  414. if (pm_dbg_dir != NULL) {
  415. sprintf(name, "%d", reg_set);
  416. (void) debugfs_create_file(name, S_IRUGO,
  417. pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
  418. }
  419. return 0;
  420. }
  421. static int pwrdm_suspend_get(void *data, u64 *val)
  422. {
  423. int ret = -EINVAL;
  424. if (cpu_is_omap34xx())
  425. ret = omap3_pm_get_suspend_state((struct powerdomain *)data);
  426. *val = ret;
  427. if (ret >= 0)
  428. return 0;
  429. return *val;
  430. }
  431. static int pwrdm_suspend_set(void *data, u64 val)
  432. {
  433. if (cpu_is_omap34xx())
  434. return omap3_pm_set_suspend_state(
  435. (struct powerdomain *)data, (int)val);
  436. return -EINVAL;
  437. }
  438. DEFINE_SIMPLE_ATTRIBUTE(pwrdm_suspend_fops, pwrdm_suspend_get,
  439. pwrdm_suspend_set, "%llu\n");
  440. static int __init pwrdms_setup(struct powerdomain *pwrdm, void *dir)
  441. {
  442. int i;
  443. s64 t;
  444. struct dentry *d;
  445. t = sched_clock();
  446. for (i = 0; i < 4; i++)
  447. pwrdm->state_timer[i] = 0;
  448. pwrdm->timer = t;
  449. if (strncmp(pwrdm->name, "dpll", 4) == 0)
  450. return 0;
  451. d = debugfs_create_dir(pwrdm->name, (struct dentry *)dir);
  452. (void) debugfs_create_file("suspend", S_IRUGO|S_IWUSR, d,
  453. (void *)pwrdm, &pwrdm_suspend_fops);
  454. return 0;
  455. }
  456. static int option_get(void *data, u64 *val)
  457. {
  458. u32 *option = data;
  459. *val = *option;
  460. return 0;
  461. }
  462. static int option_set(void *data, u64 val)
  463. {
  464. u32 *option = data;
  465. *option = val;
  466. if (option == &enable_off_mode) {
  467. if (val)
  468. omap_pm_enable_off_mode();
  469. else
  470. omap_pm_disable_off_mode();
  471. if (cpu_is_omap34xx())
  472. omap3_pm_off_mode_enable(val);
  473. }
  474. return 0;
  475. }
  476. DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
  477. static int __init pm_dbg_init(void)
  478. {
  479. int i;
  480. struct dentry *d;
  481. char name[2];
  482. if (pm_dbg_init_done)
  483. return 0;
  484. if (cpu_is_omap34xx())
  485. pm_dbg_reg_modules = omap3_pm_reg_modules;
  486. else {
  487. printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
  488. return -ENODEV;
  489. }
  490. d = debugfs_create_dir("pm_debug", NULL);
  491. if (IS_ERR(d))
  492. return PTR_ERR(d);
  493. (void) debugfs_create_file("count", S_IRUGO,
  494. d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
  495. (void) debugfs_create_file("time", S_IRUGO,
  496. d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
  497. pwrdm_for_each(pwrdms_setup, (void *)d);
  498. pm_dbg_dir = debugfs_create_dir("registers", d);
  499. if (IS_ERR(pm_dbg_dir))
  500. return PTR_ERR(pm_dbg_dir);
  501. (void) debugfs_create_file("current", S_IRUGO,
  502. pm_dbg_dir, (void *)0, &debug_reg_fops);
  503. for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
  504. if (pm_dbg_reg_set[i] != NULL) {
  505. sprintf(name, "%d", i+1);
  506. (void) debugfs_create_file(name, S_IRUGO,
  507. pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
  508. }
  509. (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
  510. &enable_off_mode, &pm_dbg_option_fops);
  511. (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
  512. &sleep_while_idle, &pm_dbg_option_fops);
  513. pm_dbg_init_done = 1;
  514. return 0;
  515. }
  516. arch_initcall(pm_dbg_init);
  517. #endif