imx28.dtsi 26 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076
  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. ethernet0 = &mac0;
  16. ethernet1 = &mac1;
  17. gpio0 = &gpio0;
  18. gpio1 = &gpio1;
  19. gpio2 = &gpio2;
  20. gpio3 = &gpio3;
  21. gpio4 = &gpio4;
  22. saif0 = &saif0;
  23. saif1 = &saif1;
  24. serial0 = &auart0;
  25. serial1 = &auart1;
  26. serial2 = &auart2;
  27. serial3 = &auart3;
  28. serial4 = &auart4;
  29. spi0 = &ssp1;
  30. spi1 = &ssp2;
  31. };
  32. cpus {
  33. #address-cells = <0>;
  34. #size-cells = <0>;
  35. cpu {
  36. compatible = "arm,arm926ej-s";
  37. device_type = "cpu";
  38. };
  39. };
  40. apb@80000000 {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. reg = <0x80000000 0x80000>;
  45. ranges;
  46. apbh@80000000 {
  47. compatible = "simple-bus";
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. reg = <0x80000000 0x3c900>;
  51. ranges;
  52. icoll: interrupt-controller@80000000 {
  53. compatible = "fsl,imx28-icoll", "fsl,icoll";
  54. interrupt-controller;
  55. #interrupt-cells = <1>;
  56. reg = <0x80000000 0x2000>;
  57. };
  58. hsadc: hsadc@80002000 {
  59. reg = <0x80002000 0x2000>;
  60. interrupts = <13>;
  61. dmas = <&dma_apbh 12>;
  62. dma-names = "rx";
  63. status = "disabled";
  64. };
  65. dma_apbh: dma-apbh@80004000 {
  66. compatible = "fsl,imx28-dma-apbh";
  67. reg = <0x80004000 0x2000>;
  68. interrupts = <82 83 84 85
  69. 88 88 88 88
  70. 88 88 88 88
  71. 87 86 0 0>;
  72. interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
  73. "gpmi0", "gmpi1", "gpmi2", "gmpi3",
  74. "gpmi4", "gmpi5", "gpmi6", "gmpi7",
  75. "hsadc", "lcdif", "empty", "empty";
  76. #dma-cells = <1>;
  77. dma-channels = <16>;
  78. clocks = <&clks 25>;
  79. };
  80. perfmon: perfmon@80006000 {
  81. reg = <0x80006000 0x800>;
  82. interrupts = <27>;
  83. status = "disabled";
  84. };
  85. gpmi: gpmi-nand@8000c000 {
  86. compatible = "fsl,imx28-gpmi-nand";
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
  90. reg-names = "gpmi-nand", "bch";
  91. interrupts = <41>;
  92. interrupt-names = "bch";
  93. clocks = <&clks 50>;
  94. clock-names = "gpmi_io";
  95. dmas = <&dma_apbh 4>;
  96. dma-names = "rx-tx";
  97. status = "disabled";
  98. };
  99. ssp0: ssp@80010000 {
  100. #address-cells = <1>;
  101. #size-cells = <0>;
  102. reg = <0x80010000 0x2000>;
  103. interrupts = <96>;
  104. clocks = <&clks 46>;
  105. dmas = <&dma_apbh 0>;
  106. dma-names = "rx-tx";
  107. status = "disabled";
  108. };
  109. ssp1: ssp@80012000 {
  110. #address-cells = <1>;
  111. #size-cells = <0>;
  112. reg = <0x80012000 0x2000>;
  113. interrupts = <97>;
  114. clocks = <&clks 47>;
  115. dmas = <&dma_apbh 1>;
  116. dma-names = "rx-tx";
  117. status = "disabled";
  118. };
  119. ssp2: ssp@80014000 {
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. reg = <0x80014000 0x2000>;
  123. interrupts = <98>;
  124. clocks = <&clks 48>;
  125. dmas = <&dma_apbh 2>;
  126. dma-names = "rx-tx";
  127. status = "disabled";
  128. };
  129. ssp3: ssp@80016000 {
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. reg = <0x80016000 0x2000>;
  133. interrupts = <99>;
  134. clocks = <&clks 49>;
  135. dmas = <&dma_apbh 3>;
  136. dma-names = "rx-tx";
  137. status = "disabled";
  138. };
  139. pinctrl: pinctrl@80018000 {
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. compatible = "fsl,imx28-pinctrl", "simple-bus";
  143. reg = <0x80018000 0x2000>;
  144. gpio0: gpio@0 {
  145. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  146. interrupts = <127>;
  147. gpio-controller;
  148. #gpio-cells = <2>;
  149. interrupt-controller;
  150. #interrupt-cells = <2>;
  151. };
  152. gpio1: gpio@1 {
  153. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  154. interrupts = <126>;
  155. gpio-controller;
  156. #gpio-cells = <2>;
  157. interrupt-controller;
  158. #interrupt-cells = <2>;
  159. };
  160. gpio2: gpio@2 {
  161. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  162. interrupts = <125>;
  163. gpio-controller;
  164. #gpio-cells = <2>;
  165. interrupt-controller;
  166. #interrupt-cells = <2>;
  167. };
  168. gpio3: gpio@3 {
  169. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  170. interrupts = <124>;
  171. gpio-controller;
  172. #gpio-cells = <2>;
  173. interrupt-controller;
  174. #interrupt-cells = <2>;
  175. };
  176. gpio4: gpio@4 {
  177. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  178. interrupts = <123>;
  179. gpio-controller;
  180. #gpio-cells = <2>;
  181. interrupt-controller;
  182. #interrupt-cells = <2>;
  183. };
  184. duart_pins_a: duart@0 {
  185. reg = <0>;
  186. fsl,pinmux-ids = <
  187. 0x3102 /* MX28_PAD_PWM0__DUART_RX */
  188. 0x3112 /* MX28_PAD_PWM1__DUART_TX */
  189. >;
  190. fsl,drive-strength = <0>;
  191. fsl,voltage = <1>;
  192. fsl,pull-up = <0>;
  193. };
  194. duart_pins_b: duart@1 {
  195. reg = <1>;
  196. fsl,pinmux-ids = <
  197. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  198. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  199. >;
  200. fsl,drive-strength = <0>;
  201. fsl,voltage = <1>;
  202. fsl,pull-up = <0>;
  203. };
  204. duart_4pins_a: duart-4pins@0 {
  205. reg = <0>;
  206. fsl,pinmux-ids = <
  207. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  208. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  209. 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
  210. 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
  211. >;
  212. fsl,drive-strength = <0>;
  213. fsl,voltage = <1>;
  214. fsl,pull-up = <0>;
  215. };
  216. gpmi_pins_a: gpmi-nand@0 {
  217. reg = <0>;
  218. fsl,pinmux-ids = <
  219. 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
  220. 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
  221. 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
  222. 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
  223. 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
  224. 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
  225. 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
  226. 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
  227. 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
  228. 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
  229. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  230. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  231. 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
  232. 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
  233. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  234. >;
  235. fsl,drive-strength = <0>;
  236. fsl,voltage = <1>;
  237. fsl,pull-up = <0>;
  238. };
  239. gpmi_status_cfg: gpmi-status-cfg {
  240. fsl,pinmux-ids = <
  241. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  242. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  243. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  244. >;
  245. fsl,drive-strength = <2>;
  246. };
  247. auart0_pins_a: auart0@0 {
  248. reg = <0>;
  249. fsl,pinmux-ids = <
  250. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  251. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  252. 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
  253. 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
  254. >;
  255. fsl,drive-strength = <0>;
  256. fsl,voltage = <1>;
  257. fsl,pull-up = <0>;
  258. };
  259. auart0_2pins_a: auart0-2pins@0 {
  260. reg = <0>;
  261. fsl,pinmux-ids = <
  262. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  263. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  264. >;
  265. fsl,drive-strength = <0>;
  266. fsl,voltage = <1>;
  267. fsl,pull-up = <0>;
  268. };
  269. auart1_pins_a: auart1@0 {
  270. reg = <0>;
  271. fsl,pinmux-ids = <
  272. 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
  273. 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
  274. 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
  275. 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
  276. >;
  277. fsl,drive-strength = <0>;
  278. fsl,voltage = <1>;
  279. fsl,pull-up = <0>;
  280. };
  281. auart1_2pins_a: auart1-2pins@0 {
  282. reg = <0>;
  283. fsl,pinmux-ids = <
  284. 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
  285. 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
  286. >;
  287. fsl,drive-strength = <0>;
  288. fsl,voltage = <1>;
  289. fsl,pull-up = <0>;
  290. };
  291. auart2_2pins_a: auart2-2pins@0 {
  292. reg = <0>;
  293. fsl,pinmux-ids = <
  294. 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
  295. 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
  296. >;
  297. fsl,drive-strength = <0>;
  298. fsl,voltage = <1>;
  299. fsl,pull-up = <0>;
  300. };
  301. auart2_2pins_b: auart2-2pins@1 {
  302. reg = <1>;
  303. fsl,pinmux-ids = <
  304. 0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
  305. 0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
  306. >;
  307. fsl,drive-strength = <0>;
  308. fsl,voltage = <1>;
  309. fsl,pull-up = <0>;
  310. };
  311. auart3_pins_a: auart3@0 {
  312. reg = <0>;
  313. fsl,pinmux-ids = <
  314. 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
  315. 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
  316. 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
  317. 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
  318. >;
  319. fsl,drive-strength = <0>;
  320. fsl,voltage = <1>;
  321. fsl,pull-up = <0>;
  322. };
  323. auart3_2pins_a: auart3-2pins@0 {
  324. reg = <0>;
  325. fsl,pinmux-ids = <
  326. 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
  327. 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
  328. >;
  329. fsl,drive-strength = <0>;
  330. fsl,voltage = <1>;
  331. fsl,pull-up = <0>;
  332. };
  333. auart3_2pins_b: auart3-2pins@1 {
  334. reg = <1>;
  335. fsl,pinmux-ids = <
  336. 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
  337. 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
  338. >;
  339. fsl,drive-strength = <0>;
  340. fsl,voltage = <1>;
  341. fsl,pull-up = <0>;
  342. };
  343. auart4_2pins_a: auart4@0 {
  344. reg = <0>;
  345. fsl,pinmux-ids = <
  346. 0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */
  347. 0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */
  348. >;
  349. fsl,drive-strength = <0>;
  350. fsl,voltage = <1>;
  351. fsl,pull-up = <0>;
  352. };
  353. mac0_pins_a: mac0@0 {
  354. reg = <0>;
  355. fsl,pinmux-ids = <
  356. 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
  357. 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
  358. 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
  359. 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
  360. 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
  361. 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
  362. 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
  363. 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
  364. 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
  365. >;
  366. fsl,drive-strength = <1>;
  367. fsl,voltage = <1>;
  368. fsl,pull-up = <1>;
  369. };
  370. mac1_pins_a: mac1@0 {
  371. reg = <0>;
  372. fsl,pinmux-ids = <
  373. 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
  374. 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
  375. 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
  376. 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
  377. 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
  378. 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
  379. >;
  380. fsl,drive-strength = <1>;
  381. fsl,voltage = <1>;
  382. fsl,pull-up = <1>;
  383. };
  384. mmc0_8bit_pins_a: mmc0-8bit@0 {
  385. reg = <0>;
  386. fsl,pinmux-ids = <
  387. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  388. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  389. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  390. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  391. 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
  392. 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
  393. 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
  394. 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
  395. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  396. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  397. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  398. >;
  399. fsl,drive-strength = <1>;
  400. fsl,voltage = <1>;
  401. fsl,pull-up = <1>;
  402. };
  403. mmc0_4bit_pins_a: mmc0-4bit@0 {
  404. reg = <0>;
  405. fsl,pinmux-ids = <
  406. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  407. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  408. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  409. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  410. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  411. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  412. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  413. >;
  414. fsl,drive-strength = <1>;
  415. fsl,voltage = <1>;
  416. fsl,pull-up = <1>;
  417. };
  418. mmc0_cd_cfg: mmc0-cd-cfg {
  419. fsl,pinmux-ids = <
  420. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  421. >;
  422. fsl,pull-up = <0>;
  423. };
  424. mmc0_sck_cfg: mmc0-sck-cfg {
  425. fsl,pinmux-ids = <
  426. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  427. >;
  428. fsl,drive-strength = <2>;
  429. fsl,pull-up = <0>;
  430. };
  431. i2c0_pins_a: i2c0@0 {
  432. reg = <0>;
  433. fsl,pinmux-ids = <
  434. 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
  435. 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
  436. >;
  437. fsl,drive-strength = <1>;
  438. fsl,voltage = <1>;
  439. fsl,pull-up = <1>;
  440. };
  441. i2c0_pins_b: i2c0@1 {
  442. reg = <1>;
  443. fsl,pinmux-ids = <
  444. 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
  445. 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
  446. >;
  447. fsl,drive-strength = <1>;
  448. fsl,voltage = <1>;
  449. fsl,pull-up = <1>;
  450. };
  451. i2c1_pins_a: i2c1@0 {
  452. reg = <0>;
  453. fsl,pinmux-ids = <
  454. 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
  455. 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
  456. >;
  457. fsl,drive-strength = <1>;
  458. fsl,voltage = <1>;
  459. fsl,pull-up = <1>;
  460. };
  461. saif0_pins_a: saif0@0 {
  462. reg = <0>;
  463. fsl,pinmux-ids = <
  464. 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
  465. 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
  466. 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
  467. 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
  468. >;
  469. fsl,drive-strength = <2>;
  470. fsl,voltage = <1>;
  471. fsl,pull-up = <1>;
  472. };
  473. saif0_pins_b: saif0@1 {
  474. reg = <1>;
  475. fsl,pinmux-ids = <
  476. 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
  477. 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
  478. 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
  479. >;
  480. fsl,drive-strength = <2>;
  481. fsl,voltage = <1>;
  482. fsl,pull-up = <1>;
  483. };
  484. saif1_pins_a: saif1@0 {
  485. reg = <0>;
  486. fsl,pinmux-ids = <
  487. 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
  488. >;
  489. fsl,drive-strength = <2>;
  490. fsl,voltage = <1>;
  491. fsl,pull-up = <1>;
  492. };
  493. pwm0_pins_a: pwm0@0 {
  494. reg = <0>;
  495. fsl,pinmux-ids = <
  496. 0x3100 /* MX28_PAD_PWM0__PWM_0 */
  497. >;
  498. fsl,drive-strength = <0>;
  499. fsl,voltage = <1>;
  500. fsl,pull-up = <0>;
  501. };
  502. pwm2_pins_a: pwm2@0 {
  503. reg = <0>;
  504. fsl,pinmux-ids = <
  505. 0x3120 /* MX28_PAD_PWM2__PWM_2 */
  506. >;
  507. fsl,drive-strength = <0>;
  508. fsl,voltage = <1>;
  509. fsl,pull-up = <0>;
  510. };
  511. pwm3_pins_a: pwm3@0 {
  512. reg = <0>;
  513. fsl,pinmux-ids = <
  514. 0x31c0 /* MX28_PAD_PWM3__PWM_3 */
  515. >;
  516. fsl,drive-strength = <0>;
  517. fsl,voltage = <1>;
  518. fsl,pull-up = <0>;
  519. };
  520. pwm3_pins_b: pwm3@1 {
  521. reg = <1>;
  522. fsl,pinmux-ids = <
  523. 0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
  524. >;
  525. fsl,drive-strength = <0>;
  526. fsl,voltage = <1>;
  527. fsl,pull-up = <0>;
  528. };
  529. pwm4_pins_a: pwm4@0 {
  530. reg = <0>;
  531. fsl,pinmux-ids = <
  532. 0x31d0 /* MX28_PAD_PWM4__PWM_4 */
  533. >;
  534. fsl,drive-strength = <0>;
  535. fsl,voltage = <1>;
  536. fsl,pull-up = <0>;
  537. };
  538. lcdif_24bit_pins_a: lcdif-24bit@0 {
  539. reg = <0>;
  540. fsl,pinmux-ids = <
  541. 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
  542. 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
  543. 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
  544. 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
  545. 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
  546. 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
  547. 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
  548. 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
  549. 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
  550. 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
  551. 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
  552. 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
  553. 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
  554. 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
  555. 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
  556. 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
  557. 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
  558. 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
  559. 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
  560. 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
  561. 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
  562. 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
  563. 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
  564. 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
  565. >;
  566. fsl,drive-strength = <0>;
  567. fsl,voltage = <1>;
  568. fsl,pull-up = <0>;
  569. };
  570. lcdif_16bit_pins_a: lcdif-16bit@0 {
  571. reg = <0>;
  572. fsl,pinmux-ids = <
  573. 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
  574. 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
  575. 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
  576. 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
  577. 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
  578. 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
  579. 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
  580. 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
  581. 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
  582. 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
  583. 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
  584. 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
  585. 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
  586. 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
  587. 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
  588. 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
  589. >;
  590. fsl,drive-strength = <0>;
  591. fsl,voltage = <1>;
  592. fsl,pull-up = <0>;
  593. };
  594. can0_pins_a: can0@0 {
  595. reg = <0>;
  596. fsl,pinmux-ids = <
  597. 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
  598. 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
  599. >;
  600. fsl,drive-strength = <0>;
  601. fsl,voltage = <1>;
  602. fsl,pull-up = <0>;
  603. };
  604. can1_pins_a: can1@0 {
  605. reg = <0>;
  606. fsl,pinmux-ids = <
  607. 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
  608. 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
  609. >;
  610. fsl,drive-strength = <0>;
  611. fsl,voltage = <1>;
  612. fsl,pull-up = <0>;
  613. };
  614. spi2_pins_a: spi2@0 {
  615. reg = <0>;
  616. fsl,pinmux-ids = <
  617. 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
  618. 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
  619. 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
  620. 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
  621. >;
  622. fsl,drive-strength = <1>;
  623. fsl,voltage = <1>;
  624. fsl,pull-up = <1>;
  625. };
  626. spi3_pins_a: spi3@0 {
  627. reg = <0>;
  628. fsl,pinmux-ids = <
  629. 0x3082 /* MX28_PAD_AUART2_RX__SSP3_D4 */
  630. 0x3092 /* MX28_PAD_AUART2_TX__SSP3_D5 */
  631. 0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */
  632. 0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */
  633. 0x21A0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */
  634. 0x21B0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */
  635. >;
  636. fsl,drive-strength = <1>;
  637. fsl,voltage = <1>;
  638. fsl,pull-up = <0>;
  639. };
  640. usbphy0_pins_a: usbphy0@0 {
  641. reg = <0>;
  642. fsl,pinmux-ids = <
  643. 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
  644. >;
  645. fsl,drive-strength = <2>;
  646. fsl,voltage = <1>;
  647. fsl,pull-up = <0>;
  648. };
  649. usbphy0_pins_b: usbphy0@1 {
  650. reg = <1>;
  651. fsl,pinmux-ids = <
  652. 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
  653. >;
  654. fsl,drive-strength = <2>;
  655. fsl,voltage = <1>;
  656. fsl,pull-up = <0>;
  657. };
  658. usbphy1_pins_a: usbphy1@0 {
  659. reg = <0>;
  660. fsl,pinmux-ids = <
  661. 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
  662. >;
  663. fsl,drive-strength = <2>;
  664. fsl,voltage = <1>;
  665. fsl,pull-up = <0>;
  666. };
  667. };
  668. digctl: digctl@8001c000 {
  669. compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
  670. reg = <0x8001c000 0x2000>;
  671. interrupts = <89>;
  672. status = "disabled";
  673. };
  674. etm: etm@80022000 {
  675. reg = <0x80022000 0x2000>;
  676. status = "disabled";
  677. };
  678. dma_apbx: dma-apbx@80024000 {
  679. compatible = "fsl,imx28-dma-apbx";
  680. reg = <0x80024000 0x2000>;
  681. interrupts = <78 79 66 0
  682. 80 81 68 69
  683. 70 71 72 73
  684. 74 75 76 77>;
  685. interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
  686. "saif0", "saif1", "i2c0", "i2c1",
  687. "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
  688. "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
  689. #dma-cells = <1>;
  690. dma-channels = <16>;
  691. clocks = <&clks 26>;
  692. };
  693. dcp: dcp@80028000 {
  694. reg = <0x80028000 0x2000>;
  695. interrupts = <52 53 54>;
  696. compatible = "fsl-dcp";
  697. };
  698. pxp: pxp@8002a000 {
  699. reg = <0x8002a000 0x2000>;
  700. interrupts = <39>;
  701. status = "disabled";
  702. };
  703. ocotp: ocotp@8002c000 {
  704. compatible = "fsl,ocotp";
  705. reg = <0x8002c000 0x2000>;
  706. status = "disabled";
  707. };
  708. axi-ahb@8002e000 {
  709. reg = <0x8002e000 0x2000>;
  710. status = "disabled";
  711. };
  712. lcdif: lcdif@80030000 {
  713. compatible = "fsl,imx28-lcdif";
  714. reg = <0x80030000 0x2000>;
  715. interrupts = <38>;
  716. clocks = <&clks 55>;
  717. dmas = <&dma_apbh 13>;
  718. dma-names = "rx";
  719. status = "disabled";
  720. };
  721. can0: can@80032000 {
  722. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  723. reg = <0x80032000 0x2000>;
  724. interrupts = <8>;
  725. clocks = <&clks 58>, <&clks 58>;
  726. clock-names = "ipg", "per";
  727. status = "disabled";
  728. };
  729. can1: can@80034000 {
  730. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  731. reg = <0x80034000 0x2000>;
  732. interrupts = <9>;
  733. clocks = <&clks 59>, <&clks 59>;
  734. clock-names = "ipg", "per";
  735. status = "disabled";
  736. };
  737. simdbg: simdbg@8003c000 {
  738. reg = <0x8003c000 0x200>;
  739. status = "disabled";
  740. };
  741. simgpmisel: simgpmisel@8003c200 {
  742. reg = <0x8003c200 0x100>;
  743. status = "disabled";
  744. };
  745. simsspsel: simsspsel@8003c300 {
  746. reg = <0x8003c300 0x100>;
  747. status = "disabled";
  748. };
  749. simmemsel: simmemsel@8003c400 {
  750. reg = <0x8003c400 0x100>;
  751. status = "disabled";
  752. };
  753. gpiomon: gpiomon@8003c500 {
  754. reg = <0x8003c500 0x100>;
  755. status = "disabled";
  756. };
  757. simenet: simenet@8003c700 {
  758. reg = <0x8003c700 0x100>;
  759. status = "disabled";
  760. };
  761. armjtag: armjtag@8003c800 {
  762. reg = <0x8003c800 0x100>;
  763. status = "disabled";
  764. };
  765. };
  766. apbx@80040000 {
  767. compatible = "simple-bus";
  768. #address-cells = <1>;
  769. #size-cells = <1>;
  770. reg = <0x80040000 0x40000>;
  771. ranges;
  772. clks: clkctrl@80040000 {
  773. compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
  774. reg = <0x80040000 0x2000>;
  775. #clock-cells = <1>;
  776. };
  777. saif0: saif@80042000 {
  778. compatible = "fsl,imx28-saif";
  779. reg = <0x80042000 0x2000>;
  780. interrupts = <59>;
  781. #clock-cells = <0>;
  782. clocks = <&clks 53>;
  783. dmas = <&dma_apbx 4>;
  784. dma-names = "rx-tx";
  785. status = "disabled";
  786. };
  787. power: power@80044000 {
  788. reg = <0x80044000 0x2000>;
  789. status = "disabled";
  790. };
  791. saif1: saif@80046000 {
  792. compatible = "fsl,imx28-saif";
  793. reg = <0x80046000 0x2000>;
  794. interrupts = <58>;
  795. clocks = <&clks 54>;
  796. dmas = <&dma_apbx 5>;
  797. dma-names = "rx-tx";
  798. status = "disabled";
  799. };
  800. lradc: lradc@80050000 {
  801. compatible = "fsl,imx28-lradc";
  802. reg = <0x80050000 0x2000>;
  803. interrupts = <10 14 15 16 17 18 19
  804. 20 21 22 23 24 25>;
  805. status = "disabled";
  806. };
  807. spdif: spdif@80054000 {
  808. reg = <0x80054000 0x2000>;
  809. interrupts = <45>;
  810. dmas = <&dma_apbx 2>;
  811. dma-names = "tx";
  812. status = "disabled";
  813. };
  814. mxs_rtc: rtc@80056000 {
  815. compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
  816. reg = <0x80056000 0x2000>;
  817. interrupts = <29>;
  818. };
  819. i2c0: i2c@80058000 {
  820. #address-cells = <1>;
  821. #size-cells = <0>;
  822. compatible = "fsl,imx28-i2c";
  823. reg = <0x80058000 0x2000>;
  824. interrupts = <111>;
  825. clock-frequency = <100000>;
  826. dmas = <&dma_apbx 6>;
  827. dma-names = "rx-tx";
  828. status = "disabled";
  829. };
  830. i2c1: i2c@8005a000 {
  831. #address-cells = <1>;
  832. #size-cells = <0>;
  833. compatible = "fsl,imx28-i2c";
  834. reg = <0x8005a000 0x2000>;
  835. interrupts = <110>;
  836. clock-frequency = <100000>;
  837. dmas = <&dma_apbx 7>;
  838. dma-names = "rx-tx";
  839. status = "disabled";
  840. };
  841. pwm: pwm@80064000 {
  842. compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
  843. reg = <0x80064000 0x2000>;
  844. clocks = <&clks 44>;
  845. #pwm-cells = <2>;
  846. fsl,pwm-number = <8>;
  847. status = "disabled";
  848. };
  849. timer: timrot@80068000 {
  850. compatible = "fsl,imx28-timrot", "fsl,timrot";
  851. reg = <0x80068000 0x2000>;
  852. interrupts = <48 49 50 51>;
  853. clocks = <&clks 26>;
  854. };
  855. auart0: serial@8006a000 {
  856. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  857. reg = <0x8006a000 0x2000>;
  858. interrupts = <112>;
  859. dmas = <&dma_apbx 8>, <&dma_apbx 9>;
  860. dma-names = "rx", "tx";
  861. clocks = <&clks 45>;
  862. status = "disabled";
  863. };
  864. auart1: serial@8006c000 {
  865. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  866. reg = <0x8006c000 0x2000>;
  867. interrupts = <113>;
  868. dmas = <&dma_apbx 10>, <&dma_apbx 11>;
  869. dma-names = "rx", "tx";
  870. clocks = <&clks 45>;
  871. status = "disabled";
  872. };
  873. auart2: serial@8006e000 {
  874. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  875. reg = <0x8006e000 0x2000>;
  876. interrupts = <114>;
  877. dmas = <&dma_apbx 12>, <&dma_apbx 13>;
  878. dma-names = "rx", "tx";
  879. clocks = <&clks 45>;
  880. status = "disabled";
  881. };
  882. auart3: serial@80070000 {
  883. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  884. reg = <0x80070000 0x2000>;
  885. interrupts = <115>;
  886. dmas = <&dma_apbx 14>, <&dma_apbx 15>;
  887. dma-names = "rx", "tx";
  888. clocks = <&clks 45>;
  889. status = "disabled";
  890. };
  891. auart4: serial@80072000 {
  892. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  893. reg = <0x80072000 0x2000>;
  894. interrupts = <116>;
  895. dmas = <&dma_apbx 0>, <&dma_apbx 1>;
  896. dma-names = "rx", "tx";
  897. clocks = <&clks 45>;
  898. status = "disabled";
  899. };
  900. duart: serial@80074000 {
  901. compatible = "arm,pl011", "arm,primecell";
  902. reg = <0x80074000 0x1000>;
  903. interrupts = <47>;
  904. clocks = <&clks 45>, <&clks 26>;
  905. clock-names = "uart", "apb_pclk";
  906. status = "disabled";
  907. };
  908. usbphy0: usbphy@8007c000 {
  909. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  910. reg = <0x8007c000 0x2000>;
  911. clocks = <&clks 62>;
  912. status = "disabled";
  913. };
  914. usbphy1: usbphy@8007e000 {
  915. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  916. reg = <0x8007e000 0x2000>;
  917. clocks = <&clks 63>;
  918. status = "disabled";
  919. };
  920. };
  921. };
  922. ahb@80080000 {
  923. compatible = "simple-bus";
  924. #address-cells = <1>;
  925. #size-cells = <1>;
  926. reg = <0x80080000 0x80000>;
  927. ranges;
  928. usb0: usb@80080000 {
  929. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  930. reg = <0x80080000 0x10000>;
  931. interrupts = <93>;
  932. clocks = <&clks 60>;
  933. fsl,usbphy = <&usbphy0>;
  934. status = "disabled";
  935. };
  936. usb1: usb@80090000 {
  937. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  938. reg = <0x80090000 0x10000>;
  939. interrupts = <92>;
  940. clocks = <&clks 61>;
  941. fsl,usbphy = <&usbphy1>;
  942. status = "disabled";
  943. };
  944. dflpt: dflpt@800c0000 {
  945. reg = <0x800c0000 0x10000>;
  946. status = "disabled";
  947. };
  948. mac0: ethernet@800f0000 {
  949. compatible = "fsl,imx28-fec";
  950. reg = <0x800f0000 0x4000>;
  951. interrupts = <101>;
  952. clocks = <&clks 57>, <&clks 57>, <&clks 64>;
  953. clock-names = "ipg", "ahb", "enet_out";
  954. status = "disabled";
  955. };
  956. mac1: ethernet@800f4000 {
  957. compatible = "fsl,imx28-fec";
  958. reg = <0x800f4000 0x4000>;
  959. interrupts = <102>;
  960. clocks = <&clks 57>, <&clks 57>;
  961. clock-names = "ipg", "ahb";
  962. status = "disabled";
  963. };
  964. etn_switch: switch@800f8000 {
  965. reg = <0x800f8000 0x8000>;
  966. status = "disabled";
  967. };
  968. };
  969. };