devices.c 23 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/devices.c
  3. *
  4. * OMAP2 platform device setup/initialization
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/io.h>
  16. #include <linux/clk.h>
  17. #include <mach/hardware.h>
  18. #include <mach/irqs.h>
  19. #include <asm/mach-types.h>
  20. #include <asm/mach/map.h>
  21. #include <asm/pmu.h>
  22. #include <plat/control.h>
  23. #include <plat/tc.h>
  24. #include <plat/board.h>
  25. #include <plat/mcbsp.h>
  26. #include <mach/gpio.h>
  27. #include <plat/mmc.h>
  28. #include <plat/dma.h>
  29. #include "mux.h"
  30. #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  31. static struct resource cam_resources[] = {
  32. {
  33. .start = OMAP24XX_CAMERA_BASE,
  34. .end = OMAP24XX_CAMERA_BASE + 0xfff,
  35. .flags = IORESOURCE_MEM,
  36. },
  37. {
  38. .start = INT_24XX_CAM_IRQ,
  39. .flags = IORESOURCE_IRQ,
  40. }
  41. };
  42. static struct platform_device omap_cam_device = {
  43. .name = "omap24xxcam",
  44. .id = -1,
  45. .num_resources = ARRAY_SIZE(cam_resources),
  46. .resource = cam_resources,
  47. };
  48. static inline void omap_init_camera(void)
  49. {
  50. platform_device_register(&omap_cam_device);
  51. }
  52. #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  53. static struct resource omap3isp_resources[] = {
  54. {
  55. .start = OMAP3430_ISP_BASE,
  56. .end = OMAP3430_ISP_END,
  57. .flags = IORESOURCE_MEM,
  58. },
  59. {
  60. .start = OMAP3430_ISP_CBUFF_BASE,
  61. .end = OMAP3430_ISP_CBUFF_END,
  62. .flags = IORESOURCE_MEM,
  63. },
  64. {
  65. .start = OMAP3430_ISP_CCP2_BASE,
  66. .end = OMAP3430_ISP_CCP2_END,
  67. .flags = IORESOURCE_MEM,
  68. },
  69. {
  70. .start = OMAP3430_ISP_CCDC_BASE,
  71. .end = OMAP3430_ISP_CCDC_END,
  72. .flags = IORESOURCE_MEM,
  73. },
  74. {
  75. .start = OMAP3430_ISP_HIST_BASE,
  76. .end = OMAP3430_ISP_HIST_END,
  77. .flags = IORESOURCE_MEM,
  78. },
  79. {
  80. .start = OMAP3430_ISP_H3A_BASE,
  81. .end = OMAP3430_ISP_H3A_END,
  82. .flags = IORESOURCE_MEM,
  83. },
  84. {
  85. .start = OMAP3430_ISP_PREV_BASE,
  86. .end = OMAP3430_ISP_PREV_END,
  87. .flags = IORESOURCE_MEM,
  88. },
  89. {
  90. .start = OMAP3430_ISP_RESZ_BASE,
  91. .end = OMAP3430_ISP_RESZ_END,
  92. .flags = IORESOURCE_MEM,
  93. },
  94. {
  95. .start = OMAP3430_ISP_SBL_BASE,
  96. .end = OMAP3430_ISP_SBL_END,
  97. .flags = IORESOURCE_MEM,
  98. },
  99. {
  100. .start = OMAP3430_ISP_CSI2A_BASE,
  101. .end = OMAP3430_ISP_CSI2A_END,
  102. .flags = IORESOURCE_MEM,
  103. },
  104. {
  105. .start = OMAP3430_ISP_CSI2PHY_BASE,
  106. .end = OMAP3430_ISP_CSI2PHY_END,
  107. .flags = IORESOURCE_MEM,
  108. },
  109. {
  110. .start = INT_34XX_CAM_IRQ,
  111. .flags = IORESOURCE_IRQ,
  112. }
  113. };
  114. static struct platform_device omap3isp_device = {
  115. .name = "omap3isp",
  116. .id = -1,
  117. .num_resources = ARRAY_SIZE(omap3isp_resources),
  118. .resource = omap3isp_resources,
  119. };
  120. static inline void omap_init_camera(void)
  121. {
  122. platform_device_register(&omap3isp_device);
  123. }
  124. #else
  125. static inline void omap_init_camera(void)
  126. {
  127. }
  128. #endif
  129. #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
  130. #define MBOX_REG_SIZE 0x120
  131. #ifdef CONFIG_ARCH_OMAP2
  132. static struct resource omap2_mbox_resources[] = {
  133. {
  134. .start = OMAP24XX_MAILBOX_BASE,
  135. .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
  136. .flags = IORESOURCE_MEM,
  137. },
  138. {
  139. .start = INT_24XX_MAIL_U0_MPU,
  140. .flags = IORESOURCE_IRQ,
  141. .name = "dsp",
  142. },
  143. {
  144. .start = INT_24XX_MAIL_U3_MPU,
  145. .flags = IORESOURCE_IRQ,
  146. .name = "iva",
  147. },
  148. };
  149. static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
  150. #else
  151. #define omap2_mbox_resources NULL
  152. #define omap2_mbox_resources_sz 0
  153. #endif
  154. #ifdef CONFIG_ARCH_OMAP3
  155. static struct resource omap3_mbox_resources[] = {
  156. {
  157. .start = OMAP34XX_MAILBOX_BASE,
  158. .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
  159. .flags = IORESOURCE_MEM,
  160. },
  161. {
  162. .start = INT_24XX_MAIL_U0_MPU,
  163. .flags = IORESOURCE_IRQ,
  164. .name = "dsp",
  165. },
  166. };
  167. static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
  168. #else
  169. #define omap3_mbox_resources NULL
  170. #define omap3_mbox_resources_sz 0
  171. #endif
  172. #ifdef CONFIG_ARCH_OMAP4
  173. #define OMAP4_MBOX_REG_SIZE 0x130
  174. static struct resource omap4_mbox_resources[] = {
  175. {
  176. .start = OMAP44XX_MAILBOX_BASE,
  177. .end = OMAP44XX_MAILBOX_BASE +
  178. OMAP4_MBOX_REG_SIZE - 1,
  179. .flags = IORESOURCE_MEM,
  180. },
  181. {
  182. .start = OMAP44XX_IRQ_MAIL_U0,
  183. .flags = IORESOURCE_IRQ,
  184. .name = "mbox",
  185. },
  186. };
  187. static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
  188. #else
  189. #define omap4_mbox_resources NULL
  190. #define omap4_mbox_resources_sz 0
  191. #endif
  192. static struct platform_device mbox_device = {
  193. .name = "omap-mailbox",
  194. .id = -1,
  195. };
  196. static inline void omap_init_mbox(void)
  197. {
  198. if (cpu_is_omap24xx()) {
  199. mbox_device.resource = omap2_mbox_resources;
  200. mbox_device.num_resources = omap2_mbox_resources_sz;
  201. } else if (cpu_is_omap34xx()) {
  202. mbox_device.resource = omap3_mbox_resources;
  203. mbox_device.num_resources = omap3_mbox_resources_sz;
  204. } else if (cpu_is_omap44xx()) {
  205. mbox_device.resource = omap4_mbox_resources;
  206. mbox_device.num_resources = omap4_mbox_resources_sz;
  207. } else {
  208. pr_err("%s: platform not supported\n", __func__);
  209. return;
  210. }
  211. platform_device_register(&mbox_device);
  212. }
  213. #else
  214. static inline void omap_init_mbox(void) { }
  215. #endif /* CONFIG_OMAP_MBOX_FWK */
  216. static inline void omap_init_sti(void) {}
  217. #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
  218. static struct platform_device omap_pcm = {
  219. .name = "omap-pcm-audio",
  220. .id = -1,
  221. };
  222. /*
  223. * OMAP2420 has 2 McBSP ports
  224. * OMAP2430 has 5 McBSP ports
  225. * OMAP3 has 5 McBSP ports
  226. * OMAP4 has 4 McBSP ports
  227. */
  228. OMAP_MCBSP_PLATFORM_DEVICE(1);
  229. OMAP_MCBSP_PLATFORM_DEVICE(2);
  230. OMAP_MCBSP_PLATFORM_DEVICE(3);
  231. OMAP_MCBSP_PLATFORM_DEVICE(4);
  232. OMAP_MCBSP_PLATFORM_DEVICE(5);
  233. static void omap_init_audio(void)
  234. {
  235. platform_device_register(&omap_mcbsp1);
  236. platform_device_register(&omap_mcbsp2);
  237. if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
  238. platform_device_register(&omap_mcbsp3);
  239. platform_device_register(&omap_mcbsp4);
  240. }
  241. if (cpu_is_omap243x() || cpu_is_omap34xx())
  242. platform_device_register(&omap_mcbsp5);
  243. platform_device_register(&omap_pcm);
  244. }
  245. #else
  246. static inline void omap_init_audio(void) {}
  247. #endif
  248. #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
  249. #include <plat/mcspi.h>
  250. #define OMAP2_MCSPI1_BASE 0x48098000
  251. #define OMAP2_MCSPI2_BASE 0x4809a000
  252. #define OMAP2_MCSPI3_BASE 0x480b8000
  253. #define OMAP2_MCSPI4_BASE 0x480ba000
  254. #define OMAP4_MCSPI1_BASE 0x48098100
  255. #define OMAP4_MCSPI2_BASE 0x4809a100
  256. #define OMAP4_MCSPI3_BASE 0x480b8100
  257. #define OMAP4_MCSPI4_BASE 0x480ba100
  258. static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
  259. .num_cs = 4,
  260. };
  261. static struct resource omap2_mcspi1_resources[] = {
  262. {
  263. .start = OMAP2_MCSPI1_BASE,
  264. .end = OMAP2_MCSPI1_BASE + 0xff,
  265. .flags = IORESOURCE_MEM,
  266. },
  267. };
  268. static struct platform_device omap2_mcspi1 = {
  269. .name = "omap2_mcspi",
  270. .id = 1,
  271. .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
  272. .resource = omap2_mcspi1_resources,
  273. .dev = {
  274. .platform_data = &omap2_mcspi1_config,
  275. },
  276. };
  277. static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
  278. .num_cs = 2,
  279. };
  280. static struct resource omap2_mcspi2_resources[] = {
  281. {
  282. .start = OMAP2_MCSPI2_BASE,
  283. .end = OMAP2_MCSPI2_BASE + 0xff,
  284. .flags = IORESOURCE_MEM,
  285. },
  286. };
  287. static struct platform_device omap2_mcspi2 = {
  288. .name = "omap2_mcspi",
  289. .id = 2,
  290. .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
  291. .resource = omap2_mcspi2_resources,
  292. .dev = {
  293. .platform_data = &omap2_mcspi2_config,
  294. },
  295. };
  296. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
  297. defined(CONFIG_ARCH_OMAP4)
  298. static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
  299. .num_cs = 2,
  300. };
  301. static struct resource omap2_mcspi3_resources[] = {
  302. {
  303. .start = OMAP2_MCSPI3_BASE,
  304. .end = OMAP2_MCSPI3_BASE + 0xff,
  305. .flags = IORESOURCE_MEM,
  306. },
  307. };
  308. static struct platform_device omap2_mcspi3 = {
  309. .name = "omap2_mcspi",
  310. .id = 3,
  311. .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
  312. .resource = omap2_mcspi3_resources,
  313. .dev = {
  314. .platform_data = &omap2_mcspi3_config,
  315. },
  316. };
  317. #endif
  318. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  319. static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
  320. .num_cs = 1,
  321. };
  322. static struct resource omap2_mcspi4_resources[] = {
  323. {
  324. .start = OMAP2_MCSPI4_BASE,
  325. .end = OMAP2_MCSPI4_BASE + 0xff,
  326. .flags = IORESOURCE_MEM,
  327. },
  328. };
  329. static struct platform_device omap2_mcspi4 = {
  330. .name = "omap2_mcspi",
  331. .id = 4,
  332. .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
  333. .resource = omap2_mcspi4_resources,
  334. .dev = {
  335. .platform_data = &omap2_mcspi4_config,
  336. },
  337. };
  338. #endif
  339. #ifdef CONFIG_ARCH_OMAP4
  340. static inline void omap4_mcspi_fixup(void)
  341. {
  342. omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
  343. omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
  344. omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
  345. omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
  346. omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
  347. omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
  348. omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
  349. omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
  350. }
  351. #else
  352. static inline void omap4_mcspi_fixup(void)
  353. {
  354. }
  355. #endif
  356. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
  357. defined(CONFIG_ARCH_OMAP4)
  358. static inline void omap2_mcspi3_init(void)
  359. {
  360. platform_device_register(&omap2_mcspi3);
  361. }
  362. #else
  363. static inline void omap2_mcspi3_init(void)
  364. {
  365. }
  366. #endif
  367. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  368. static inline void omap2_mcspi4_init(void)
  369. {
  370. platform_device_register(&omap2_mcspi4);
  371. }
  372. #else
  373. static inline void omap2_mcspi4_init(void)
  374. {
  375. }
  376. #endif
  377. static void omap_init_mcspi(void)
  378. {
  379. if (cpu_is_omap44xx())
  380. omap4_mcspi_fixup();
  381. platform_device_register(&omap2_mcspi1);
  382. platform_device_register(&omap2_mcspi2);
  383. if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
  384. omap2_mcspi3_init();
  385. if (cpu_is_omap343x() || cpu_is_omap44xx())
  386. omap2_mcspi4_init();
  387. }
  388. #else
  389. static inline void omap_init_mcspi(void) {}
  390. #endif
  391. static struct resource omap2_pmu_resource = {
  392. .start = 3,
  393. .end = 3,
  394. .flags = IORESOURCE_IRQ,
  395. };
  396. static struct resource omap3_pmu_resource = {
  397. .start = INT_34XX_BENCH_MPU_EMUL,
  398. .end = INT_34XX_BENCH_MPU_EMUL,
  399. .flags = IORESOURCE_IRQ,
  400. };
  401. static struct platform_device omap_pmu_device = {
  402. .name = "arm-pmu",
  403. .id = ARM_PMU_DEVICE_CPU,
  404. .num_resources = 1,
  405. };
  406. static void omap_init_pmu(void)
  407. {
  408. if (cpu_is_omap24xx())
  409. omap_pmu_device.resource = &omap2_pmu_resource;
  410. else if (cpu_is_omap34xx())
  411. omap_pmu_device.resource = &omap3_pmu_resource;
  412. else
  413. return;
  414. platform_device_register(&omap_pmu_device);
  415. }
  416. #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
  417. #ifdef CONFIG_ARCH_OMAP2
  418. static struct resource omap2_sham_resources[] = {
  419. {
  420. .start = OMAP24XX_SEC_SHA1MD5_BASE,
  421. .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
  422. .flags = IORESOURCE_MEM,
  423. },
  424. {
  425. .start = INT_24XX_SHA1MD5,
  426. .flags = IORESOURCE_IRQ,
  427. }
  428. };
  429. static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
  430. #else
  431. #define omap2_sham_resources NULL
  432. #define omap2_sham_resources_sz 0
  433. #endif
  434. #ifdef CONFIG_ARCH_OMAP3
  435. static struct resource omap3_sham_resources[] = {
  436. {
  437. .start = OMAP34XX_SEC_SHA1MD5_BASE,
  438. .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
  439. .flags = IORESOURCE_MEM,
  440. },
  441. {
  442. .start = INT_34XX_SHA1MD52_IRQ,
  443. .flags = IORESOURCE_IRQ,
  444. },
  445. {
  446. .start = OMAP34XX_DMA_SHA1MD5_RX,
  447. .flags = IORESOURCE_DMA,
  448. }
  449. };
  450. static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
  451. #else
  452. #define omap3_sham_resources NULL
  453. #define omap3_sham_resources_sz 0
  454. #endif
  455. static struct platform_device sham_device = {
  456. .name = "omap-sham",
  457. .id = -1,
  458. };
  459. static void omap_init_sham(void)
  460. {
  461. if (cpu_is_omap24xx()) {
  462. sham_device.resource = omap2_sham_resources;
  463. sham_device.num_resources = omap2_sham_resources_sz;
  464. } else if (cpu_is_omap34xx()) {
  465. sham_device.resource = omap3_sham_resources;
  466. sham_device.num_resources = omap3_sham_resources_sz;
  467. } else {
  468. pr_err("%s: platform not supported\n", __func__);
  469. return;
  470. }
  471. platform_device_register(&sham_device);
  472. }
  473. #else
  474. static inline void omap_init_sham(void) { }
  475. #endif
  476. #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
  477. #ifdef CONFIG_ARCH_OMAP24XX
  478. static struct resource omap2_aes_resources[] = {
  479. {
  480. .start = OMAP24XX_SEC_AES_BASE,
  481. .end = OMAP24XX_SEC_AES_BASE + 0x4C,
  482. .flags = IORESOURCE_MEM,
  483. },
  484. {
  485. .start = OMAP24XX_DMA_AES_TX,
  486. .flags = IORESOURCE_DMA,
  487. },
  488. {
  489. .start = OMAP24XX_DMA_AES_RX,
  490. .flags = IORESOURCE_DMA,
  491. }
  492. };
  493. static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
  494. #else
  495. #define omap2_aes_resources NULL
  496. #define omap2_aes_resources_sz 0
  497. #endif
  498. #ifdef CONFIG_ARCH_OMAP34XX
  499. static struct resource omap3_aes_resources[] = {
  500. {
  501. .start = OMAP34XX_SEC_AES_BASE,
  502. .end = OMAP34XX_SEC_AES_BASE + 0x4C,
  503. .flags = IORESOURCE_MEM,
  504. },
  505. {
  506. .start = OMAP34XX_DMA_AES2_TX,
  507. .flags = IORESOURCE_DMA,
  508. },
  509. {
  510. .start = OMAP34XX_DMA_AES2_RX,
  511. .flags = IORESOURCE_DMA,
  512. }
  513. };
  514. static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
  515. #else
  516. #define omap3_aes_resources NULL
  517. #define omap3_aes_resources_sz 0
  518. #endif
  519. static struct platform_device aes_device = {
  520. .name = "omap-aes",
  521. .id = -1,
  522. };
  523. static void omap_init_aes(void)
  524. {
  525. if (cpu_is_omap24xx()) {
  526. aes_device.resource = omap2_aes_resources;
  527. aes_device.num_resources = omap2_aes_resources_sz;
  528. } else if (cpu_is_omap34xx()) {
  529. aes_device.resource = omap3_aes_resources;
  530. aes_device.num_resources = omap3_aes_resources_sz;
  531. } else {
  532. pr_err("%s: platform not supported\n", __func__);
  533. return;
  534. }
  535. platform_device_register(&aes_device);
  536. }
  537. #else
  538. static inline void omap_init_aes(void) { }
  539. #endif
  540. /*-------------------------------------------------------------------------*/
  541. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  542. #define MMCHS_SYSCONFIG 0x0010
  543. #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
  544. #define MMCHS_SYSSTATUS 0x0014
  545. #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
  546. static struct platform_device dummy_pdev = {
  547. .dev = {
  548. .bus = &platform_bus_type,
  549. },
  550. };
  551. /**
  552. * omap_hsmmc_reset() - Full reset of each HS-MMC controller
  553. *
  554. * Ensure that each MMC controller is fully reset. Controllers
  555. * left in an unknown state (by bootloader) may prevent retention
  556. * or OFF-mode. This is especially important in cases where the
  557. * MMC driver is not enabled, _or_ built as a module.
  558. *
  559. * In order for reset to work, interface, functional and debounce
  560. * clocks must be enabled. The debounce clock comes from func_32k_clk
  561. * and is not under SW control, so we only enable i- and f-clocks.
  562. **/
  563. static void __init omap_hsmmc_reset(void)
  564. {
  565. u32 i, nr_controllers;
  566. if (cpu_is_omap242x())
  567. return;
  568. nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
  569. (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
  570. for (i = 0; i < nr_controllers; i++) {
  571. u32 v, base = 0;
  572. struct clk *iclk, *fclk;
  573. struct device *dev = &dummy_pdev.dev;
  574. switch (i) {
  575. case 0:
  576. base = OMAP2_MMC1_BASE;
  577. break;
  578. case 1:
  579. base = OMAP2_MMC2_BASE;
  580. break;
  581. case 2:
  582. base = OMAP3_MMC3_BASE;
  583. break;
  584. case 3:
  585. if (!cpu_is_omap44xx())
  586. return;
  587. base = OMAP4_MMC4_BASE;
  588. break;
  589. case 4:
  590. if (!cpu_is_omap44xx())
  591. return;
  592. base = OMAP4_MMC5_BASE;
  593. break;
  594. }
  595. if (cpu_is_omap44xx())
  596. base += OMAP4_MMC_REG_OFFSET;
  597. dummy_pdev.id = i;
  598. dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
  599. iclk = clk_get(dev, "ick");
  600. if (iclk && clk_enable(iclk))
  601. iclk = NULL;
  602. fclk = clk_get(dev, "fck");
  603. if (fclk && clk_enable(fclk))
  604. fclk = NULL;
  605. if (!iclk || !fclk) {
  606. printk(KERN_WARNING
  607. "%s: Unable to enable clocks for MMC%d, "
  608. "cannot reset.\n", __func__, i);
  609. break;
  610. }
  611. omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
  612. v = omap_readl(base + MMCHS_SYSSTATUS);
  613. while (!(omap_readl(base + MMCHS_SYSSTATUS) &
  614. MMCHS_SYSSTATUS_RESETDONE))
  615. cpu_relax();
  616. if (fclk) {
  617. clk_disable(fclk);
  618. clk_put(fclk);
  619. }
  620. if (iclk) {
  621. clk_disable(iclk);
  622. clk_put(iclk);
  623. }
  624. }
  625. }
  626. #else
  627. static inline void omap_hsmmc_reset(void) {}
  628. #endif
  629. #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
  630. defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  631. static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
  632. int controller_nr)
  633. {
  634. if ((mmc_controller->slots[0].switch_pin > 0) && \
  635. (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
  636. omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
  637. OMAP_PIN_INPUT_PULLUP);
  638. if ((mmc_controller->slots[0].gpio_wp > 0) && \
  639. (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
  640. omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
  641. OMAP_PIN_INPUT_PULLUP);
  642. if (cpu_is_omap2420() && controller_nr == 0) {
  643. omap_mux_init_signal("sdmmc_cmd", 0);
  644. omap_mux_init_signal("sdmmc_clki", 0);
  645. omap_mux_init_signal("sdmmc_clko", 0);
  646. omap_mux_init_signal("sdmmc_dat0", 0);
  647. omap_mux_init_signal("sdmmc_dat_dir0", 0);
  648. omap_mux_init_signal("sdmmc_cmd_dir", 0);
  649. if (mmc_controller->slots[0].wires == 4) {
  650. omap_mux_init_signal("sdmmc_dat1", 0);
  651. omap_mux_init_signal("sdmmc_dat2", 0);
  652. omap_mux_init_signal("sdmmc_dat3", 0);
  653. omap_mux_init_signal("sdmmc_dat_dir1", 0);
  654. omap_mux_init_signal("sdmmc_dat_dir2", 0);
  655. omap_mux_init_signal("sdmmc_dat_dir3", 0);
  656. }
  657. /*
  658. * Use internal loop-back in MMC/SDIO Module Input Clock
  659. * selection
  660. */
  661. if (mmc_controller->slots[0].internal_clock) {
  662. u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  663. v |= (1 << 24);
  664. omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
  665. }
  666. }
  667. if (cpu_is_omap34xx()) {
  668. if (controller_nr == 0) {
  669. omap_mux_init_signal("sdmmc1_clk",
  670. OMAP_PIN_INPUT_PULLUP);
  671. omap_mux_init_signal("sdmmc1_cmd",
  672. OMAP_PIN_INPUT_PULLUP);
  673. omap_mux_init_signal("sdmmc1_dat0",
  674. OMAP_PIN_INPUT_PULLUP);
  675. if (mmc_controller->slots[0].wires == 4 ||
  676. mmc_controller->slots[0].wires == 8) {
  677. omap_mux_init_signal("sdmmc1_dat1",
  678. OMAP_PIN_INPUT_PULLUP);
  679. omap_mux_init_signal("sdmmc1_dat2",
  680. OMAP_PIN_INPUT_PULLUP);
  681. omap_mux_init_signal("sdmmc1_dat3",
  682. OMAP_PIN_INPUT_PULLUP);
  683. }
  684. if (mmc_controller->slots[0].wires == 8) {
  685. omap_mux_init_signal("sdmmc1_dat4",
  686. OMAP_PIN_INPUT_PULLUP);
  687. omap_mux_init_signal("sdmmc1_dat5",
  688. OMAP_PIN_INPUT_PULLUP);
  689. omap_mux_init_signal("sdmmc1_dat6",
  690. OMAP_PIN_INPUT_PULLUP);
  691. omap_mux_init_signal("sdmmc1_dat7",
  692. OMAP_PIN_INPUT_PULLUP);
  693. }
  694. }
  695. if (controller_nr == 1) {
  696. /* MMC2 */
  697. omap_mux_init_signal("sdmmc2_clk",
  698. OMAP_PIN_INPUT_PULLUP);
  699. omap_mux_init_signal("sdmmc2_cmd",
  700. OMAP_PIN_INPUT_PULLUP);
  701. omap_mux_init_signal("sdmmc2_dat0",
  702. OMAP_PIN_INPUT_PULLUP);
  703. /*
  704. * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
  705. * in the board-*.c files
  706. */
  707. if (mmc_controller->slots[0].wires == 4 ||
  708. mmc_controller->slots[0].wires == 8) {
  709. omap_mux_init_signal("sdmmc2_dat1",
  710. OMAP_PIN_INPUT_PULLUP);
  711. omap_mux_init_signal("sdmmc2_dat2",
  712. OMAP_PIN_INPUT_PULLUP);
  713. omap_mux_init_signal("sdmmc2_dat3",
  714. OMAP_PIN_INPUT_PULLUP);
  715. }
  716. if (mmc_controller->slots[0].wires == 8) {
  717. omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
  718. OMAP_PIN_INPUT_PULLUP);
  719. omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
  720. OMAP_PIN_INPUT_PULLUP);
  721. omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
  722. OMAP_PIN_INPUT_PULLUP);
  723. omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
  724. OMAP_PIN_INPUT_PULLUP);
  725. }
  726. }
  727. /*
  728. * For MMC3 the pins need to be muxed in the board-*.c files
  729. */
  730. }
  731. }
  732. void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
  733. int nr_controllers)
  734. {
  735. int i;
  736. char *name;
  737. for (i = 0; i < nr_controllers; i++) {
  738. unsigned long base, size;
  739. unsigned int irq = 0;
  740. if (!mmc_data[i])
  741. continue;
  742. omap2_mmc_mux(mmc_data[i], i);
  743. switch (i) {
  744. case 0:
  745. base = OMAP2_MMC1_BASE;
  746. irq = INT_24XX_MMC_IRQ;
  747. break;
  748. case 1:
  749. base = OMAP2_MMC2_BASE;
  750. irq = INT_24XX_MMC2_IRQ;
  751. break;
  752. case 2:
  753. if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
  754. return;
  755. base = OMAP3_MMC3_BASE;
  756. irq = INT_34XX_MMC3_IRQ;
  757. break;
  758. case 3:
  759. if (!cpu_is_omap44xx())
  760. return;
  761. base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
  762. irq = OMAP44XX_IRQ_MMC4;
  763. break;
  764. case 4:
  765. if (!cpu_is_omap44xx())
  766. return;
  767. base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
  768. irq = OMAP44XX_IRQ_MMC5;
  769. break;
  770. default:
  771. continue;
  772. }
  773. if (cpu_is_omap2420()) {
  774. size = OMAP2420_MMC_SIZE;
  775. name = "mmci-omap";
  776. } else if (cpu_is_omap44xx()) {
  777. if (i < 3) {
  778. base += OMAP4_MMC_REG_OFFSET;
  779. irq += OMAP44XX_IRQ_GIC_START;
  780. }
  781. size = OMAP4_HSMMC_SIZE;
  782. name = "mmci-omap-hs";
  783. } else {
  784. size = OMAP3_HSMMC_SIZE;
  785. name = "mmci-omap-hs";
  786. }
  787. omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
  788. };
  789. }
  790. #endif
  791. /*-------------------------------------------------------------------------*/
  792. #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
  793. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
  794. #define OMAP_HDQ_BASE 0x480B2000
  795. #endif
  796. static struct resource omap_hdq_resources[] = {
  797. {
  798. .start = OMAP_HDQ_BASE,
  799. .end = OMAP_HDQ_BASE + 0x1C,
  800. .flags = IORESOURCE_MEM,
  801. },
  802. {
  803. .start = INT_24XX_HDQ_IRQ,
  804. .flags = IORESOURCE_IRQ,
  805. },
  806. };
  807. static struct platform_device omap_hdq_dev = {
  808. .name = "omap_hdq",
  809. .id = 0,
  810. .dev = {
  811. .platform_data = NULL,
  812. },
  813. .num_resources = ARRAY_SIZE(omap_hdq_resources),
  814. .resource = omap_hdq_resources,
  815. };
  816. static inline void omap_hdq_init(void)
  817. {
  818. (void) platform_device_register(&omap_hdq_dev);
  819. }
  820. #else
  821. static inline void omap_hdq_init(void) {}
  822. #endif
  823. /*---------------------------------------------------------------------------*/
  824. #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
  825. defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
  826. #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
  827. static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
  828. };
  829. #else
  830. static struct resource omap_vout_resource[2] = {
  831. };
  832. #endif
  833. static struct platform_device omap_vout_device = {
  834. .name = "omap_vout",
  835. .num_resources = ARRAY_SIZE(omap_vout_resource),
  836. .resource = &omap_vout_resource[0],
  837. .id = -1,
  838. };
  839. static void omap_init_vout(void)
  840. {
  841. if (platform_device_register(&omap_vout_device) < 0)
  842. printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
  843. }
  844. #else
  845. static inline void omap_init_vout(void) {}
  846. #endif
  847. /*-------------------------------------------------------------------------*/
  848. static int __init omap2_init_devices(void)
  849. {
  850. /* please keep these calls, and their implementations above,
  851. * in alphabetical order so they're easier to sort through.
  852. */
  853. omap_hsmmc_reset();
  854. omap_init_audio();
  855. omap_init_camera();
  856. omap_init_mbox();
  857. omap_init_mcspi();
  858. omap_init_pmu();
  859. omap_hdq_init();
  860. omap_init_sti();
  861. omap_init_sham();
  862. omap_init_aes();
  863. omap_init_vout();
  864. return 0;
  865. }
  866. arch_initcall(omap2_init_devices);