mthca_main.c 31 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
  4. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_main.c 1396 2004-12-28 04:10:27Z roland $
  35. */
  36. #include <linux/config.h>
  37. #include <linux/module.h>
  38. #include <linux/init.h>
  39. #include <linux/errno.h>
  40. #include <linux/pci.h>
  41. #include <linux/interrupt.h>
  42. #include "mthca_dev.h"
  43. #include "mthca_config_reg.h"
  44. #include "mthca_cmd.h"
  45. #include "mthca_profile.h"
  46. #include "mthca_memfree.h"
  47. MODULE_AUTHOR("Roland Dreier");
  48. MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
  49. MODULE_LICENSE("Dual BSD/GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. #ifdef CONFIG_PCI_MSI
  52. static int msi_x = 0;
  53. module_param(msi_x, int, 0444);
  54. MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  55. static int msi = 0;
  56. module_param(msi, int, 0444);
  57. MODULE_PARM_DESC(msi, "attempt to use MSI if nonzero");
  58. #else /* CONFIG_PCI_MSI */
  59. #define msi_x (0)
  60. #define msi (0)
  61. #endif /* CONFIG_PCI_MSI */
  62. static const char mthca_version[] __devinitdata =
  63. DRV_NAME ": Mellanox InfiniBand HCA driver v"
  64. DRV_VERSION " (" DRV_RELDATE ")\n";
  65. static struct mthca_profile default_profile = {
  66. .num_qp = 1 << 16,
  67. .rdb_per_qp = 4,
  68. .num_cq = 1 << 16,
  69. .num_mcg = 1 << 13,
  70. .num_mpt = 1 << 17,
  71. .num_mtt = 1 << 20,
  72. .num_udav = 1 << 15, /* Tavor only */
  73. .fmr_reserved_mtts = 1 << 18, /* Tavor only */
  74. .uarc_size = 1 << 18, /* Arbel only */
  75. };
  76. static int __devinit mthca_tune_pci(struct mthca_dev *mdev)
  77. {
  78. int cap;
  79. u16 val;
  80. /* First try to max out Read Byte Count */
  81. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
  82. if (cap) {
  83. if (pci_read_config_word(mdev->pdev, cap + PCI_X_CMD, &val)) {
  84. mthca_err(mdev, "Couldn't read PCI-X command register, "
  85. "aborting.\n");
  86. return -ENODEV;
  87. }
  88. val = (val & ~PCI_X_CMD_MAX_READ) | (3 << 2);
  89. if (pci_write_config_word(mdev->pdev, cap + PCI_X_CMD, val)) {
  90. mthca_err(mdev, "Couldn't write PCI-X command register, "
  91. "aborting.\n");
  92. return -ENODEV;
  93. }
  94. } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
  95. mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
  96. cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP);
  97. if (cap) {
  98. if (pci_read_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, &val)) {
  99. mthca_err(mdev, "Couldn't read PCI Express device control "
  100. "register, aborting.\n");
  101. return -ENODEV;
  102. }
  103. val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
  104. if (pci_write_config_word(mdev->pdev, cap + PCI_EXP_DEVCTL, val)) {
  105. mthca_err(mdev, "Couldn't write PCI Express device control "
  106. "register, aborting.\n");
  107. return -ENODEV;
  108. }
  109. } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
  110. mthca_info(mdev, "No PCI Express capability, "
  111. "not setting Max Read Request Size.\n");
  112. return 0;
  113. }
  114. static int __devinit mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
  115. {
  116. int err;
  117. u8 status;
  118. err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
  119. if (err) {
  120. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  121. return err;
  122. }
  123. if (status) {
  124. mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
  125. "aborting.\n", status);
  126. return -EINVAL;
  127. }
  128. if (dev_lim->min_page_sz > PAGE_SIZE) {
  129. mthca_err(mdev, "HCA minimum page size of %d bigger than "
  130. "kernel PAGE_SIZE of %ld, aborting.\n",
  131. dev_lim->min_page_sz, PAGE_SIZE);
  132. return -ENODEV;
  133. }
  134. if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
  135. mthca_err(mdev, "HCA has %d ports, but we only support %d, "
  136. "aborting.\n",
  137. dev_lim->num_ports, MTHCA_MAX_PORTS);
  138. return -ENODEV;
  139. }
  140. mdev->limits.num_ports = dev_lim->num_ports;
  141. mdev->limits.vl_cap = dev_lim->max_vl;
  142. mdev->limits.mtu_cap = dev_lim->max_mtu;
  143. mdev->limits.gid_table_len = dev_lim->max_gids;
  144. mdev->limits.pkey_table_len = dev_lim->max_pkeys;
  145. mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
  146. mdev->limits.max_sg = dev_lim->max_sg;
  147. mdev->limits.reserved_qps = dev_lim->reserved_qps;
  148. mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
  149. mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
  150. mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
  151. mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
  152. mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
  153. mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
  154. mdev->limits.reserved_uars = dev_lim->reserved_uars;
  155. mdev->limits.reserved_pds = dev_lim->reserved_pds;
  156. mdev->limits.port_width_cap = dev_lim->max_port_width;
  157. mdev->limits.flags = dev_lim->flags;
  158. /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
  159. May be doable since hardware supports it for SRQ.
  160. IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
  161. IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
  162. supported by driver. */
  163. mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  164. IB_DEVICE_PORT_ACTIVE_EVENT |
  165. IB_DEVICE_SYS_IMAGE_GUID |
  166. IB_DEVICE_RC_RNR_NAK_GEN;
  167. if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
  168. mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  169. if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
  170. mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  171. if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
  172. mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
  173. if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
  174. mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  175. if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
  176. mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  177. if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
  178. mdev->mthca_flags |= MTHCA_FLAG_SRQ;
  179. return 0;
  180. }
  181. static int __devinit mthca_init_tavor(struct mthca_dev *mdev)
  182. {
  183. u8 status;
  184. int err;
  185. struct mthca_dev_lim dev_lim;
  186. struct mthca_profile profile;
  187. struct mthca_init_hca_param init_hca;
  188. err = mthca_SYS_EN(mdev, &status);
  189. if (err) {
  190. mthca_err(mdev, "SYS_EN command failed, aborting.\n");
  191. return err;
  192. }
  193. if (status) {
  194. mthca_err(mdev, "SYS_EN returned status 0x%02x, "
  195. "aborting.\n", status);
  196. return -EINVAL;
  197. }
  198. err = mthca_QUERY_FW(mdev, &status);
  199. if (err) {
  200. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  201. goto err_disable;
  202. }
  203. if (status) {
  204. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  205. "aborting.\n", status);
  206. err = -EINVAL;
  207. goto err_disable;
  208. }
  209. err = mthca_QUERY_DDR(mdev, &status);
  210. if (err) {
  211. mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
  212. goto err_disable;
  213. }
  214. if (status) {
  215. mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
  216. "aborting.\n", status);
  217. err = -EINVAL;
  218. goto err_disable;
  219. }
  220. err = mthca_dev_lim(mdev, &dev_lim);
  221. profile = default_profile;
  222. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  223. profile.uarc_size = 0;
  224. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  225. profile.num_srq = dev_lim.max_srqs;
  226. err = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  227. if (err < 0)
  228. goto err_disable;
  229. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  230. if (err) {
  231. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  232. goto err_disable;
  233. }
  234. if (status) {
  235. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  236. "aborting.\n", status);
  237. err = -EINVAL;
  238. goto err_disable;
  239. }
  240. return 0;
  241. err_disable:
  242. mthca_SYS_DIS(mdev, &status);
  243. return err;
  244. }
  245. static int __devinit mthca_load_fw(struct mthca_dev *mdev)
  246. {
  247. u8 status;
  248. int err;
  249. /* FIXME: use HCA-attached memory for FW if present */
  250. mdev->fw.arbel.fw_icm =
  251. mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
  252. GFP_HIGHUSER | __GFP_NOWARN);
  253. if (!mdev->fw.arbel.fw_icm) {
  254. mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
  255. return -ENOMEM;
  256. }
  257. err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
  258. if (err) {
  259. mthca_err(mdev, "MAP_FA command failed, aborting.\n");
  260. goto err_free;
  261. }
  262. if (status) {
  263. mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
  264. err = -EINVAL;
  265. goto err_free;
  266. }
  267. err = mthca_RUN_FW(mdev, &status);
  268. if (err) {
  269. mthca_err(mdev, "RUN_FW command failed, aborting.\n");
  270. goto err_unmap_fa;
  271. }
  272. if (status) {
  273. mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
  274. err = -EINVAL;
  275. goto err_unmap_fa;
  276. }
  277. return 0;
  278. err_unmap_fa:
  279. mthca_UNMAP_FA(mdev, &status);
  280. err_free:
  281. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  282. return err;
  283. }
  284. static int __devinit mthca_init_icm(struct mthca_dev *mdev,
  285. struct mthca_dev_lim *dev_lim,
  286. struct mthca_init_hca_param *init_hca,
  287. u64 icm_size)
  288. {
  289. u64 aux_pages;
  290. u8 status;
  291. int err;
  292. err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
  293. if (err) {
  294. mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
  295. return err;
  296. }
  297. if (status) {
  298. mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
  299. "aborting.\n", status);
  300. return -EINVAL;
  301. }
  302. mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
  303. (unsigned long long) icm_size >> 10,
  304. (unsigned long long) aux_pages << 2);
  305. mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
  306. GFP_HIGHUSER | __GFP_NOWARN);
  307. if (!mdev->fw.arbel.aux_icm) {
  308. mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
  309. return -ENOMEM;
  310. }
  311. err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
  312. if (err) {
  313. mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
  314. goto err_free_aux;
  315. }
  316. if (status) {
  317. mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
  318. err = -EINVAL;
  319. goto err_free_aux;
  320. }
  321. err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
  322. if (err) {
  323. mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
  324. goto err_unmap_aux;
  325. }
  326. mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
  327. MTHCA_MTT_SEG_SIZE,
  328. mdev->limits.num_mtt_segs,
  329. mdev->limits.reserved_mtts, 1);
  330. if (!mdev->mr_table.mtt_table) {
  331. mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
  332. err = -ENOMEM;
  333. goto err_unmap_eq;
  334. }
  335. mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
  336. dev_lim->mpt_entry_sz,
  337. mdev->limits.num_mpts,
  338. mdev->limits.reserved_mrws, 1);
  339. if (!mdev->mr_table.mpt_table) {
  340. mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
  341. err = -ENOMEM;
  342. goto err_unmap_mtt;
  343. }
  344. mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
  345. dev_lim->qpc_entry_sz,
  346. mdev->limits.num_qps,
  347. mdev->limits.reserved_qps, 0);
  348. if (!mdev->qp_table.qp_table) {
  349. mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
  350. err = -ENOMEM;
  351. goto err_unmap_mpt;
  352. }
  353. mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
  354. dev_lim->eqpc_entry_sz,
  355. mdev->limits.num_qps,
  356. mdev->limits.reserved_qps, 0);
  357. if (!mdev->qp_table.eqp_table) {
  358. mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
  359. err = -ENOMEM;
  360. goto err_unmap_qp;
  361. }
  362. mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
  363. MTHCA_RDB_ENTRY_SIZE,
  364. mdev->limits.num_qps <<
  365. mdev->qp_table.rdb_shift,
  366. 0, 0);
  367. if (!mdev->qp_table.rdb_table) {
  368. mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
  369. err = -ENOMEM;
  370. goto err_unmap_eqp;
  371. }
  372. mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
  373. dev_lim->cqc_entry_sz,
  374. mdev->limits.num_cqs,
  375. mdev->limits.reserved_cqs, 0);
  376. if (!mdev->cq_table.table) {
  377. mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
  378. err = -ENOMEM;
  379. goto err_unmap_rdb;
  380. }
  381. if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
  382. mdev->srq_table.table =
  383. mthca_alloc_icm_table(mdev, init_hca->srqc_base,
  384. dev_lim->srq_entry_sz,
  385. mdev->limits.num_srqs,
  386. mdev->limits.reserved_srqs, 0);
  387. if (!mdev->srq_table.table) {
  388. mthca_err(mdev, "Failed to map SRQ context memory, "
  389. "aborting.\n");
  390. err = -ENOMEM;
  391. goto err_unmap_cq;
  392. }
  393. }
  394. /*
  395. * It's not strictly required, but for simplicity just map the
  396. * whole multicast group table now. The table isn't very big
  397. * and it's a lot easier than trying to track ref counts.
  398. */
  399. mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
  400. MTHCA_MGM_ENTRY_SIZE,
  401. mdev->limits.num_mgms +
  402. mdev->limits.num_amgms,
  403. mdev->limits.num_mgms +
  404. mdev->limits.num_amgms,
  405. 0);
  406. if (!mdev->mcg_table.table) {
  407. mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
  408. err = -ENOMEM;
  409. goto err_unmap_srq;
  410. }
  411. return 0;
  412. err_unmap_srq:
  413. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  414. mthca_free_icm_table(mdev, mdev->srq_table.table);
  415. err_unmap_cq:
  416. mthca_free_icm_table(mdev, mdev->cq_table.table);
  417. err_unmap_rdb:
  418. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  419. err_unmap_eqp:
  420. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  421. err_unmap_qp:
  422. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  423. err_unmap_mpt:
  424. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  425. err_unmap_mtt:
  426. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  427. err_unmap_eq:
  428. mthca_unmap_eq_icm(mdev);
  429. err_unmap_aux:
  430. mthca_UNMAP_ICM_AUX(mdev, &status);
  431. err_free_aux:
  432. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  433. return err;
  434. }
  435. static void mthca_free_icms(struct mthca_dev *mdev)
  436. {
  437. u8 status;
  438. mthca_free_icm_table(mdev, mdev->mcg_table.table);
  439. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  440. mthca_free_icm_table(mdev, mdev->srq_table.table);
  441. mthca_free_icm_table(mdev, mdev->cq_table.table);
  442. mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
  443. mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
  444. mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
  445. mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
  446. mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
  447. mthca_unmap_eq_icm(mdev);
  448. mthca_UNMAP_ICM_AUX(mdev, &status);
  449. mthca_free_icm(mdev, mdev->fw.arbel.aux_icm);
  450. }
  451. static int __devinit mthca_init_arbel(struct mthca_dev *mdev)
  452. {
  453. struct mthca_dev_lim dev_lim;
  454. struct mthca_profile profile;
  455. struct mthca_init_hca_param init_hca;
  456. u64 icm_size;
  457. u8 status;
  458. int err;
  459. err = mthca_QUERY_FW(mdev, &status);
  460. if (err) {
  461. mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
  462. return err;
  463. }
  464. if (status) {
  465. mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
  466. "aborting.\n", status);
  467. return -EINVAL;
  468. }
  469. err = mthca_ENABLE_LAM(mdev, &status);
  470. if (err) {
  471. mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
  472. return err;
  473. }
  474. if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
  475. mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
  476. mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
  477. } else if (status) {
  478. mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
  479. "aborting.\n", status);
  480. return -EINVAL;
  481. }
  482. err = mthca_load_fw(mdev);
  483. if (err) {
  484. mthca_err(mdev, "Failed to start FW, aborting.\n");
  485. goto err_disable;
  486. }
  487. err = mthca_dev_lim(mdev, &dev_lim);
  488. if (err) {
  489. mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
  490. goto err_stop_fw;
  491. }
  492. profile = default_profile;
  493. profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
  494. profile.num_udav = 0;
  495. if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
  496. profile.num_srq = dev_lim.max_srqs;
  497. icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
  498. if ((int) icm_size < 0) {
  499. err = icm_size;
  500. goto err_stop_fw;
  501. }
  502. err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
  503. if (err)
  504. goto err_stop_fw;
  505. err = mthca_INIT_HCA(mdev, &init_hca, &status);
  506. if (err) {
  507. mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
  508. goto err_free_icm;
  509. }
  510. if (status) {
  511. mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
  512. "aborting.\n", status);
  513. err = -EINVAL;
  514. goto err_free_icm;
  515. }
  516. return 0;
  517. err_free_icm:
  518. mthca_free_icms(mdev);
  519. err_stop_fw:
  520. mthca_UNMAP_FA(mdev, &status);
  521. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  522. err_disable:
  523. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  524. mthca_DISABLE_LAM(mdev, &status);
  525. return err;
  526. }
  527. static void mthca_close_hca(struct mthca_dev *mdev)
  528. {
  529. u8 status;
  530. mthca_CLOSE_HCA(mdev, 0, &status);
  531. if (mthca_is_memfree(mdev)) {
  532. mthca_free_icms(mdev);
  533. mthca_UNMAP_FA(mdev, &status);
  534. mthca_free_icm(mdev, mdev->fw.arbel.fw_icm);
  535. if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
  536. mthca_DISABLE_LAM(mdev, &status);
  537. } else
  538. mthca_SYS_DIS(mdev, &status);
  539. }
  540. static int __devinit mthca_init_hca(struct mthca_dev *mdev)
  541. {
  542. u8 status;
  543. int err;
  544. struct mthca_adapter adapter;
  545. if (mthca_is_memfree(mdev))
  546. err = mthca_init_arbel(mdev);
  547. else
  548. err = mthca_init_tavor(mdev);
  549. if (err)
  550. return err;
  551. err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
  552. if (err) {
  553. mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
  554. goto err_close;
  555. }
  556. if (status) {
  557. mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
  558. "aborting.\n", status);
  559. err = -EINVAL;
  560. goto err_close;
  561. }
  562. mdev->eq_table.inta_pin = adapter.inta_pin;
  563. mdev->rev_id = adapter.revision_id;
  564. memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
  565. return 0;
  566. err_close:
  567. mthca_close_hca(mdev);
  568. return err;
  569. }
  570. static int __devinit mthca_setup_hca(struct mthca_dev *dev)
  571. {
  572. int err;
  573. u8 status;
  574. MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
  575. err = mthca_init_uar_table(dev);
  576. if (err) {
  577. mthca_err(dev, "Failed to initialize "
  578. "user access region table, aborting.\n");
  579. return err;
  580. }
  581. err = mthca_uar_alloc(dev, &dev->driver_uar);
  582. if (err) {
  583. mthca_err(dev, "Failed to allocate driver access region, "
  584. "aborting.\n");
  585. goto err_uar_table_free;
  586. }
  587. dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
  588. if (!dev->kar) {
  589. mthca_err(dev, "Couldn't map kernel access region, "
  590. "aborting.\n");
  591. err = -ENOMEM;
  592. goto err_uar_free;
  593. }
  594. err = mthca_init_pd_table(dev);
  595. if (err) {
  596. mthca_err(dev, "Failed to initialize "
  597. "protection domain table, aborting.\n");
  598. goto err_kar_unmap;
  599. }
  600. err = mthca_init_mr_table(dev);
  601. if (err) {
  602. mthca_err(dev, "Failed to initialize "
  603. "memory region table, aborting.\n");
  604. goto err_pd_table_free;
  605. }
  606. err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
  607. if (err) {
  608. mthca_err(dev, "Failed to create driver PD, "
  609. "aborting.\n");
  610. goto err_mr_table_free;
  611. }
  612. err = mthca_init_eq_table(dev);
  613. if (err) {
  614. mthca_err(dev, "Failed to initialize "
  615. "event queue table, aborting.\n");
  616. goto err_pd_free;
  617. }
  618. err = mthca_cmd_use_events(dev);
  619. if (err) {
  620. mthca_err(dev, "Failed to switch to event-driven "
  621. "firmware commands, aborting.\n");
  622. goto err_eq_table_free;
  623. }
  624. err = mthca_NOP(dev, &status);
  625. if (err || status) {
  626. mthca_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting.\n",
  627. dev->mthca_flags & MTHCA_FLAG_MSI_X ?
  628. dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector :
  629. dev->pdev->irq);
  630. if (dev->mthca_flags & (MTHCA_FLAG_MSI | MTHCA_FLAG_MSI_X))
  631. mthca_err(dev, "Try again with MSI/MSI-X disabled.\n");
  632. else
  633. mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
  634. goto err_cmd_poll;
  635. }
  636. mthca_dbg(dev, "NOP command IRQ test passed\n");
  637. err = mthca_init_cq_table(dev);
  638. if (err) {
  639. mthca_err(dev, "Failed to initialize "
  640. "completion queue table, aborting.\n");
  641. goto err_cmd_poll;
  642. }
  643. err = mthca_init_srq_table(dev);
  644. if (err) {
  645. mthca_err(dev, "Failed to initialize "
  646. "shared receive queue table, aborting.\n");
  647. goto err_cq_table_free;
  648. }
  649. err = mthca_init_qp_table(dev);
  650. if (err) {
  651. mthca_err(dev, "Failed to initialize "
  652. "queue pair table, aborting.\n");
  653. goto err_srq_table_free;
  654. }
  655. err = mthca_init_av_table(dev);
  656. if (err) {
  657. mthca_err(dev, "Failed to initialize "
  658. "address vector table, aborting.\n");
  659. goto err_qp_table_free;
  660. }
  661. err = mthca_init_mcg_table(dev);
  662. if (err) {
  663. mthca_err(dev, "Failed to initialize "
  664. "multicast group table, aborting.\n");
  665. goto err_av_table_free;
  666. }
  667. return 0;
  668. err_av_table_free:
  669. mthca_cleanup_av_table(dev);
  670. err_qp_table_free:
  671. mthca_cleanup_qp_table(dev);
  672. err_srq_table_free:
  673. mthca_cleanup_srq_table(dev);
  674. err_cq_table_free:
  675. mthca_cleanup_cq_table(dev);
  676. err_cmd_poll:
  677. mthca_cmd_use_polling(dev);
  678. err_eq_table_free:
  679. mthca_cleanup_eq_table(dev);
  680. err_pd_free:
  681. mthca_pd_free(dev, &dev->driver_pd);
  682. err_mr_table_free:
  683. mthca_cleanup_mr_table(dev);
  684. err_pd_table_free:
  685. mthca_cleanup_pd_table(dev);
  686. err_kar_unmap:
  687. iounmap(dev->kar);
  688. err_uar_free:
  689. mthca_uar_free(dev, &dev->driver_uar);
  690. err_uar_table_free:
  691. mthca_cleanup_uar_table(dev);
  692. return err;
  693. }
  694. static int __devinit mthca_request_regions(struct pci_dev *pdev,
  695. int ddr_hidden)
  696. {
  697. int err;
  698. /*
  699. * We can't just use pci_request_regions() because the MSI-X
  700. * table is right in the middle of the first BAR. If we did
  701. * pci_request_region and grab all of the first BAR, then
  702. * setting up MSI-X would fail, since the PCI core wants to do
  703. * request_mem_region on the MSI-X vector table.
  704. *
  705. * So just request what we need right now, and request any
  706. * other regions we need when setting up EQs.
  707. */
  708. if (!request_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  709. MTHCA_HCR_SIZE, DRV_NAME))
  710. return -EBUSY;
  711. err = pci_request_region(pdev, 2, DRV_NAME);
  712. if (err)
  713. goto err_bar2_failed;
  714. if (!ddr_hidden) {
  715. err = pci_request_region(pdev, 4, DRV_NAME);
  716. if (err)
  717. goto err_bar4_failed;
  718. }
  719. return 0;
  720. err_bar4_failed:
  721. pci_release_region(pdev, 2);
  722. err_bar2_failed:
  723. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  724. MTHCA_HCR_SIZE);
  725. return err;
  726. }
  727. static void mthca_release_regions(struct pci_dev *pdev,
  728. int ddr_hidden)
  729. {
  730. if (!ddr_hidden)
  731. pci_release_region(pdev, 4);
  732. pci_release_region(pdev, 2);
  733. release_mem_region(pci_resource_start(pdev, 0) + MTHCA_HCR_BASE,
  734. MTHCA_HCR_SIZE);
  735. }
  736. static int __devinit mthca_enable_msi_x(struct mthca_dev *mdev)
  737. {
  738. struct msix_entry entries[3];
  739. int err;
  740. entries[0].entry = 0;
  741. entries[1].entry = 1;
  742. entries[2].entry = 2;
  743. err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
  744. if (err) {
  745. if (err > 0)
  746. mthca_info(mdev, "Only %d MSI-X vectors available, "
  747. "not using MSI-X\n", err);
  748. return err;
  749. }
  750. mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
  751. mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
  752. mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
  753. return 0;
  754. }
  755. /* Types of supported HCA */
  756. enum {
  757. TAVOR, /* MT23108 */
  758. ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
  759. ARBEL_NATIVE, /* MT25208 with extended features */
  760. SINAI /* MT25204 */
  761. };
  762. #define MTHCA_FW_VER(major, minor, subminor) \
  763. (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
  764. static struct {
  765. u64 latest_fw;
  766. int is_memfree;
  767. int is_pcie;
  768. } mthca_hca_table[] = {
  769. [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 3, 3), .is_memfree = 0, .is_pcie = 0 },
  770. [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 7, 0), .is_memfree = 0, .is_pcie = 1 },
  771. [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 1, 0), .is_memfree = 1, .is_pcie = 1 },
  772. [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 0, 1), .is_memfree = 1, .is_pcie = 1 }
  773. };
  774. static int __devinit mthca_init_one(struct pci_dev *pdev,
  775. const struct pci_device_id *id)
  776. {
  777. static int mthca_version_printed = 0;
  778. int ddr_hidden = 0;
  779. int err;
  780. struct mthca_dev *mdev;
  781. if (!mthca_version_printed) {
  782. printk(KERN_INFO "%s", mthca_version);
  783. ++mthca_version_printed;
  784. }
  785. printk(KERN_INFO PFX "Initializing %s\n",
  786. pci_name(pdev));
  787. if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
  788. printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
  789. pci_name(pdev), id->driver_data);
  790. return -ENODEV;
  791. }
  792. err = pci_enable_device(pdev);
  793. if (err) {
  794. dev_err(&pdev->dev, "Cannot enable PCI device, "
  795. "aborting.\n");
  796. return err;
  797. }
  798. /*
  799. * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
  800. * be present)
  801. */
  802. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
  803. pci_resource_len(pdev, 0) != 1 << 20) {
  804. dev_err(&pdev->dev, "Missing DCS, aborting.\n");
  805. err = -ENODEV;
  806. goto err_disable_pdev;
  807. }
  808. if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM) ||
  809. pci_resource_len(pdev, 2) != 1 << 23) {
  810. dev_err(&pdev->dev, "Missing UAR, aborting.\n");
  811. err = -ENODEV;
  812. goto err_disable_pdev;
  813. }
  814. if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
  815. ddr_hidden = 1;
  816. err = mthca_request_regions(pdev, ddr_hidden);
  817. if (err) {
  818. dev_err(&pdev->dev, "Cannot obtain PCI resources, "
  819. "aborting.\n");
  820. goto err_disable_pdev;
  821. }
  822. pci_set_master(pdev);
  823. err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  824. if (err) {
  825. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
  826. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  827. if (err) {
  828. dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
  829. goto err_free_res;
  830. }
  831. }
  832. err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
  833. if (err) {
  834. dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
  835. "consistent PCI DMA mask.\n");
  836. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  837. if (err) {
  838. dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
  839. "aborting.\n");
  840. goto err_free_res;
  841. }
  842. }
  843. mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
  844. if (!mdev) {
  845. dev_err(&pdev->dev, "Device struct alloc failed, "
  846. "aborting.\n");
  847. err = -ENOMEM;
  848. goto err_free_res;
  849. }
  850. mdev->pdev = pdev;
  851. if (ddr_hidden)
  852. mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
  853. if (mthca_hca_table[id->driver_data].is_memfree)
  854. mdev->mthca_flags |= MTHCA_FLAG_MEMFREE;
  855. if (mthca_hca_table[id->driver_data].is_pcie)
  856. mdev->mthca_flags |= MTHCA_FLAG_PCIE;
  857. /*
  858. * Now reset the HCA before we touch the PCI capabilities or
  859. * attempt a firmware command, since a boot ROM may have left
  860. * the HCA in an undefined state.
  861. */
  862. err = mthca_reset(mdev);
  863. if (err) {
  864. mthca_err(mdev, "Failed to reset HCA, aborting.\n");
  865. goto err_free_dev;
  866. }
  867. if (msi_x && !mthca_enable_msi_x(mdev))
  868. mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
  869. if (msi && !(mdev->mthca_flags & MTHCA_FLAG_MSI_X) &&
  870. !pci_enable_msi(pdev))
  871. mdev->mthca_flags |= MTHCA_FLAG_MSI;
  872. if (mthca_cmd_init(mdev)) {
  873. mthca_err(mdev, "Failed to init command interface, aborting.\n");
  874. goto err_free_dev;
  875. }
  876. err = mthca_tune_pci(mdev);
  877. if (err)
  878. goto err_cmd;
  879. err = mthca_init_hca(mdev);
  880. if (err)
  881. goto err_cmd;
  882. if (mdev->fw_ver < mthca_hca_table[id->driver_data].latest_fw) {
  883. mthca_warn(mdev, "HCA FW version %x.%x.%x is old (%x.%x.%x is current).\n",
  884. (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
  885. (int) (mdev->fw_ver & 0xffff),
  886. (int) (mthca_hca_table[id->driver_data].latest_fw >> 32),
  887. (int) (mthca_hca_table[id->driver_data].latest_fw >> 16) & 0xffff,
  888. (int) (mthca_hca_table[id->driver_data].latest_fw & 0xffff));
  889. mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
  890. }
  891. err = mthca_setup_hca(mdev);
  892. if (err)
  893. goto err_close;
  894. err = mthca_register_device(mdev);
  895. if (err)
  896. goto err_cleanup;
  897. err = mthca_create_agents(mdev);
  898. if (err)
  899. goto err_unregister;
  900. pci_set_drvdata(pdev, mdev);
  901. return 0;
  902. err_unregister:
  903. mthca_unregister_device(mdev);
  904. err_cleanup:
  905. mthca_cleanup_mcg_table(mdev);
  906. mthca_cleanup_av_table(mdev);
  907. mthca_cleanup_qp_table(mdev);
  908. mthca_cleanup_srq_table(mdev);
  909. mthca_cleanup_cq_table(mdev);
  910. mthca_cmd_use_polling(mdev);
  911. mthca_cleanup_eq_table(mdev);
  912. mthca_pd_free(mdev, &mdev->driver_pd);
  913. mthca_cleanup_mr_table(mdev);
  914. mthca_cleanup_pd_table(mdev);
  915. mthca_cleanup_uar_table(mdev);
  916. err_close:
  917. mthca_close_hca(mdev);
  918. err_cmd:
  919. mthca_cmd_cleanup(mdev);
  920. err_free_dev:
  921. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  922. pci_disable_msix(pdev);
  923. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  924. pci_disable_msi(pdev);
  925. ib_dealloc_device(&mdev->ib_dev);
  926. err_free_res:
  927. mthca_release_regions(pdev, ddr_hidden);
  928. err_disable_pdev:
  929. pci_disable_device(pdev);
  930. pci_set_drvdata(pdev, NULL);
  931. return err;
  932. }
  933. static void __devexit mthca_remove_one(struct pci_dev *pdev)
  934. {
  935. struct mthca_dev *mdev = pci_get_drvdata(pdev);
  936. u8 status;
  937. int p;
  938. if (mdev) {
  939. mthca_free_agents(mdev);
  940. mthca_unregister_device(mdev);
  941. for (p = 1; p <= mdev->limits.num_ports; ++p)
  942. mthca_CLOSE_IB(mdev, p, &status);
  943. mthca_cleanup_mcg_table(mdev);
  944. mthca_cleanup_av_table(mdev);
  945. mthca_cleanup_qp_table(mdev);
  946. mthca_cleanup_srq_table(mdev);
  947. mthca_cleanup_cq_table(mdev);
  948. mthca_cmd_use_polling(mdev);
  949. mthca_cleanup_eq_table(mdev);
  950. mthca_pd_free(mdev, &mdev->driver_pd);
  951. mthca_cleanup_mr_table(mdev);
  952. mthca_cleanup_pd_table(mdev);
  953. iounmap(mdev->kar);
  954. mthca_uar_free(mdev, &mdev->driver_uar);
  955. mthca_cleanup_uar_table(mdev);
  956. mthca_close_hca(mdev);
  957. mthca_cmd_cleanup(mdev);
  958. if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
  959. pci_disable_msix(pdev);
  960. if (mdev->mthca_flags & MTHCA_FLAG_MSI)
  961. pci_disable_msi(pdev);
  962. ib_dealloc_device(&mdev->ib_dev);
  963. mthca_release_regions(pdev, mdev->mthca_flags &
  964. MTHCA_FLAG_DDR_HIDDEN);
  965. pci_disable_device(pdev);
  966. pci_set_drvdata(pdev, NULL);
  967. }
  968. }
  969. static struct pci_device_id mthca_pci_table[] = {
  970. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
  971. .driver_data = TAVOR },
  972. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
  973. .driver_data = TAVOR },
  974. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  975. .driver_data = ARBEL_COMPAT },
  976. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
  977. .driver_data = ARBEL_COMPAT },
  978. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
  979. .driver_data = ARBEL_NATIVE },
  980. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
  981. .driver_data = ARBEL_NATIVE },
  982. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
  983. .driver_data = SINAI },
  984. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
  985. .driver_data = SINAI },
  986. { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  987. .driver_data = SINAI },
  988. { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
  989. .driver_data = SINAI },
  990. { 0, }
  991. };
  992. MODULE_DEVICE_TABLE(pci, mthca_pci_table);
  993. static struct pci_driver mthca_driver = {
  994. .name = DRV_NAME,
  995. .id_table = mthca_pci_table,
  996. .probe = mthca_init_one,
  997. .remove = __devexit_p(mthca_remove_one)
  998. };
  999. static int __init mthca_init(void)
  1000. {
  1001. int ret;
  1002. ret = pci_register_driver(&mthca_driver);
  1003. return ret < 0 ? ret : 0;
  1004. }
  1005. static void __exit mthca_cleanup(void)
  1006. {
  1007. pci_unregister_driver(&mthca_driver);
  1008. }
  1009. module_init(mthca_init);
  1010. module_exit(mthca_cleanup);