netxen_nic_init.c 39 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR (0xffffffff)
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  50. uint32_t ctx, uint32_t ringid);
  51. #if 0
  52. static void netxen_nic_locked_write_reg(struct netxen_adapter *adapter,
  53. unsigned long off, int *data)
  54. {
  55. void __iomem *addr = pci_base_offset(adapter, off);
  56. writel(*data, addr);
  57. }
  58. #endif /* 0 */
  59. static void crb_addr_transform_setup(void)
  60. {
  61. crb_addr_transform(XDMA);
  62. crb_addr_transform(TIMR);
  63. crb_addr_transform(SRE);
  64. crb_addr_transform(SQN3);
  65. crb_addr_transform(SQN2);
  66. crb_addr_transform(SQN1);
  67. crb_addr_transform(SQN0);
  68. crb_addr_transform(SQS3);
  69. crb_addr_transform(SQS2);
  70. crb_addr_transform(SQS1);
  71. crb_addr_transform(SQS0);
  72. crb_addr_transform(RPMX7);
  73. crb_addr_transform(RPMX6);
  74. crb_addr_transform(RPMX5);
  75. crb_addr_transform(RPMX4);
  76. crb_addr_transform(RPMX3);
  77. crb_addr_transform(RPMX2);
  78. crb_addr_transform(RPMX1);
  79. crb_addr_transform(RPMX0);
  80. crb_addr_transform(ROMUSB);
  81. crb_addr_transform(SN);
  82. crb_addr_transform(QMN);
  83. crb_addr_transform(QMS);
  84. crb_addr_transform(PGNI);
  85. crb_addr_transform(PGND);
  86. crb_addr_transform(PGN3);
  87. crb_addr_transform(PGN2);
  88. crb_addr_transform(PGN1);
  89. crb_addr_transform(PGN0);
  90. crb_addr_transform(PGSI);
  91. crb_addr_transform(PGSD);
  92. crb_addr_transform(PGS3);
  93. crb_addr_transform(PGS2);
  94. crb_addr_transform(PGS1);
  95. crb_addr_transform(PGS0);
  96. crb_addr_transform(PS);
  97. crb_addr_transform(PH);
  98. crb_addr_transform(NIU);
  99. crb_addr_transform(I2Q);
  100. crb_addr_transform(EG);
  101. crb_addr_transform(MN);
  102. crb_addr_transform(MS);
  103. crb_addr_transform(CAS2);
  104. crb_addr_transform(CAS1);
  105. crb_addr_transform(CAS0);
  106. crb_addr_transform(CAM);
  107. crb_addr_transform(C2C1);
  108. crb_addr_transform(C2C0);
  109. crb_addr_transform(SMB);
  110. crb_addr_transform(OCM0);
  111. crb_addr_transform(I2C0);
  112. }
  113. int netxen_init_firmware(struct netxen_adapter *adapter)
  114. {
  115. u32 state = 0, loops = 0, err = 0;
  116. /* Window 1 call */
  117. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  118. if (state == PHAN_INITIALIZE_ACK)
  119. return 0;
  120. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  121. msleep(1);
  122. /* Window 1 call */
  123. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  124. loops++;
  125. }
  126. if (loops >= 2000) {
  127. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  128. state);
  129. err = -EIO;
  130. return err;
  131. }
  132. /* Window 1 call */
  133. adapter->pci_write_normalize(adapter,
  134. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  135. adapter->pci_write_normalize(adapter,
  136. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  137. adapter->pci_write_normalize(adapter,
  138. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  139. adapter->pci_write_normalize(adapter,
  140. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  141. return err;
  142. }
  143. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  144. {
  145. struct netxen_recv_context *recv_ctx;
  146. struct nx_host_rds_ring *rds_ring;
  147. struct netxen_rx_buffer *rx_buf;
  148. int i, ctxid, ring;
  149. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  150. recv_ctx = &adapter->recv_ctx[ctxid];
  151. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  152. rds_ring = &recv_ctx->rds_rings[ring];
  153. for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
  154. rx_buf = &(rds_ring->rx_buf_arr[i]);
  155. if (rx_buf->state == NETXEN_BUFFER_FREE)
  156. continue;
  157. pci_unmap_single(adapter->pdev,
  158. rx_buf->dma,
  159. rds_ring->dma_size,
  160. PCI_DMA_FROMDEVICE);
  161. if (rx_buf->skb != NULL)
  162. dev_kfree_skb_any(rx_buf->skb);
  163. }
  164. }
  165. }
  166. }
  167. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  168. {
  169. struct netxen_cmd_buffer *cmd_buf;
  170. struct netxen_skb_frag *buffrag;
  171. int i, j;
  172. cmd_buf = adapter->cmd_buf_arr;
  173. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  174. buffrag = cmd_buf->frag_array;
  175. if (buffrag->dma) {
  176. pci_unmap_single(adapter->pdev, buffrag->dma,
  177. buffrag->length, PCI_DMA_TODEVICE);
  178. buffrag->dma = 0ULL;
  179. }
  180. for (j = 0; j < cmd_buf->frag_count; j++) {
  181. buffrag++;
  182. if (buffrag->dma) {
  183. pci_unmap_page(adapter->pdev, buffrag->dma,
  184. buffrag->length,
  185. PCI_DMA_TODEVICE);
  186. buffrag->dma = 0ULL;
  187. }
  188. }
  189. /* Free the skb we received in netxen_nic_xmit_frame */
  190. if (cmd_buf->skb) {
  191. dev_kfree_skb_any(cmd_buf->skb);
  192. cmd_buf->skb = NULL;
  193. }
  194. cmd_buf++;
  195. }
  196. }
  197. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  198. {
  199. struct netxen_recv_context *recv_ctx;
  200. struct nx_host_rds_ring *rds_ring;
  201. int ctx, ring;
  202. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  203. recv_ctx = &adapter->recv_ctx[ctx];
  204. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  205. rds_ring = &recv_ctx->rds_rings[ring];
  206. if (rds_ring->rx_buf_arr) {
  207. vfree(rds_ring->rx_buf_arr);
  208. rds_ring->rx_buf_arr = NULL;
  209. }
  210. }
  211. }
  212. if (adapter->cmd_buf_arr)
  213. vfree(adapter->cmd_buf_arr);
  214. return;
  215. }
  216. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  217. {
  218. struct netxen_recv_context *recv_ctx;
  219. struct nx_host_rds_ring *rds_ring;
  220. struct netxen_rx_buffer *rx_buf;
  221. int ctx, ring, i, num_rx_bufs;
  222. struct netxen_cmd_buffer *cmd_buf_arr;
  223. struct net_device *netdev = adapter->netdev;
  224. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  225. if (cmd_buf_arr == NULL) {
  226. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  227. netdev->name);
  228. return -ENOMEM;
  229. }
  230. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  231. adapter->cmd_buf_arr = cmd_buf_arr;
  232. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  233. recv_ctx = &adapter->recv_ctx[ctx];
  234. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  235. rds_ring = &recv_ctx->rds_rings[ring];
  236. switch (RCV_DESC_TYPE(ring)) {
  237. case RCV_DESC_NORMAL:
  238. rds_ring->max_rx_desc_count =
  239. adapter->max_rx_desc_count;
  240. rds_ring->flags = RCV_DESC_NORMAL;
  241. if (adapter->ahw.cut_through) {
  242. rds_ring->dma_size =
  243. NX_CT_DEFAULT_RX_BUF_LEN;
  244. rds_ring->skb_size =
  245. NX_CT_DEFAULT_RX_BUF_LEN;
  246. } else {
  247. rds_ring->dma_size = RX_DMA_MAP_LEN;
  248. rds_ring->skb_size =
  249. MAX_RX_BUFFER_LENGTH;
  250. }
  251. break;
  252. case RCV_DESC_JUMBO:
  253. rds_ring->max_rx_desc_count =
  254. adapter->max_jumbo_rx_desc_count;
  255. rds_ring->flags = RCV_DESC_JUMBO;
  256. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  257. rds_ring->dma_size =
  258. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  259. else
  260. rds_ring->dma_size =
  261. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  262. rds_ring->skb_size =
  263. rds_ring->dma_size + NET_IP_ALIGN;
  264. break;
  265. case RCV_RING_LRO:
  266. rds_ring->max_rx_desc_count =
  267. adapter->max_lro_rx_desc_count;
  268. rds_ring->flags = RCV_DESC_LRO;
  269. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  270. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  271. break;
  272. }
  273. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  274. vmalloc(RCV_BUFFSIZE);
  275. if (rds_ring->rx_buf_arr == NULL) {
  276. printk(KERN_ERR "%s: Failed to allocate "
  277. "rx buffer ring %d\n",
  278. netdev->name, ring);
  279. /* free whatever was already allocated */
  280. goto err_out;
  281. }
  282. memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
  283. INIT_LIST_HEAD(&rds_ring->free_list);
  284. rds_ring->begin_alloc = 0;
  285. /*
  286. * Now go through all of them, set reference handles
  287. * and put them in the queues.
  288. */
  289. num_rx_bufs = rds_ring->max_rx_desc_count;
  290. rx_buf = rds_ring->rx_buf_arr;
  291. for (i = 0; i < num_rx_bufs; i++) {
  292. list_add_tail(&rx_buf->list,
  293. &rds_ring->free_list);
  294. rx_buf->ref_handle = i;
  295. rx_buf->state = NETXEN_BUFFER_FREE;
  296. rx_buf++;
  297. }
  298. }
  299. }
  300. return 0;
  301. err_out:
  302. netxen_free_sw_resources(adapter);
  303. return -ENOMEM;
  304. }
  305. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  306. {
  307. switch (adapter->ahw.board_type) {
  308. case NETXEN_NIC_GBE:
  309. adapter->enable_phy_interrupts =
  310. netxen_niu_gbe_enable_phy_interrupts;
  311. adapter->disable_phy_interrupts =
  312. netxen_niu_gbe_disable_phy_interrupts;
  313. adapter->macaddr_set = netxen_niu_macaddr_set;
  314. adapter->set_mtu = netxen_nic_set_mtu_gb;
  315. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  316. adapter->phy_read = netxen_niu_gbe_phy_read;
  317. adapter->phy_write = netxen_niu_gbe_phy_write;
  318. adapter->init_port = netxen_niu_gbe_init_port;
  319. adapter->stop_port = netxen_niu_disable_gbe_port;
  320. break;
  321. case NETXEN_NIC_XGBE:
  322. adapter->enable_phy_interrupts =
  323. netxen_niu_xgbe_enable_phy_interrupts;
  324. adapter->disable_phy_interrupts =
  325. netxen_niu_xgbe_disable_phy_interrupts;
  326. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  327. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  328. adapter->init_port = netxen_niu_xg_init_port;
  329. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  330. adapter->stop_port = netxen_niu_disable_xg_port;
  331. break;
  332. default:
  333. break;
  334. }
  335. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  336. adapter->set_mtu = nx_fw_cmd_set_mtu;
  337. adapter->set_promisc = netxen_p3_nic_set_promisc;
  338. }
  339. }
  340. /*
  341. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  342. * address to external PCI CRB address.
  343. */
  344. static u32 netxen_decode_crb_addr(u32 addr)
  345. {
  346. int i;
  347. u32 base_addr, offset, pci_base;
  348. crb_addr_transform_setup();
  349. pci_base = NETXEN_ADDR_ERROR;
  350. base_addr = addr & 0xfff00000;
  351. offset = addr & 0x000fffff;
  352. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  353. if (crb_addr_xform[i] == base_addr) {
  354. pci_base = i << 20;
  355. break;
  356. }
  357. }
  358. if (pci_base == NETXEN_ADDR_ERROR)
  359. return pci_base;
  360. else
  361. return (pci_base + offset);
  362. }
  363. static long rom_max_timeout = 100;
  364. static long rom_lock_timeout = 10000;
  365. #if 0
  366. static long rom_write_timeout = 700;
  367. #endif
  368. static int rom_lock(struct netxen_adapter *adapter)
  369. {
  370. int iter;
  371. u32 done = 0;
  372. int timeout = 0;
  373. while (!done) {
  374. /* acquire semaphore2 from PCI HW block */
  375. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  376. &done);
  377. if (done == 1)
  378. break;
  379. if (timeout >= rom_lock_timeout)
  380. return -EIO;
  381. timeout++;
  382. /*
  383. * Yield CPU
  384. */
  385. if (!in_atomic())
  386. schedule();
  387. else {
  388. for (iter = 0; iter < 20; iter++)
  389. cpu_relax(); /*This a nop instr on i386 */
  390. }
  391. }
  392. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  393. return 0;
  394. }
  395. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  396. {
  397. long timeout = 0;
  398. long done = 0;
  399. while (done == 0) {
  400. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  401. done &= 2;
  402. timeout++;
  403. if (timeout >= rom_max_timeout) {
  404. printk("Timeout reached waiting for rom done");
  405. return -EIO;
  406. }
  407. }
  408. return 0;
  409. }
  410. #if 0
  411. static int netxen_rom_wren(struct netxen_adapter *adapter)
  412. {
  413. /* Set write enable latch in ROM status register */
  414. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  415. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  416. M25P_INSTR_WREN);
  417. if (netxen_wait_rom_done(adapter)) {
  418. return -1;
  419. }
  420. return 0;
  421. }
  422. static unsigned int netxen_rdcrbreg(struct netxen_adapter *adapter,
  423. unsigned int addr)
  424. {
  425. unsigned int data = 0xdeaddead;
  426. data = netxen_nic_reg_read(adapter, addr);
  427. return data;
  428. }
  429. static int netxen_do_rom_rdsr(struct netxen_adapter *adapter)
  430. {
  431. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  432. M25P_INSTR_RDSR);
  433. if (netxen_wait_rom_done(adapter)) {
  434. return -1;
  435. }
  436. return netxen_rdcrbreg(adapter, NETXEN_ROMUSB_ROM_RDATA);
  437. }
  438. #endif
  439. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  440. {
  441. u32 val;
  442. /* release semaphore2 */
  443. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  444. }
  445. #if 0
  446. static int netxen_rom_wip_poll(struct netxen_adapter *adapter)
  447. {
  448. long timeout = 0;
  449. long wip = 1;
  450. int val;
  451. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  452. while (wip != 0) {
  453. val = netxen_do_rom_rdsr(adapter);
  454. wip = val & 1;
  455. timeout++;
  456. if (timeout > rom_max_timeout) {
  457. return -1;
  458. }
  459. }
  460. return 0;
  461. }
  462. static int do_rom_fast_write(struct netxen_adapter *adapter, int addr,
  463. int data)
  464. {
  465. if (netxen_rom_wren(adapter)) {
  466. return -1;
  467. }
  468. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  469. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  470. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  471. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  472. M25P_INSTR_PP);
  473. if (netxen_wait_rom_done(adapter)) {
  474. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  475. return -1;
  476. }
  477. return netxen_rom_wip_poll(adapter);
  478. }
  479. #endif
  480. static int do_rom_fast_read(struct netxen_adapter *adapter,
  481. int addr, int *valp)
  482. {
  483. cond_resched();
  484. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  485. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  486. udelay(100); /* prevent bursting on CRB */
  487. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  488. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  489. if (netxen_wait_rom_done(adapter)) {
  490. printk("Error waiting for rom done\n");
  491. return -EIO;
  492. }
  493. /* reset abyte_cnt and dummy_byte_cnt */
  494. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  495. udelay(100); /* prevent bursting on CRB */
  496. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  497. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  498. return 0;
  499. }
  500. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  501. u8 *bytes, size_t size)
  502. {
  503. int addridx;
  504. int ret = 0;
  505. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  506. int v;
  507. ret = do_rom_fast_read(adapter, addridx, &v);
  508. if (ret != 0)
  509. break;
  510. *(__le32 *)bytes = cpu_to_le32(v);
  511. bytes += 4;
  512. }
  513. return ret;
  514. }
  515. int
  516. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  517. u8 *bytes, size_t size)
  518. {
  519. int ret;
  520. ret = rom_lock(adapter);
  521. if (ret < 0)
  522. return ret;
  523. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  524. netxen_rom_unlock(adapter);
  525. return ret;
  526. }
  527. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  528. {
  529. int ret;
  530. if (rom_lock(adapter) != 0)
  531. return -EIO;
  532. ret = do_rom_fast_read(adapter, addr, valp);
  533. netxen_rom_unlock(adapter);
  534. return ret;
  535. }
  536. #if 0
  537. int netxen_rom_fast_write(struct netxen_adapter *adapter, int addr, int data)
  538. {
  539. int ret = 0;
  540. if (rom_lock(adapter) != 0) {
  541. return -1;
  542. }
  543. ret = do_rom_fast_write(adapter, addr, data);
  544. netxen_rom_unlock(adapter);
  545. return ret;
  546. }
  547. static int do_rom_fast_write_words(struct netxen_adapter *adapter,
  548. int addr, u8 *bytes, size_t size)
  549. {
  550. int addridx = addr;
  551. int ret = 0;
  552. while (addridx < (addr + size)) {
  553. int last_attempt = 0;
  554. int timeout = 0;
  555. int data;
  556. data = le32_to_cpu((*(__le32*)bytes));
  557. ret = do_rom_fast_write(adapter, addridx, data);
  558. if (ret < 0)
  559. return ret;
  560. while(1) {
  561. int data1;
  562. ret = do_rom_fast_read(adapter, addridx, &data1);
  563. if (ret < 0)
  564. return ret;
  565. if (data1 == data)
  566. break;
  567. if (timeout++ >= rom_write_timeout) {
  568. if (last_attempt++ < 4) {
  569. ret = do_rom_fast_write(adapter,
  570. addridx, data);
  571. if (ret < 0)
  572. return ret;
  573. }
  574. else {
  575. printk(KERN_INFO "Data write did not "
  576. "succeed at address 0x%x\n", addridx);
  577. break;
  578. }
  579. }
  580. }
  581. bytes += 4;
  582. addridx += 4;
  583. }
  584. return ret;
  585. }
  586. int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
  587. u8 *bytes, size_t size)
  588. {
  589. int ret = 0;
  590. ret = rom_lock(adapter);
  591. if (ret < 0)
  592. return ret;
  593. ret = do_rom_fast_write_words(adapter, addr, bytes, size);
  594. netxen_rom_unlock(adapter);
  595. return ret;
  596. }
  597. static int netxen_rom_wrsr(struct netxen_adapter *adapter, int data)
  598. {
  599. int ret;
  600. ret = netxen_rom_wren(adapter);
  601. if (ret < 0)
  602. return ret;
  603. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_ROM_WDATA, data);
  604. netxen_crb_writelit_adapter(adapter,
  605. NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0x1);
  606. ret = netxen_wait_rom_done(adapter);
  607. if (ret < 0)
  608. return ret;
  609. return netxen_rom_wip_poll(adapter);
  610. }
  611. static int netxen_rom_rdsr(struct netxen_adapter *adapter)
  612. {
  613. int ret;
  614. ret = rom_lock(adapter);
  615. if (ret < 0)
  616. return ret;
  617. ret = netxen_do_rom_rdsr(adapter);
  618. netxen_rom_unlock(adapter);
  619. return ret;
  620. }
  621. int netxen_backup_crbinit(struct netxen_adapter *adapter)
  622. {
  623. int ret = FLASH_SUCCESS;
  624. int val;
  625. char *buffer = kmalloc(NETXEN_FLASH_SECTOR_SIZE, GFP_KERNEL);
  626. if (!buffer)
  627. return -ENOMEM;
  628. /* unlock sector 63 */
  629. val = netxen_rom_rdsr(adapter);
  630. val = val & 0xe3;
  631. ret = netxen_rom_wrsr(adapter, val);
  632. if (ret != FLASH_SUCCESS)
  633. goto out_kfree;
  634. ret = netxen_rom_wip_poll(adapter);
  635. if (ret != FLASH_SUCCESS)
  636. goto out_kfree;
  637. /* copy sector 0 to sector 63 */
  638. ret = netxen_rom_fast_read_words(adapter, NETXEN_CRBINIT_START,
  639. buffer, NETXEN_FLASH_SECTOR_SIZE);
  640. if (ret != FLASH_SUCCESS)
  641. goto out_kfree;
  642. ret = netxen_rom_fast_write_words(adapter, NETXEN_FIXED_START,
  643. buffer, NETXEN_FLASH_SECTOR_SIZE);
  644. if (ret != FLASH_SUCCESS)
  645. goto out_kfree;
  646. /* lock sector 63 */
  647. val = netxen_rom_rdsr(adapter);
  648. if (!(val & 0x8)) {
  649. val |= (0x1 << 2);
  650. /* lock sector 63 */
  651. if (netxen_rom_wrsr(adapter, val) == 0) {
  652. ret = netxen_rom_wip_poll(adapter);
  653. if (ret != FLASH_SUCCESS)
  654. goto out_kfree;
  655. /* lock SR writes */
  656. ret = netxen_rom_wip_poll(adapter);
  657. if (ret != FLASH_SUCCESS)
  658. goto out_kfree;
  659. }
  660. }
  661. out_kfree:
  662. kfree(buffer);
  663. return ret;
  664. }
  665. static int netxen_do_rom_se(struct netxen_adapter *adapter, int addr)
  666. {
  667. netxen_rom_wren(adapter);
  668. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  669. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  670. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE,
  671. M25P_INSTR_SE);
  672. if (netxen_wait_rom_done(adapter)) {
  673. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  674. return -1;
  675. }
  676. return netxen_rom_wip_poll(adapter);
  677. }
  678. static void check_erased_flash(struct netxen_adapter *adapter, int addr)
  679. {
  680. int i;
  681. int val;
  682. int count = 0, erased_errors = 0;
  683. int range;
  684. range = (addr == NETXEN_USER_START) ?
  685. NETXEN_FIXED_START : addr + NETXEN_FLASH_SECTOR_SIZE;
  686. for (i = addr; i < range; i += 4) {
  687. netxen_rom_fast_read(adapter, i, &val);
  688. if (val != 0xffffffff)
  689. erased_errors++;
  690. count++;
  691. }
  692. if (erased_errors)
  693. printk(KERN_INFO "0x%x out of 0x%x words fail to be erased "
  694. "for sector address: %x\n", erased_errors, count, addr);
  695. }
  696. int netxen_rom_se(struct netxen_adapter *adapter, int addr)
  697. {
  698. int ret = 0;
  699. if (rom_lock(adapter) != 0) {
  700. return -1;
  701. }
  702. ret = netxen_do_rom_se(adapter, addr);
  703. netxen_rom_unlock(adapter);
  704. msleep(30);
  705. check_erased_flash(adapter, addr);
  706. return ret;
  707. }
  708. static int netxen_flash_erase_sections(struct netxen_adapter *adapter,
  709. int start, int end)
  710. {
  711. int ret = FLASH_SUCCESS;
  712. int i;
  713. for (i = start; i < end; i++) {
  714. ret = netxen_rom_se(adapter, i * NETXEN_FLASH_SECTOR_SIZE);
  715. if (ret)
  716. break;
  717. ret = netxen_rom_wip_poll(adapter);
  718. if (ret < 0)
  719. return ret;
  720. }
  721. return ret;
  722. }
  723. int
  724. netxen_flash_erase_secondary(struct netxen_adapter *adapter)
  725. {
  726. int ret = FLASH_SUCCESS;
  727. int start, end;
  728. start = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  729. end = NETXEN_USER_START / NETXEN_FLASH_SECTOR_SIZE;
  730. ret = netxen_flash_erase_sections(adapter, start, end);
  731. return ret;
  732. }
  733. int
  734. netxen_flash_erase_primary(struct netxen_adapter *adapter)
  735. {
  736. int ret = FLASH_SUCCESS;
  737. int start, end;
  738. start = NETXEN_PRIMARY_START / NETXEN_FLASH_SECTOR_SIZE;
  739. end = NETXEN_SECONDARY_START / NETXEN_FLASH_SECTOR_SIZE;
  740. ret = netxen_flash_erase_sections(adapter, start, end);
  741. return ret;
  742. }
  743. void netxen_halt_pegs(struct netxen_adapter *adapter)
  744. {
  745. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x3c, 1);
  746. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x3c, 1);
  747. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x3c, 1);
  748. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x3c, 1);
  749. }
  750. int netxen_flash_unlock(struct netxen_adapter *adapter)
  751. {
  752. int ret = 0;
  753. ret = netxen_rom_wrsr(adapter, 0);
  754. if (ret < 0)
  755. return ret;
  756. ret = netxen_rom_wren(adapter);
  757. if (ret < 0)
  758. return ret;
  759. return ret;
  760. }
  761. #endif /* 0 */
  762. #define NETXEN_BOARDTYPE 0x4008
  763. #define NETXEN_BOARDNUM 0x400c
  764. #define NETXEN_CHIPNUM 0x4010
  765. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  766. {
  767. int addr, val;
  768. int i, init_delay = 0;
  769. struct crb_addr_pair *buf;
  770. unsigned offset, n;
  771. u32 off;
  772. /* resetall */
  773. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  774. 0xffffffff);
  775. if (verbose) {
  776. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  777. printk("P2 ROM board type: 0x%08x\n", val);
  778. else
  779. printk("Could not read board type\n");
  780. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  781. printk("P2 ROM board num: 0x%08x\n", val);
  782. else
  783. printk("Could not read board number\n");
  784. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  785. printk("P2 ROM chip num: 0x%08x\n", val);
  786. else
  787. printk("Could not read chip number\n");
  788. }
  789. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  790. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  791. (n != 0xcafecafeUL) ||
  792. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  793. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  794. "n: %08x\n", netxen_nic_driver_name, n);
  795. return -EIO;
  796. }
  797. offset = n & 0xffffU;
  798. n = (n >> 16) & 0xffffU;
  799. } else {
  800. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  801. !(n & 0x80000000)) {
  802. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  803. "n: %08x\n", netxen_nic_driver_name, n);
  804. return -EIO;
  805. }
  806. offset = 1;
  807. n &= ~0x80000000;
  808. }
  809. if (n < 1024) {
  810. if (verbose)
  811. printk(KERN_DEBUG "%s: %d CRB init values found"
  812. " in ROM.\n", netxen_nic_driver_name, n);
  813. } else {
  814. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  815. " initialized.\n", __func__, n);
  816. return -EIO;
  817. }
  818. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  819. if (buf == NULL) {
  820. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  821. netxen_nic_driver_name);
  822. return -ENOMEM;
  823. }
  824. for (i = 0; i < n; i++) {
  825. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  826. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0)
  827. return -EIO;
  828. buf[i].addr = addr;
  829. buf[i].data = val;
  830. if (verbose)
  831. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  832. netxen_nic_driver_name,
  833. (u32)netxen_decode_crb_addr(addr), val);
  834. }
  835. for (i = 0; i < n; i++) {
  836. off = netxen_decode_crb_addr(buf[i].addr);
  837. if (off == NETXEN_ADDR_ERROR) {
  838. printk(KERN_ERR"CRB init value out of range %x\n",
  839. buf[i].addr);
  840. continue;
  841. }
  842. off += NETXEN_PCI_CRBSPACE;
  843. /* skipping cold reboot MAGIC */
  844. if (off == NETXEN_CAM_RAM(0x1fc))
  845. continue;
  846. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  847. /* do not reset PCI */
  848. if (off == (ROMUSB_GLB + 0xbc))
  849. continue;
  850. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  851. buf[i].data = 0x1020;
  852. /* skip the function enable register */
  853. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  854. continue;
  855. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  856. continue;
  857. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  858. continue;
  859. }
  860. if (off == NETXEN_ADDR_ERROR) {
  861. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  862. netxen_nic_driver_name, buf[i].addr);
  863. continue;
  864. }
  865. /* After writing this register, HW needs time for CRB */
  866. /* to quiet down (else crb_window returns 0xffffffff) */
  867. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  868. init_delay = 1;
  869. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  870. /* hold xdma in reset also */
  871. buf[i].data = NETXEN_NIC_XDMA_RESET;
  872. }
  873. }
  874. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  875. if (init_delay == 1) {
  876. msleep(1000);
  877. init_delay = 0;
  878. }
  879. msleep(1);
  880. }
  881. kfree(buf);
  882. /* disable_peg_cache_all */
  883. /* unreset_net_cache */
  884. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  885. adapter->hw_read_wx(adapter,
  886. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  887. netxen_crb_writelit_adapter(adapter,
  888. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  889. }
  890. /* p2dn replyCount */
  891. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  892. /* disable_peg_cache 0 */
  893. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  894. /* disable_peg_cache 1 */
  895. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  896. /* peg_clr_all */
  897. /* peg_clr 0 */
  898. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  899. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  900. /* peg_clr 1 */
  901. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  902. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  903. /* peg_clr 2 */
  904. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  905. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  906. /* peg_clr 3 */
  907. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  908. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  909. return 0;
  910. }
  911. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  912. {
  913. uint64_t addr;
  914. uint32_t hi;
  915. uint32_t lo;
  916. adapter->dummy_dma.addr =
  917. pci_alloc_consistent(adapter->pdev,
  918. NETXEN_HOST_DUMMY_DMA_SIZE,
  919. &adapter->dummy_dma.phys_addr);
  920. if (adapter->dummy_dma.addr == NULL) {
  921. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  922. __func__);
  923. return -ENOMEM;
  924. }
  925. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  926. hi = (addr >> 32) & 0xffffffff;
  927. lo = addr & 0xffffffff;
  928. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  929. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  930. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  931. uint32_t temp = 0;
  932. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  933. }
  934. return 0;
  935. }
  936. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  937. {
  938. int i;
  939. if (adapter->dummy_dma.addr) {
  940. i = 100;
  941. do {
  942. if (dma_watchdog_shutdown_request(adapter) == 1)
  943. break;
  944. msleep(50);
  945. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  946. break;
  947. } while (--i);
  948. if (i) {
  949. pci_free_consistent(adapter->pdev,
  950. NETXEN_HOST_DUMMY_DMA_SIZE,
  951. adapter->dummy_dma.addr,
  952. adapter->dummy_dma.phys_addr);
  953. adapter->dummy_dma.addr = NULL;
  954. } else {
  955. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  956. adapter->netdev->name);
  957. }
  958. }
  959. }
  960. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  961. {
  962. u32 val = 0;
  963. int retries = 60;
  964. if (!pegtune_val) {
  965. do {
  966. val = adapter->pci_read_normalize(adapter,
  967. CRB_CMDPEG_STATE);
  968. if (val == PHAN_INITIALIZE_COMPLETE ||
  969. val == PHAN_INITIALIZE_ACK)
  970. return 0;
  971. msleep(500);
  972. } while (--retries);
  973. if (!retries) {
  974. pegtune_val = adapter->pci_read_normalize(adapter,
  975. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  976. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  977. "pegtune_val=%x\n", pegtune_val);
  978. return -1;
  979. }
  980. }
  981. return 0;
  982. }
  983. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  984. {
  985. u32 val = 0;
  986. int retries = 2000;
  987. do {
  988. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  989. if (val == PHAN_PEG_RCV_INITIALIZED)
  990. return 0;
  991. msleep(10);
  992. } while (--retries);
  993. if (!retries) {
  994. printk(KERN_ERR "Receive Peg initialization not "
  995. "complete, state: 0x%x.\n", val);
  996. return -EIO;
  997. }
  998. return 0;
  999. }
  1000. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1001. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1002. {
  1003. struct netxen_rx_buffer *buffer;
  1004. struct sk_buff *skb;
  1005. buffer = &rds_ring->rx_buf_arr[index];
  1006. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1007. PCI_DMA_FROMDEVICE);
  1008. skb = buffer->skb;
  1009. if (!skb)
  1010. goto no_skb;
  1011. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1012. adapter->stats.csummed++;
  1013. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1014. } else
  1015. skb->ip_summed = CHECKSUM_NONE;
  1016. skb->dev = adapter->netdev;
  1017. buffer->skb = NULL;
  1018. no_skb:
  1019. buffer->state = NETXEN_BUFFER_FREE;
  1020. buffer->lro_current_frags = 0;
  1021. buffer->lro_expected_frags = 0;
  1022. list_add_tail(&buffer->list, &rds_ring->free_list);
  1023. return skb;
  1024. }
  1025. /*
  1026. * netxen_process_rcv() send the received packet to the protocol stack.
  1027. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  1028. * invoke the routine to send more rx buffers to the Phantom...
  1029. */
  1030. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  1031. struct status_desc *desc, struct status_desc *frag_desc)
  1032. {
  1033. struct net_device *netdev = adapter->netdev;
  1034. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  1035. int index = netxen_get_sts_refhandle(sts_data);
  1036. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1037. struct netxen_rx_buffer *buffer;
  1038. struct sk_buff *skb;
  1039. u32 length = netxen_get_sts_totallength(sts_data);
  1040. u32 desc_ctx;
  1041. u16 pkt_offset = 0, cksum;
  1042. struct nx_host_rds_ring *rds_ring;
  1043. desc_ctx = netxen_get_sts_type(sts_data);
  1044. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  1045. printk("%s: %s Bad Rcv descriptor ring\n",
  1046. netxen_nic_driver_name, netdev->name);
  1047. return;
  1048. }
  1049. rds_ring = &recv_ctx->rds_rings[desc_ctx];
  1050. if (unlikely(index > rds_ring->max_rx_desc_count)) {
  1051. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  1052. index, rds_ring->max_rx_desc_count);
  1053. return;
  1054. }
  1055. buffer = &rds_ring->rx_buf_arr[index];
  1056. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1057. buffer->lro_current_frags++;
  1058. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  1059. buffer->lro_expected_frags =
  1060. netxen_get_sts_desc_lro_cnt(desc);
  1061. buffer->lro_length = length;
  1062. }
  1063. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  1064. if (buffer->lro_expected_frags != 0) {
  1065. printk("LRO: (refhandle:%x) recv frag. "
  1066. "wait for last. flags: %x expected:%d "
  1067. "have:%d\n", index,
  1068. netxen_get_sts_desc_lro_last_frag(desc),
  1069. buffer->lro_expected_frags,
  1070. buffer->lro_current_frags);
  1071. }
  1072. return;
  1073. }
  1074. }
  1075. cksum = netxen_get_sts_status(sts_data);
  1076. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1077. if (!skb)
  1078. return;
  1079. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  1080. /* True length was only available on the last pkt */
  1081. skb_put(skb, buffer->lro_length);
  1082. } else {
  1083. if (length > rds_ring->skb_size)
  1084. skb_put(skb, rds_ring->skb_size);
  1085. else
  1086. skb_put(skb, length);
  1087. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  1088. if (pkt_offset)
  1089. skb_pull(skb, pkt_offset);
  1090. }
  1091. skb->protocol = eth_type_trans(skb, netdev);
  1092. /*
  1093. * rx buffer chaining is disabled, walk and free
  1094. * any spurious rx buffer chain.
  1095. */
  1096. if (frag_desc) {
  1097. u16 i, nr_frags = desc->nr_frags;
  1098. dev_kfree_skb_any(skb);
  1099. for (i = 0; i < nr_frags; i++) {
  1100. index = frag_desc->frag_handles[i];
  1101. skb = netxen_process_rxbuf(adapter,
  1102. rds_ring, index, cksum);
  1103. if (skb)
  1104. dev_kfree_skb_any(skb);
  1105. }
  1106. adapter->stats.rxdropped++;
  1107. } else {
  1108. netif_receive_skb(skb);
  1109. netdev->last_rx = jiffies;
  1110. adapter->stats.no_rcv++;
  1111. adapter->stats.rxbytes += length;
  1112. }
  1113. }
  1114. /* Process Receive status ring */
  1115. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  1116. {
  1117. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  1118. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  1119. struct status_desc *desc, *frag_desc;
  1120. u32 consumer = recv_ctx->status_rx_consumer;
  1121. int count = 0, ring;
  1122. u64 sts_data;
  1123. u16 opcode;
  1124. while (count < max) {
  1125. desc = &desc_head[consumer];
  1126. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  1127. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  1128. netxen_get_sts_owner(desc));
  1129. break;
  1130. }
  1131. sts_data = le64_to_cpu(desc->status_desc_data);
  1132. opcode = netxen_get_sts_opcode(sts_data);
  1133. frag_desc = NULL;
  1134. if (opcode == NETXEN_NIC_RXPKT_DESC) {
  1135. if (desc->nr_frags) {
  1136. consumer = get_next_index(consumer,
  1137. adapter->max_rx_desc_count);
  1138. frag_desc = &desc_head[consumer];
  1139. netxen_set_sts_owner(frag_desc,
  1140. STATUS_OWNER_PHANTOM);
  1141. }
  1142. }
  1143. netxen_process_rcv(adapter, ctxid, desc, frag_desc);
  1144. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  1145. consumer = get_next_index(consumer,
  1146. adapter->max_rx_desc_count);
  1147. count++;
  1148. }
  1149. for (ring = 0; ring < adapter->max_rds_rings; ring++)
  1150. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  1151. /* update the consumer index in phantom */
  1152. if (count) {
  1153. recv_ctx->status_rx_consumer = consumer;
  1154. /* Window = 1 */
  1155. adapter->pci_write_normalize(adapter,
  1156. recv_ctx->crb_sts_consumer, consumer);
  1157. }
  1158. return count;
  1159. }
  1160. /* Process Command status ring */
  1161. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1162. {
  1163. u32 last_consumer, consumer;
  1164. int count = 0, i;
  1165. struct netxen_cmd_buffer *buffer;
  1166. struct pci_dev *pdev = adapter->pdev;
  1167. struct net_device *netdev = adapter->netdev;
  1168. struct netxen_skb_frag *frag;
  1169. int done = 0;
  1170. last_consumer = adapter->last_cmd_consumer;
  1171. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1172. while (last_consumer != consumer) {
  1173. buffer = &adapter->cmd_buf_arr[last_consumer];
  1174. if (buffer->skb) {
  1175. frag = &buffer->frag_array[0];
  1176. pci_unmap_single(pdev, frag->dma, frag->length,
  1177. PCI_DMA_TODEVICE);
  1178. frag->dma = 0ULL;
  1179. for (i = 1; i < buffer->frag_count; i++) {
  1180. frag++; /* Get the next frag */
  1181. pci_unmap_page(pdev, frag->dma, frag->length,
  1182. PCI_DMA_TODEVICE);
  1183. frag->dma = 0ULL;
  1184. }
  1185. adapter->stats.xmitfinished++;
  1186. dev_kfree_skb_any(buffer->skb);
  1187. buffer->skb = NULL;
  1188. }
  1189. last_consumer = get_next_index(last_consumer,
  1190. adapter->max_tx_desc_count);
  1191. if (++count >= MAX_STATUS_HANDLE)
  1192. break;
  1193. }
  1194. if (count) {
  1195. adapter->last_cmd_consumer = last_consumer;
  1196. smp_mb();
  1197. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  1198. netif_tx_lock(netdev);
  1199. netif_wake_queue(netdev);
  1200. smp_mb();
  1201. netif_tx_unlock(netdev);
  1202. }
  1203. }
  1204. /*
  1205. * If everything is freed up to consumer then check if the ring is full
  1206. * If the ring is full then check if more needs to be freed and
  1207. * schedule the call back again.
  1208. *
  1209. * This happens when there are 2 CPUs. One could be freeing and the
  1210. * other filling it. If the ring is full when we get out of here and
  1211. * the card has already interrupted the host then the host can miss the
  1212. * interrupt.
  1213. *
  1214. * There is still a possible race condition and the host could miss an
  1215. * interrupt. The card has to take care of this.
  1216. */
  1217. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  1218. done = (last_consumer == consumer);
  1219. return (done);
  1220. }
  1221. /*
  1222. * netxen_post_rx_buffers puts buffer in the Phantom memory
  1223. */
  1224. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  1225. {
  1226. struct pci_dev *pdev = adapter->pdev;
  1227. struct sk_buff *skb;
  1228. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1229. struct nx_host_rds_ring *rds_ring = NULL;
  1230. uint producer;
  1231. struct rcv_desc *pdesc;
  1232. struct netxen_rx_buffer *buffer;
  1233. int count = 0;
  1234. int index = 0;
  1235. netxen_ctx_msg msg = 0;
  1236. dma_addr_t dma;
  1237. struct list_head *head;
  1238. rds_ring = &recv_ctx->rds_rings[ringid];
  1239. producer = rds_ring->producer;
  1240. index = rds_ring->begin_alloc;
  1241. head = &rds_ring->free_list;
  1242. /* We can start writing rx descriptors into the phantom memory. */
  1243. while (!list_empty(head)) {
  1244. skb = dev_alloc_skb(rds_ring->skb_size);
  1245. if (unlikely(!skb)) {
  1246. rds_ring->begin_alloc = index;
  1247. break;
  1248. }
  1249. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1250. list_del(&buffer->list);
  1251. count++; /* now there should be no failure */
  1252. pdesc = &rds_ring->desc_head[producer];
  1253. if (!adapter->ahw.cut_through)
  1254. skb_reserve(skb, 2);
  1255. /* This will be setup when we receive the
  1256. * buffer after it has been filled FSL TBD TBD
  1257. * skb->dev = netdev;
  1258. */
  1259. dma = pci_map_single(pdev, skb->data, rds_ring->dma_size,
  1260. PCI_DMA_FROMDEVICE);
  1261. pdesc->addr_buffer = cpu_to_le64(dma);
  1262. buffer->skb = skb;
  1263. buffer->state = NETXEN_BUFFER_BUSY;
  1264. buffer->dma = dma;
  1265. /* make a rcv descriptor */
  1266. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1267. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1268. DPRINTK(INFO, "done writing descripter\n");
  1269. producer =
  1270. get_next_index(producer, rds_ring->max_rx_desc_count);
  1271. index = get_next_index(index, rds_ring->max_rx_desc_count);
  1272. }
  1273. /* if we did allocate buffers, then write the count to Phantom */
  1274. if (count) {
  1275. rds_ring->begin_alloc = index;
  1276. rds_ring->producer = producer;
  1277. /* Window = 1 */
  1278. adapter->pci_write_normalize(adapter,
  1279. rds_ring->crb_rcv_producer,
  1280. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1281. if (adapter->fw_major < 4) {
  1282. /*
  1283. * Write a doorbell msg to tell phanmon of change in
  1284. * receive ring producer
  1285. * Only for firmware version < 4.0.0
  1286. */
  1287. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1288. netxen_set_msg_privid(msg);
  1289. netxen_set_msg_count(msg,
  1290. ((producer -
  1291. 1) & (rds_ring->
  1292. max_rx_desc_count - 1)));
  1293. netxen_set_msg_ctxid(msg, adapter->portnum);
  1294. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1295. writel(msg,
  1296. DB_NORMALIZE(adapter,
  1297. NETXEN_RCV_PRODUCER_OFFSET));
  1298. }
  1299. }
  1300. }
  1301. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1302. uint32_t ctx, uint32_t ringid)
  1303. {
  1304. struct pci_dev *pdev = adapter->pdev;
  1305. struct sk_buff *skb;
  1306. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1307. struct nx_host_rds_ring *rds_ring = NULL;
  1308. u32 producer;
  1309. struct rcv_desc *pdesc;
  1310. struct netxen_rx_buffer *buffer;
  1311. int count = 0;
  1312. int index = 0;
  1313. struct list_head *head;
  1314. rds_ring = &recv_ctx->rds_rings[ringid];
  1315. producer = rds_ring->producer;
  1316. index = rds_ring->begin_alloc;
  1317. head = &rds_ring->free_list;
  1318. /* We can start writing rx descriptors into the phantom memory. */
  1319. while (!list_empty(head)) {
  1320. skb = dev_alloc_skb(rds_ring->skb_size);
  1321. if (unlikely(!skb)) {
  1322. rds_ring->begin_alloc = index;
  1323. break;
  1324. }
  1325. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1326. list_del(&buffer->list);
  1327. count++; /* now there should be no failure */
  1328. pdesc = &rds_ring->desc_head[producer];
  1329. if (!adapter->ahw.cut_through)
  1330. skb_reserve(skb, 2);
  1331. buffer->skb = skb;
  1332. buffer->state = NETXEN_BUFFER_BUSY;
  1333. buffer->dma = pci_map_single(pdev, skb->data,
  1334. rds_ring->dma_size,
  1335. PCI_DMA_FROMDEVICE);
  1336. /* make a rcv descriptor */
  1337. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1338. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1339. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1340. producer =
  1341. get_next_index(producer, rds_ring->max_rx_desc_count);
  1342. index = get_next_index(index, rds_ring->max_rx_desc_count);
  1343. buffer = &rds_ring->rx_buf_arr[index];
  1344. }
  1345. /* if we did allocate buffers, then write the count to Phantom */
  1346. if (count) {
  1347. rds_ring->begin_alloc = index;
  1348. rds_ring->producer = producer;
  1349. /* Window = 1 */
  1350. adapter->pci_write_normalize(adapter,
  1351. rds_ring->crb_rcv_producer,
  1352. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1353. wmb();
  1354. }
  1355. }
  1356. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1357. {
  1358. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1359. return;
  1360. }