mpc8360emds.dts 8.2 KB

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  1. /*
  2. * MPC8360E EMDS Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /*
  12. /memreserve/ 00000000 1000000;
  13. */
  14. / {
  15. model = "MPC8360EPB";
  16. compatible = "MPC83xx";
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. linux,phandle = <100>;
  20. cpus {
  21. #cpus = <1>;
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. linux,phandle = <200>;
  25. PowerPC,8360@0 {
  26. device_type = "cpu";
  27. reg = <0>;
  28. d-cache-line-size = <20>; // 32 bytes
  29. i-cache-line-size = <20>; // 32 bytes
  30. d-cache-size = <8000>; // L1, 32K
  31. i-cache-size = <8000>; // L1, 32K
  32. timebase-frequency = <3EF1480>;
  33. bus-frequency = <FBC5200>;
  34. clock-frequency = <1F78A400>;
  35. 32-bit;
  36. linux,phandle = <201>;
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. linux,phandle = <300>;
  42. reg = <00000000 10000000>;
  43. };
  44. bcsr@f8000000 {
  45. device_type = "board-control";
  46. reg = <f8000000 8000>;
  47. };
  48. soc8360@e0000000 {
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. #interrupt-cells = <2>;
  52. device_type = "soc";
  53. ranges = <0 e0000000 00100000>;
  54. reg = <e0000000 00000200>;
  55. bus-frequency = <FBC5200>;
  56. wdt@200 {
  57. device_type = "watchdog";
  58. compatible = "mpc83xx_wdt";
  59. reg = <200 100>;
  60. };
  61. i2c@3000 {
  62. device_type = "i2c";
  63. compatible = "fsl-i2c";
  64. reg = <3000 100>;
  65. interrupts = <e 8>;
  66. interrupt-parent = <700>;
  67. dfsrr;
  68. };
  69. i2c@3100 {
  70. device_type = "i2c";
  71. compatible = "fsl-i2c";
  72. reg = <3100 100>;
  73. interrupts = <f 8>;
  74. interrupt-parent = <700>;
  75. dfsrr;
  76. };
  77. serial@4500 {
  78. device_type = "serial";
  79. compatible = "ns16550";
  80. reg = <4500 100>;
  81. clock-frequency = <FBC5200>;
  82. interrupts = <9 8>;
  83. interrupt-parent = <700>;
  84. };
  85. serial@4600 {
  86. device_type = "serial";
  87. compatible = "ns16550";
  88. reg = <4600 100>;
  89. clock-frequency = <FBC5200>;
  90. interrupts = <a 8>;
  91. interrupt-parent = <700>;
  92. };
  93. crypto@30000 {
  94. device_type = "crypto";
  95. model = "SEC2";
  96. compatible = "talitos";
  97. reg = <30000 10000>;
  98. interrupts = <b 8>;
  99. interrupt-parent = <700>;
  100. num-channels = <4>;
  101. channel-fifo-len = <18>;
  102. exec-units-mask = <0000007e>;
  103. /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
  104. descriptor-types-mask = <01010ebf>;
  105. };
  106. pci@8500 {
  107. linux,phandle = <8500>;
  108. interrupt-map-mask = <f800 0 0 7>;
  109. interrupt-map = <
  110. /* IDSEL 0x11 AD17 */
  111. 8800 0 0 1 700 14 8
  112. 8800 0 0 2 700 15 8
  113. 8800 0 0 3 700 16 8
  114. 8800 0 0 4 700 17 8
  115. /* IDSEL 0x12 AD18 */
  116. 9000 0 0 1 700 16 8
  117. 9000 0 0 2 700 17 8
  118. 9000 0 0 3 700 14 8
  119. 9000 0 0 4 700 15 8
  120. /* IDSEL 0x13 AD19 */
  121. 9800 0 0 1 700 17 8
  122. 9800 0 0 2 700 14 8
  123. 9800 0 0 3 700 15 8
  124. 9800 0 0 4 700 16 8
  125. /* IDSEL 0x15 AD21*/
  126. a800 0 0 1 700 14 8
  127. a800 0 0 2 700 15 8
  128. a800 0 0 3 700 16 8
  129. a800 0 0 4 700 17 8
  130. /* IDSEL 0x16 AD22*/
  131. b000 0 0 1 700 17 8
  132. b000 0 0 2 700 14 8
  133. b000 0 0 3 700 15 8
  134. b000 0 0 4 700 16 8
  135. /* IDSEL 0x17 AD23*/
  136. b800 0 0 1 700 16 8
  137. b800 0 0 2 700 17 8
  138. b800 0 0 3 700 14 8
  139. b800 0 0 4 700 15 8
  140. /* IDSEL 0x18 AD24*/
  141. c000 0 0 1 700 15 8
  142. c000 0 0 2 700 16 8
  143. c000 0 0 3 700 17 8
  144. c000 0 0 4 700 14 8>;
  145. interrupt-parent = <700>;
  146. interrupts = <42 8>;
  147. bus-range = <0 0>;
  148. ranges = <02000000 0 a0000000 a0000000 0 10000000
  149. 42000000 0 80000000 80000000 0 10000000
  150. 01000000 0 00000000 e2000000 0 00100000>;
  151. clock-frequency = <3f940aa>;
  152. #interrupt-cells = <1>;
  153. #size-cells = <2>;
  154. #address-cells = <3>;
  155. reg = <8500 100>;
  156. compatible = "83xx";
  157. device_type = "pci";
  158. };
  159. pic@700 {
  160. linux,phandle = <700>;
  161. interrupt-controller;
  162. #address-cells = <0>;
  163. #interrupt-cells = <2>;
  164. reg = <700 100>;
  165. built-in;
  166. device_type = "ipic";
  167. };
  168. par_io@1400 {
  169. reg = <1400 100>;
  170. device_type = "par_io";
  171. num-ports = <7>;
  172. ucc_pin@01 {
  173. linux,phandle = <140001>;
  174. pio-map = <
  175. /* port pin dir open_drain assignment has_irq */
  176. 0 3 1 0 1 0 /* TxD0 */
  177. 0 4 1 0 1 0 /* TxD1 */
  178. 0 5 1 0 1 0 /* TxD2 */
  179. 0 6 1 0 1 0 /* TxD3 */
  180. 1 6 1 0 3 0 /* TxD4 */
  181. 1 7 1 0 1 0 /* TxD5 */
  182. 1 9 1 0 2 0 /* TxD6 */
  183. 1 a 1 0 2 0 /* TxD7 */
  184. 0 9 2 0 1 0 /* RxD0 */
  185. 0 a 2 0 1 0 /* RxD1 */
  186. 0 b 2 0 1 0 /* RxD2 */
  187. 0 c 2 0 1 0 /* RxD3 */
  188. 0 d 2 0 1 0 /* RxD4 */
  189. 1 1 2 0 2 0 /* RxD5 */
  190. 1 0 2 0 2 0 /* RxD6 */
  191. 1 4 2 0 2 0 /* RxD7 */
  192. 0 7 1 0 1 0 /* TX_EN */
  193. 0 8 1 0 1 0 /* TX_ER */
  194. 0 f 2 0 1 0 /* RX_DV */
  195. 0 10 2 0 1 0 /* RX_ER */
  196. 0 0 2 0 1 0 /* RX_CLK */
  197. 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
  198. 2 8 2 0 1 0>; /* GTX125 - CLK9 */
  199. };
  200. ucc_pin@02 {
  201. linux,phandle = <140002>;
  202. pio-map = <
  203. /* port pin dir open_drain assignment has_irq */
  204. 0 11 1 0 1 0 /* TxD0 */
  205. 0 12 1 0 1 0 /* TxD1 */
  206. 0 13 1 0 1 0 /* TxD2 */
  207. 0 14 1 0 1 0 /* TxD3 */
  208. 1 2 1 0 1 0 /* TxD4 */
  209. 1 3 1 0 2 0 /* TxD5 */
  210. 1 5 1 0 3 0 /* TxD6 */
  211. 1 8 1 0 3 0 /* TxD7 */
  212. 0 17 2 0 1 0 /* RxD0 */
  213. 0 18 2 0 1 0 /* RxD1 */
  214. 0 19 2 0 1 0 /* RxD2 */
  215. 0 1a 2 0 1 0 /* RxD3 */
  216. 0 1b 2 0 1 0 /* RxD4 */
  217. 1 c 2 0 2 0 /* RxD5 */
  218. 1 d 2 0 3 0 /* RxD6 */
  219. 1 b 2 0 2 0 /* RxD7 */
  220. 0 15 1 0 1 0 /* TX_EN */
  221. 0 16 1 0 1 0 /* TX_ER */
  222. 0 1d 2 0 1 0 /* RX_DV */
  223. 0 1e 2 0 1 0 /* RX_ER */
  224. 0 1f 2 0 1 0 /* RX_CLK */
  225. 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
  226. 2 3 2 0 1 0 /* GTX125 - CLK4 */
  227. 0 1 3 0 2 0 /* MDIO */
  228. 0 2 1 0 1 0>; /* MDC */
  229. };
  230. };
  231. };
  232. qe@e0100000 {
  233. #address-cells = <1>;
  234. #size-cells = <1>;
  235. device_type = "qe";
  236. model = "QE";
  237. ranges = <0 e0100000 00100000>;
  238. reg = <e0100000 480>;
  239. brg-frequency = <0>;
  240. bus-frequency = <179A7B00>;
  241. muram@10000 {
  242. device_type = "muram";
  243. ranges = <0 00010000 0000c000>;
  244. data-only@0{
  245. reg = <0 c000>;
  246. };
  247. };
  248. spi@4c0 {
  249. device_type = "spi";
  250. compatible = "fsl_spi";
  251. reg = <4c0 40>;
  252. interrupts = <2>;
  253. interrupt-parent = <80>;
  254. mode = "cpu";
  255. };
  256. spi@500 {
  257. device_type = "spi";
  258. compatible = "fsl_spi";
  259. reg = <500 40>;
  260. interrupts = <1>;
  261. interrupt-parent = <80>;
  262. mode = "cpu";
  263. };
  264. usb@6c0 {
  265. device_type = "usb";
  266. compatible = "qe_udc";
  267. reg = <6c0 40 8B00 100>;
  268. interrupts = <b>;
  269. interrupt-parent = <80>;
  270. mode = "slave";
  271. };
  272. ucc@2000 {
  273. device_type = "network";
  274. compatible = "ucc_geth";
  275. model = "UCC";
  276. device-id = <1>;
  277. reg = <2000 200>;
  278. interrupts = <20>;
  279. interrupt-parent = <80>;
  280. mac-address = [ 00 04 9f 00 23 23 ];
  281. rx-clock = <0>;
  282. tx-clock = <19>;
  283. phy-handle = <212000>;
  284. pio-handle = <140001>;
  285. };
  286. ucc@3000 {
  287. device_type = "network";
  288. compatible = "ucc_geth";
  289. model = "UCC";
  290. device-id = <2>;
  291. reg = <3000 200>;
  292. interrupts = <21>;
  293. interrupt-parent = <80>;
  294. mac-address = [ 00 11 22 33 44 55 ];
  295. rx-clock = <0>;
  296. tx-clock = <14>;
  297. phy-handle = <212001>;
  298. pio-handle = <140002>;
  299. };
  300. mdio@2120 {
  301. #address-cells = <1>;
  302. #size-cells = <0>;
  303. reg = <2120 18>;
  304. device_type = "mdio";
  305. compatible = "ucc_geth_phy";
  306. ethernet-phy@00 {
  307. linux,phandle = <212000>;
  308. interrupt-parent = <700>;
  309. interrupts = <11 2>;
  310. reg = <0>;
  311. device_type = "ethernet-phy";
  312. interface = <6>; //ENET_1000_GMII
  313. };
  314. ethernet-phy@01 {
  315. linux,phandle = <212001>;
  316. interrupt-parent = <700>;
  317. interrupts = <12 2>;
  318. reg = <1>;
  319. device_type = "ethernet-phy";
  320. interface = <6>;
  321. };
  322. };
  323. qeic@80 {
  324. linux,phandle = <80>;
  325. interrupt-controller;
  326. device_type = "qeic";
  327. #address-cells = <0>;
  328. #interrupt-cells = <1>;
  329. reg = <80 80>;
  330. built-in;
  331. big-endian;
  332. interrupts = <20 8 21 8>; //high:32 low:33
  333. interrupt-parent = <700>;
  334. };
  335. };
  336. };