iwl3945-base.c 242 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945.h"
  46. #include "iwl-helpers.h"
  47. #ifdef CONFIG_IWL3945_DEBUG
  48. u32 iwl3945_debug_level;
  49. #endif
  50. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  51. struct iwl3945_tx_queue *txq);
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /* module parameters */
  58. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  59. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  60. static int iwl3945_param_disable; /* def: 0 = enable radio */
  61. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  62. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  63. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  64. int iwl3945_param_queues_num = IWL_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  65. /*
  66. * module name, copyright, version, etc.
  67. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  68. */
  69. #define DRV_DESCRIPTION \
  70. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  71. #ifdef CONFIG_IWL3945_DEBUG
  72. #define VD "d"
  73. #else
  74. #define VD
  75. #endif
  76. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  77. #define VS "s"
  78. #else
  79. #define VS
  80. #endif
  81. #define IWLWIFI_VERSION "1.2.26k" VD VS
  82. #define DRV_COPYRIGHT "Copyright(c) 2003-2007 Intel Corporation"
  83. #define DRV_VERSION IWLWIFI_VERSION
  84. /* Change firmware file name, using "-" and incrementing number,
  85. * *only* when uCode interface or architecture changes so that it
  86. * is not compatible with earlier drivers.
  87. * This number will also appear in << 8 position of 1st dword of uCode file */
  88. #define IWL3945_UCODE_API "-1"
  89. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  90. MODULE_VERSION(DRV_VERSION);
  91. MODULE_AUTHOR(DRV_COPYRIGHT);
  92. MODULE_LICENSE("GPL");
  93. static __le16 *ieee80211_get_qos_ctrl(struct ieee80211_hdr *hdr)
  94. {
  95. u16 fc = le16_to_cpu(hdr->frame_control);
  96. int hdr_len = ieee80211_get_hdrlen(fc);
  97. if ((fc & 0x00cc) == (IEEE80211_STYPE_QOS_DATA | IEEE80211_FTYPE_DATA))
  98. return (__le16 *) ((u8 *) hdr + hdr_len - QOS_CONTROL_LEN);
  99. return NULL;
  100. }
  101. static const struct ieee80211_supported_band *iwl3945_get_band(
  102. struct iwl3945_priv *priv, enum ieee80211_band band)
  103. {
  104. return priv->hw->wiphy->bands[band];
  105. }
  106. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  107. {
  108. /* Single white space is for Linksys APs */
  109. if (essid_len == 1 && essid[0] == ' ')
  110. return 1;
  111. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  112. while (essid_len) {
  113. essid_len--;
  114. if (essid[essid_len] != '\0')
  115. return 0;
  116. }
  117. return 1;
  118. }
  119. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  120. {
  121. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  122. const char *s = essid;
  123. char *d = escaped;
  124. if (iwl3945_is_empty_essid(essid, essid_len)) {
  125. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  126. return escaped;
  127. }
  128. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  129. while (essid_len--) {
  130. if (*s == '\0') {
  131. *d++ = '\\';
  132. *d++ = '0';
  133. s++;
  134. } else
  135. *d++ = *s++;
  136. }
  137. *d = '\0';
  138. return escaped;
  139. }
  140. static void iwl3945_print_hex_dump(int level, void *p, u32 len)
  141. {
  142. #ifdef CONFIG_IWL3945_DEBUG
  143. if (!(iwl3945_debug_level & level))
  144. return;
  145. print_hex_dump(KERN_DEBUG, "iwl data: ", DUMP_PREFIX_OFFSET, 16, 1,
  146. p, len, 1);
  147. #endif
  148. }
  149. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  150. * DMA services
  151. *
  152. * Theory of operation
  153. *
  154. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  155. * of buffer descriptors, each of which points to one or more data buffers for
  156. * the device to read from or fill. Driver and device exchange status of each
  157. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  158. * entries in each circular buffer, to protect against confusing empty and full
  159. * queue states.
  160. *
  161. * The device reads or writes the data in the queues via the device's several
  162. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  163. *
  164. * For Tx queue, there are low mark and high mark limits. If, after queuing
  165. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  166. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  167. * Tx queue resumed.
  168. *
  169. * The 3945 operates with six queues: One receive queue, one transmit queue
  170. * (#4) for sending commands to the device firmware, and four transmit queues
  171. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  172. ***************************************************/
  173. static int iwl3945_queue_space(const struct iwl3945_queue *q)
  174. {
  175. int s = q->read_ptr - q->write_ptr;
  176. if (q->read_ptr > q->write_ptr)
  177. s -= q->n_bd;
  178. if (s <= 0)
  179. s += q->n_window;
  180. /* keep some reserve to not confuse empty and full situations */
  181. s -= 2;
  182. if (s < 0)
  183. s = 0;
  184. return s;
  185. }
  186. /**
  187. * iwl3945_queue_inc_wrap - increment queue index, wrap back to beginning
  188. * @index -- current index
  189. * @n_bd -- total number of entries in queue (must be power of 2)
  190. */
  191. static inline int iwl3945_queue_inc_wrap(int index, int n_bd)
  192. {
  193. return ++index & (n_bd - 1);
  194. }
  195. /**
  196. * iwl3945_queue_dec_wrap - increment queue index, wrap back to end
  197. * @index -- current index
  198. * @n_bd -- total number of entries in queue (must be power of 2)
  199. */
  200. static inline int iwl3945_queue_dec_wrap(int index, int n_bd)
  201. {
  202. return --index & (n_bd - 1);
  203. }
  204. static inline int x2_queue_used(const struct iwl3945_queue *q, int i)
  205. {
  206. return q->write_ptr > q->read_ptr ?
  207. (i >= q->read_ptr && i < q->write_ptr) :
  208. !(i < q->read_ptr && i >= q->write_ptr);
  209. }
  210. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  211. {
  212. /* This is for scan command, the big buffer at end of command array */
  213. if (is_huge)
  214. return q->n_window; /* must be power of 2 */
  215. /* Otherwise, use normal size buffers */
  216. return index & (q->n_window - 1);
  217. }
  218. /**
  219. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  220. */
  221. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  222. int count, int slots_num, u32 id)
  223. {
  224. q->n_bd = count;
  225. q->n_window = slots_num;
  226. q->id = id;
  227. /* count must be power-of-two size, otherwise iwl3945_queue_inc_wrap
  228. * and iwl3945_queue_dec_wrap are broken. */
  229. BUG_ON(!is_power_of_2(count));
  230. /* slots_num must be power-of-two size, otherwise
  231. * get_cmd_index is broken. */
  232. BUG_ON(!is_power_of_2(slots_num));
  233. q->low_mark = q->n_window / 4;
  234. if (q->low_mark < 4)
  235. q->low_mark = 4;
  236. q->high_mark = q->n_window / 8;
  237. if (q->high_mark < 2)
  238. q->high_mark = 2;
  239. q->write_ptr = q->read_ptr = 0;
  240. return 0;
  241. }
  242. /**
  243. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  244. */
  245. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  246. struct iwl3945_tx_queue *txq, u32 id)
  247. {
  248. struct pci_dev *dev = priv->pci_dev;
  249. /* Driver private data, only for Tx (not command) queues,
  250. * not shared with device. */
  251. if (id != IWL_CMD_QUEUE_NUM) {
  252. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  253. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  254. if (!txq->txb) {
  255. IWL_ERROR("kmalloc for auxiliary BD "
  256. "structures failed\n");
  257. goto error;
  258. }
  259. } else
  260. txq->txb = NULL;
  261. /* Circular buffer of transmit frame descriptors (TFDs),
  262. * shared with device */
  263. txq->bd = pci_alloc_consistent(dev,
  264. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  265. &txq->q.dma_addr);
  266. if (!txq->bd) {
  267. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  268. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  269. goto error;
  270. }
  271. txq->q.id = id;
  272. return 0;
  273. error:
  274. if (txq->txb) {
  275. kfree(txq->txb);
  276. txq->txb = NULL;
  277. }
  278. return -ENOMEM;
  279. }
  280. /**
  281. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  282. */
  283. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  284. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  285. {
  286. struct pci_dev *dev = priv->pci_dev;
  287. int len;
  288. int rc = 0;
  289. /*
  290. * Alloc buffer array for commands (Tx or other types of commands).
  291. * For the command queue (#4), allocate command space + one big
  292. * command for scan, since scan command is very huge; the system will
  293. * not have two scans at the same time, so only one is needed.
  294. * For data Tx queues (all other queues), no super-size command
  295. * space is needed.
  296. */
  297. len = sizeof(struct iwl3945_cmd) * slots_num;
  298. if (txq_id == IWL_CMD_QUEUE_NUM)
  299. len += IWL_MAX_SCAN_SIZE;
  300. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  301. if (!txq->cmd)
  302. return -ENOMEM;
  303. /* Alloc driver data array and TFD circular buffer */
  304. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  305. if (rc) {
  306. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  307. return -ENOMEM;
  308. }
  309. txq->need_update = 0;
  310. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  311. * iwl3945_queue_inc_wrap and iwl3945_queue_dec_wrap are broken. */
  312. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  313. /* Initialize queue high/low-water, head/tail indexes */
  314. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  315. /* Tell device where to find queue, enable DMA channel. */
  316. iwl3945_hw_tx_queue_init(priv, txq);
  317. return 0;
  318. }
  319. /**
  320. * iwl3945_tx_queue_free - Deallocate DMA queue.
  321. * @txq: Transmit queue to deallocate.
  322. *
  323. * Empty queue by removing and destroying all BD's.
  324. * Free all buffers.
  325. * 0-fill, but do not free "txq" descriptor structure.
  326. */
  327. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  328. {
  329. struct iwl3945_queue *q = &txq->q;
  330. struct pci_dev *dev = priv->pci_dev;
  331. int len;
  332. if (q->n_bd == 0)
  333. return;
  334. /* first, empty all BD's */
  335. for (; q->write_ptr != q->read_ptr;
  336. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd))
  337. iwl3945_hw_txq_free_tfd(priv, txq);
  338. len = sizeof(struct iwl3945_cmd) * q->n_window;
  339. if (q->id == IWL_CMD_QUEUE_NUM)
  340. len += IWL_MAX_SCAN_SIZE;
  341. /* De-alloc array of command/tx buffers */
  342. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  343. /* De-alloc circular buffer of TFDs */
  344. if (txq->q.n_bd)
  345. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  346. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  347. /* De-alloc array of per-TFD driver data */
  348. if (txq->txb) {
  349. kfree(txq->txb);
  350. txq->txb = NULL;
  351. }
  352. /* 0-fill queue descriptor structure */
  353. memset(txq, 0, sizeof(*txq));
  354. }
  355. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  356. /*************** STATION TABLE MANAGEMENT ****
  357. * mac80211 should be examined to determine if sta_info is duplicating
  358. * the functionality provided here
  359. */
  360. /**************************************************************/
  361. #if 0 /* temporary disable till we add real remove station */
  362. /**
  363. * iwl3945_remove_station - Remove driver's knowledge of station.
  364. *
  365. * NOTE: This does not remove station from device's station table.
  366. */
  367. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  368. {
  369. int index = IWL_INVALID_STATION;
  370. int i;
  371. unsigned long flags;
  372. spin_lock_irqsave(&priv->sta_lock, flags);
  373. if (is_ap)
  374. index = IWL_AP_ID;
  375. else if (is_broadcast_ether_addr(addr))
  376. index = priv->hw_setting.bcast_sta_id;
  377. else
  378. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  379. if (priv->stations[i].used &&
  380. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  381. addr)) {
  382. index = i;
  383. break;
  384. }
  385. if (unlikely(index == IWL_INVALID_STATION))
  386. goto out;
  387. if (priv->stations[index].used) {
  388. priv->stations[index].used = 0;
  389. priv->num_stations--;
  390. }
  391. BUG_ON(priv->num_stations < 0);
  392. out:
  393. spin_unlock_irqrestore(&priv->sta_lock, flags);
  394. return 0;
  395. }
  396. #endif
  397. /**
  398. * iwl3945_clear_stations_table - Clear the driver's station table
  399. *
  400. * NOTE: This does not clear or otherwise alter the device's station table.
  401. */
  402. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  403. {
  404. unsigned long flags;
  405. spin_lock_irqsave(&priv->sta_lock, flags);
  406. priv->num_stations = 0;
  407. memset(priv->stations, 0, sizeof(priv->stations));
  408. spin_unlock_irqrestore(&priv->sta_lock, flags);
  409. }
  410. /**
  411. * iwl3945_add_station - Add station to station tables in driver and device
  412. */
  413. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  414. {
  415. int i;
  416. int index = IWL_INVALID_STATION;
  417. struct iwl3945_station_entry *station;
  418. unsigned long flags_spin;
  419. DECLARE_MAC_BUF(mac);
  420. u8 rate;
  421. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  422. if (is_ap)
  423. index = IWL_AP_ID;
  424. else if (is_broadcast_ether_addr(addr))
  425. index = priv->hw_setting.bcast_sta_id;
  426. else
  427. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  428. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  429. addr)) {
  430. index = i;
  431. break;
  432. }
  433. if (!priv->stations[i].used &&
  434. index == IWL_INVALID_STATION)
  435. index = i;
  436. }
  437. /* These two conditions has the same outcome but keep them separate
  438. since they have different meaning */
  439. if (unlikely(index == IWL_INVALID_STATION)) {
  440. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  441. return index;
  442. }
  443. if (priv->stations[index].used &&
  444. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  445. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  446. return index;
  447. }
  448. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  449. station = &priv->stations[index];
  450. station->used = 1;
  451. priv->num_stations++;
  452. /* Set up the REPLY_ADD_STA command to send to device */
  453. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  454. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  455. station->sta.mode = 0;
  456. station->sta.sta.sta_id = index;
  457. station->sta.station_flags = 0;
  458. if (priv->band == IEEE80211_BAND_5GHZ)
  459. rate = IWL_RATE_6M_PLCP;
  460. else
  461. rate = IWL_RATE_1M_PLCP;
  462. /* Turn on both antennas for the station... */
  463. station->sta.rate_n_flags =
  464. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  465. station->current_rate.rate_n_flags =
  466. le16_to_cpu(station->sta.rate_n_flags);
  467. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  468. /* Add station to device's station table */
  469. iwl3945_send_add_station(priv, &station->sta, flags);
  470. return index;
  471. }
  472. /*************** DRIVER STATUS FUNCTIONS *****/
  473. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  474. {
  475. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  476. * set but EXIT_PENDING is not */
  477. return test_bit(STATUS_READY, &priv->status) &&
  478. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  479. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  480. }
  481. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  482. {
  483. return test_bit(STATUS_ALIVE, &priv->status);
  484. }
  485. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  486. {
  487. return test_bit(STATUS_INIT, &priv->status);
  488. }
  489. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  490. {
  491. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  492. test_bit(STATUS_RF_KILL_SW, &priv->status);
  493. }
  494. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  495. {
  496. if (iwl3945_is_rfkill(priv))
  497. return 0;
  498. return iwl3945_is_ready(priv);
  499. }
  500. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  501. #define IWL_CMD(x) case x : return #x
  502. static const char *get_cmd_string(u8 cmd)
  503. {
  504. switch (cmd) {
  505. IWL_CMD(REPLY_ALIVE);
  506. IWL_CMD(REPLY_ERROR);
  507. IWL_CMD(REPLY_RXON);
  508. IWL_CMD(REPLY_RXON_ASSOC);
  509. IWL_CMD(REPLY_QOS_PARAM);
  510. IWL_CMD(REPLY_RXON_TIMING);
  511. IWL_CMD(REPLY_ADD_STA);
  512. IWL_CMD(REPLY_REMOVE_STA);
  513. IWL_CMD(REPLY_REMOVE_ALL_STA);
  514. IWL_CMD(REPLY_3945_RX);
  515. IWL_CMD(REPLY_TX);
  516. IWL_CMD(REPLY_RATE_SCALE);
  517. IWL_CMD(REPLY_LEDS_CMD);
  518. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  519. IWL_CMD(RADAR_NOTIFICATION);
  520. IWL_CMD(REPLY_QUIET_CMD);
  521. IWL_CMD(REPLY_CHANNEL_SWITCH);
  522. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  523. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  524. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  525. IWL_CMD(POWER_TABLE_CMD);
  526. IWL_CMD(PM_SLEEP_NOTIFICATION);
  527. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  528. IWL_CMD(REPLY_SCAN_CMD);
  529. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  530. IWL_CMD(SCAN_START_NOTIFICATION);
  531. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  532. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  533. IWL_CMD(BEACON_NOTIFICATION);
  534. IWL_CMD(REPLY_TX_BEACON);
  535. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  536. IWL_CMD(QUIET_NOTIFICATION);
  537. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  538. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  539. IWL_CMD(REPLY_BT_CONFIG);
  540. IWL_CMD(REPLY_STATISTICS_CMD);
  541. IWL_CMD(STATISTICS_NOTIFICATION);
  542. IWL_CMD(REPLY_CARD_STATE_CMD);
  543. IWL_CMD(CARD_STATE_NOTIFICATION);
  544. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  545. default:
  546. return "UNKNOWN";
  547. }
  548. }
  549. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  550. /**
  551. * iwl3945_enqueue_hcmd - enqueue a uCode command
  552. * @priv: device private data point
  553. * @cmd: a point to the ucode command structure
  554. *
  555. * The function returns < 0 values to indicate the operation is
  556. * failed. On success, it turns the index (> 0) of command in the
  557. * command queue.
  558. */
  559. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  560. {
  561. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  562. struct iwl3945_queue *q = &txq->q;
  563. struct iwl3945_tfd_frame *tfd;
  564. u32 *control_flags;
  565. struct iwl3945_cmd *out_cmd;
  566. u32 idx;
  567. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  568. dma_addr_t phys_addr;
  569. int pad;
  570. u16 count;
  571. int ret;
  572. unsigned long flags;
  573. /* If any of the command structures end up being larger than
  574. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  575. * we will need to increase the size of the TFD entries */
  576. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  577. !(cmd->meta.flags & CMD_SIZE_HUGE));
  578. if (iwl3945_is_rfkill(priv)) {
  579. IWL_DEBUG_INFO("Not sending command - RF KILL");
  580. return -EIO;
  581. }
  582. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  583. IWL_ERROR("No space for Tx\n");
  584. return -ENOSPC;
  585. }
  586. spin_lock_irqsave(&priv->hcmd_lock, flags);
  587. tfd = &txq->bd[q->write_ptr];
  588. memset(tfd, 0, sizeof(*tfd));
  589. control_flags = (u32 *) tfd;
  590. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  591. out_cmd = &txq->cmd[idx];
  592. out_cmd->hdr.cmd = cmd->id;
  593. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  594. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  595. /* At this point, the out_cmd now has all of the incoming cmd
  596. * information */
  597. out_cmd->hdr.flags = 0;
  598. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  599. INDEX_TO_SEQ(q->write_ptr));
  600. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  601. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  602. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  603. offsetof(struct iwl3945_cmd, hdr);
  604. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  605. pad = U32_PAD(cmd->len);
  606. count = TFD_CTL_COUNT_GET(*control_flags);
  607. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  608. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  609. "%d bytes at %d[%d]:%d\n",
  610. get_cmd_string(out_cmd->hdr.cmd),
  611. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  612. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  613. txq->need_update = 1;
  614. /* Increment and update queue's write index */
  615. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  616. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  617. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  618. return ret ? ret : idx;
  619. }
  620. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  621. {
  622. int ret;
  623. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  624. /* An asynchronous command can not expect an SKB to be set. */
  625. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  626. /* An asynchronous command MUST have a callback. */
  627. BUG_ON(!cmd->meta.u.callback);
  628. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  629. return -EBUSY;
  630. ret = iwl3945_enqueue_hcmd(priv, cmd);
  631. if (ret < 0) {
  632. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  633. get_cmd_string(cmd->id), ret);
  634. return ret;
  635. }
  636. return 0;
  637. }
  638. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  639. {
  640. int cmd_idx;
  641. int ret;
  642. static atomic_t entry = ATOMIC_INIT(0); /* reentrance protection */
  643. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  644. /* A synchronous command can not have a callback set. */
  645. BUG_ON(cmd->meta.u.callback != NULL);
  646. if (atomic_xchg(&entry, 1)) {
  647. IWL_ERROR("Error sending %s: Already sending a host command\n",
  648. get_cmd_string(cmd->id));
  649. return -EBUSY;
  650. }
  651. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  652. if (cmd->meta.flags & CMD_WANT_SKB)
  653. cmd->meta.source = &cmd->meta;
  654. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  655. if (cmd_idx < 0) {
  656. ret = cmd_idx;
  657. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  658. get_cmd_string(cmd->id), ret);
  659. goto out;
  660. }
  661. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  662. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  663. HOST_COMPLETE_TIMEOUT);
  664. if (!ret) {
  665. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  666. IWL_ERROR("Error sending %s: time out after %dms.\n",
  667. get_cmd_string(cmd->id),
  668. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  669. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  670. ret = -ETIMEDOUT;
  671. goto cancel;
  672. }
  673. }
  674. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  675. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  676. get_cmd_string(cmd->id));
  677. ret = -ECANCELED;
  678. goto fail;
  679. }
  680. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  681. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  682. get_cmd_string(cmd->id));
  683. ret = -EIO;
  684. goto fail;
  685. }
  686. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  687. IWL_ERROR("Error: Response NULL in '%s'\n",
  688. get_cmd_string(cmd->id));
  689. ret = -EIO;
  690. goto out;
  691. }
  692. ret = 0;
  693. goto out;
  694. cancel:
  695. if (cmd->meta.flags & CMD_WANT_SKB) {
  696. struct iwl3945_cmd *qcmd;
  697. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  698. * TX cmd queue. Otherwise in case the cmd comes
  699. * in later, it will possibly set an invalid
  700. * address (cmd->meta.source). */
  701. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  702. qcmd->meta.flags &= ~CMD_WANT_SKB;
  703. }
  704. fail:
  705. if (cmd->meta.u.skb) {
  706. dev_kfree_skb_any(cmd->meta.u.skb);
  707. cmd->meta.u.skb = NULL;
  708. }
  709. out:
  710. atomic_set(&entry, 0);
  711. return ret;
  712. }
  713. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  714. {
  715. if (cmd->meta.flags & CMD_ASYNC)
  716. return iwl3945_send_cmd_async(priv, cmd);
  717. return iwl3945_send_cmd_sync(priv, cmd);
  718. }
  719. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  720. {
  721. struct iwl3945_host_cmd cmd = {
  722. .id = id,
  723. .len = len,
  724. .data = data,
  725. };
  726. return iwl3945_send_cmd_sync(priv, &cmd);
  727. }
  728. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  729. {
  730. struct iwl3945_host_cmd cmd = {
  731. .id = id,
  732. .len = sizeof(val),
  733. .data = &val,
  734. };
  735. return iwl3945_send_cmd_sync(priv, &cmd);
  736. }
  737. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  738. {
  739. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  740. }
  741. /**
  742. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  743. * @band: 2.4 or 5 GHz band
  744. * @channel: Any channel valid for the requested band
  745. * In addition to setting the staging RXON, priv->band is also set.
  746. *
  747. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  748. * in the staging RXON flag structure based on the band
  749. */
  750. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  751. enum ieee80211_band band,
  752. u16 channel)
  753. {
  754. if (!iwl3945_get_channel_info(priv, band, channel)) {
  755. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  756. channel, band);
  757. return -EINVAL;
  758. }
  759. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  760. (priv->band == band))
  761. return 0;
  762. priv->staging_rxon.channel = cpu_to_le16(channel);
  763. if (band == IEEE80211_BAND_5GHZ)
  764. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  765. else
  766. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  767. priv->band = band;
  768. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  769. return 0;
  770. }
  771. /**
  772. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  773. *
  774. * NOTE: This is really only useful during development and can eventually
  775. * be #ifdef'd out once the driver is stable and folks aren't actively
  776. * making changes
  777. */
  778. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  779. {
  780. int error = 0;
  781. int counter = 1;
  782. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  783. error |= le32_to_cpu(rxon->flags &
  784. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  785. RXON_FLG_RADAR_DETECT_MSK));
  786. if (error)
  787. IWL_WARNING("check 24G fields %d | %d\n",
  788. counter++, error);
  789. } else {
  790. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  791. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  792. if (error)
  793. IWL_WARNING("check 52 fields %d | %d\n",
  794. counter++, error);
  795. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  796. if (error)
  797. IWL_WARNING("check 52 CCK %d | %d\n",
  798. counter++, error);
  799. }
  800. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  801. if (error)
  802. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  803. /* make sure basic rates 6Mbps and 1Mbps are supported */
  804. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  805. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  806. if (error)
  807. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  808. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  809. if (error)
  810. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  811. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  812. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  813. if (error)
  814. IWL_WARNING("check CCK and short slot %d | %d\n",
  815. counter++, error);
  816. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  817. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  818. if (error)
  819. IWL_WARNING("check CCK & auto detect %d | %d\n",
  820. counter++, error);
  821. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  822. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  823. if (error)
  824. IWL_WARNING("check TGG and auto detect %d | %d\n",
  825. counter++, error);
  826. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  827. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  828. RXON_FLG_ANT_A_MSK)) == 0);
  829. if (error)
  830. IWL_WARNING("check antenna %d %d\n", counter++, error);
  831. if (error)
  832. IWL_WARNING("Tuning to channel %d\n",
  833. le16_to_cpu(rxon->channel));
  834. if (error) {
  835. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  836. return -1;
  837. }
  838. return 0;
  839. }
  840. /**
  841. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  842. * @priv: staging_rxon is compared to active_rxon
  843. *
  844. * If the RXON structure is changing enough to require a new tune,
  845. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  846. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  847. */
  848. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  849. {
  850. /* These items are only settable from the full RXON command */
  851. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  852. compare_ether_addr(priv->staging_rxon.bssid_addr,
  853. priv->active_rxon.bssid_addr) ||
  854. compare_ether_addr(priv->staging_rxon.node_addr,
  855. priv->active_rxon.node_addr) ||
  856. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  857. priv->active_rxon.wlap_bssid_addr) ||
  858. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  859. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  860. (priv->staging_rxon.air_propagation !=
  861. priv->active_rxon.air_propagation) ||
  862. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  863. return 1;
  864. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  865. * be updated with the RXON_ASSOC command -- however only some
  866. * flag transitions are allowed using RXON_ASSOC */
  867. /* Check if we are not switching bands */
  868. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  869. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  870. return 1;
  871. /* Check if we are switching association toggle */
  872. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  873. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  874. return 1;
  875. return 0;
  876. }
  877. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  878. {
  879. int rc = 0;
  880. struct iwl3945_rx_packet *res = NULL;
  881. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  882. struct iwl3945_host_cmd cmd = {
  883. .id = REPLY_RXON_ASSOC,
  884. .len = sizeof(rxon_assoc),
  885. .meta.flags = CMD_WANT_SKB,
  886. .data = &rxon_assoc,
  887. };
  888. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  889. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  890. if ((rxon1->flags == rxon2->flags) &&
  891. (rxon1->filter_flags == rxon2->filter_flags) &&
  892. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  893. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  894. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  895. return 0;
  896. }
  897. rxon_assoc.flags = priv->staging_rxon.flags;
  898. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  899. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  900. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  901. rxon_assoc.reserved = 0;
  902. rc = iwl3945_send_cmd_sync(priv, &cmd);
  903. if (rc)
  904. return rc;
  905. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  906. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  907. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  908. rc = -EIO;
  909. }
  910. priv->alloc_rxb_skb--;
  911. dev_kfree_skb_any(cmd.meta.u.skb);
  912. return rc;
  913. }
  914. /**
  915. * iwl3945_commit_rxon - commit staging_rxon to hardware
  916. *
  917. * The RXON command in staging_rxon is committed to the hardware and
  918. * the active_rxon structure is updated with the new data. This
  919. * function correctly transitions out of the RXON_ASSOC_MSK state if
  920. * a HW tune is required based on the RXON structure changes.
  921. */
  922. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  923. {
  924. /* cast away the const for active_rxon in this function */
  925. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  926. int rc = 0;
  927. DECLARE_MAC_BUF(mac);
  928. if (!iwl3945_is_alive(priv))
  929. return -1;
  930. /* always get timestamp with Rx frame */
  931. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  932. /* select antenna */
  933. priv->staging_rxon.flags &=
  934. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  935. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  936. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  937. if (rc) {
  938. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  939. return -EINVAL;
  940. }
  941. /* If we don't need to send a full RXON, we can use
  942. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  943. * and other flags for the current radio configuration. */
  944. if (!iwl3945_full_rxon_required(priv)) {
  945. rc = iwl3945_send_rxon_assoc(priv);
  946. if (rc) {
  947. IWL_ERROR("Error setting RXON_ASSOC "
  948. "configuration (%d).\n", rc);
  949. return rc;
  950. }
  951. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  952. return 0;
  953. }
  954. /* If we are currently associated and the new config requires
  955. * an RXON_ASSOC and the new config wants the associated mask enabled,
  956. * we must clear the associated from the active configuration
  957. * before we apply the new config */
  958. if (iwl3945_is_associated(priv) &&
  959. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  960. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  961. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  962. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  963. sizeof(struct iwl3945_rxon_cmd),
  964. &priv->active_rxon);
  965. /* If the mask clearing failed then we set
  966. * active_rxon back to what it was previously */
  967. if (rc) {
  968. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  969. IWL_ERROR("Error clearing ASSOC_MSK on current "
  970. "configuration (%d).\n", rc);
  971. return rc;
  972. }
  973. }
  974. IWL_DEBUG_INFO("Sending RXON\n"
  975. "* with%s RXON_FILTER_ASSOC_MSK\n"
  976. "* channel = %d\n"
  977. "* bssid = %s\n",
  978. ((priv->staging_rxon.filter_flags &
  979. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  980. le16_to_cpu(priv->staging_rxon.channel),
  981. print_mac(mac, priv->staging_rxon.bssid_addr));
  982. /* Apply the new configuration */
  983. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  984. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  985. if (rc) {
  986. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  987. return rc;
  988. }
  989. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  990. iwl3945_clear_stations_table(priv);
  991. /* If we issue a new RXON command which required a tune then we must
  992. * send a new TXPOWER command or we won't be able to Tx any frames */
  993. rc = iwl3945_hw_reg_send_txpower(priv);
  994. if (rc) {
  995. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  996. return rc;
  997. }
  998. /* Add the broadcast address so we can send broadcast frames */
  999. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  1000. IWL_INVALID_STATION) {
  1001. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  1002. return -EIO;
  1003. }
  1004. /* If we have set the ASSOC_MSK and we are in BSS mode then
  1005. * add the IWL_AP_ID to the station rate table */
  1006. if (iwl3945_is_associated(priv) &&
  1007. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  1008. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  1009. == IWL_INVALID_STATION) {
  1010. IWL_ERROR("Error adding AP address for transmit.\n");
  1011. return -EIO;
  1012. }
  1013. /* Init the hardware's rate fallback order based on the band */
  1014. rc = iwl3945_init_hw_rate_table(priv);
  1015. if (rc) {
  1016. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  1017. return -EIO;
  1018. }
  1019. return 0;
  1020. }
  1021. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  1022. {
  1023. struct iwl3945_bt_cmd bt_cmd = {
  1024. .flags = 3,
  1025. .lead_time = 0xAA,
  1026. .max_kill = 1,
  1027. .kill_ack_mask = 0,
  1028. .kill_cts_mask = 0,
  1029. };
  1030. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1031. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  1032. }
  1033. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  1034. {
  1035. int rc = 0;
  1036. struct iwl3945_rx_packet *res;
  1037. struct iwl3945_host_cmd cmd = {
  1038. .id = REPLY_SCAN_ABORT_CMD,
  1039. .meta.flags = CMD_WANT_SKB,
  1040. };
  1041. /* If there isn't a scan actively going on in the hardware
  1042. * then we are in between scan bands and not actually
  1043. * actively scanning, so don't send the abort command */
  1044. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1045. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1046. return 0;
  1047. }
  1048. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1049. if (rc) {
  1050. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1051. return rc;
  1052. }
  1053. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1054. if (res->u.status != CAN_ABORT_STATUS) {
  1055. /* The scan abort will return 1 for success or
  1056. * 2 for "failure". A failure condition can be
  1057. * due to simply not being in an active scan which
  1058. * can occur if we send the scan abort before we
  1059. * the microcode has notified us that a scan is
  1060. * completed. */
  1061. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1062. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1063. clear_bit(STATUS_SCAN_HW, &priv->status);
  1064. }
  1065. dev_kfree_skb_any(cmd.meta.u.skb);
  1066. return rc;
  1067. }
  1068. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1069. struct iwl3945_cmd *cmd,
  1070. struct sk_buff *skb)
  1071. {
  1072. return 1;
  1073. }
  1074. /*
  1075. * CARD_STATE_CMD
  1076. *
  1077. * Use: Sets the device's internal card state to enable, disable, or halt
  1078. *
  1079. * When in the 'enable' state the card operates as normal.
  1080. * When in the 'disable' state, the card enters into a low power mode.
  1081. * When in the 'halt' state, the card is shut down and must be fully
  1082. * restarted to come back on.
  1083. */
  1084. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1085. {
  1086. struct iwl3945_host_cmd cmd = {
  1087. .id = REPLY_CARD_STATE_CMD,
  1088. .len = sizeof(u32),
  1089. .data = &flags,
  1090. .meta.flags = meta_flag,
  1091. };
  1092. if (meta_flag & CMD_ASYNC)
  1093. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1094. return iwl3945_send_cmd(priv, &cmd);
  1095. }
  1096. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1097. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1098. {
  1099. struct iwl3945_rx_packet *res = NULL;
  1100. if (!skb) {
  1101. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1102. return 1;
  1103. }
  1104. res = (struct iwl3945_rx_packet *)skb->data;
  1105. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1106. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1107. res->hdr.flags);
  1108. return 1;
  1109. }
  1110. switch (res->u.add_sta.status) {
  1111. case ADD_STA_SUCCESS_MSK:
  1112. break;
  1113. default:
  1114. break;
  1115. }
  1116. /* We didn't cache the SKB; let the caller free it */
  1117. return 1;
  1118. }
  1119. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1120. struct iwl3945_addsta_cmd *sta, u8 flags)
  1121. {
  1122. struct iwl3945_rx_packet *res = NULL;
  1123. int rc = 0;
  1124. struct iwl3945_host_cmd cmd = {
  1125. .id = REPLY_ADD_STA,
  1126. .len = sizeof(struct iwl3945_addsta_cmd),
  1127. .meta.flags = flags,
  1128. .data = sta,
  1129. };
  1130. if (flags & CMD_ASYNC)
  1131. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1132. else
  1133. cmd.meta.flags |= CMD_WANT_SKB;
  1134. rc = iwl3945_send_cmd(priv, &cmd);
  1135. if (rc || (flags & CMD_ASYNC))
  1136. return rc;
  1137. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1138. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1139. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1140. res->hdr.flags);
  1141. rc = -EIO;
  1142. }
  1143. if (rc == 0) {
  1144. switch (res->u.add_sta.status) {
  1145. case ADD_STA_SUCCESS_MSK:
  1146. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1147. break;
  1148. default:
  1149. rc = -EIO;
  1150. IWL_WARNING("REPLY_ADD_STA failed\n");
  1151. break;
  1152. }
  1153. }
  1154. priv->alloc_rxb_skb--;
  1155. dev_kfree_skb_any(cmd.meta.u.skb);
  1156. return rc;
  1157. }
  1158. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1159. struct ieee80211_key_conf *keyconf,
  1160. u8 sta_id)
  1161. {
  1162. unsigned long flags;
  1163. __le16 key_flags = 0;
  1164. switch (keyconf->alg) {
  1165. case ALG_CCMP:
  1166. key_flags |= STA_KEY_FLG_CCMP;
  1167. key_flags |= cpu_to_le16(
  1168. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1169. key_flags &= ~STA_KEY_FLG_INVALID;
  1170. break;
  1171. case ALG_TKIP:
  1172. case ALG_WEP:
  1173. default:
  1174. return -EINVAL;
  1175. }
  1176. spin_lock_irqsave(&priv->sta_lock, flags);
  1177. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1178. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1179. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1180. keyconf->keylen);
  1181. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1182. keyconf->keylen);
  1183. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1184. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1185. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1186. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1187. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1188. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1189. return 0;
  1190. }
  1191. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1192. {
  1193. unsigned long flags;
  1194. spin_lock_irqsave(&priv->sta_lock, flags);
  1195. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1196. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1197. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1198. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1199. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1200. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1201. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1202. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1203. return 0;
  1204. }
  1205. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1206. {
  1207. struct list_head *element;
  1208. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1209. priv->frames_count);
  1210. while (!list_empty(&priv->free_frames)) {
  1211. element = priv->free_frames.next;
  1212. list_del(element);
  1213. kfree(list_entry(element, struct iwl3945_frame, list));
  1214. priv->frames_count--;
  1215. }
  1216. if (priv->frames_count) {
  1217. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1218. priv->frames_count);
  1219. priv->frames_count = 0;
  1220. }
  1221. }
  1222. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1223. {
  1224. struct iwl3945_frame *frame;
  1225. struct list_head *element;
  1226. if (list_empty(&priv->free_frames)) {
  1227. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1228. if (!frame) {
  1229. IWL_ERROR("Could not allocate frame!\n");
  1230. return NULL;
  1231. }
  1232. priv->frames_count++;
  1233. return frame;
  1234. }
  1235. element = priv->free_frames.next;
  1236. list_del(element);
  1237. return list_entry(element, struct iwl3945_frame, list);
  1238. }
  1239. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1240. {
  1241. memset(frame, 0, sizeof(*frame));
  1242. list_add(&frame->list, &priv->free_frames);
  1243. }
  1244. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1245. struct ieee80211_hdr *hdr,
  1246. const u8 *dest, int left)
  1247. {
  1248. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1249. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1250. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1251. return 0;
  1252. if (priv->ibss_beacon->len > left)
  1253. return 0;
  1254. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1255. return priv->ibss_beacon->len;
  1256. }
  1257. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1258. {
  1259. u8 i;
  1260. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1261. i = iwl3945_rates[i].next_ieee) {
  1262. if (rate_mask & (1 << i))
  1263. return iwl3945_rates[i].plcp;
  1264. }
  1265. return IWL_RATE_INVALID;
  1266. }
  1267. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1268. {
  1269. struct iwl3945_frame *frame;
  1270. unsigned int frame_size;
  1271. int rc;
  1272. u8 rate;
  1273. frame = iwl3945_get_free_frame(priv);
  1274. if (!frame) {
  1275. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1276. "command.\n");
  1277. return -ENOMEM;
  1278. }
  1279. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1280. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1281. 0xFF0);
  1282. if (rate == IWL_INVALID_RATE)
  1283. rate = IWL_RATE_6M_PLCP;
  1284. } else {
  1285. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1286. if (rate == IWL_INVALID_RATE)
  1287. rate = IWL_RATE_1M_PLCP;
  1288. }
  1289. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1290. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1291. &frame->u.cmd[0]);
  1292. iwl3945_free_frame(priv, frame);
  1293. return rc;
  1294. }
  1295. /******************************************************************************
  1296. *
  1297. * EEPROM related functions
  1298. *
  1299. ******************************************************************************/
  1300. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1301. {
  1302. memcpy(mac, priv->eeprom.mac_address, 6);
  1303. }
  1304. /*
  1305. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1306. * embedded controller) as EEPROM reader; each read is a series of pulses
  1307. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1308. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1309. * simply claims ownership, which should be safe when this function is called
  1310. * (i.e. before loading uCode!).
  1311. */
  1312. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1313. {
  1314. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1315. return 0;
  1316. }
  1317. /**
  1318. * iwl3945_eeprom_init - read EEPROM contents
  1319. *
  1320. * Load the EEPROM contents from adapter into priv->eeprom
  1321. *
  1322. * NOTE: This routine uses the non-debug IO access functions.
  1323. */
  1324. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1325. {
  1326. u16 *e = (u16 *)&priv->eeprom;
  1327. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1328. u32 r;
  1329. int sz = sizeof(priv->eeprom);
  1330. int rc;
  1331. int i;
  1332. u16 addr;
  1333. /* The EEPROM structure has several padding buffers within it
  1334. * and when adding new EEPROM maps is subject to programmer errors
  1335. * which may be very difficult to identify without explicitly
  1336. * checking the resulting size of the eeprom map. */
  1337. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1338. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1339. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1340. return -ENOENT;
  1341. }
  1342. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1343. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1344. if (rc < 0) {
  1345. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1346. return -ENOENT;
  1347. }
  1348. /* eeprom is an array of 16bit values */
  1349. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1350. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1351. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1352. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1353. i += IWL_EEPROM_ACCESS_DELAY) {
  1354. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1355. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1356. break;
  1357. udelay(IWL_EEPROM_ACCESS_DELAY);
  1358. }
  1359. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1360. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1361. return -ETIMEDOUT;
  1362. }
  1363. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1364. }
  1365. return 0;
  1366. }
  1367. /******************************************************************************
  1368. *
  1369. * Misc. internal state and helper functions
  1370. *
  1371. ******************************************************************************/
  1372. #ifdef CONFIG_IWL3945_DEBUG
  1373. /**
  1374. * iwl3945_report_frame - dump frame to syslog during debug sessions
  1375. *
  1376. * You may hack this function to show different aspects of received frames,
  1377. * including selective frame dumps.
  1378. * group100 parameter selects whether to show 1 out of 100 good frames.
  1379. */
  1380. void iwl3945_report_frame(struct iwl3945_priv *priv,
  1381. struct iwl3945_rx_packet *pkt,
  1382. struct ieee80211_hdr *header, int group100)
  1383. {
  1384. u32 to_us;
  1385. u32 print_summary = 0;
  1386. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  1387. u32 hundred = 0;
  1388. u32 dataframe = 0;
  1389. u16 fc;
  1390. u16 seq_ctl;
  1391. u16 channel;
  1392. u16 phy_flags;
  1393. int rate_sym;
  1394. u16 length;
  1395. u16 status;
  1396. u16 bcn_tmr;
  1397. u32 tsf_low;
  1398. u64 tsf;
  1399. u8 rssi;
  1400. u8 agc;
  1401. u16 sig_avg;
  1402. u16 noise_diff;
  1403. struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  1404. struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  1405. struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
  1406. u8 *data = IWL_RX_DATA(pkt);
  1407. /* MAC header */
  1408. fc = le16_to_cpu(header->frame_control);
  1409. seq_ctl = le16_to_cpu(header->seq_ctrl);
  1410. /* metadata */
  1411. channel = le16_to_cpu(rx_hdr->channel);
  1412. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  1413. rate_sym = rx_hdr->rate;
  1414. length = le16_to_cpu(rx_hdr->len);
  1415. /* end-of-frame status and timestamp */
  1416. status = le32_to_cpu(rx_end->status);
  1417. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  1418. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  1419. tsf = le64_to_cpu(rx_end->timestamp);
  1420. /* signal statistics */
  1421. rssi = rx_stats->rssi;
  1422. agc = rx_stats->agc;
  1423. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  1424. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  1425. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  1426. /* if data frame is to us and all is good,
  1427. * (optionally) print summary for only 1 out of every 100 */
  1428. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  1429. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  1430. dataframe = 1;
  1431. if (!group100)
  1432. print_summary = 1; /* print each frame */
  1433. else if (priv->framecnt_to_us < 100) {
  1434. priv->framecnt_to_us++;
  1435. print_summary = 0;
  1436. } else {
  1437. priv->framecnt_to_us = 0;
  1438. print_summary = 1;
  1439. hundred = 1;
  1440. }
  1441. } else {
  1442. /* print summary for all other frames */
  1443. print_summary = 1;
  1444. }
  1445. if (print_summary) {
  1446. char *title;
  1447. u32 rate;
  1448. if (hundred)
  1449. title = "100Frames";
  1450. else if (fc & IEEE80211_FCTL_RETRY)
  1451. title = "Retry";
  1452. else if (ieee80211_is_assoc_response(fc))
  1453. title = "AscRsp";
  1454. else if (ieee80211_is_reassoc_response(fc))
  1455. title = "RasRsp";
  1456. else if (ieee80211_is_probe_response(fc)) {
  1457. title = "PrbRsp";
  1458. print_dump = 1; /* dump frame contents */
  1459. } else if (ieee80211_is_beacon(fc)) {
  1460. title = "Beacon";
  1461. print_dump = 1; /* dump frame contents */
  1462. } else if (ieee80211_is_atim(fc))
  1463. title = "ATIM";
  1464. else if (ieee80211_is_auth(fc))
  1465. title = "Auth";
  1466. else if (ieee80211_is_deauth(fc))
  1467. title = "DeAuth";
  1468. else if (ieee80211_is_disassoc(fc))
  1469. title = "DisAssoc";
  1470. else
  1471. title = "Frame";
  1472. rate = iwl3945_rate_index_from_plcp(rate_sym);
  1473. if (rate == -1)
  1474. rate = 0;
  1475. else
  1476. rate = iwl3945_rates[rate].ieee / 2;
  1477. /* print frame summary.
  1478. * MAC addresses show just the last byte (for brevity),
  1479. * but you can hack it to show more, if you'd like to. */
  1480. if (dataframe)
  1481. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  1482. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  1483. title, fc, header->addr1[5],
  1484. length, rssi, channel, rate);
  1485. else {
  1486. /* src/dst addresses assume managed mode */
  1487. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  1488. "src=0x%02x, rssi=%u, tim=%lu usec, "
  1489. "phy=0x%02x, chnl=%d\n",
  1490. title, fc, header->addr1[5],
  1491. header->addr3[5], rssi,
  1492. tsf_low - priv->scan_start_tsf,
  1493. phy_flags, channel);
  1494. }
  1495. }
  1496. if (print_dump)
  1497. iwl3945_print_hex_dump(IWL_DL_RX, data, length);
  1498. }
  1499. #endif
  1500. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1501. {
  1502. if (priv->hw_setting.shared_virt)
  1503. pci_free_consistent(priv->pci_dev,
  1504. sizeof(struct iwl3945_shared),
  1505. priv->hw_setting.shared_virt,
  1506. priv->hw_setting.shared_phys);
  1507. }
  1508. /**
  1509. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1510. *
  1511. * return : set the bit for each supported rate insert in ie
  1512. */
  1513. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1514. u16 basic_rate, int *left)
  1515. {
  1516. u16 ret_rates = 0, bit;
  1517. int i;
  1518. u8 *cnt = ie;
  1519. u8 *rates = ie + 1;
  1520. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1521. if (bit & supported_rate) {
  1522. ret_rates |= bit;
  1523. rates[*cnt] = iwl3945_rates[i].ieee |
  1524. ((bit & basic_rate) ? 0x80 : 0x00);
  1525. (*cnt)++;
  1526. (*left)--;
  1527. if ((*left <= 0) ||
  1528. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1529. break;
  1530. }
  1531. }
  1532. return ret_rates;
  1533. }
  1534. /**
  1535. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1536. */
  1537. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1538. struct ieee80211_mgmt *frame,
  1539. int left, int is_direct)
  1540. {
  1541. int len = 0;
  1542. u8 *pos = NULL;
  1543. u16 active_rates, ret_rates, cck_rates;
  1544. /* Make sure there is enough space for the probe request,
  1545. * two mandatory IEs and the data */
  1546. left -= 24;
  1547. if (left < 0)
  1548. return 0;
  1549. len += 24;
  1550. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1551. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1552. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1553. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1554. frame->seq_ctrl = 0;
  1555. /* fill in our indirect SSID IE */
  1556. /* ...next IE... */
  1557. left -= 2;
  1558. if (left < 0)
  1559. return 0;
  1560. len += 2;
  1561. pos = &(frame->u.probe_req.variable[0]);
  1562. *pos++ = WLAN_EID_SSID;
  1563. *pos++ = 0;
  1564. /* fill in our direct SSID IE... */
  1565. if (is_direct) {
  1566. /* ...next IE... */
  1567. left -= 2 + priv->essid_len;
  1568. if (left < 0)
  1569. return 0;
  1570. /* ... fill it in... */
  1571. *pos++ = WLAN_EID_SSID;
  1572. *pos++ = priv->essid_len;
  1573. memcpy(pos, priv->essid, priv->essid_len);
  1574. pos += priv->essid_len;
  1575. len += 2 + priv->essid_len;
  1576. }
  1577. /* fill in supported rate */
  1578. /* ...next IE... */
  1579. left -= 2;
  1580. if (left < 0)
  1581. return 0;
  1582. /* ... fill it in... */
  1583. *pos++ = WLAN_EID_SUPP_RATES;
  1584. *pos = 0;
  1585. priv->active_rate = priv->rates_mask;
  1586. active_rates = priv->active_rate;
  1587. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1588. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1589. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1590. priv->active_rate_basic, &left);
  1591. active_rates &= ~ret_rates;
  1592. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1593. priv->active_rate_basic, &left);
  1594. active_rates &= ~ret_rates;
  1595. len += 2 + *pos;
  1596. pos += (*pos) + 1;
  1597. if (active_rates == 0)
  1598. goto fill_end;
  1599. /* fill in supported extended rate */
  1600. /* ...next IE... */
  1601. left -= 2;
  1602. if (left < 0)
  1603. return 0;
  1604. /* ... fill it in... */
  1605. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1606. *pos = 0;
  1607. iwl3945_supported_rate_to_ie(pos, active_rates,
  1608. priv->active_rate_basic, &left);
  1609. if (*pos > 0)
  1610. len += 2 + *pos;
  1611. fill_end:
  1612. return (u16)len;
  1613. }
  1614. /*
  1615. * QoS support
  1616. */
  1617. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1618. struct iwl3945_qosparam_cmd *qos)
  1619. {
  1620. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1621. sizeof(struct iwl3945_qosparam_cmd), qos);
  1622. }
  1623. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1624. {
  1625. u16 cw_min = 15;
  1626. u16 cw_max = 1023;
  1627. u8 aifs = 2;
  1628. u8 is_legacy = 0;
  1629. unsigned long flags;
  1630. int i;
  1631. spin_lock_irqsave(&priv->lock, flags);
  1632. priv->qos_data.qos_active = 0;
  1633. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1634. if (priv->qos_data.qos_enable)
  1635. priv->qos_data.qos_active = 1;
  1636. if (!(priv->active_rate & 0xfff0)) {
  1637. cw_min = 31;
  1638. is_legacy = 1;
  1639. }
  1640. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1641. if (priv->qos_data.qos_enable)
  1642. priv->qos_data.qos_active = 1;
  1643. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1644. cw_min = 31;
  1645. is_legacy = 1;
  1646. }
  1647. if (priv->qos_data.qos_active)
  1648. aifs = 3;
  1649. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1650. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1651. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1652. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1653. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1654. if (priv->qos_data.qos_active) {
  1655. i = 1;
  1656. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1657. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1658. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1659. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1660. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1661. i = 2;
  1662. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1663. cpu_to_le16((cw_min + 1) / 2 - 1);
  1664. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1665. cpu_to_le16(cw_max);
  1666. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1667. if (is_legacy)
  1668. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1669. cpu_to_le16(6016);
  1670. else
  1671. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1672. cpu_to_le16(3008);
  1673. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1674. i = 3;
  1675. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1676. cpu_to_le16((cw_min + 1) / 4 - 1);
  1677. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1678. cpu_to_le16((cw_max + 1) / 2 - 1);
  1679. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1680. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1681. if (is_legacy)
  1682. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1683. cpu_to_le16(3264);
  1684. else
  1685. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1686. cpu_to_le16(1504);
  1687. } else {
  1688. for (i = 1; i < 4; i++) {
  1689. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1690. cpu_to_le16(cw_min);
  1691. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1692. cpu_to_le16(cw_max);
  1693. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1694. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1695. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1696. }
  1697. }
  1698. IWL_DEBUG_QOS("set QoS to default \n");
  1699. spin_unlock_irqrestore(&priv->lock, flags);
  1700. }
  1701. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1702. {
  1703. unsigned long flags;
  1704. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1705. return;
  1706. if (!priv->qos_data.qos_enable)
  1707. return;
  1708. spin_lock_irqsave(&priv->lock, flags);
  1709. priv->qos_data.def_qos_parm.qos_flags = 0;
  1710. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1711. !priv->qos_data.qos_cap.q_AP.txop_request)
  1712. priv->qos_data.def_qos_parm.qos_flags |=
  1713. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1714. if (priv->qos_data.qos_active)
  1715. priv->qos_data.def_qos_parm.qos_flags |=
  1716. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1717. spin_unlock_irqrestore(&priv->lock, flags);
  1718. if (force || iwl3945_is_associated(priv)) {
  1719. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1720. priv->qos_data.qos_active);
  1721. iwl3945_send_qos_params_command(priv,
  1722. &(priv->qos_data.def_qos_parm));
  1723. }
  1724. }
  1725. /*
  1726. * Power management (not Tx power!) functions
  1727. */
  1728. #define MSEC_TO_USEC 1024
  1729. #define NOSLP __constant_cpu_to_le32(0)
  1730. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1731. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1732. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1733. __constant_cpu_to_le32(X1), \
  1734. __constant_cpu_to_le32(X2), \
  1735. __constant_cpu_to_le32(X3), \
  1736. __constant_cpu_to_le32(X4)}
  1737. /* default power management (not Tx power) table values */
  1738. /* for tim 0-10 */
  1739. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1740. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1741. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1742. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1743. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1744. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1745. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1746. };
  1747. /* for tim > 10 */
  1748. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1749. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1750. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1751. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1752. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1753. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1754. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1755. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1756. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1757. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1758. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1759. };
  1760. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1761. {
  1762. int rc = 0, i;
  1763. struct iwl3945_power_mgr *pow_data;
  1764. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1765. u16 pci_pm;
  1766. IWL_DEBUG_POWER("Initialize power \n");
  1767. pow_data = &(priv->power_data);
  1768. memset(pow_data, 0, sizeof(*pow_data));
  1769. pow_data->active_index = IWL_POWER_RANGE_0;
  1770. pow_data->dtim_val = 0xffff;
  1771. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1772. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1773. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1774. if (rc != 0)
  1775. return 0;
  1776. else {
  1777. struct iwl3945_powertable_cmd *cmd;
  1778. IWL_DEBUG_POWER("adjust power command flags\n");
  1779. for (i = 0; i < IWL_POWER_AC; i++) {
  1780. cmd = &pow_data->pwr_range_0[i].cmd;
  1781. if (pci_pm & 0x1)
  1782. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1783. else
  1784. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1785. }
  1786. }
  1787. return rc;
  1788. }
  1789. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1790. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1791. {
  1792. int rc = 0, i;
  1793. u8 skip;
  1794. u32 max_sleep = 0;
  1795. struct iwl3945_power_vec_entry *range;
  1796. u8 period = 0;
  1797. struct iwl3945_power_mgr *pow_data;
  1798. if (mode > IWL_POWER_INDEX_5) {
  1799. IWL_DEBUG_POWER("Error invalid power mode \n");
  1800. return -1;
  1801. }
  1802. pow_data = &(priv->power_data);
  1803. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1804. range = &pow_data->pwr_range_0[0];
  1805. else
  1806. range = &pow_data->pwr_range_1[1];
  1807. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1808. #ifdef IWL_MAC80211_DISABLE
  1809. if (priv->assoc_network != NULL) {
  1810. unsigned long flags;
  1811. period = priv->assoc_network->tim.tim_period;
  1812. }
  1813. #endif /*IWL_MAC80211_DISABLE */
  1814. skip = range[mode].no_dtim;
  1815. if (period == 0) {
  1816. period = 1;
  1817. skip = 0;
  1818. }
  1819. if (skip == 0) {
  1820. max_sleep = period;
  1821. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1822. } else {
  1823. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1824. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1825. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1826. }
  1827. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1828. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1829. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1830. }
  1831. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1832. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1833. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1834. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1835. le32_to_cpu(cmd->sleep_interval[0]),
  1836. le32_to_cpu(cmd->sleep_interval[1]),
  1837. le32_to_cpu(cmd->sleep_interval[2]),
  1838. le32_to_cpu(cmd->sleep_interval[3]),
  1839. le32_to_cpu(cmd->sleep_interval[4]));
  1840. return rc;
  1841. }
  1842. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1843. {
  1844. u32 uninitialized_var(final_mode);
  1845. int rc;
  1846. struct iwl3945_powertable_cmd cmd;
  1847. /* If on battery, set to 3,
  1848. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1849. * else user level */
  1850. switch (mode) {
  1851. case IWL_POWER_BATTERY:
  1852. final_mode = IWL_POWER_INDEX_3;
  1853. break;
  1854. case IWL_POWER_AC:
  1855. final_mode = IWL_POWER_MODE_CAM;
  1856. break;
  1857. default:
  1858. final_mode = mode;
  1859. break;
  1860. }
  1861. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1862. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1863. if (final_mode == IWL_POWER_MODE_CAM)
  1864. clear_bit(STATUS_POWER_PMI, &priv->status);
  1865. else
  1866. set_bit(STATUS_POWER_PMI, &priv->status);
  1867. return rc;
  1868. }
  1869. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1870. {
  1871. /* Filter incoming packets to determine if they are targeted toward
  1872. * this network, discarding packets coming from ourselves */
  1873. switch (priv->iw_mode) {
  1874. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1875. /* packets from our adapter are dropped (echo) */
  1876. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1877. return 0;
  1878. /* {broad,multi}cast packets to our IBSS go through */
  1879. if (is_multicast_ether_addr(header->addr1))
  1880. return !compare_ether_addr(header->addr3, priv->bssid);
  1881. /* packets to our adapter go through */
  1882. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1883. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1884. /* packets from our adapter are dropped (echo) */
  1885. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1886. return 0;
  1887. /* {broad,multi}cast packets to our BSS go through */
  1888. if (is_multicast_ether_addr(header->addr1))
  1889. return !compare_ether_addr(header->addr2, priv->bssid);
  1890. /* packets to our adapter go through */
  1891. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1892. }
  1893. return 1;
  1894. }
  1895. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  1896. static const char *iwl3945_get_tx_fail_reason(u32 status)
  1897. {
  1898. switch (status & TX_STATUS_MSK) {
  1899. case TX_STATUS_SUCCESS:
  1900. return "SUCCESS";
  1901. TX_STATUS_ENTRY(SHORT_LIMIT);
  1902. TX_STATUS_ENTRY(LONG_LIMIT);
  1903. TX_STATUS_ENTRY(FIFO_UNDERRUN);
  1904. TX_STATUS_ENTRY(MGMNT_ABORT);
  1905. TX_STATUS_ENTRY(NEXT_FRAG);
  1906. TX_STATUS_ENTRY(LIFE_EXPIRE);
  1907. TX_STATUS_ENTRY(DEST_PS);
  1908. TX_STATUS_ENTRY(ABORTED);
  1909. TX_STATUS_ENTRY(BT_RETRY);
  1910. TX_STATUS_ENTRY(STA_INVALID);
  1911. TX_STATUS_ENTRY(FRAG_DROPPED);
  1912. TX_STATUS_ENTRY(TID_DISABLE);
  1913. TX_STATUS_ENTRY(FRAME_FLUSHED);
  1914. TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
  1915. TX_STATUS_ENTRY(TX_LOCKED);
  1916. TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
  1917. }
  1918. return "UNKNOWN";
  1919. }
  1920. /**
  1921. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1922. *
  1923. * NOTE: priv->mutex is not required before calling this function
  1924. */
  1925. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1926. {
  1927. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1928. clear_bit(STATUS_SCANNING, &priv->status);
  1929. return 0;
  1930. }
  1931. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1932. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1933. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1934. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1935. queue_work(priv->workqueue, &priv->abort_scan);
  1936. } else
  1937. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1938. return test_bit(STATUS_SCANNING, &priv->status);
  1939. }
  1940. return 0;
  1941. }
  1942. /**
  1943. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1944. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1945. *
  1946. * NOTE: priv->mutex must be held before calling this function
  1947. */
  1948. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1949. {
  1950. unsigned long now = jiffies;
  1951. int ret;
  1952. ret = iwl3945_scan_cancel(priv);
  1953. if (ret && ms) {
  1954. mutex_unlock(&priv->mutex);
  1955. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1956. test_bit(STATUS_SCANNING, &priv->status))
  1957. msleep(1);
  1958. mutex_lock(&priv->mutex);
  1959. return test_bit(STATUS_SCANNING, &priv->status);
  1960. }
  1961. return ret;
  1962. }
  1963. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1964. {
  1965. /* Reset ieee stats */
  1966. /* We don't reset the net_device_stats (ieee->stats) on
  1967. * re-association */
  1968. priv->last_seq_num = -1;
  1969. priv->last_frag_num = -1;
  1970. priv->last_packet_time = 0;
  1971. iwl3945_scan_cancel(priv);
  1972. }
  1973. #define MAX_UCODE_BEACON_INTERVAL 1024
  1974. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1975. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1976. {
  1977. u16 new_val = 0;
  1978. u16 beacon_factor = 0;
  1979. beacon_factor =
  1980. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1981. / MAX_UCODE_BEACON_INTERVAL;
  1982. new_val = beacon_val / beacon_factor;
  1983. return cpu_to_le16(new_val);
  1984. }
  1985. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1986. {
  1987. u64 interval_tm_unit;
  1988. u64 tsf, result;
  1989. unsigned long flags;
  1990. struct ieee80211_conf *conf = NULL;
  1991. u16 beacon_int = 0;
  1992. conf = ieee80211_get_hw_conf(priv->hw);
  1993. spin_lock_irqsave(&priv->lock, flags);
  1994. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1995. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1996. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1997. tsf = priv->timestamp1;
  1998. tsf = ((tsf << 32) | priv->timestamp0);
  1999. beacon_int = priv->beacon_int;
  2000. spin_unlock_irqrestore(&priv->lock, flags);
  2001. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  2002. if (beacon_int == 0) {
  2003. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  2004. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  2005. } else {
  2006. priv->rxon_timing.beacon_interval =
  2007. cpu_to_le16(beacon_int);
  2008. priv->rxon_timing.beacon_interval =
  2009. iwl3945_adjust_beacon_interval(
  2010. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2011. }
  2012. priv->rxon_timing.atim_window = 0;
  2013. } else {
  2014. priv->rxon_timing.beacon_interval =
  2015. iwl3945_adjust_beacon_interval(conf->beacon_int);
  2016. /* TODO: we need to get atim_window from upper stack
  2017. * for now we set to 0 */
  2018. priv->rxon_timing.atim_window = 0;
  2019. }
  2020. interval_tm_unit =
  2021. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  2022. result = do_div(tsf, interval_tm_unit);
  2023. priv->rxon_timing.beacon_init_val =
  2024. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  2025. IWL_DEBUG_ASSOC
  2026. ("beacon interval %d beacon timer %d beacon tim %d\n",
  2027. le16_to_cpu(priv->rxon_timing.beacon_interval),
  2028. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  2029. le16_to_cpu(priv->rxon_timing.atim_window));
  2030. }
  2031. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  2032. {
  2033. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  2034. IWL_ERROR("APs don't scan.\n");
  2035. return 0;
  2036. }
  2037. if (!iwl3945_is_ready_rf(priv)) {
  2038. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  2039. return -EIO;
  2040. }
  2041. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2042. IWL_DEBUG_SCAN("Scan already in progress.\n");
  2043. return -EAGAIN;
  2044. }
  2045. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2046. IWL_DEBUG_SCAN("Scan request while abort pending. "
  2047. "Queuing.\n");
  2048. return -EAGAIN;
  2049. }
  2050. IWL_DEBUG_INFO("Starting scan...\n");
  2051. priv->scan_bands = 2;
  2052. set_bit(STATUS_SCANNING, &priv->status);
  2053. priv->scan_start = jiffies;
  2054. priv->scan_pass_start = priv->scan_start;
  2055. queue_work(priv->workqueue, &priv->request_scan);
  2056. return 0;
  2057. }
  2058. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  2059. {
  2060. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  2061. if (hw_decrypt)
  2062. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  2063. else
  2064. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  2065. return 0;
  2066. }
  2067. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  2068. enum ieee80211_band band)
  2069. {
  2070. if (band == IEEE80211_BAND_5GHZ) {
  2071. priv->staging_rxon.flags &=
  2072. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  2073. | RXON_FLG_CCK_MSK);
  2074. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2075. } else {
  2076. /* Copied from iwl3945_bg_post_associate() */
  2077. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2078. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2079. else
  2080. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2081. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  2082. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2083. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  2084. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  2085. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  2086. }
  2087. }
  2088. /*
  2089. * initialize rxon structure with default values from eeprom
  2090. */
  2091. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  2092. {
  2093. const struct iwl3945_channel_info *ch_info;
  2094. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  2095. switch (priv->iw_mode) {
  2096. case IEEE80211_IF_TYPE_AP:
  2097. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  2098. break;
  2099. case IEEE80211_IF_TYPE_STA:
  2100. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  2101. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  2102. break;
  2103. case IEEE80211_IF_TYPE_IBSS:
  2104. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  2105. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  2106. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  2107. RXON_FILTER_ACCEPT_GRP_MSK;
  2108. break;
  2109. case IEEE80211_IF_TYPE_MNTR:
  2110. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  2111. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  2112. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  2113. break;
  2114. }
  2115. #if 0
  2116. /* TODO: Figure out when short_preamble would be set and cache from
  2117. * that */
  2118. if (!hw_to_local(priv->hw)->short_preamble)
  2119. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2120. else
  2121. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2122. #endif
  2123. ch_info = iwl3945_get_channel_info(priv, priv->band,
  2124. le16_to_cpu(priv->staging_rxon.channel));
  2125. if (!ch_info)
  2126. ch_info = &priv->channel_info[0];
  2127. /*
  2128. * in some case A channels are all non IBSS
  2129. * in this case force B/G channel
  2130. */
  2131. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  2132. !(is_channel_ibss(ch_info)))
  2133. ch_info = &priv->channel_info[0];
  2134. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  2135. if (is_channel_a_band(ch_info))
  2136. priv->band = IEEE80211_BAND_5GHZ;
  2137. else
  2138. priv->band = IEEE80211_BAND_2GHZ;
  2139. iwl3945_set_flags_for_phymode(priv, priv->band);
  2140. priv->staging_rxon.ofdm_basic_rates =
  2141. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2142. priv->staging_rxon.cck_basic_rates =
  2143. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2144. }
  2145. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  2146. {
  2147. if (mode == IEEE80211_IF_TYPE_IBSS) {
  2148. const struct iwl3945_channel_info *ch_info;
  2149. ch_info = iwl3945_get_channel_info(priv,
  2150. priv->band,
  2151. le16_to_cpu(priv->staging_rxon.channel));
  2152. if (!ch_info || !is_channel_ibss(ch_info)) {
  2153. IWL_ERROR("channel %d not IBSS channel\n",
  2154. le16_to_cpu(priv->staging_rxon.channel));
  2155. return -EINVAL;
  2156. }
  2157. }
  2158. priv->iw_mode = mode;
  2159. iwl3945_connection_init_rx_config(priv);
  2160. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2161. iwl3945_clear_stations_table(priv);
  2162. /* dont commit rxon if rf-kill is on*/
  2163. if (!iwl3945_is_ready_rf(priv))
  2164. return -EAGAIN;
  2165. cancel_delayed_work(&priv->scan_check);
  2166. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  2167. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  2168. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  2169. return -EAGAIN;
  2170. }
  2171. iwl3945_commit_rxon(priv);
  2172. return 0;
  2173. }
  2174. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  2175. struct ieee80211_tx_control *ctl,
  2176. struct iwl3945_cmd *cmd,
  2177. struct sk_buff *skb_frag,
  2178. int last_frag)
  2179. {
  2180. struct iwl3945_hw_key *keyinfo = &priv->stations[ctl->key_idx].keyinfo;
  2181. switch (keyinfo->alg) {
  2182. case ALG_CCMP:
  2183. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  2184. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  2185. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  2186. break;
  2187. case ALG_TKIP:
  2188. #if 0
  2189. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2190. if (last_frag)
  2191. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2192. 8);
  2193. else
  2194. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2195. #endif
  2196. break;
  2197. case ALG_WEP:
  2198. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2199. (ctl->key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2200. if (keyinfo->keylen == 13)
  2201. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2202. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2203. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2204. "with key %d\n", ctl->key_idx);
  2205. break;
  2206. default:
  2207. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2208. break;
  2209. }
  2210. }
  2211. /*
  2212. * handle build REPLY_TX command notification.
  2213. */
  2214. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2215. struct iwl3945_cmd *cmd,
  2216. struct ieee80211_tx_control *ctrl,
  2217. struct ieee80211_hdr *hdr,
  2218. int is_unicast, u8 std_id)
  2219. {
  2220. __le16 *qc;
  2221. u16 fc = le16_to_cpu(hdr->frame_control);
  2222. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2223. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2224. if (!(ctrl->flags & IEEE80211_TXCTL_NO_ACK)) {
  2225. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2226. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
  2227. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2228. if (ieee80211_is_probe_response(fc) &&
  2229. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2230. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2231. } else {
  2232. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2233. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2234. }
  2235. cmd->cmd.tx.sta_id = std_id;
  2236. if (ieee80211_get_morefrag(hdr))
  2237. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2238. qc = ieee80211_get_qos_ctrl(hdr);
  2239. if (qc) {
  2240. cmd->cmd.tx.tid_tspec = (u8) (le16_to_cpu(*qc) & 0xf);
  2241. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2242. } else
  2243. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2244. if (ctrl->flags & IEEE80211_TXCTL_USE_RTS_CTS) {
  2245. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2246. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2247. } else if (ctrl->flags & IEEE80211_TXCTL_USE_CTS_PROTECT) {
  2248. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2249. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2250. }
  2251. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2252. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2253. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2254. if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
  2255. if ((fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_ASSOC_REQ ||
  2256. (fc & IEEE80211_FCTL_STYPE) == IEEE80211_STYPE_REASSOC_REQ)
  2257. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2258. else
  2259. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2260. } else
  2261. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2262. cmd->cmd.tx.driver_txop = 0;
  2263. cmd->cmd.tx.tx_flags = tx_flags;
  2264. cmd->cmd.tx.next_frame_len = 0;
  2265. }
  2266. /**
  2267. * iwl3945_get_sta_id - Find station's index within station table
  2268. */
  2269. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2270. {
  2271. int sta_id;
  2272. u16 fc = le16_to_cpu(hdr->frame_control);
  2273. /* If this frame is broadcast or management, use broadcast station id */
  2274. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2275. is_multicast_ether_addr(hdr->addr1))
  2276. return priv->hw_setting.bcast_sta_id;
  2277. switch (priv->iw_mode) {
  2278. /* If we are a client station in a BSS network, use the special
  2279. * AP station entry (that's the only station we communicate with) */
  2280. case IEEE80211_IF_TYPE_STA:
  2281. return IWL_AP_ID;
  2282. /* If we are an AP, then find the station, or use BCAST */
  2283. case IEEE80211_IF_TYPE_AP:
  2284. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2285. if (sta_id != IWL_INVALID_STATION)
  2286. return sta_id;
  2287. return priv->hw_setting.bcast_sta_id;
  2288. /* If this frame is going out to an IBSS network, find the station,
  2289. * or create a new station table entry */
  2290. case IEEE80211_IF_TYPE_IBSS: {
  2291. DECLARE_MAC_BUF(mac);
  2292. /* Create new station table entry */
  2293. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2294. if (sta_id != IWL_INVALID_STATION)
  2295. return sta_id;
  2296. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2297. if (sta_id != IWL_INVALID_STATION)
  2298. return sta_id;
  2299. IWL_DEBUG_DROP("Station %s not in station map. "
  2300. "Defaulting to broadcast...\n",
  2301. print_mac(mac, hdr->addr1));
  2302. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2303. return priv->hw_setting.bcast_sta_id;
  2304. }
  2305. default:
  2306. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2307. return priv->hw_setting.bcast_sta_id;
  2308. }
  2309. }
  2310. /*
  2311. * start REPLY_TX command process
  2312. */
  2313. static int iwl3945_tx_skb(struct iwl3945_priv *priv,
  2314. struct sk_buff *skb, struct ieee80211_tx_control *ctl)
  2315. {
  2316. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2317. struct iwl3945_tfd_frame *tfd;
  2318. u32 *control_flags;
  2319. int txq_id = ctl->queue;
  2320. struct iwl3945_tx_queue *txq = NULL;
  2321. struct iwl3945_queue *q = NULL;
  2322. dma_addr_t phys_addr;
  2323. dma_addr_t txcmd_phys;
  2324. struct iwl3945_cmd *out_cmd = NULL;
  2325. u16 len, idx, len_org;
  2326. u8 id, hdr_len, unicast;
  2327. u8 sta_id;
  2328. u16 seq_number = 0;
  2329. u16 fc;
  2330. __le16 *qc;
  2331. u8 wait_write_ptr = 0;
  2332. unsigned long flags;
  2333. int rc;
  2334. spin_lock_irqsave(&priv->lock, flags);
  2335. if (iwl3945_is_rfkill(priv)) {
  2336. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2337. goto drop_unlock;
  2338. }
  2339. if (!priv->vif) {
  2340. IWL_DEBUG_DROP("Dropping - !priv->vif\n");
  2341. goto drop_unlock;
  2342. }
  2343. if ((ctl->tx_rate->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2344. IWL_ERROR("ERROR: No TX rate available.\n");
  2345. goto drop_unlock;
  2346. }
  2347. unicast = !is_multicast_ether_addr(hdr->addr1);
  2348. id = 0;
  2349. fc = le16_to_cpu(hdr->frame_control);
  2350. #ifdef CONFIG_IWL3945_DEBUG
  2351. if (ieee80211_is_auth(fc))
  2352. IWL_DEBUG_TX("Sending AUTH frame\n");
  2353. else if (ieee80211_is_assoc_request(fc))
  2354. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2355. else if (ieee80211_is_reassoc_request(fc))
  2356. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2357. #endif
  2358. /* drop all data frame if we are not associated */
  2359. if ((!iwl3945_is_associated(priv) ||
  2360. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
  2361. ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA)) {
  2362. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2363. goto drop_unlock;
  2364. }
  2365. spin_unlock_irqrestore(&priv->lock, flags);
  2366. hdr_len = ieee80211_get_hdrlen(fc);
  2367. /* Find (or create) index into station table for destination station */
  2368. sta_id = iwl3945_get_sta_id(priv, hdr);
  2369. if (sta_id == IWL_INVALID_STATION) {
  2370. DECLARE_MAC_BUF(mac);
  2371. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2372. print_mac(mac, hdr->addr1));
  2373. goto drop;
  2374. }
  2375. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2376. qc = ieee80211_get_qos_ctrl(hdr);
  2377. if (qc) {
  2378. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2379. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2380. IEEE80211_SCTL_SEQ;
  2381. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2382. (hdr->seq_ctrl &
  2383. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2384. seq_number += 0x10;
  2385. }
  2386. /* Descriptor for chosen Tx queue */
  2387. txq = &priv->txq[txq_id];
  2388. q = &txq->q;
  2389. spin_lock_irqsave(&priv->lock, flags);
  2390. /* Set up first empty TFD within this queue's circular TFD buffer */
  2391. tfd = &txq->bd[q->write_ptr];
  2392. memset(tfd, 0, sizeof(*tfd));
  2393. control_flags = (u32 *) tfd;
  2394. idx = get_cmd_index(q, q->write_ptr, 0);
  2395. /* Set up driver data for this TFD */
  2396. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2397. txq->txb[q->write_ptr].skb[0] = skb;
  2398. memcpy(&(txq->txb[q->write_ptr].status.control),
  2399. ctl, sizeof(struct ieee80211_tx_control));
  2400. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2401. out_cmd = &txq->cmd[idx];
  2402. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2403. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2404. /*
  2405. * Set up the Tx-command (not MAC!) header.
  2406. * Store the chosen Tx queue and TFD index within the sequence field;
  2407. * after Tx, uCode's Tx response will return this value so driver can
  2408. * locate the frame within the tx queue and do post-tx processing.
  2409. */
  2410. out_cmd->hdr.cmd = REPLY_TX;
  2411. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2412. INDEX_TO_SEQ(q->write_ptr)));
  2413. /* Copy MAC header from skb into command buffer */
  2414. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2415. /*
  2416. * Use the first empty entry in this queue's command buffer array
  2417. * to contain the Tx command and MAC header concatenated together
  2418. * (payload data will be in another buffer).
  2419. * Size of this varies, due to varying MAC header length.
  2420. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2421. * of the MAC header (device reads on dword boundaries).
  2422. * We'll tell device about this padding later.
  2423. */
  2424. len = priv->hw_setting.tx_cmd_len +
  2425. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2426. len_org = len;
  2427. len = (len + 3) & ~3;
  2428. if (len_org != len)
  2429. len_org = 1;
  2430. else
  2431. len_org = 0;
  2432. /* Physical address of this Tx command's header (not MAC header!),
  2433. * within command buffer array. */
  2434. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2435. offsetof(struct iwl3945_cmd, hdr);
  2436. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2437. * first entry */
  2438. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2439. if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT))
  2440. iwl3945_build_tx_cmd_hwcrypto(priv, ctl, out_cmd, skb, 0);
  2441. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2442. * if any (802.11 null frames have no payload). */
  2443. len = skb->len - hdr_len;
  2444. if (len) {
  2445. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2446. len, PCI_DMA_TODEVICE);
  2447. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2448. }
  2449. if (!len)
  2450. /* If there is no payload, then we use only one Tx buffer */
  2451. *control_flags = TFD_CTL_COUNT_SET(1);
  2452. else
  2453. /* Else use 2 buffers.
  2454. * Tell 3945 about any padding after MAC header */
  2455. *control_flags = TFD_CTL_COUNT_SET(2) |
  2456. TFD_CTL_PAD_SET(U32_PAD(len));
  2457. /* Total # bytes to be transmitted */
  2458. len = (u16)skb->len;
  2459. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2460. /* TODO need this for burst mode later on */
  2461. iwl3945_build_tx_cmd_basic(priv, out_cmd, ctl, hdr, unicast, sta_id);
  2462. /* set is_hcca to 0; it probably will never be implemented */
  2463. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, ctl, hdr, sta_id, 0);
  2464. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2465. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2466. if (!ieee80211_get_morefrag(hdr)) {
  2467. txq->need_update = 1;
  2468. if (qc) {
  2469. u8 tid = (u8)(le16_to_cpu(*qc) & 0xf);
  2470. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2471. }
  2472. } else {
  2473. wait_write_ptr = 1;
  2474. txq->need_update = 0;
  2475. }
  2476. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2477. sizeof(out_cmd->cmd.tx));
  2478. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2479. ieee80211_get_hdrlen(fc));
  2480. /* Tell device the write index *just past* this latest filled TFD */
  2481. q->write_ptr = iwl3945_queue_inc_wrap(q->write_ptr, q->n_bd);
  2482. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2483. spin_unlock_irqrestore(&priv->lock, flags);
  2484. if (rc)
  2485. return rc;
  2486. if ((iwl3945_queue_space(q) < q->high_mark)
  2487. && priv->mac80211_registered) {
  2488. if (wait_write_ptr) {
  2489. spin_lock_irqsave(&priv->lock, flags);
  2490. txq->need_update = 1;
  2491. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2492. spin_unlock_irqrestore(&priv->lock, flags);
  2493. }
  2494. ieee80211_stop_queue(priv->hw, ctl->queue);
  2495. }
  2496. return 0;
  2497. drop_unlock:
  2498. spin_unlock_irqrestore(&priv->lock, flags);
  2499. drop:
  2500. return -1;
  2501. }
  2502. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2503. {
  2504. const struct ieee80211_supported_band *sband = NULL;
  2505. struct ieee80211_rate *rate;
  2506. int i;
  2507. sband = iwl3945_get_band(priv, priv->band);
  2508. if (!sband) {
  2509. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2510. return;
  2511. }
  2512. priv->active_rate = 0;
  2513. priv->active_rate_basic = 0;
  2514. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2515. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2516. for (i = 0; i < sband->n_bitrates; i++) {
  2517. rate = &sband->bitrates[i];
  2518. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2519. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2520. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2521. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2522. priv->active_rate |= (1 << rate->hw_value);
  2523. }
  2524. }
  2525. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2526. priv->active_rate, priv->active_rate_basic);
  2527. /*
  2528. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2529. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2530. * OFDM
  2531. */
  2532. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2533. priv->staging_rxon.cck_basic_rates =
  2534. ((priv->active_rate_basic &
  2535. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2536. else
  2537. priv->staging_rxon.cck_basic_rates =
  2538. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2539. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2540. priv->staging_rxon.ofdm_basic_rates =
  2541. ((priv->active_rate_basic &
  2542. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2543. IWL_FIRST_OFDM_RATE) & 0xFF;
  2544. else
  2545. priv->staging_rxon.ofdm_basic_rates =
  2546. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2547. }
  2548. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2549. {
  2550. unsigned long flags;
  2551. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2552. return;
  2553. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2554. disable_radio ? "OFF" : "ON");
  2555. if (disable_radio) {
  2556. iwl3945_scan_cancel(priv);
  2557. /* FIXME: This is a workaround for AP */
  2558. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2559. spin_lock_irqsave(&priv->lock, flags);
  2560. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2561. CSR_UCODE_SW_BIT_RFKILL);
  2562. spin_unlock_irqrestore(&priv->lock, flags);
  2563. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2564. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2565. }
  2566. return;
  2567. }
  2568. spin_lock_irqsave(&priv->lock, flags);
  2569. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2570. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2571. spin_unlock_irqrestore(&priv->lock, flags);
  2572. /* wake up ucode */
  2573. msleep(10);
  2574. spin_lock_irqsave(&priv->lock, flags);
  2575. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2576. if (!iwl3945_grab_nic_access(priv))
  2577. iwl3945_release_nic_access(priv);
  2578. spin_unlock_irqrestore(&priv->lock, flags);
  2579. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2580. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2581. "disabled by HW switch\n");
  2582. return;
  2583. }
  2584. queue_work(priv->workqueue, &priv->restart);
  2585. return;
  2586. }
  2587. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2588. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2589. {
  2590. u16 fc =
  2591. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2592. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2593. return;
  2594. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2595. return;
  2596. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2597. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2598. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2599. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2600. RX_RES_STATUS_BAD_ICV_MIC)
  2601. stats->flag |= RX_FLAG_MMIC_ERROR;
  2602. case RX_RES_STATUS_SEC_TYPE_WEP:
  2603. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2604. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2605. RX_RES_STATUS_DECRYPT_OK) {
  2606. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2607. stats->flag |= RX_FLAG_DECRYPTED;
  2608. }
  2609. break;
  2610. default:
  2611. break;
  2612. }
  2613. }
  2614. #define IWL_PACKET_RETRY_TIME HZ
  2615. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2616. {
  2617. u16 sc = le16_to_cpu(header->seq_ctrl);
  2618. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2619. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2620. u16 *last_seq, *last_frag;
  2621. unsigned long *last_time;
  2622. switch (priv->iw_mode) {
  2623. case IEEE80211_IF_TYPE_IBSS:{
  2624. struct list_head *p;
  2625. struct iwl3945_ibss_seq *entry = NULL;
  2626. u8 *mac = header->addr2;
  2627. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2628. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2629. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2630. if (!compare_ether_addr(entry->mac, mac))
  2631. break;
  2632. }
  2633. if (p == &priv->ibss_mac_hash[index]) {
  2634. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2635. if (!entry) {
  2636. IWL_ERROR("Cannot malloc new mac entry\n");
  2637. return 0;
  2638. }
  2639. memcpy(entry->mac, mac, ETH_ALEN);
  2640. entry->seq_num = seq;
  2641. entry->frag_num = frag;
  2642. entry->packet_time = jiffies;
  2643. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2644. return 0;
  2645. }
  2646. last_seq = &entry->seq_num;
  2647. last_frag = &entry->frag_num;
  2648. last_time = &entry->packet_time;
  2649. break;
  2650. }
  2651. case IEEE80211_IF_TYPE_STA:
  2652. last_seq = &priv->last_seq_num;
  2653. last_frag = &priv->last_frag_num;
  2654. last_time = &priv->last_packet_time;
  2655. break;
  2656. default:
  2657. return 0;
  2658. }
  2659. if ((*last_seq == seq) &&
  2660. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2661. if (*last_frag == frag)
  2662. goto drop;
  2663. if (*last_frag + 1 != frag)
  2664. /* out-of-order fragment */
  2665. goto drop;
  2666. } else
  2667. *last_seq = seq;
  2668. *last_frag = frag;
  2669. *last_time = jiffies;
  2670. return 0;
  2671. drop:
  2672. return 1;
  2673. }
  2674. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2675. #include "iwl-spectrum.h"
  2676. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2677. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2678. #define TIME_UNIT 1024
  2679. /*
  2680. * extended beacon time format
  2681. * time in usec will be changed into a 32-bit value in 8:24 format
  2682. * the high 1 byte is the beacon counts
  2683. * the lower 3 bytes is the time in usec within one beacon interval
  2684. */
  2685. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2686. {
  2687. u32 quot;
  2688. u32 rem;
  2689. u32 interval = beacon_interval * 1024;
  2690. if (!interval || !usec)
  2691. return 0;
  2692. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2693. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2694. return (quot << 24) + rem;
  2695. }
  2696. /* base is usually what we get from ucode with each received frame,
  2697. * the same as HW timer counter counting down
  2698. */
  2699. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2700. {
  2701. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2702. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2703. u32 interval = beacon_interval * TIME_UNIT;
  2704. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2705. (addon & BEACON_TIME_MASK_HIGH);
  2706. if (base_low > addon_low)
  2707. res += base_low - addon_low;
  2708. else if (base_low < addon_low) {
  2709. res += interval + base_low - addon_low;
  2710. res += (1 << 24);
  2711. } else
  2712. res += (1 << 24);
  2713. return cpu_to_le32(res);
  2714. }
  2715. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2716. struct ieee80211_measurement_params *params,
  2717. u8 type)
  2718. {
  2719. struct iwl3945_spectrum_cmd spectrum;
  2720. struct iwl3945_rx_packet *res;
  2721. struct iwl3945_host_cmd cmd = {
  2722. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2723. .data = (void *)&spectrum,
  2724. .meta.flags = CMD_WANT_SKB,
  2725. };
  2726. u32 add_time = le64_to_cpu(params->start_time);
  2727. int rc;
  2728. int spectrum_resp_status;
  2729. int duration = le16_to_cpu(params->duration);
  2730. if (iwl3945_is_associated(priv))
  2731. add_time =
  2732. iwl3945_usecs_to_beacons(
  2733. le64_to_cpu(params->start_time) - priv->last_tsf,
  2734. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2735. memset(&spectrum, 0, sizeof(spectrum));
  2736. spectrum.channel_count = cpu_to_le16(1);
  2737. spectrum.flags =
  2738. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2739. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2740. cmd.len = sizeof(spectrum);
  2741. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2742. if (iwl3945_is_associated(priv))
  2743. spectrum.start_time =
  2744. iwl3945_add_beacon_time(priv->last_beacon_time,
  2745. add_time,
  2746. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2747. else
  2748. spectrum.start_time = 0;
  2749. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2750. spectrum.channels[0].channel = params->channel;
  2751. spectrum.channels[0].type = type;
  2752. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2753. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2754. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2755. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2756. if (rc)
  2757. return rc;
  2758. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2759. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2760. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2761. rc = -EIO;
  2762. }
  2763. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2764. switch (spectrum_resp_status) {
  2765. case 0: /* Command will be handled */
  2766. if (res->u.spectrum.id != 0xff) {
  2767. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2768. res->u.spectrum.id);
  2769. priv->measurement_status &= ~MEASUREMENT_READY;
  2770. }
  2771. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2772. rc = 0;
  2773. break;
  2774. case 1: /* Command will not be handled */
  2775. rc = -EAGAIN;
  2776. break;
  2777. }
  2778. dev_kfree_skb_any(cmd.meta.u.skb);
  2779. return rc;
  2780. }
  2781. #endif
  2782. static void iwl3945_txstatus_to_ieee(struct iwl3945_priv *priv,
  2783. struct iwl3945_tx_info *tx_sta)
  2784. {
  2785. tx_sta->status.ack_signal = 0;
  2786. tx_sta->status.excessive_retries = 0;
  2787. tx_sta->status.queue_length = 0;
  2788. tx_sta->status.queue_number = 0;
  2789. if (in_interrupt())
  2790. ieee80211_tx_status_irqsafe(priv->hw,
  2791. tx_sta->skb[0], &(tx_sta->status));
  2792. else
  2793. ieee80211_tx_status(priv->hw,
  2794. tx_sta->skb[0], &(tx_sta->status));
  2795. tx_sta->skb[0] = NULL;
  2796. }
  2797. /**
  2798. * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
  2799. *
  2800. * When FW advances 'R' index, all entries between old and new 'R' index
  2801. * need to be reclaimed. As result, some free space forms. If there is
  2802. * enough free space (> low mark), wake the stack that feeds us.
  2803. */
  2804. static int iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, int txq_id, int index)
  2805. {
  2806. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2807. struct iwl3945_queue *q = &txq->q;
  2808. int nfreed = 0;
  2809. if ((index >= q->n_bd) || (x2_queue_used(q, index) == 0)) {
  2810. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2811. "is out of range [0-%d] %d %d.\n", txq_id,
  2812. index, q->n_bd, q->write_ptr, q->read_ptr);
  2813. return 0;
  2814. }
  2815. for (index = iwl3945_queue_inc_wrap(index, q->n_bd);
  2816. q->read_ptr != index;
  2817. q->read_ptr = iwl3945_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2818. if (txq_id != IWL_CMD_QUEUE_NUM) {
  2819. iwl3945_txstatus_to_ieee(priv,
  2820. &(txq->txb[txq->q.read_ptr]));
  2821. iwl3945_hw_txq_free_tfd(priv, txq);
  2822. } else if (nfreed > 1) {
  2823. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2824. q->write_ptr, q->read_ptr);
  2825. queue_work(priv->workqueue, &priv->restart);
  2826. }
  2827. nfreed++;
  2828. }
  2829. if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
  2830. (txq_id != IWL_CMD_QUEUE_NUM) &&
  2831. priv->mac80211_registered)
  2832. ieee80211_wake_queue(priv->hw, txq_id);
  2833. return nfreed;
  2834. }
  2835. static int iwl3945_is_tx_success(u32 status)
  2836. {
  2837. return (status & 0xFF) == 0x1;
  2838. }
  2839. /******************************************************************************
  2840. *
  2841. * Generic RX handler implementations
  2842. *
  2843. ******************************************************************************/
  2844. /**
  2845. * iwl3945_rx_reply_tx - Handle Tx response
  2846. */
  2847. static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
  2848. struct iwl3945_rx_mem_buffer *rxb)
  2849. {
  2850. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2851. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2852. int txq_id = SEQ_TO_QUEUE(sequence);
  2853. int index = SEQ_TO_INDEX(sequence);
  2854. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2855. struct ieee80211_tx_status *tx_status;
  2856. struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  2857. u32 status = le32_to_cpu(tx_resp->status);
  2858. if ((index >= txq->q.n_bd) || (x2_queue_used(&txq->q, index) == 0)) {
  2859. IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
  2860. "is out of range [0-%d] %d %d\n", txq_id,
  2861. index, txq->q.n_bd, txq->q.write_ptr,
  2862. txq->q.read_ptr);
  2863. return;
  2864. }
  2865. tx_status = &(txq->txb[txq->q.read_ptr].status);
  2866. tx_status->retry_count = tx_resp->failure_frame;
  2867. tx_status->queue_number = status;
  2868. tx_status->queue_length = tx_resp->bt_kill_count;
  2869. tx_status->queue_length |= tx_resp->failure_rts;
  2870. tx_status->flags =
  2871. iwl3945_is_tx_success(status) ? IEEE80211_TX_STATUS_ACK : 0;
  2872. IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
  2873. txq_id, iwl3945_get_tx_fail_reason(status), status,
  2874. tx_resp->rate, tx_resp->failure_frame);
  2875. IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
  2876. if (index != -1)
  2877. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  2878. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  2879. IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
  2880. }
  2881. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2882. struct iwl3945_rx_mem_buffer *rxb)
  2883. {
  2884. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2885. struct iwl3945_alive_resp *palive;
  2886. struct delayed_work *pwork;
  2887. palive = &pkt->u.alive_frame;
  2888. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2889. "0x%01X 0x%01X\n",
  2890. palive->is_valid, palive->ver_type,
  2891. palive->ver_subtype);
  2892. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2893. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2894. memcpy(&priv->card_alive_init,
  2895. &pkt->u.alive_frame,
  2896. sizeof(struct iwl3945_init_alive_resp));
  2897. pwork = &priv->init_alive_start;
  2898. } else {
  2899. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2900. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2901. sizeof(struct iwl3945_alive_resp));
  2902. pwork = &priv->alive_start;
  2903. iwl3945_disable_events(priv);
  2904. }
  2905. /* We delay the ALIVE response by 5ms to
  2906. * give the HW RF Kill time to activate... */
  2907. if (palive->is_valid == UCODE_VALID_OK)
  2908. queue_delayed_work(priv->workqueue, pwork,
  2909. msecs_to_jiffies(5));
  2910. else
  2911. IWL_WARNING("uCode did not respond OK.\n");
  2912. }
  2913. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2914. struct iwl3945_rx_mem_buffer *rxb)
  2915. {
  2916. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2917. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2918. return;
  2919. }
  2920. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2921. struct iwl3945_rx_mem_buffer *rxb)
  2922. {
  2923. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2924. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2925. "seq 0x%04X ser 0x%08X\n",
  2926. le32_to_cpu(pkt->u.err_resp.error_type),
  2927. get_cmd_string(pkt->u.err_resp.cmd_id),
  2928. pkt->u.err_resp.cmd_id,
  2929. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2930. le32_to_cpu(pkt->u.err_resp.error_info));
  2931. }
  2932. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2933. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2934. {
  2935. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2936. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2937. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2938. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2939. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2940. rxon->channel = csa->channel;
  2941. priv->staging_rxon.channel = csa->channel;
  2942. }
  2943. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2944. struct iwl3945_rx_mem_buffer *rxb)
  2945. {
  2946. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2947. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2948. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2949. if (!report->state) {
  2950. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2951. "Spectrum Measure Notification: Start\n");
  2952. return;
  2953. }
  2954. memcpy(&priv->measure_report, report, sizeof(*report));
  2955. priv->measurement_status |= MEASUREMENT_READY;
  2956. #endif
  2957. }
  2958. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2959. struct iwl3945_rx_mem_buffer *rxb)
  2960. {
  2961. #ifdef CONFIG_IWL3945_DEBUG
  2962. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2963. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2964. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2965. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2966. #endif
  2967. }
  2968. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2969. struct iwl3945_rx_mem_buffer *rxb)
  2970. {
  2971. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2972. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2973. "notification for %s:\n",
  2974. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2975. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2976. }
  2977. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2978. {
  2979. struct iwl3945_priv *priv =
  2980. container_of(work, struct iwl3945_priv, beacon_update);
  2981. struct sk_buff *beacon;
  2982. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2983. beacon = ieee80211_beacon_get(priv->hw, priv->vif, NULL);
  2984. if (!beacon) {
  2985. IWL_ERROR("update beacon failed\n");
  2986. return;
  2987. }
  2988. mutex_lock(&priv->mutex);
  2989. /* new beacon skb is allocated every time; dispose previous.*/
  2990. if (priv->ibss_beacon)
  2991. dev_kfree_skb(priv->ibss_beacon);
  2992. priv->ibss_beacon = beacon;
  2993. mutex_unlock(&priv->mutex);
  2994. iwl3945_send_beacon_cmd(priv);
  2995. }
  2996. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2997. struct iwl3945_rx_mem_buffer *rxb)
  2998. {
  2999. #ifdef CONFIG_IWL3945_DEBUG
  3000. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3001. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  3002. u8 rate = beacon->beacon_notify_hdr.rate;
  3003. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  3004. "tsf %d %d rate %d\n",
  3005. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  3006. beacon->beacon_notify_hdr.failure_frame,
  3007. le32_to_cpu(beacon->ibss_mgr_status),
  3008. le32_to_cpu(beacon->high_tsf),
  3009. le32_to_cpu(beacon->low_tsf), rate);
  3010. #endif
  3011. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  3012. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  3013. queue_work(priv->workqueue, &priv->beacon_update);
  3014. }
  3015. /* Service response to REPLY_SCAN_CMD (0x80) */
  3016. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  3017. struct iwl3945_rx_mem_buffer *rxb)
  3018. {
  3019. #ifdef CONFIG_IWL3945_DEBUG
  3020. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3021. struct iwl3945_scanreq_notification *notif =
  3022. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  3023. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  3024. #endif
  3025. }
  3026. /* Service SCAN_START_NOTIFICATION (0x82) */
  3027. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  3028. struct iwl3945_rx_mem_buffer *rxb)
  3029. {
  3030. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3031. struct iwl3945_scanstart_notification *notif =
  3032. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  3033. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  3034. IWL_DEBUG_SCAN("Scan start: "
  3035. "%d [802.11%s] "
  3036. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  3037. notif->channel,
  3038. notif->band ? "bg" : "a",
  3039. notif->tsf_high,
  3040. notif->tsf_low, notif->status, notif->beacon_timer);
  3041. }
  3042. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  3043. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  3044. struct iwl3945_rx_mem_buffer *rxb)
  3045. {
  3046. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3047. struct iwl3945_scanresults_notification *notif =
  3048. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  3049. IWL_DEBUG_SCAN("Scan ch.res: "
  3050. "%d [802.11%s] "
  3051. "(TSF: 0x%08X:%08X) - %d "
  3052. "elapsed=%lu usec (%dms since last)\n",
  3053. notif->channel,
  3054. notif->band ? "bg" : "a",
  3055. le32_to_cpu(notif->tsf_high),
  3056. le32_to_cpu(notif->tsf_low),
  3057. le32_to_cpu(notif->statistics[0]),
  3058. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  3059. jiffies_to_msecs(elapsed_jiffies
  3060. (priv->last_scan_jiffies, jiffies)));
  3061. priv->last_scan_jiffies = jiffies;
  3062. priv->next_scan_jiffies = 0;
  3063. }
  3064. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  3065. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  3066. struct iwl3945_rx_mem_buffer *rxb)
  3067. {
  3068. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3069. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  3070. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  3071. scan_notif->scanned_channels,
  3072. scan_notif->tsf_low,
  3073. scan_notif->tsf_high, scan_notif->status);
  3074. /* The HW is no longer scanning */
  3075. clear_bit(STATUS_SCAN_HW, &priv->status);
  3076. /* The scan completion notification came in, so kill that timer... */
  3077. cancel_delayed_work(&priv->scan_check);
  3078. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  3079. (priv->scan_bands == 2) ? "2.4" : "5.2",
  3080. jiffies_to_msecs(elapsed_jiffies
  3081. (priv->scan_pass_start, jiffies)));
  3082. /* Remove this scanned band from the list
  3083. * of pending bands to scan */
  3084. priv->scan_bands--;
  3085. /* If a request to abort was given, or the scan did not succeed
  3086. * then we reset the scan state machine and terminate,
  3087. * re-queuing another scan if one has been requested */
  3088. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  3089. IWL_DEBUG_INFO("Aborted scan completed.\n");
  3090. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  3091. } else {
  3092. /* If there are more bands on this scan pass reschedule */
  3093. if (priv->scan_bands > 0)
  3094. goto reschedule;
  3095. }
  3096. priv->last_scan_jiffies = jiffies;
  3097. priv->next_scan_jiffies = 0;
  3098. IWL_DEBUG_INFO("Setting scan to off\n");
  3099. clear_bit(STATUS_SCANNING, &priv->status);
  3100. IWL_DEBUG_INFO("Scan took %dms\n",
  3101. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  3102. queue_work(priv->workqueue, &priv->scan_completed);
  3103. return;
  3104. reschedule:
  3105. priv->scan_pass_start = jiffies;
  3106. queue_work(priv->workqueue, &priv->request_scan);
  3107. }
  3108. /* Handle notification from uCode that card's power state is changing
  3109. * due to software, hardware, or critical temperature RFKILL */
  3110. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  3111. struct iwl3945_rx_mem_buffer *rxb)
  3112. {
  3113. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  3114. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  3115. unsigned long status = priv->status;
  3116. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  3117. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  3118. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  3119. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  3120. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  3121. if (flags & HW_CARD_DISABLED)
  3122. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3123. else
  3124. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3125. if (flags & SW_CARD_DISABLED)
  3126. set_bit(STATUS_RF_KILL_SW, &priv->status);
  3127. else
  3128. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  3129. iwl3945_scan_cancel(priv);
  3130. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  3131. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  3132. (test_bit(STATUS_RF_KILL_SW, &status) !=
  3133. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  3134. queue_work(priv->workqueue, &priv->rf_kill);
  3135. else
  3136. wake_up_interruptible(&priv->wait_command_queue);
  3137. }
  3138. /**
  3139. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  3140. *
  3141. * Setup the RX handlers for each of the reply types sent from the uCode
  3142. * to the host.
  3143. *
  3144. * This function chains into the hardware specific files for them to setup
  3145. * any hardware specific handlers as well.
  3146. */
  3147. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  3148. {
  3149. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  3150. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  3151. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  3152. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  3153. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  3154. iwl3945_rx_spectrum_measure_notif;
  3155. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  3156. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  3157. iwl3945_rx_pm_debug_statistics_notif;
  3158. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  3159. /*
  3160. * The same handler is used for both the REPLY to a discrete
  3161. * statistics request from the host as well as for the periodic
  3162. * statistics notifications (after received beacons) from the uCode.
  3163. */
  3164. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  3165. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  3166. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  3167. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  3168. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  3169. iwl3945_rx_scan_results_notif;
  3170. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  3171. iwl3945_rx_scan_complete_notif;
  3172. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  3173. priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
  3174. /* Set up hardware specific Rx handlers */
  3175. iwl3945_hw_rx_handler_setup(priv);
  3176. }
  3177. /**
  3178. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  3179. * @rxb: Rx buffer to reclaim
  3180. *
  3181. * If an Rx buffer has an async callback associated with it the callback
  3182. * will be executed. The attached skb (if present) will only be freed
  3183. * if the callback returns 1
  3184. */
  3185. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  3186. struct iwl3945_rx_mem_buffer *rxb)
  3187. {
  3188. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3189. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  3190. int txq_id = SEQ_TO_QUEUE(sequence);
  3191. int index = SEQ_TO_INDEX(sequence);
  3192. int huge = sequence & SEQ_HUGE_FRAME;
  3193. int cmd_index;
  3194. struct iwl3945_cmd *cmd;
  3195. /* If a Tx command is being handled and it isn't in the actual
  3196. * command queue then there a command routing bug has been introduced
  3197. * in the queue management code. */
  3198. if (txq_id != IWL_CMD_QUEUE_NUM)
  3199. IWL_ERROR("Error wrong command queue %d command id 0x%X\n",
  3200. txq_id, pkt->hdr.cmd);
  3201. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  3202. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  3203. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  3204. /* Input error checking is done when commands are added to queue. */
  3205. if (cmd->meta.flags & CMD_WANT_SKB) {
  3206. cmd->meta.source->u.skb = rxb->skb;
  3207. rxb->skb = NULL;
  3208. } else if (cmd->meta.u.callback &&
  3209. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  3210. rxb->skb = NULL;
  3211. iwl3945_tx_queue_reclaim(priv, txq_id, index);
  3212. if (!(cmd->meta.flags & CMD_ASYNC)) {
  3213. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3214. wake_up_interruptible(&priv->wait_command_queue);
  3215. }
  3216. }
  3217. /************************** RX-FUNCTIONS ****************************/
  3218. /*
  3219. * Rx theory of operation
  3220. *
  3221. * The host allocates 32 DMA target addresses and passes the host address
  3222. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  3223. * 0 to 31
  3224. *
  3225. * Rx Queue Indexes
  3226. * The host/firmware share two index registers for managing the Rx buffers.
  3227. *
  3228. * The READ index maps to the first position that the firmware may be writing
  3229. * to -- the driver can read up to (but not including) this position and get
  3230. * good data.
  3231. * The READ index is managed by the firmware once the card is enabled.
  3232. *
  3233. * The WRITE index maps to the last position the driver has read from -- the
  3234. * position preceding WRITE is the last slot the firmware can place a packet.
  3235. *
  3236. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  3237. * WRITE = READ.
  3238. *
  3239. * During initialization, the host sets up the READ queue position to the first
  3240. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  3241. *
  3242. * When the firmware places a packet in a buffer, it will advance the READ index
  3243. * and fire the RX interrupt. The driver can then query the READ index and
  3244. * process as many packets as possible, moving the WRITE index forward as it
  3245. * resets the Rx queue buffers with new memory.
  3246. *
  3247. * The management in the driver is as follows:
  3248. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  3249. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  3250. * to replenish the iwl->rxq->rx_free.
  3251. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  3252. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  3253. * 'processed' and 'read' driver indexes as well)
  3254. * + A received packet is processed and handed to the kernel network stack,
  3255. * detached from the iwl->rxq. The driver 'processed' index is updated.
  3256. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  3257. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3258. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3259. * were enough free buffers and RX_STALLED is set it is cleared.
  3260. *
  3261. *
  3262. * Driver sequence:
  3263. *
  3264. * iwl3945_rx_queue_alloc() Allocates rx_free
  3265. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3266. * iwl3945_rx_queue_restock
  3267. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3268. * queue, updates firmware pointers, and updates
  3269. * the WRITE index. If insufficient rx_free buffers
  3270. * are available, schedules iwl3945_rx_replenish
  3271. *
  3272. * -- enable interrupts --
  3273. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3274. * READ INDEX, detaching the SKB from the pool.
  3275. * Moves the packet buffer from queue to rx_used.
  3276. * Calls iwl3945_rx_queue_restock to refill any empty
  3277. * slots.
  3278. * ...
  3279. *
  3280. */
  3281. /**
  3282. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3283. */
  3284. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3285. {
  3286. int s = q->read - q->write;
  3287. if (s <= 0)
  3288. s += RX_QUEUE_SIZE;
  3289. /* keep some buffer to not confuse full and empty queue */
  3290. s -= 2;
  3291. if (s < 0)
  3292. s = 0;
  3293. return s;
  3294. }
  3295. /**
  3296. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3297. */
  3298. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3299. {
  3300. u32 reg = 0;
  3301. int rc = 0;
  3302. unsigned long flags;
  3303. spin_lock_irqsave(&q->lock, flags);
  3304. if (q->need_update == 0)
  3305. goto exit_unlock;
  3306. /* If power-saving is in use, make sure device is awake */
  3307. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3308. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3309. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3310. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3311. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3312. goto exit_unlock;
  3313. }
  3314. rc = iwl3945_grab_nic_access(priv);
  3315. if (rc)
  3316. goto exit_unlock;
  3317. /* Device expects a multiple of 8 */
  3318. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3319. q->write & ~0x7);
  3320. iwl3945_release_nic_access(priv);
  3321. /* Else device is assumed to be awake */
  3322. } else
  3323. /* Device expects a multiple of 8 */
  3324. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3325. q->need_update = 0;
  3326. exit_unlock:
  3327. spin_unlock_irqrestore(&q->lock, flags);
  3328. return rc;
  3329. }
  3330. /**
  3331. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3332. */
  3333. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3334. dma_addr_t dma_addr)
  3335. {
  3336. return cpu_to_le32((u32)dma_addr);
  3337. }
  3338. /**
  3339. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3340. *
  3341. * If there are slots in the RX queue that need to be restocked,
  3342. * and we have free pre-allocated buffers, fill the ranks as much
  3343. * as we can, pulling from rx_free.
  3344. *
  3345. * This moves the 'write' index forward to catch up with 'processed', and
  3346. * also updates the memory address in the firmware to reference the new
  3347. * target buffer.
  3348. */
  3349. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3350. {
  3351. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3352. struct list_head *element;
  3353. struct iwl3945_rx_mem_buffer *rxb;
  3354. unsigned long flags;
  3355. int write, rc;
  3356. spin_lock_irqsave(&rxq->lock, flags);
  3357. write = rxq->write & ~0x7;
  3358. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3359. /* Get next free Rx buffer, remove from free list */
  3360. element = rxq->rx_free.next;
  3361. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3362. list_del(element);
  3363. /* Point to Rx buffer via next RBD in circular buffer */
  3364. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3365. rxq->queue[rxq->write] = rxb;
  3366. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3367. rxq->free_count--;
  3368. }
  3369. spin_unlock_irqrestore(&rxq->lock, flags);
  3370. /* If the pre-allocated buffer pool is dropping low, schedule to
  3371. * refill it */
  3372. if (rxq->free_count <= RX_LOW_WATERMARK)
  3373. queue_work(priv->workqueue, &priv->rx_replenish);
  3374. /* If we've added more space for the firmware to place data, tell it.
  3375. * Increment device's write pointer in multiples of 8. */
  3376. if ((write != (rxq->write & ~0x7))
  3377. || (abs(rxq->write - rxq->read) > 7)) {
  3378. spin_lock_irqsave(&rxq->lock, flags);
  3379. rxq->need_update = 1;
  3380. spin_unlock_irqrestore(&rxq->lock, flags);
  3381. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3382. if (rc)
  3383. return rc;
  3384. }
  3385. return 0;
  3386. }
  3387. /**
  3388. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3389. *
  3390. * When moving to rx_free an SKB is allocated for the slot.
  3391. *
  3392. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3393. * This is called as a scheduled work item (except for during initialization)
  3394. */
  3395. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3396. {
  3397. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3398. struct list_head *element;
  3399. struct iwl3945_rx_mem_buffer *rxb;
  3400. unsigned long flags;
  3401. spin_lock_irqsave(&rxq->lock, flags);
  3402. while (!list_empty(&rxq->rx_used)) {
  3403. element = rxq->rx_used.next;
  3404. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3405. /* Alloc a new receive buffer */
  3406. rxb->skb =
  3407. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3408. if (!rxb->skb) {
  3409. if (net_ratelimit())
  3410. printk(KERN_CRIT DRV_NAME
  3411. ": Can not allocate SKB buffers\n");
  3412. /* We don't reschedule replenish work here -- we will
  3413. * call the restock method and if it still needs
  3414. * more buffers it will schedule replenish */
  3415. break;
  3416. }
  3417. /* If radiotap head is required, reserve some headroom here.
  3418. * The physical head count is a variable rx_stats->phy_count.
  3419. * We reserve 4 bytes here. Plus these extra bytes, the
  3420. * headroom of the physical head should be enough for the
  3421. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3422. */
  3423. skb_reserve(rxb->skb, 4);
  3424. priv->alloc_rxb_skb++;
  3425. list_del(element);
  3426. /* Get physical address of RB/SKB */
  3427. rxb->dma_addr =
  3428. pci_map_single(priv->pci_dev, rxb->skb->data,
  3429. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3430. list_add_tail(&rxb->list, &rxq->rx_free);
  3431. rxq->free_count++;
  3432. }
  3433. spin_unlock_irqrestore(&rxq->lock, flags);
  3434. }
  3435. /*
  3436. * this should be called while priv->lock is locked
  3437. */
  3438. static void __iwl3945_rx_replenish(void *data)
  3439. {
  3440. struct iwl3945_priv *priv = data;
  3441. iwl3945_rx_allocate(priv);
  3442. iwl3945_rx_queue_restock(priv);
  3443. }
  3444. void iwl3945_rx_replenish(void *data)
  3445. {
  3446. struct iwl3945_priv *priv = data;
  3447. unsigned long flags;
  3448. iwl3945_rx_allocate(priv);
  3449. spin_lock_irqsave(&priv->lock, flags);
  3450. iwl3945_rx_queue_restock(priv);
  3451. spin_unlock_irqrestore(&priv->lock, flags);
  3452. }
  3453. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3454. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3455. * This free routine walks the list of POOL entries and if SKB is set to
  3456. * non NULL it is unmapped and freed
  3457. */
  3458. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3459. {
  3460. int i;
  3461. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3462. if (rxq->pool[i].skb != NULL) {
  3463. pci_unmap_single(priv->pci_dev,
  3464. rxq->pool[i].dma_addr,
  3465. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3466. dev_kfree_skb(rxq->pool[i].skb);
  3467. }
  3468. }
  3469. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3470. rxq->dma_addr);
  3471. rxq->bd = NULL;
  3472. }
  3473. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3474. {
  3475. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3476. struct pci_dev *dev = priv->pci_dev;
  3477. int i;
  3478. spin_lock_init(&rxq->lock);
  3479. INIT_LIST_HEAD(&rxq->rx_free);
  3480. INIT_LIST_HEAD(&rxq->rx_used);
  3481. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3482. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3483. if (!rxq->bd)
  3484. return -ENOMEM;
  3485. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3486. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3487. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3488. /* Set us so that we have processed and used all buffers, but have
  3489. * not restocked the Rx queue with fresh buffers */
  3490. rxq->read = rxq->write = 0;
  3491. rxq->free_count = 0;
  3492. rxq->need_update = 0;
  3493. return 0;
  3494. }
  3495. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3496. {
  3497. unsigned long flags;
  3498. int i;
  3499. spin_lock_irqsave(&rxq->lock, flags);
  3500. INIT_LIST_HEAD(&rxq->rx_free);
  3501. INIT_LIST_HEAD(&rxq->rx_used);
  3502. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3503. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3504. /* In the reset function, these buffers may have been allocated
  3505. * to an SKB, so we need to unmap and free potential storage */
  3506. if (rxq->pool[i].skb != NULL) {
  3507. pci_unmap_single(priv->pci_dev,
  3508. rxq->pool[i].dma_addr,
  3509. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3510. priv->alloc_rxb_skb--;
  3511. dev_kfree_skb(rxq->pool[i].skb);
  3512. rxq->pool[i].skb = NULL;
  3513. }
  3514. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3515. }
  3516. /* Set us so that we have processed and used all buffers, but have
  3517. * not restocked the Rx queue with fresh buffers */
  3518. rxq->read = rxq->write = 0;
  3519. rxq->free_count = 0;
  3520. spin_unlock_irqrestore(&rxq->lock, flags);
  3521. }
  3522. /* Convert linear signal-to-noise ratio into dB */
  3523. static u8 ratio2dB[100] = {
  3524. /* 0 1 2 3 4 5 6 7 8 9 */
  3525. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3526. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3527. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3528. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3529. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3530. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3531. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3532. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3533. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3534. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3535. };
  3536. /* Calculates a relative dB value from a ratio of linear
  3537. * (i.e. not dB) signal levels.
  3538. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3539. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3540. {
  3541. /* 1000:1 or higher just report as 60 dB */
  3542. if (sig_ratio >= 1000)
  3543. return 60;
  3544. /* 100:1 or higher, divide by 10 and use table,
  3545. * add 20 dB to make up for divide by 10 */
  3546. if (sig_ratio >= 100)
  3547. return (20 + (int)ratio2dB[sig_ratio/10]);
  3548. /* We shouldn't see this */
  3549. if (sig_ratio < 1)
  3550. return 0;
  3551. /* Use table for ratios 1:1 - 99:1 */
  3552. return (int)ratio2dB[sig_ratio];
  3553. }
  3554. #define PERFECT_RSSI (-20) /* dBm */
  3555. #define WORST_RSSI (-95) /* dBm */
  3556. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3557. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3558. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3559. * about formulas used below. */
  3560. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3561. {
  3562. int sig_qual;
  3563. int degradation = PERFECT_RSSI - rssi_dbm;
  3564. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3565. * as indicator; formula is (signal dbm - noise dbm).
  3566. * SNR at or above 40 is a great signal (100%).
  3567. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3568. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3569. if (noise_dbm) {
  3570. if (rssi_dbm - noise_dbm >= 40)
  3571. return 100;
  3572. else if (rssi_dbm < noise_dbm)
  3573. return 0;
  3574. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3575. /* Else use just the signal level.
  3576. * This formula is a least squares fit of data points collected and
  3577. * compared with a reference system that had a percentage (%) display
  3578. * for signal quality. */
  3579. } else
  3580. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3581. (15 * RSSI_RANGE + 62 * degradation)) /
  3582. (RSSI_RANGE * RSSI_RANGE);
  3583. if (sig_qual > 100)
  3584. sig_qual = 100;
  3585. else if (sig_qual < 1)
  3586. sig_qual = 0;
  3587. return sig_qual;
  3588. }
  3589. /**
  3590. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3591. *
  3592. * Uses the priv->rx_handlers callback function array to invoke
  3593. * the appropriate handlers, including command responses,
  3594. * frame-received notifications, and other notifications.
  3595. */
  3596. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3597. {
  3598. struct iwl3945_rx_mem_buffer *rxb;
  3599. struct iwl3945_rx_packet *pkt;
  3600. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3601. u32 r, i;
  3602. int reclaim;
  3603. unsigned long flags;
  3604. u8 fill_rx = 0;
  3605. u32 count = 8;
  3606. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3607. * buffer that the driver may process (last buffer filled by ucode). */
  3608. r = iwl3945_hw_get_rx_read(priv);
  3609. i = rxq->read;
  3610. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3611. fill_rx = 1;
  3612. /* Rx interrupt, but nothing sent from uCode */
  3613. if (i == r)
  3614. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3615. while (i != r) {
  3616. rxb = rxq->queue[i];
  3617. /* If an RXB doesn't have a Rx queue slot associated with it,
  3618. * then a bug has been introduced in the queue refilling
  3619. * routines -- catch it here */
  3620. BUG_ON(rxb == NULL);
  3621. rxq->queue[i] = NULL;
  3622. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3623. IWL_RX_BUF_SIZE,
  3624. PCI_DMA_FROMDEVICE);
  3625. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3626. /* Reclaim a command buffer only if this packet is a response
  3627. * to a (driver-originated) command.
  3628. * If the packet (e.g. Rx frame) originated from uCode,
  3629. * there is no command buffer to reclaim.
  3630. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3631. * but apparently a few don't get set; catch them here. */
  3632. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3633. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3634. (pkt->hdr.cmd != REPLY_TX);
  3635. /* Based on type of command response or notification,
  3636. * handle those that need handling via function in
  3637. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3638. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3639. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3640. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3641. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3642. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3643. } else {
  3644. /* No handling needed */
  3645. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3646. "r %d i %d No handler needed for %s, 0x%02x\n",
  3647. r, i, get_cmd_string(pkt->hdr.cmd),
  3648. pkt->hdr.cmd);
  3649. }
  3650. if (reclaim) {
  3651. /* Invoke any callbacks, transfer the skb to caller, and
  3652. * fire off the (possibly) blocking iwl3945_send_cmd()
  3653. * as we reclaim the driver command queue */
  3654. if (rxb && rxb->skb)
  3655. iwl3945_tx_cmd_complete(priv, rxb);
  3656. else
  3657. IWL_WARNING("Claim null rxb?\n");
  3658. }
  3659. /* For now we just don't re-use anything. We can tweak this
  3660. * later to try and re-use notification packets and SKBs that
  3661. * fail to Rx correctly */
  3662. if (rxb->skb != NULL) {
  3663. priv->alloc_rxb_skb--;
  3664. dev_kfree_skb_any(rxb->skb);
  3665. rxb->skb = NULL;
  3666. }
  3667. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3668. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3669. spin_lock_irqsave(&rxq->lock, flags);
  3670. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3671. spin_unlock_irqrestore(&rxq->lock, flags);
  3672. i = (i + 1) & RX_QUEUE_MASK;
  3673. /* If there are a lot of unused frames,
  3674. * restock the Rx queue so ucode won't assert. */
  3675. if (fill_rx) {
  3676. count++;
  3677. if (count >= 8) {
  3678. priv->rxq.read = i;
  3679. __iwl3945_rx_replenish(priv);
  3680. count = 0;
  3681. }
  3682. }
  3683. }
  3684. /* Backtrack one entry */
  3685. priv->rxq.read = i;
  3686. iwl3945_rx_queue_restock(priv);
  3687. }
  3688. /**
  3689. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3690. */
  3691. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3692. struct iwl3945_tx_queue *txq)
  3693. {
  3694. u32 reg = 0;
  3695. int rc = 0;
  3696. int txq_id = txq->q.id;
  3697. if (txq->need_update == 0)
  3698. return rc;
  3699. /* if we're trying to save power */
  3700. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3701. /* wake up nic if it's powered down ...
  3702. * uCode will wake up, and interrupt us again, so next
  3703. * time we'll skip this part. */
  3704. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3705. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3706. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3707. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3708. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3709. return rc;
  3710. }
  3711. /* restore this queue's parameters in nic hardware. */
  3712. rc = iwl3945_grab_nic_access(priv);
  3713. if (rc)
  3714. return rc;
  3715. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3716. txq->q.write_ptr | (txq_id << 8));
  3717. iwl3945_release_nic_access(priv);
  3718. /* else not in power-save mode, uCode will never sleep when we're
  3719. * trying to tx (during RFKILL, we're not trying to tx). */
  3720. } else
  3721. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3722. txq->q.write_ptr | (txq_id << 8));
  3723. txq->need_update = 0;
  3724. return rc;
  3725. }
  3726. #ifdef CONFIG_IWL3945_DEBUG
  3727. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3728. {
  3729. DECLARE_MAC_BUF(mac);
  3730. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3731. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3732. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3733. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3734. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3735. le32_to_cpu(rxon->filter_flags));
  3736. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3737. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3738. rxon->ofdm_basic_rates);
  3739. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3740. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3741. print_mac(mac, rxon->node_addr));
  3742. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3743. print_mac(mac, rxon->bssid_addr));
  3744. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3745. }
  3746. #endif
  3747. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3748. {
  3749. IWL_DEBUG_ISR("Enabling interrupts\n");
  3750. set_bit(STATUS_INT_ENABLED, &priv->status);
  3751. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3752. }
  3753. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3754. {
  3755. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3756. /* disable interrupts from uCode/NIC to host */
  3757. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3758. /* acknowledge/clear/reset any interrupts still pending
  3759. * from uCode or flow handler (Rx/Tx DMA) */
  3760. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3761. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3762. IWL_DEBUG_ISR("Disabled interrupts\n");
  3763. }
  3764. static const char *desc_lookup(int i)
  3765. {
  3766. switch (i) {
  3767. case 1:
  3768. return "FAIL";
  3769. case 2:
  3770. return "BAD_PARAM";
  3771. case 3:
  3772. return "BAD_CHECKSUM";
  3773. case 4:
  3774. return "NMI_INTERRUPT";
  3775. case 5:
  3776. return "SYSASSERT";
  3777. case 6:
  3778. return "FATAL_ERROR";
  3779. }
  3780. return "UNKNOWN";
  3781. }
  3782. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3783. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3784. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3785. {
  3786. u32 i;
  3787. u32 desc, time, count, base, data1;
  3788. u32 blink1, blink2, ilink1, ilink2;
  3789. int rc;
  3790. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3791. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3792. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3793. return;
  3794. }
  3795. rc = iwl3945_grab_nic_access(priv);
  3796. if (rc) {
  3797. IWL_WARNING("Can not read from adapter at this time.\n");
  3798. return;
  3799. }
  3800. count = iwl3945_read_targ_mem(priv, base);
  3801. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3802. IWL_ERROR("Start IWL Error Log Dump:\n");
  3803. IWL_ERROR("Status: 0x%08lX, Config: %08X count: %d\n",
  3804. priv->status, priv->config, count);
  3805. }
  3806. IWL_ERROR("Desc Time asrtPC blink2 "
  3807. "ilink1 nmiPC Line\n");
  3808. for (i = ERROR_START_OFFSET;
  3809. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3810. i += ERROR_ELEM_SIZE) {
  3811. desc = iwl3945_read_targ_mem(priv, base + i);
  3812. time =
  3813. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3814. blink1 =
  3815. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3816. blink2 =
  3817. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3818. ilink1 =
  3819. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3820. ilink2 =
  3821. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3822. data1 =
  3823. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3824. IWL_ERROR
  3825. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3826. desc_lookup(desc), desc, time, blink1, blink2,
  3827. ilink1, ilink2, data1);
  3828. }
  3829. iwl3945_release_nic_access(priv);
  3830. }
  3831. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3832. /**
  3833. * iwl3945_print_event_log - Dump error event log to syslog
  3834. *
  3835. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3836. */
  3837. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3838. u32 num_events, u32 mode)
  3839. {
  3840. u32 i;
  3841. u32 base; /* SRAM byte address of event log header */
  3842. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3843. u32 ptr; /* SRAM byte address of log data */
  3844. u32 ev, time, data; /* event log data */
  3845. if (num_events == 0)
  3846. return;
  3847. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3848. if (mode == 0)
  3849. event_size = 2 * sizeof(u32);
  3850. else
  3851. event_size = 3 * sizeof(u32);
  3852. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3853. /* "time" is actually "data" for mode 0 (no timestamp).
  3854. * place event id # at far right for easier visual parsing. */
  3855. for (i = 0; i < num_events; i++) {
  3856. ev = iwl3945_read_targ_mem(priv, ptr);
  3857. ptr += sizeof(u32);
  3858. time = iwl3945_read_targ_mem(priv, ptr);
  3859. ptr += sizeof(u32);
  3860. if (mode == 0)
  3861. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3862. else {
  3863. data = iwl3945_read_targ_mem(priv, ptr);
  3864. ptr += sizeof(u32);
  3865. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3866. }
  3867. }
  3868. }
  3869. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3870. {
  3871. int rc;
  3872. u32 base; /* SRAM byte address of event log header */
  3873. u32 capacity; /* event log capacity in # entries */
  3874. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3875. u32 num_wraps; /* # times uCode wrapped to top of log */
  3876. u32 next_entry; /* index of next entry to be written by uCode */
  3877. u32 size; /* # entries that we'll print */
  3878. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3879. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3880. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3881. return;
  3882. }
  3883. rc = iwl3945_grab_nic_access(priv);
  3884. if (rc) {
  3885. IWL_WARNING("Can not read from adapter at this time.\n");
  3886. return;
  3887. }
  3888. /* event log header */
  3889. capacity = iwl3945_read_targ_mem(priv, base);
  3890. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3891. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3892. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3893. size = num_wraps ? capacity : next_entry;
  3894. /* bail out if nothing in log */
  3895. if (size == 0) {
  3896. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3897. iwl3945_release_nic_access(priv);
  3898. return;
  3899. }
  3900. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3901. size, num_wraps);
  3902. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3903. * i.e the next one that uCode would fill. */
  3904. if (num_wraps)
  3905. iwl3945_print_event_log(priv, next_entry,
  3906. capacity - next_entry, mode);
  3907. /* (then/else) start at top of log */
  3908. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3909. iwl3945_release_nic_access(priv);
  3910. }
  3911. /**
  3912. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3913. */
  3914. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3915. {
  3916. /* Set the FW error flag -- cleared on iwl3945_down */
  3917. set_bit(STATUS_FW_ERROR, &priv->status);
  3918. /* Cancel currently queued command. */
  3919. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3920. #ifdef CONFIG_IWL3945_DEBUG
  3921. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3922. iwl3945_dump_nic_error_log(priv);
  3923. iwl3945_dump_nic_event_log(priv);
  3924. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3925. }
  3926. #endif
  3927. wake_up_interruptible(&priv->wait_command_queue);
  3928. /* Keep the restart process from trying to send host
  3929. * commands by clearing the INIT status bit */
  3930. clear_bit(STATUS_READY, &priv->status);
  3931. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3932. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3933. "Restarting adapter due to uCode error.\n");
  3934. if (iwl3945_is_associated(priv)) {
  3935. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3936. sizeof(priv->recovery_rxon));
  3937. priv->error_recovering = 1;
  3938. }
  3939. queue_work(priv->workqueue, &priv->restart);
  3940. }
  3941. }
  3942. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3943. {
  3944. unsigned long flags;
  3945. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3946. sizeof(priv->staging_rxon));
  3947. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3948. iwl3945_commit_rxon(priv);
  3949. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3950. spin_lock_irqsave(&priv->lock, flags);
  3951. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3952. priv->error_recovering = 0;
  3953. spin_unlock_irqrestore(&priv->lock, flags);
  3954. }
  3955. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3956. {
  3957. u32 inta, handled = 0;
  3958. u32 inta_fh;
  3959. unsigned long flags;
  3960. #ifdef CONFIG_IWL3945_DEBUG
  3961. u32 inta_mask;
  3962. #endif
  3963. spin_lock_irqsave(&priv->lock, flags);
  3964. /* Ack/clear/reset pending uCode interrupts.
  3965. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3966. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3967. inta = iwl3945_read32(priv, CSR_INT);
  3968. iwl3945_write32(priv, CSR_INT, inta);
  3969. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3970. * Any new interrupts that happen after this, either while we're
  3971. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3972. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3973. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3974. #ifdef CONFIG_IWL3945_DEBUG
  3975. if (iwl3945_debug_level & IWL_DL_ISR) {
  3976. /* just for debug */
  3977. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3978. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3979. inta, inta_mask, inta_fh);
  3980. }
  3981. #endif
  3982. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3983. * atomic, make sure that inta covers all the interrupts that
  3984. * we've discovered, even if FH interrupt came in just after
  3985. * reading CSR_INT. */
  3986. if (inta_fh & CSR_FH_INT_RX_MASK)
  3987. inta |= CSR_INT_BIT_FH_RX;
  3988. if (inta_fh & CSR_FH_INT_TX_MASK)
  3989. inta |= CSR_INT_BIT_FH_TX;
  3990. /* Now service all interrupt bits discovered above. */
  3991. if (inta & CSR_INT_BIT_HW_ERR) {
  3992. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3993. /* Tell the device to stop sending interrupts */
  3994. iwl3945_disable_interrupts(priv);
  3995. iwl3945_irq_handle_error(priv);
  3996. handled |= CSR_INT_BIT_HW_ERR;
  3997. spin_unlock_irqrestore(&priv->lock, flags);
  3998. return;
  3999. }
  4000. #ifdef CONFIG_IWL3945_DEBUG
  4001. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  4002. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  4003. if (inta & CSR_INT_BIT_SCD)
  4004. IWL_DEBUG_ISR("Scheduler finished to transmit "
  4005. "the frame/frames.\n");
  4006. /* Alive notification via Rx interrupt will do the real work */
  4007. if (inta & CSR_INT_BIT_ALIVE)
  4008. IWL_DEBUG_ISR("Alive interrupt\n");
  4009. }
  4010. #endif
  4011. /* Safely ignore these bits for debug checks below */
  4012. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  4013. /* HW RF KILL switch toggled (4965 only) */
  4014. if (inta & CSR_INT_BIT_RF_KILL) {
  4015. int hw_rf_kill = 0;
  4016. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  4017. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  4018. hw_rf_kill = 1;
  4019. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  4020. "RF_KILL bit toggled to %s.\n",
  4021. hw_rf_kill ? "disable radio":"enable radio");
  4022. /* Queue restart only if RF_KILL switch was set to "kill"
  4023. * when we loaded driver, and is now set to "enable".
  4024. * After we're Alive, RF_KILL gets handled by
  4025. * iwl3945_rx_card_state_notif() */
  4026. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  4027. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4028. queue_work(priv->workqueue, &priv->restart);
  4029. }
  4030. handled |= CSR_INT_BIT_RF_KILL;
  4031. }
  4032. /* Chip got too hot and stopped itself (4965 only) */
  4033. if (inta & CSR_INT_BIT_CT_KILL) {
  4034. IWL_ERROR("Microcode CT kill error detected.\n");
  4035. handled |= CSR_INT_BIT_CT_KILL;
  4036. }
  4037. /* Error detected by uCode */
  4038. if (inta & CSR_INT_BIT_SW_ERR) {
  4039. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  4040. inta);
  4041. iwl3945_irq_handle_error(priv);
  4042. handled |= CSR_INT_BIT_SW_ERR;
  4043. }
  4044. /* uCode wakes up after power-down sleep */
  4045. if (inta & CSR_INT_BIT_WAKEUP) {
  4046. IWL_DEBUG_ISR("Wakeup interrupt\n");
  4047. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  4048. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  4049. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  4050. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  4051. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  4052. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  4053. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  4054. handled |= CSR_INT_BIT_WAKEUP;
  4055. }
  4056. /* All uCode command responses, including Tx command responses,
  4057. * Rx "responses" (frame-received notification), and other
  4058. * notifications from uCode come through here*/
  4059. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  4060. iwl3945_rx_handle(priv);
  4061. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  4062. }
  4063. if (inta & CSR_INT_BIT_FH_TX) {
  4064. IWL_DEBUG_ISR("Tx interrupt\n");
  4065. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  4066. if (!iwl3945_grab_nic_access(priv)) {
  4067. iwl3945_write_direct32(priv,
  4068. FH_TCSR_CREDIT
  4069. (ALM_FH_SRVC_CHNL), 0x0);
  4070. iwl3945_release_nic_access(priv);
  4071. }
  4072. handled |= CSR_INT_BIT_FH_TX;
  4073. }
  4074. if (inta & ~handled)
  4075. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  4076. if (inta & ~CSR_INI_SET_MASK) {
  4077. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  4078. inta & ~CSR_INI_SET_MASK);
  4079. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  4080. }
  4081. /* Re-enable all interrupts */
  4082. iwl3945_enable_interrupts(priv);
  4083. #ifdef CONFIG_IWL3945_DEBUG
  4084. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  4085. inta = iwl3945_read32(priv, CSR_INT);
  4086. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  4087. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4088. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  4089. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  4090. }
  4091. #endif
  4092. spin_unlock_irqrestore(&priv->lock, flags);
  4093. }
  4094. static irqreturn_t iwl3945_isr(int irq, void *data)
  4095. {
  4096. struct iwl3945_priv *priv = data;
  4097. u32 inta, inta_mask;
  4098. u32 inta_fh;
  4099. if (!priv)
  4100. return IRQ_NONE;
  4101. spin_lock(&priv->lock);
  4102. /* Disable (but don't clear!) interrupts here to avoid
  4103. * back-to-back ISRs and sporadic interrupts from our NIC.
  4104. * If we have something to service, the tasklet will re-enable ints.
  4105. * If we *don't* have something, we'll re-enable before leaving here. */
  4106. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  4107. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  4108. /* Discover which interrupts are active/pending */
  4109. inta = iwl3945_read32(priv, CSR_INT);
  4110. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  4111. /* Ignore interrupt if there's nothing in NIC to service.
  4112. * This may be due to IRQ shared with another device,
  4113. * or due to sporadic interrupts thrown from our NIC. */
  4114. if (!inta && !inta_fh) {
  4115. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  4116. goto none;
  4117. }
  4118. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  4119. /* Hardware disappeared */
  4120. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  4121. goto unplugged;
  4122. }
  4123. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  4124. inta, inta_mask, inta_fh);
  4125. inta &= ~CSR_INT_BIT_SCD;
  4126. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  4127. if (likely(inta || inta_fh))
  4128. tasklet_schedule(&priv->irq_tasklet);
  4129. unplugged:
  4130. spin_unlock(&priv->lock);
  4131. return IRQ_HANDLED;
  4132. none:
  4133. /* re-enable interrupts here since we don't have anything to service. */
  4134. iwl3945_enable_interrupts(priv);
  4135. spin_unlock(&priv->lock);
  4136. return IRQ_NONE;
  4137. }
  4138. /************************** EEPROM BANDS ****************************
  4139. *
  4140. * The iwl3945_eeprom_band definitions below provide the mapping from the
  4141. * EEPROM contents to the specific channel number supported for each
  4142. * band.
  4143. *
  4144. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  4145. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  4146. * The specific geography and calibration information for that channel
  4147. * is contained in the eeprom map itself.
  4148. *
  4149. * During init, we copy the eeprom information and channel map
  4150. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  4151. *
  4152. * channel_map_24/52 provides the index in the channel_info array for a
  4153. * given channel. We have to have two separate maps as there is channel
  4154. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  4155. * band_2
  4156. *
  4157. * A value of 0xff stored in the channel_map indicates that the channel
  4158. * is not supported by the hardware at all.
  4159. *
  4160. * A value of 0xfe in the channel_map indicates that the channel is not
  4161. * valid for Tx with the current hardware. This means that
  4162. * while the system can tune and receive on a given channel, it may not
  4163. * be able to associate or transmit any frames on that
  4164. * channel. There is no corresponding channel information for that
  4165. * entry.
  4166. *
  4167. *********************************************************************/
  4168. /* 2.4 GHz */
  4169. static const u8 iwl3945_eeprom_band_1[14] = {
  4170. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  4171. };
  4172. /* 5.2 GHz bands */
  4173. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  4174. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  4175. };
  4176. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  4177. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  4178. };
  4179. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  4180. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  4181. };
  4182. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  4183. 145, 149, 153, 157, 161, 165
  4184. };
  4185. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  4186. int *eeprom_ch_count,
  4187. const struct iwl3945_eeprom_channel
  4188. **eeprom_ch_info,
  4189. const u8 **eeprom_ch_index)
  4190. {
  4191. switch (band) {
  4192. case 1: /* 2.4GHz band */
  4193. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  4194. *eeprom_ch_info = priv->eeprom.band_1_channels;
  4195. *eeprom_ch_index = iwl3945_eeprom_band_1;
  4196. break;
  4197. case 2: /* 4.9GHz band */
  4198. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  4199. *eeprom_ch_info = priv->eeprom.band_2_channels;
  4200. *eeprom_ch_index = iwl3945_eeprom_band_2;
  4201. break;
  4202. case 3: /* 5.2GHz band */
  4203. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  4204. *eeprom_ch_info = priv->eeprom.band_3_channels;
  4205. *eeprom_ch_index = iwl3945_eeprom_band_3;
  4206. break;
  4207. case 4: /* 5.5GHz band */
  4208. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  4209. *eeprom_ch_info = priv->eeprom.band_4_channels;
  4210. *eeprom_ch_index = iwl3945_eeprom_band_4;
  4211. break;
  4212. case 5: /* 5.7GHz band */
  4213. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  4214. *eeprom_ch_info = priv->eeprom.band_5_channels;
  4215. *eeprom_ch_index = iwl3945_eeprom_band_5;
  4216. break;
  4217. default:
  4218. BUG();
  4219. return;
  4220. }
  4221. }
  4222. /**
  4223. * iwl3945_get_channel_info - Find driver's private channel info
  4224. *
  4225. * Based on band and channel number.
  4226. */
  4227. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  4228. enum ieee80211_band band, u16 channel)
  4229. {
  4230. int i;
  4231. switch (band) {
  4232. case IEEE80211_BAND_5GHZ:
  4233. for (i = 14; i < priv->channel_count; i++) {
  4234. if (priv->channel_info[i].channel == channel)
  4235. return &priv->channel_info[i];
  4236. }
  4237. break;
  4238. case IEEE80211_BAND_2GHZ:
  4239. if (channel >= 1 && channel <= 14)
  4240. return &priv->channel_info[channel - 1];
  4241. break;
  4242. case IEEE80211_NUM_BANDS:
  4243. WARN_ON(1);
  4244. }
  4245. return NULL;
  4246. }
  4247. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4248. ? # x " " : "")
  4249. /**
  4250. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  4251. */
  4252. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4253. {
  4254. int eeprom_ch_count = 0;
  4255. const u8 *eeprom_ch_index = NULL;
  4256. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4257. int band, ch;
  4258. struct iwl3945_channel_info *ch_info;
  4259. if (priv->channel_count) {
  4260. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4261. return 0;
  4262. }
  4263. if (priv->eeprom.version < 0x2f) {
  4264. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4265. priv->eeprom.version);
  4266. return -EINVAL;
  4267. }
  4268. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4269. priv->channel_count =
  4270. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4271. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4272. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4273. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4274. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4275. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4276. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4277. priv->channel_count, GFP_KERNEL);
  4278. if (!priv->channel_info) {
  4279. IWL_ERROR("Could not allocate channel_info\n");
  4280. priv->channel_count = 0;
  4281. return -ENOMEM;
  4282. }
  4283. ch_info = priv->channel_info;
  4284. /* Loop through the 5 EEPROM bands adding them in order to the
  4285. * channel map we maintain (that contains additional information than
  4286. * what just in the EEPROM) */
  4287. for (band = 1; band <= 5; band++) {
  4288. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4289. &eeprom_ch_info, &eeprom_ch_index);
  4290. /* Loop through each band adding each of the channels */
  4291. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4292. ch_info->channel = eeprom_ch_index[ch];
  4293. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  4294. IEEE80211_BAND_5GHZ;
  4295. /* permanently store EEPROM's channel regulatory flags
  4296. * and max power in channel info database. */
  4297. ch_info->eeprom = eeprom_ch_info[ch];
  4298. /* Copy the run-time flags so they are there even on
  4299. * invalid channels */
  4300. ch_info->flags = eeprom_ch_info[ch].flags;
  4301. if (!(is_channel_valid(ch_info))) {
  4302. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4303. "No traffic\n",
  4304. ch_info->channel,
  4305. ch_info->flags,
  4306. is_channel_a_band(ch_info) ?
  4307. "5.2" : "2.4");
  4308. ch_info++;
  4309. continue;
  4310. }
  4311. /* Initialize regulatory-based run-time data */
  4312. ch_info->max_power_avg = ch_info->curr_txpow =
  4313. eeprom_ch_info[ch].max_power_avg;
  4314. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4315. ch_info->min_power = 0;
  4316. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4317. " %ddBm): Ad-Hoc %ssupported\n",
  4318. ch_info->channel,
  4319. is_channel_a_band(ch_info) ?
  4320. "5.2" : "2.4",
  4321. CHECK_AND_PRINT(IBSS),
  4322. CHECK_AND_PRINT(ACTIVE),
  4323. CHECK_AND_PRINT(RADAR),
  4324. CHECK_AND_PRINT(WIDE),
  4325. CHECK_AND_PRINT(NARROW),
  4326. CHECK_AND_PRINT(DFS),
  4327. eeprom_ch_info[ch].flags,
  4328. eeprom_ch_info[ch].max_power_avg,
  4329. ((eeprom_ch_info[ch].
  4330. flags & EEPROM_CHANNEL_IBSS)
  4331. && !(eeprom_ch_info[ch].
  4332. flags & EEPROM_CHANNEL_RADAR))
  4333. ? "" : "not ");
  4334. /* Set the user_txpower_limit to the highest power
  4335. * supported by any channel */
  4336. if (eeprom_ch_info[ch].max_power_avg >
  4337. priv->user_txpower_limit)
  4338. priv->user_txpower_limit =
  4339. eeprom_ch_info[ch].max_power_avg;
  4340. ch_info++;
  4341. }
  4342. }
  4343. /* Set up txpower settings in driver for all channels */
  4344. if (iwl3945_txpower_set_from_eeprom(priv))
  4345. return -EIO;
  4346. return 0;
  4347. }
  4348. /*
  4349. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4350. */
  4351. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4352. {
  4353. kfree(priv->channel_info);
  4354. priv->channel_count = 0;
  4355. }
  4356. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4357. * sending probe req. This should be set long enough to hear probe responses
  4358. * from more than one AP. */
  4359. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4360. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4361. /* For faster active scanning, scan will move to the next channel if fewer than
  4362. * PLCP_QUIET_THRESH packets are heard on this channel within
  4363. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4364. * time if it's a quiet channel (nothing responded to our probe, and there's
  4365. * no other traffic).
  4366. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4367. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4368. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4369. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4370. * Must be set longer than active dwell time.
  4371. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4372. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4373. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4374. #define IWL_PASSIVE_DWELL_BASE (100)
  4375. #define IWL_CHANNEL_TUNE_TIME 5
  4376. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4377. enum ieee80211_band band)
  4378. {
  4379. if (band == IEEE80211_BAND_5GHZ)
  4380. return IWL_ACTIVE_DWELL_TIME_52;
  4381. else
  4382. return IWL_ACTIVE_DWELL_TIME_24;
  4383. }
  4384. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4385. enum ieee80211_band band)
  4386. {
  4387. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4388. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4389. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4390. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4391. if (iwl3945_is_associated(priv)) {
  4392. /* If we're associated, we clamp the maximum passive
  4393. * dwell time to be 98% of the beacon interval (minus
  4394. * 2 * channel tune time) */
  4395. passive = priv->beacon_int;
  4396. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4397. passive = IWL_PASSIVE_DWELL_BASE;
  4398. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4399. }
  4400. if (passive <= active)
  4401. passive = active + 1;
  4402. return passive;
  4403. }
  4404. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4405. enum ieee80211_band band,
  4406. u8 is_active, u8 direct_mask,
  4407. struct iwl3945_scan_channel *scan_ch)
  4408. {
  4409. const struct ieee80211_channel *channels = NULL;
  4410. const struct ieee80211_supported_band *sband;
  4411. const struct iwl3945_channel_info *ch_info;
  4412. u16 passive_dwell = 0;
  4413. u16 active_dwell = 0;
  4414. int added, i;
  4415. sband = iwl3945_get_band(priv, band);
  4416. if (!sband)
  4417. return 0;
  4418. channels = sband->channels;
  4419. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4420. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4421. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4422. if (channels[i].hw_value ==
  4423. le16_to_cpu(priv->active_rxon.channel)) {
  4424. if (iwl3945_is_associated(priv)) {
  4425. IWL_DEBUG_SCAN
  4426. ("Skipping current channel %d\n",
  4427. le16_to_cpu(priv->active_rxon.channel));
  4428. continue;
  4429. }
  4430. } else if (priv->only_active_channel)
  4431. continue;
  4432. scan_ch->channel = channels[i].hw_value;
  4433. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4434. if (!is_channel_valid(ch_info)) {
  4435. IWL_DEBUG_SCAN("Channel %d is INVALID for this SKU.\n",
  4436. scan_ch->channel);
  4437. continue;
  4438. }
  4439. if (!is_active || is_channel_passive(ch_info) ||
  4440. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4441. scan_ch->type = 0; /* passive */
  4442. else
  4443. scan_ch->type = 1; /* active */
  4444. if (scan_ch->type & 1)
  4445. scan_ch->type |= (direct_mask << 1);
  4446. if (is_channel_narrow(ch_info))
  4447. scan_ch->type |= (1 << 7);
  4448. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4449. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4450. /* Set txpower levels to defaults */
  4451. scan_ch->tpc.dsp_atten = 110;
  4452. /* scan_pwr_info->tpc.dsp_atten; */
  4453. /*scan_pwr_info->tpc.tx_gain; */
  4454. if (band == IEEE80211_BAND_5GHZ)
  4455. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4456. else {
  4457. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4458. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4459. * power level:
  4460. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4461. */
  4462. }
  4463. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4464. scan_ch->channel,
  4465. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4466. (scan_ch->type & 1) ?
  4467. active_dwell : passive_dwell);
  4468. scan_ch++;
  4469. added++;
  4470. }
  4471. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4472. return added;
  4473. }
  4474. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4475. struct ieee80211_rate *rates)
  4476. {
  4477. int i;
  4478. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4479. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4480. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4481. rates[i].hw_value_short = i;
  4482. rates[i].flags = 0;
  4483. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4484. /*
  4485. * If CCK != 1M then set short preamble rate flag.
  4486. */
  4487. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4488. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4489. }
  4490. }
  4491. }
  4492. /**
  4493. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4494. */
  4495. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4496. {
  4497. struct iwl3945_channel_info *ch;
  4498. struct ieee80211_supported_band *band;
  4499. struct ieee80211_channel *channels;
  4500. struct ieee80211_channel *geo_ch;
  4501. struct ieee80211_rate *rates;
  4502. int i = 0;
  4503. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4504. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4505. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4506. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4507. return 0;
  4508. }
  4509. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4510. priv->channel_count, GFP_KERNEL);
  4511. if (!channels)
  4512. return -ENOMEM;
  4513. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_MAX_RATES + 1)),
  4514. GFP_KERNEL);
  4515. if (!rates) {
  4516. kfree(channels);
  4517. return -ENOMEM;
  4518. }
  4519. /* 5.2GHz channels start after the 2.4GHz channels */
  4520. band = &priv->bands[IEEE80211_BAND_5GHZ];
  4521. band->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4522. band->bitrates = &rates[4];
  4523. band->n_bitrates = 8; /* just OFDM */
  4524. band = &priv->bands[IEEE80211_BAND_2GHZ];
  4525. band->channels = channels;
  4526. band->bitrates = rates;
  4527. band->n_bitrates = 12; /* OFDM & CCK */
  4528. priv->ieee_channels = channels;
  4529. priv->ieee_rates = rates;
  4530. iwl3945_init_hw_rates(priv, rates);
  4531. for (i = 0, geo_ch = channels; i < priv->channel_count; i++) {
  4532. ch = &priv->channel_info[i];
  4533. if (!is_channel_valid(ch)) {
  4534. IWL_DEBUG_INFO("Channel %d [%sGHz] is restricted -- "
  4535. "skipping.\n",
  4536. ch->channel, is_channel_a_band(ch) ?
  4537. "5.2" : "2.4");
  4538. continue;
  4539. }
  4540. if (is_channel_a_band(ch))
  4541. geo_ch = &priv->bands[IEEE80211_BAND_5GHZ].channels[priv->bands[IEEE80211_BAND_5GHZ].n_channels++];
  4542. else
  4543. geo_ch = &priv->bands[IEEE80211_BAND_2GHZ].channels[priv->bands[IEEE80211_BAND_2GHZ].n_channels++];
  4544. geo_ch->center_freq = ieee80211chan2mhz(ch->channel);
  4545. geo_ch->max_power = ch->max_power_avg;
  4546. geo_ch->max_antenna_gain = 0xff;
  4547. geo_ch->hw_value = ch->channel;
  4548. if (is_channel_valid(ch)) {
  4549. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4550. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4551. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4552. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4553. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4554. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4555. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4556. priv->max_channel_txpower_limit =
  4557. ch->max_power_avg;
  4558. } else
  4559. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4560. }
  4561. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && priv->is_abg) {
  4562. printk(KERN_INFO DRV_NAME
  4563. ": Incorrectly detected BG card as ABG. Please send "
  4564. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4565. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4566. priv->is_abg = 0;
  4567. }
  4568. printk(KERN_INFO DRV_NAME
  4569. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4570. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4571. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4572. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->bands[IEEE80211_BAND_2GHZ];
  4573. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->bands[IEEE80211_BAND_5GHZ];
  4574. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4575. return 0;
  4576. }
  4577. /*
  4578. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4579. */
  4580. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4581. {
  4582. kfree(priv->ieee_channels);
  4583. kfree(priv->ieee_rates);
  4584. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4585. }
  4586. /******************************************************************************
  4587. *
  4588. * uCode download functions
  4589. *
  4590. ******************************************************************************/
  4591. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4592. {
  4593. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4594. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4595. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4596. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4597. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4598. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4599. }
  4600. /**
  4601. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4602. * looking at all data.
  4603. */
  4604. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4605. {
  4606. u32 val;
  4607. u32 save_len = len;
  4608. int rc = 0;
  4609. u32 errcnt;
  4610. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4611. rc = iwl3945_grab_nic_access(priv);
  4612. if (rc)
  4613. return rc;
  4614. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4615. errcnt = 0;
  4616. for (; len > 0; len -= sizeof(u32), image++) {
  4617. /* read data comes through single port, auto-incr addr */
  4618. /* NOTE: Use the debugless read so we don't flood kernel log
  4619. * if IWL_DL_IO is set */
  4620. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4621. if (val != le32_to_cpu(*image)) {
  4622. IWL_ERROR("uCode INST section is invalid at "
  4623. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4624. save_len - len, val, le32_to_cpu(*image));
  4625. rc = -EIO;
  4626. errcnt++;
  4627. if (errcnt >= 20)
  4628. break;
  4629. }
  4630. }
  4631. iwl3945_release_nic_access(priv);
  4632. if (!errcnt)
  4633. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4634. return rc;
  4635. }
  4636. /**
  4637. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4638. * using sample data 100 bytes apart. If these sample points are good,
  4639. * it's a pretty good bet that everything between them is good, too.
  4640. */
  4641. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4642. {
  4643. u32 val;
  4644. int rc = 0;
  4645. u32 errcnt = 0;
  4646. u32 i;
  4647. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4648. rc = iwl3945_grab_nic_access(priv);
  4649. if (rc)
  4650. return rc;
  4651. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4652. /* read data comes through single port, auto-incr addr */
  4653. /* NOTE: Use the debugless read so we don't flood kernel log
  4654. * if IWL_DL_IO is set */
  4655. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4656. i + RTC_INST_LOWER_BOUND);
  4657. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4658. if (val != le32_to_cpu(*image)) {
  4659. #if 0 /* Enable this if you want to see details */
  4660. IWL_ERROR("uCode INST section is invalid at "
  4661. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4662. i, val, *image);
  4663. #endif
  4664. rc = -EIO;
  4665. errcnt++;
  4666. if (errcnt >= 3)
  4667. break;
  4668. }
  4669. }
  4670. iwl3945_release_nic_access(priv);
  4671. return rc;
  4672. }
  4673. /**
  4674. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4675. * and verify its contents
  4676. */
  4677. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4678. {
  4679. __le32 *image;
  4680. u32 len;
  4681. int rc = 0;
  4682. /* Try bootstrap */
  4683. image = (__le32 *)priv->ucode_boot.v_addr;
  4684. len = priv->ucode_boot.len;
  4685. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4686. if (rc == 0) {
  4687. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4688. return 0;
  4689. }
  4690. /* Try initialize */
  4691. image = (__le32 *)priv->ucode_init.v_addr;
  4692. len = priv->ucode_init.len;
  4693. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4694. if (rc == 0) {
  4695. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4696. return 0;
  4697. }
  4698. /* Try runtime/protocol */
  4699. image = (__le32 *)priv->ucode_code.v_addr;
  4700. len = priv->ucode_code.len;
  4701. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4702. if (rc == 0) {
  4703. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4704. return 0;
  4705. }
  4706. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4707. /* Since nothing seems to match, show first several data entries in
  4708. * instruction SRAM, so maybe visual inspection will give a clue.
  4709. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4710. image = (__le32 *)priv->ucode_boot.v_addr;
  4711. len = priv->ucode_boot.len;
  4712. rc = iwl3945_verify_inst_full(priv, image, len);
  4713. return rc;
  4714. }
  4715. /* check contents of special bootstrap uCode SRAM */
  4716. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4717. {
  4718. __le32 *image = priv->ucode_boot.v_addr;
  4719. u32 len = priv->ucode_boot.len;
  4720. u32 reg;
  4721. u32 val;
  4722. IWL_DEBUG_INFO("Begin verify bsm\n");
  4723. /* verify BSM SRAM contents */
  4724. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4725. for (reg = BSM_SRAM_LOWER_BOUND;
  4726. reg < BSM_SRAM_LOWER_BOUND + len;
  4727. reg += sizeof(u32), image ++) {
  4728. val = iwl3945_read_prph(priv, reg);
  4729. if (val != le32_to_cpu(*image)) {
  4730. IWL_ERROR("BSM uCode verification failed at "
  4731. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4732. BSM_SRAM_LOWER_BOUND,
  4733. reg - BSM_SRAM_LOWER_BOUND, len,
  4734. val, le32_to_cpu(*image));
  4735. return -EIO;
  4736. }
  4737. }
  4738. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4739. return 0;
  4740. }
  4741. /**
  4742. * iwl3945_load_bsm - Load bootstrap instructions
  4743. *
  4744. * BSM operation:
  4745. *
  4746. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4747. * in special SRAM that does not power down during RFKILL. When powering back
  4748. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4749. * the bootstrap program into the on-board processor, and starts it.
  4750. *
  4751. * The bootstrap program loads (via DMA) instructions and data for a new
  4752. * program from host DRAM locations indicated by the host driver in the
  4753. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4754. * automatically.
  4755. *
  4756. * When initializing the NIC, the host driver points the BSM to the
  4757. * "initialize" uCode image. This uCode sets up some internal data, then
  4758. * notifies host via "initialize alive" that it is complete.
  4759. *
  4760. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4761. * normal runtime uCode instructions and a backup uCode data cache buffer
  4762. * (filled initially with starting data values for the on-board processor),
  4763. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4764. * which begins normal operation.
  4765. *
  4766. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4767. * the backup data cache in DRAM before SRAM is powered down.
  4768. *
  4769. * When powering back up, the BSM loads the bootstrap program. This reloads
  4770. * the runtime uCode instructions and the backup data cache into SRAM,
  4771. * and re-launches the runtime uCode from where it left off.
  4772. */
  4773. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4774. {
  4775. __le32 *image = priv->ucode_boot.v_addr;
  4776. u32 len = priv->ucode_boot.len;
  4777. dma_addr_t pinst;
  4778. dma_addr_t pdata;
  4779. u32 inst_len;
  4780. u32 data_len;
  4781. int rc;
  4782. int i;
  4783. u32 done;
  4784. u32 reg_offset;
  4785. IWL_DEBUG_INFO("Begin load bsm\n");
  4786. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4787. if (len > IWL_MAX_BSM_SIZE)
  4788. return -EINVAL;
  4789. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4790. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4791. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4792. * after the "initialize" uCode has run, to point to
  4793. * runtime/protocol instructions and backup data cache. */
  4794. pinst = priv->ucode_init.p_addr;
  4795. pdata = priv->ucode_init_data.p_addr;
  4796. inst_len = priv->ucode_init.len;
  4797. data_len = priv->ucode_init_data.len;
  4798. rc = iwl3945_grab_nic_access(priv);
  4799. if (rc)
  4800. return rc;
  4801. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4802. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4803. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4804. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4805. /* Fill BSM memory with bootstrap instructions */
  4806. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4807. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4808. reg_offset += sizeof(u32), image++)
  4809. _iwl3945_write_prph(priv, reg_offset,
  4810. le32_to_cpu(*image));
  4811. rc = iwl3945_verify_bsm(priv);
  4812. if (rc) {
  4813. iwl3945_release_nic_access(priv);
  4814. return rc;
  4815. }
  4816. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4817. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4818. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4819. RTC_INST_LOWER_BOUND);
  4820. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4821. /* Load bootstrap code into instruction SRAM now,
  4822. * to prepare to load "initialize" uCode */
  4823. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4824. BSM_WR_CTRL_REG_BIT_START);
  4825. /* Wait for load of bootstrap uCode to finish */
  4826. for (i = 0; i < 100; i++) {
  4827. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4828. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4829. break;
  4830. udelay(10);
  4831. }
  4832. if (i < 100)
  4833. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4834. else {
  4835. IWL_ERROR("BSM write did not complete!\n");
  4836. return -EIO;
  4837. }
  4838. /* Enable future boot loads whenever power management unit triggers it
  4839. * (e.g. when powering back up after power-save shutdown) */
  4840. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4841. BSM_WR_CTRL_REG_BIT_START_EN);
  4842. iwl3945_release_nic_access(priv);
  4843. return 0;
  4844. }
  4845. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4846. {
  4847. /* Remove all resets to allow NIC to operate */
  4848. iwl3945_write32(priv, CSR_RESET, 0);
  4849. }
  4850. /**
  4851. * iwl3945_read_ucode - Read uCode images from disk file.
  4852. *
  4853. * Copy into buffers for card to fetch via bus-mastering
  4854. */
  4855. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4856. {
  4857. struct iwl3945_ucode *ucode;
  4858. int ret = 0;
  4859. const struct firmware *ucode_raw;
  4860. /* firmware file name contains uCode/driver compatibility version */
  4861. const char *name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode";
  4862. u8 *src;
  4863. size_t len;
  4864. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4865. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4866. * request_firmware() is synchronous, file is in memory on return. */
  4867. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4868. if (ret < 0) {
  4869. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4870. name, ret);
  4871. goto error;
  4872. }
  4873. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4874. name, ucode_raw->size);
  4875. /* Make sure that we got at least our header! */
  4876. if (ucode_raw->size < sizeof(*ucode)) {
  4877. IWL_ERROR("File size way too small!\n");
  4878. ret = -EINVAL;
  4879. goto err_release;
  4880. }
  4881. /* Data from ucode file: header followed by uCode images */
  4882. ucode = (void *)ucode_raw->data;
  4883. ver = le32_to_cpu(ucode->ver);
  4884. inst_size = le32_to_cpu(ucode->inst_size);
  4885. data_size = le32_to_cpu(ucode->data_size);
  4886. init_size = le32_to_cpu(ucode->init_size);
  4887. init_data_size = le32_to_cpu(ucode->init_data_size);
  4888. boot_size = le32_to_cpu(ucode->boot_size);
  4889. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4890. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4891. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4892. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4893. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4894. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4895. /* Verify size of file vs. image size info in file's header */
  4896. if (ucode_raw->size < sizeof(*ucode) +
  4897. inst_size + data_size + init_size +
  4898. init_data_size + boot_size) {
  4899. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4900. (int)ucode_raw->size);
  4901. ret = -EINVAL;
  4902. goto err_release;
  4903. }
  4904. /* Verify that uCode images will fit in card's SRAM */
  4905. if (inst_size > IWL_MAX_INST_SIZE) {
  4906. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4907. inst_size);
  4908. ret = -EINVAL;
  4909. goto err_release;
  4910. }
  4911. if (data_size > IWL_MAX_DATA_SIZE) {
  4912. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4913. data_size);
  4914. ret = -EINVAL;
  4915. goto err_release;
  4916. }
  4917. if (init_size > IWL_MAX_INST_SIZE) {
  4918. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4919. init_size);
  4920. ret = -EINVAL;
  4921. goto err_release;
  4922. }
  4923. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4924. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4925. init_data_size);
  4926. ret = -EINVAL;
  4927. goto err_release;
  4928. }
  4929. if (boot_size > IWL_MAX_BSM_SIZE) {
  4930. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4931. boot_size);
  4932. ret = -EINVAL;
  4933. goto err_release;
  4934. }
  4935. /* Allocate ucode buffers for card's bus-master loading ... */
  4936. /* Runtime instructions and 2 copies of data:
  4937. * 1) unmodified from disk
  4938. * 2) backup cache for save/restore during power-downs */
  4939. priv->ucode_code.len = inst_size;
  4940. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4941. priv->ucode_data.len = data_size;
  4942. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4943. priv->ucode_data_backup.len = data_size;
  4944. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4945. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4946. !priv->ucode_data_backup.v_addr)
  4947. goto err_pci_alloc;
  4948. /* Initialization instructions and data */
  4949. if (init_size && init_data_size) {
  4950. priv->ucode_init.len = init_size;
  4951. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4952. priv->ucode_init_data.len = init_data_size;
  4953. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4954. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4955. goto err_pci_alloc;
  4956. }
  4957. /* Bootstrap (instructions only, no data) */
  4958. if (boot_size) {
  4959. priv->ucode_boot.len = boot_size;
  4960. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4961. if (!priv->ucode_boot.v_addr)
  4962. goto err_pci_alloc;
  4963. }
  4964. /* Copy images into buffers for card's bus-master reads ... */
  4965. /* Runtime instructions (first block of data in file) */
  4966. src = &ucode->data[0];
  4967. len = priv->ucode_code.len;
  4968. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4969. memcpy(priv->ucode_code.v_addr, src, len);
  4970. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4971. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4972. /* Runtime data (2nd block)
  4973. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4974. src = &ucode->data[inst_size];
  4975. len = priv->ucode_data.len;
  4976. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4977. memcpy(priv->ucode_data.v_addr, src, len);
  4978. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4979. /* Initialization instructions (3rd block) */
  4980. if (init_size) {
  4981. src = &ucode->data[inst_size + data_size];
  4982. len = priv->ucode_init.len;
  4983. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4984. len);
  4985. memcpy(priv->ucode_init.v_addr, src, len);
  4986. }
  4987. /* Initialization data (4th block) */
  4988. if (init_data_size) {
  4989. src = &ucode->data[inst_size + data_size + init_size];
  4990. len = priv->ucode_init_data.len;
  4991. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4992. (int)len);
  4993. memcpy(priv->ucode_init_data.v_addr, src, len);
  4994. }
  4995. /* Bootstrap instructions (5th block) */
  4996. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4997. len = priv->ucode_boot.len;
  4998. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4999. (int)len);
  5000. memcpy(priv->ucode_boot.v_addr, src, len);
  5001. /* We have our copies now, allow OS release its copies */
  5002. release_firmware(ucode_raw);
  5003. return 0;
  5004. err_pci_alloc:
  5005. IWL_ERROR("failed to allocate pci memory\n");
  5006. ret = -ENOMEM;
  5007. iwl3945_dealloc_ucode_pci(priv);
  5008. err_release:
  5009. release_firmware(ucode_raw);
  5010. error:
  5011. return ret;
  5012. }
  5013. /**
  5014. * iwl3945_set_ucode_ptrs - Set uCode address location
  5015. *
  5016. * Tell initialization uCode where to find runtime uCode.
  5017. *
  5018. * BSM registers initially contain pointers to initialization uCode.
  5019. * We need to replace them to load runtime uCode inst and data,
  5020. * and to save runtime data when powering down.
  5021. */
  5022. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  5023. {
  5024. dma_addr_t pinst;
  5025. dma_addr_t pdata;
  5026. int rc = 0;
  5027. unsigned long flags;
  5028. /* bits 31:0 for 3945 */
  5029. pinst = priv->ucode_code.p_addr;
  5030. pdata = priv->ucode_data_backup.p_addr;
  5031. spin_lock_irqsave(&priv->lock, flags);
  5032. rc = iwl3945_grab_nic_access(priv);
  5033. if (rc) {
  5034. spin_unlock_irqrestore(&priv->lock, flags);
  5035. return rc;
  5036. }
  5037. /* Tell bootstrap uCode where to find image to load */
  5038. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  5039. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  5040. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  5041. priv->ucode_data.len);
  5042. /* Inst bytecount must be last to set up, bit 31 signals uCode
  5043. * that all new ptr/size info is in place */
  5044. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  5045. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  5046. iwl3945_release_nic_access(priv);
  5047. spin_unlock_irqrestore(&priv->lock, flags);
  5048. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  5049. return rc;
  5050. }
  5051. /**
  5052. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  5053. *
  5054. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  5055. *
  5056. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  5057. */
  5058. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  5059. {
  5060. /* Check alive response for "valid" sign from uCode */
  5061. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  5062. /* We had an error bringing up the hardware, so take it
  5063. * all the way back down so we can try again */
  5064. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  5065. goto restart;
  5066. }
  5067. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  5068. * This is a paranoid check, because we would not have gotten the
  5069. * "initialize" alive if code weren't properly loaded. */
  5070. if (iwl3945_verify_ucode(priv)) {
  5071. /* Runtime instruction load was bad;
  5072. * take it all the way back down so we can try again */
  5073. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  5074. goto restart;
  5075. }
  5076. /* Send pointers to protocol/runtime uCode image ... init code will
  5077. * load and launch runtime uCode, which will send us another "Alive"
  5078. * notification. */
  5079. IWL_DEBUG_INFO("Initialization Alive received.\n");
  5080. if (iwl3945_set_ucode_ptrs(priv)) {
  5081. /* Runtime instruction load won't happen;
  5082. * take it all the way back down so we can try again */
  5083. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  5084. goto restart;
  5085. }
  5086. return;
  5087. restart:
  5088. queue_work(priv->workqueue, &priv->restart);
  5089. }
  5090. /**
  5091. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  5092. * from protocol/runtime uCode (initialization uCode's
  5093. * Alive gets handled by iwl3945_init_alive_start()).
  5094. */
  5095. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  5096. {
  5097. int rc = 0;
  5098. int thermal_spin = 0;
  5099. u32 rfkill;
  5100. IWL_DEBUG_INFO("Runtime Alive received.\n");
  5101. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  5102. /* We had an error bringing up the hardware, so take it
  5103. * all the way back down so we can try again */
  5104. IWL_DEBUG_INFO("Alive failed.\n");
  5105. goto restart;
  5106. }
  5107. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  5108. * This is a paranoid check, because we would not have gotten the
  5109. * "runtime" alive if code weren't properly loaded. */
  5110. if (iwl3945_verify_ucode(priv)) {
  5111. /* Runtime instruction load was bad;
  5112. * take it all the way back down so we can try again */
  5113. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  5114. goto restart;
  5115. }
  5116. iwl3945_clear_stations_table(priv);
  5117. rc = iwl3945_grab_nic_access(priv);
  5118. if (rc) {
  5119. IWL_WARNING("Can not read rfkill status from adapter\n");
  5120. return;
  5121. }
  5122. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  5123. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  5124. iwl3945_release_nic_access(priv);
  5125. if (rfkill & 0x1) {
  5126. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5127. /* if rfkill is not on, then wait for thermal
  5128. * sensor in adapter to kick in */
  5129. while (iwl3945_hw_get_temperature(priv) == 0) {
  5130. thermal_spin++;
  5131. udelay(10);
  5132. }
  5133. if (thermal_spin)
  5134. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  5135. thermal_spin * 10);
  5136. } else
  5137. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5138. /* After the ALIVE response, we can send commands to 3945 uCode */
  5139. set_bit(STATUS_ALIVE, &priv->status);
  5140. /* Clear out the uCode error bit if it is set */
  5141. clear_bit(STATUS_FW_ERROR, &priv->status);
  5142. if (iwl3945_is_rfkill(priv))
  5143. return;
  5144. ieee80211_start_queues(priv->hw);
  5145. priv->active_rate = priv->rates_mask;
  5146. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  5147. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  5148. if (iwl3945_is_associated(priv)) {
  5149. struct iwl3945_rxon_cmd *active_rxon =
  5150. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  5151. memcpy(&priv->staging_rxon, &priv->active_rxon,
  5152. sizeof(priv->staging_rxon));
  5153. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5154. } else {
  5155. /* Initialize our rx_config data */
  5156. iwl3945_connection_init_rx_config(priv);
  5157. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  5158. }
  5159. /* Configure Bluetooth device coexistence support */
  5160. iwl3945_send_bt_config(priv);
  5161. /* Configure the adapter for unassociated operation */
  5162. iwl3945_commit_rxon(priv);
  5163. /* At this point, the NIC is initialized and operational */
  5164. priv->notif_missed_beacons = 0;
  5165. set_bit(STATUS_READY, &priv->status);
  5166. iwl3945_reg_txpower_periodic(priv);
  5167. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  5168. wake_up_interruptible(&priv->wait_command_queue);
  5169. if (priv->error_recovering)
  5170. iwl3945_error_recovery(priv);
  5171. return;
  5172. restart:
  5173. queue_work(priv->workqueue, &priv->restart);
  5174. }
  5175. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  5176. static void __iwl3945_down(struct iwl3945_priv *priv)
  5177. {
  5178. unsigned long flags;
  5179. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  5180. struct ieee80211_conf *conf = NULL;
  5181. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  5182. conf = ieee80211_get_hw_conf(priv->hw);
  5183. if (!exit_pending)
  5184. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5185. iwl3945_clear_stations_table(priv);
  5186. /* Unblock any waiting calls */
  5187. wake_up_interruptible_all(&priv->wait_command_queue);
  5188. /* Wipe out the EXIT_PENDING status bit if we are not actually
  5189. * exiting the module */
  5190. if (!exit_pending)
  5191. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  5192. /* stop and reset the on-board processor */
  5193. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  5194. /* tell the device to stop sending interrupts */
  5195. iwl3945_disable_interrupts(priv);
  5196. if (priv->mac80211_registered)
  5197. ieee80211_stop_queues(priv->hw);
  5198. /* If we have not previously called iwl3945_init() then
  5199. * clear all bits but the RF Kill and SUSPEND bits and return */
  5200. if (!iwl3945_is_init(priv)) {
  5201. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5202. STATUS_RF_KILL_HW |
  5203. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5204. STATUS_RF_KILL_SW |
  5205. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  5206. STATUS_GEO_CONFIGURED |
  5207. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5208. STATUS_IN_SUSPEND;
  5209. goto exit;
  5210. }
  5211. /* ...otherwise clear out all the status bits but the RF Kill and
  5212. * SUSPEND bits and continue taking the NIC down. */
  5213. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  5214. STATUS_RF_KILL_HW |
  5215. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  5216. STATUS_RF_KILL_SW |
  5217. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  5218. STATUS_GEO_CONFIGURED |
  5219. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  5220. STATUS_IN_SUSPEND |
  5221. test_bit(STATUS_FW_ERROR, &priv->status) <<
  5222. STATUS_FW_ERROR;
  5223. spin_lock_irqsave(&priv->lock, flags);
  5224. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  5225. spin_unlock_irqrestore(&priv->lock, flags);
  5226. iwl3945_hw_txq_ctx_stop(priv);
  5227. iwl3945_hw_rxq_stop(priv);
  5228. spin_lock_irqsave(&priv->lock, flags);
  5229. if (!iwl3945_grab_nic_access(priv)) {
  5230. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  5231. APMG_CLK_VAL_DMA_CLK_RQT);
  5232. iwl3945_release_nic_access(priv);
  5233. }
  5234. spin_unlock_irqrestore(&priv->lock, flags);
  5235. udelay(5);
  5236. iwl3945_hw_nic_stop_master(priv);
  5237. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  5238. iwl3945_hw_nic_reset(priv);
  5239. exit:
  5240. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5241. if (priv->ibss_beacon)
  5242. dev_kfree_skb(priv->ibss_beacon);
  5243. priv->ibss_beacon = NULL;
  5244. /* clear out any free frames */
  5245. iwl3945_clear_free_frames(priv);
  5246. }
  5247. static void iwl3945_down(struct iwl3945_priv *priv)
  5248. {
  5249. mutex_lock(&priv->mutex);
  5250. __iwl3945_down(priv);
  5251. mutex_unlock(&priv->mutex);
  5252. iwl3945_cancel_deferred_work(priv);
  5253. }
  5254. #define MAX_HW_RESTARTS 5
  5255. static int __iwl3945_up(struct iwl3945_priv *priv)
  5256. {
  5257. int rc, i;
  5258. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5259. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5260. return -EIO;
  5261. }
  5262. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5263. IWL_WARNING("Radio disabled by SW RF kill (module "
  5264. "parameter)\n");
  5265. return -ENODEV;
  5266. }
  5267. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5268. IWL_ERROR("ucode not available for device bringup\n");
  5269. return -EIO;
  5270. }
  5271. /* If platform's RF_KILL switch is NOT set to KILL */
  5272. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  5273. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  5274. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5275. else {
  5276. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5277. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  5278. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5279. return -ENODEV;
  5280. }
  5281. }
  5282. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5283. rc = iwl3945_hw_nic_init(priv);
  5284. if (rc) {
  5285. IWL_ERROR("Unable to int nic\n");
  5286. return rc;
  5287. }
  5288. /* make sure rfkill handshake bits are cleared */
  5289. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5290. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5291. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5292. /* clear (again), then enable host interrupts */
  5293. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5294. iwl3945_enable_interrupts(priv);
  5295. /* really make sure rfkill handshake bits are cleared */
  5296. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5297. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5298. /* Copy original ucode data image from disk into backup cache.
  5299. * This will be used to initialize the on-board processor's
  5300. * data SRAM for a clean start when the runtime program first loads. */
  5301. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5302. priv->ucode_data.len);
  5303. /* We return success when we resume from suspend and rf_kill is on. */
  5304. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  5305. return 0;
  5306. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5307. iwl3945_clear_stations_table(priv);
  5308. /* load bootstrap state machine,
  5309. * load bootstrap program into processor's memory,
  5310. * prepare to load the "initialize" uCode */
  5311. rc = iwl3945_load_bsm(priv);
  5312. if (rc) {
  5313. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5314. continue;
  5315. }
  5316. /* start card; "initialize" will load runtime ucode */
  5317. iwl3945_nic_start(priv);
  5318. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5319. return 0;
  5320. }
  5321. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5322. __iwl3945_down(priv);
  5323. /* tried to restart and config the device for as long as our
  5324. * patience could withstand */
  5325. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5326. return -EIO;
  5327. }
  5328. /*****************************************************************************
  5329. *
  5330. * Workqueue callbacks
  5331. *
  5332. *****************************************************************************/
  5333. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5334. {
  5335. struct iwl3945_priv *priv =
  5336. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5337. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5338. return;
  5339. mutex_lock(&priv->mutex);
  5340. iwl3945_init_alive_start(priv);
  5341. mutex_unlock(&priv->mutex);
  5342. }
  5343. static void iwl3945_bg_alive_start(struct work_struct *data)
  5344. {
  5345. struct iwl3945_priv *priv =
  5346. container_of(data, struct iwl3945_priv, alive_start.work);
  5347. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5348. return;
  5349. mutex_lock(&priv->mutex);
  5350. iwl3945_alive_start(priv);
  5351. mutex_unlock(&priv->mutex);
  5352. }
  5353. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5354. {
  5355. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5356. wake_up_interruptible(&priv->wait_command_queue);
  5357. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5358. return;
  5359. mutex_lock(&priv->mutex);
  5360. if (!iwl3945_is_rfkill(priv)) {
  5361. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5362. "HW and/or SW RF Kill no longer active, restarting "
  5363. "device\n");
  5364. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5365. queue_work(priv->workqueue, &priv->restart);
  5366. } else {
  5367. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5368. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5369. "disabled by SW switch\n");
  5370. else
  5371. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5372. "Kill switch must be turned off for "
  5373. "wireless networking to work.\n");
  5374. }
  5375. mutex_unlock(&priv->mutex);
  5376. }
  5377. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5378. static void iwl3945_bg_scan_check(struct work_struct *data)
  5379. {
  5380. struct iwl3945_priv *priv =
  5381. container_of(data, struct iwl3945_priv, scan_check.work);
  5382. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5383. return;
  5384. mutex_lock(&priv->mutex);
  5385. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5386. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5387. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5388. "Scan completion watchdog resetting adapter (%dms)\n",
  5389. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5390. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5391. iwl3945_send_scan_abort(priv);
  5392. }
  5393. mutex_unlock(&priv->mutex);
  5394. }
  5395. static void iwl3945_bg_request_scan(struct work_struct *data)
  5396. {
  5397. struct iwl3945_priv *priv =
  5398. container_of(data, struct iwl3945_priv, request_scan);
  5399. struct iwl3945_host_cmd cmd = {
  5400. .id = REPLY_SCAN_CMD,
  5401. .len = sizeof(struct iwl3945_scan_cmd),
  5402. .meta.flags = CMD_SIZE_HUGE,
  5403. };
  5404. int rc = 0;
  5405. struct iwl3945_scan_cmd *scan;
  5406. struct ieee80211_conf *conf = NULL;
  5407. u8 direct_mask;
  5408. enum ieee80211_band band;
  5409. conf = ieee80211_get_hw_conf(priv->hw);
  5410. mutex_lock(&priv->mutex);
  5411. if (!iwl3945_is_ready(priv)) {
  5412. IWL_WARNING("request scan called when driver not ready.\n");
  5413. goto done;
  5414. }
  5415. /* Make sure the scan wasn't cancelled before this queued work
  5416. * was given the chance to run... */
  5417. if (!test_bit(STATUS_SCANNING, &priv->status))
  5418. goto done;
  5419. /* This should never be called or scheduled if there is currently
  5420. * a scan active in the hardware. */
  5421. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5422. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5423. "Ignoring second request.\n");
  5424. rc = -EIO;
  5425. goto done;
  5426. }
  5427. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5428. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5429. goto done;
  5430. }
  5431. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5432. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5433. goto done;
  5434. }
  5435. if (iwl3945_is_rfkill(priv)) {
  5436. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5437. goto done;
  5438. }
  5439. if (!test_bit(STATUS_READY, &priv->status)) {
  5440. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5441. goto done;
  5442. }
  5443. if (!priv->scan_bands) {
  5444. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5445. goto done;
  5446. }
  5447. if (!priv->scan) {
  5448. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5449. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5450. if (!priv->scan) {
  5451. rc = -ENOMEM;
  5452. goto done;
  5453. }
  5454. }
  5455. scan = priv->scan;
  5456. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5457. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5458. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5459. if (iwl3945_is_associated(priv)) {
  5460. u16 interval = 0;
  5461. u32 extra;
  5462. u32 suspend_time = 100;
  5463. u32 scan_suspend_time = 100;
  5464. unsigned long flags;
  5465. IWL_DEBUG_INFO("Scanning while associated...\n");
  5466. spin_lock_irqsave(&priv->lock, flags);
  5467. interval = priv->beacon_int;
  5468. spin_unlock_irqrestore(&priv->lock, flags);
  5469. scan->suspend_time = 0;
  5470. scan->max_out_time = cpu_to_le32(200 * 1024);
  5471. if (!interval)
  5472. interval = suspend_time;
  5473. /*
  5474. * suspend time format:
  5475. * 0-19: beacon interval in usec (time before exec.)
  5476. * 20-23: 0
  5477. * 24-31: number of beacons (suspend between channels)
  5478. */
  5479. extra = (suspend_time / interval) << 24;
  5480. scan_suspend_time = 0xFF0FFFFF &
  5481. (extra | ((suspend_time % interval) * 1024));
  5482. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5483. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5484. scan_suspend_time, interval);
  5485. }
  5486. /* We should add the ability for user to lock to PASSIVE ONLY */
  5487. if (priv->one_direct_scan) {
  5488. IWL_DEBUG_SCAN
  5489. ("Kicking off one direct scan for '%s'\n",
  5490. iwl3945_escape_essid(priv->direct_ssid,
  5491. priv->direct_ssid_len));
  5492. scan->direct_scan[0].id = WLAN_EID_SSID;
  5493. scan->direct_scan[0].len = priv->direct_ssid_len;
  5494. memcpy(scan->direct_scan[0].ssid,
  5495. priv->direct_ssid, priv->direct_ssid_len);
  5496. direct_mask = 1;
  5497. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5498. scan->direct_scan[0].id = WLAN_EID_SSID;
  5499. scan->direct_scan[0].len = priv->essid_len;
  5500. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5501. direct_mask = 1;
  5502. } else
  5503. direct_mask = 0;
  5504. /* We don't build a direct scan probe request; the uCode will do
  5505. * that based on the direct_mask added to each channel entry */
  5506. scan->tx_cmd.len = cpu_to_le16(
  5507. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5508. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5509. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5510. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5511. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5512. /* flags + rate selection */
  5513. switch (priv->scan_bands) {
  5514. case 2:
  5515. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5516. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5517. scan->good_CRC_th = 0;
  5518. band = IEEE80211_BAND_2GHZ;
  5519. break;
  5520. case 1:
  5521. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5522. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5523. band = IEEE80211_BAND_5GHZ;
  5524. break;
  5525. default:
  5526. IWL_WARNING("Invalid scan band count\n");
  5527. goto done;
  5528. }
  5529. /* select Rx antennas */
  5530. scan->flags |= iwl3945_get_antenna_flags(priv);
  5531. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5532. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5533. if (direct_mask)
  5534. IWL_DEBUG_SCAN
  5535. ("Initiating direct scan for %s.\n",
  5536. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5537. else
  5538. IWL_DEBUG_SCAN("Initiating indirect scan.\n");
  5539. scan->channel_count =
  5540. iwl3945_get_channels_for_scan(
  5541. priv, band, 1, /* active */
  5542. direct_mask,
  5543. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5544. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5545. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5546. cmd.data = scan;
  5547. scan->len = cpu_to_le16(cmd.len);
  5548. set_bit(STATUS_SCAN_HW, &priv->status);
  5549. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5550. if (rc)
  5551. goto done;
  5552. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5553. IWL_SCAN_CHECK_WATCHDOG);
  5554. mutex_unlock(&priv->mutex);
  5555. return;
  5556. done:
  5557. /* inform mac80211 scan aborted */
  5558. queue_work(priv->workqueue, &priv->scan_completed);
  5559. mutex_unlock(&priv->mutex);
  5560. }
  5561. static void iwl3945_bg_up(struct work_struct *data)
  5562. {
  5563. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5564. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5565. return;
  5566. mutex_lock(&priv->mutex);
  5567. __iwl3945_up(priv);
  5568. mutex_unlock(&priv->mutex);
  5569. }
  5570. static void iwl3945_bg_restart(struct work_struct *data)
  5571. {
  5572. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5573. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5574. return;
  5575. iwl3945_down(priv);
  5576. queue_work(priv->workqueue, &priv->up);
  5577. }
  5578. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5579. {
  5580. struct iwl3945_priv *priv =
  5581. container_of(data, struct iwl3945_priv, rx_replenish);
  5582. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5583. return;
  5584. mutex_lock(&priv->mutex);
  5585. iwl3945_rx_replenish(priv);
  5586. mutex_unlock(&priv->mutex);
  5587. }
  5588. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5589. static void iwl3945_bg_post_associate(struct work_struct *data)
  5590. {
  5591. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5592. post_associate.work);
  5593. int rc = 0;
  5594. struct ieee80211_conf *conf = NULL;
  5595. DECLARE_MAC_BUF(mac);
  5596. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5597. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5598. return;
  5599. }
  5600. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5601. priv->assoc_id,
  5602. print_mac(mac, priv->active_rxon.bssid_addr));
  5603. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5604. return;
  5605. mutex_lock(&priv->mutex);
  5606. if (!priv->vif || !priv->is_open) {
  5607. mutex_unlock(&priv->mutex);
  5608. return;
  5609. }
  5610. iwl3945_scan_cancel_timeout(priv, 200);
  5611. conf = ieee80211_get_hw_conf(priv->hw);
  5612. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5613. iwl3945_commit_rxon(priv);
  5614. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5615. iwl3945_setup_rxon_timing(priv);
  5616. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5617. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5618. if (rc)
  5619. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5620. "Attempting to continue.\n");
  5621. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5622. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5623. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5624. priv->assoc_id, priv->beacon_int);
  5625. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5626. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5627. else
  5628. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5629. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5630. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5631. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5632. else
  5633. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5634. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5635. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5636. }
  5637. iwl3945_commit_rxon(priv);
  5638. switch (priv->iw_mode) {
  5639. case IEEE80211_IF_TYPE_STA:
  5640. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5641. break;
  5642. case IEEE80211_IF_TYPE_IBSS:
  5643. /* clear out the station table */
  5644. iwl3945_clear_stations_table(priv);
  5645. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5646. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5647. iwl3945_sync_sta(priv, IWL_STA_ID,
  5648. (priv->band == IEEE80211_BAND_5GHZ) ?
  5649. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5650. CMD_ASYNC);
  5651. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5652. iwl3945_send_beacon_cmd(priv);
  5653. break;
  5654. default:
  5655. IWL_ERROR("%s Should not be called in %d mode\n",
  5656. __FUNCTION__, priv->iw_mode);
  5657. break;
  5658. }
  5659. iwl3945_sequence_reset(priv);
  5660. iwl3945_activate_qos(priv, 0);
  5661. /* we have just associated, don't start scan too early */
  5662. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5663. mutex_unlock(&priv->mutex);
  5664. }
  5665. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5666. {
  5667. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5668. if (!iwl3945_is_ready(priv))
  5669. return;
  5670. mutex_lock(&priv->mutex);
  5671. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5672. iwl3945_send_scan_abort(priv);
  5673. mutex_unlock(&priv->mutex);
  5674. }
  5675. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5676. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5677. {
  5678. struct iwl3945_priv *priv =
  5679. container_of(work, struct iwl3945_priv, scan_completed);
  5680. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5681. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5682. return;
  5683. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5684. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5685. ieee80211_scan_completed(priv->hw);
  5686. /* Since setting the TXPOWER may have been deferred while
  5687. * performing the scan, fire one off */
  5688. mutex_lock(&priv->mutex);
  5689. iwl3945_hw_reg_send_txpower(priv);
  5690. mutex_unlock(&priv->mutex);
  5691. }
  5692. /*****************************************************************************
  5693. *
  5694. * mac80211 entry point functions
  5695. *
  5696. *****************************************************************************/
  5697. #define UCODE_READY_TIMEOUT (2 * HZ)
  5698. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5699. {
  5700. struct iwl3945_priv *priv = hw->priv;
  5701. int ret;
  5702. IWL_DEBUG_MAC80211("enter\n");
  5703. if (pci_enable_device(priv->pci_dev)) {
  5704. IWL_ERROR("Fail to pci_enable_device\n");
  5705. return -ENODEV;
  5706. }
  5707. pci_restore_state(priv->pci_dev);
  5708. pci_enable_msi(priv->pci_dev);
  5709. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5710. DRV_NAME, priv);
  5711. if (ret) {
  5712. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5713. goto out_disable_msi;
  5714. }
  5715. /* we should be verifying the device is ready to be opened */
  5716. mutex_lock(&priv->mutex);
  5717. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5718. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5719. * ucode filename and max sizes are card-specific. */
  5720. if (!priv->ucode_code.len) {
  5721. ret = iwl3945_read_ucode(priv);
  5722. if (ret) {
  5723. IWL_ERROR("Could not read microcode: %d\n", ret);
  5724. mutex_unlock(&priv->mutex);
  5725. goto out_release_irq;
  5726. }
  5727. }
  5728. ret = __iwl3945_up(priv);
  5729. mutex_unlock(&priv->mutex);
  5730. if (ret)
  5731. goto out_release_irq;
  5732. IWL_DEBUG_INFO("Start UP work.\n");
  5733. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5734. return 0;
  5735. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5736. * mac80211 will not be run successfully. */
  5737. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5738. test_bit(STATUS_READY, &priv->status),
  5739. UCODE_READY_TIMEOUT);
  5740. if (!ret) {
  5741. if (!test_bit(STATUS_READY, &priv->status)) {
  5742. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5743. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5744. ret = -ETIMEDOUT;
  5745. goto out_release_irq;
  5746. }
  5747. }
  5748. priv->is_open = 1;
  5749. IWL_DEBUG_MAC80211("leave\n");
  5750. return 0;
  5751. out_release_irq:
  5752. free_irq(priv->pci_dev->irq, priv);
  5753. out_disable_msi:
  5754. pci_disable_msi(priv->pci_dev);
  5755. pci_disable_device(priv->pci_dev);
  5756. priv->is_open = 0;
  5757. IWL_DEBUG_MAC80211("leave - failed\n");
  5758. return ret;
  5759. }
  5760. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5761. {
  5762. struct iwl3945_priv *priv = hw->priv;
  5763. IWL_DEBUG_MAC80211("enter\n");
  5764. if (!priv->is_open) {
  5765. IWL_DEBUG_MAC80211("leave - skip\n");
  5766. return;
  5767. }
  5768. priv->is_open = 0;
  5769. if (iwl3945_is_ready_rf(priv)) {
  5770. /* stop mac, cancel any scan request and clear
  5771. * RXON_FILTER_ASSOC_MSK BIT
  5772. */
  5773. mutex_lock(&priv->mutex);
  5774. iwl3945_scan_cancel_timeout(priv, 100);
  5775. cancel_delayed_work(&priv->post_associate);
  5776. mutex_unlock(&priv->mutex);
  5777. }
  5778. iwl3945_down(priv);
  5779. flush_workqueue(priv->workqueue);
  5780. free_irq(priv->pci_dev->irq, priv);
  5781. pci_disable_msi(priv->pci_dev);
  5782. pci_save_state(priv->pci_dev);
  5783. pci_disable_device(priv->pci_dev);
  5784. IWL_DEBUG_MAC80211("leave\n");
  5785. }
  5786. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  5787. struct ieee80211_tx_control *ctl)
  5788. {
  5789. struct iwl3945_priv *priv = hw->priv;
  5790. IWL_DEBUG_MAC80211("enter\n");
  5791. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5792. IWL_DEBUG_MAC80211("leave - monitor\n");
  5793. return -1;
  5794. }
  5795. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5796. ctl->tx_rate->bitrate);
  5797. if (iwl3945_tx_skb(priv, skb, ctl))
  5798. dev_kfree_skb_any(skb);
  5799. IWL_DEBUG_MAC80211("leave\n");
  5800. return 0;
  5801. }
  5802. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5803. struct ieee80211_if_init_conf *conf)
  5804. {
  5805. struct iwl3945_priv *priv = hw->priv;
  5806. unsigned long flags;
  5807. DECLARE_MAC_BUF(mac);
  5808. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5809. if (priv->vif) {
  5810. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5811. return -EOPNOTSUPP;
  5812. }
  5813. spin_lock_irqsave(&priv->lock, flags);
  5814. priv->vif = conf->vif;
  5815. spin_unlock_irqrestore(&priv->lock, flags);
  5816. mutex_lock(&priv->mutex);
  5817. if (conf->mac_addr) {
  5818. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5819. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5820. }
  5821. if (iwl3945_is_ready(priv))
  5822. iwl3945_set_mode(priv, conf->type);
  5823. mutex_unlock(&priv->mutex);
  5824. IWL_DEBUG_MAC80211("leave\n");
  5825. return 0;
  5826. }
  5827. /**
  5828. * iwl3945_mac_config - mac80211 config callback
  5829. *
  5830. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5831. * be set inappropriately and the driver currently sets the hardware up to
  5832. * use it whenever needed.
  5833. */
  5834. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5835. {
  5836. struct iwl3945_priv *priv = hw->priv;
  5837. const struct iwl3945_channel_info *ch_info;
  5838. unsigned long flags;
  5839. int ret = 0;
  5840. mutex_lock(&priv->mutex);
  5841. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5842. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5843. if (!iwl3945_is_ready(priv)) {
  5844. IWL_DEBUG_MAC80211("leave - not ready\n");
  5845. ret = -EIO;
  5846. goto out;
  5847. }
  5848. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5849. test_bit(STATUS_SCANNING, &priv->status))) {
  5850. IWL_DEBUG_MAC80211("leave - scanning\n");
  5851. set_bit(STATUS_CONF_PENDING, &priv->status);
  5852. mutex_unlock(&priv->mutex);
  5853. return 0;
  5854. }
  5855. spin_lock_irqsave(&priv->lock, flags);
  5856. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5857. conf->channel->hw_value);
  5858. if (!is_channel_valid(ch_info)) {
  5859. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this SKU.\n",
  5860. conf->channel->hw_value, conf->channel->band);
  5861. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5862. spin_unlock_irqrestore(&priv->lock, flags);
  5863. ret = -EINVAL;
  5864. goto out;
  5865. }
  5866. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5867. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5868. /* The list of supported rates and rate mask can be different
  5869. * for each phymode; since the phymode may have changed, reset
  5870. * the rate mask to what mac80211 lists */
  5871. iwl3945_set_rate(priv);
  5872. spin_unlock_irqrestore(&priv->lock, flags);
  5873. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5874. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5875. iwl3945_hw_channel_switch(priv, conf->channel);
  5876. goto out;
  5877. }
  5878. #endif
  5879. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5880. if (!conf->radio_enabled) {
  5881. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5882. goto out;
  5883. }
  5884. if (iwl3945_is_rfkill(priv)) {
  5885. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5886. ret = -EIO;
  5887. goto out;
  5888. }
  5889. iwl3945_set_rate(priv);
  5890. if (memcmp(&priv->active_rxon,
  5891. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5892. iwl3945_commit_rxon(priv);
  5893. else
  5894. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5895. IWL_DEBUG_MAC80211("leave\n");
  5896. out:
  5897. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5898. mutex_unlock(&priv->mutex);
  5899. return ret;
  5900. }
  5901. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5902. {
  5903. int rc = 0;
  5904. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5905. return;
  5906. /* The following should be done only at AP bring up */
  5907. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5908. /* RXON - unassoc (to set timing command) */
  5909. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5910. iwl3945_commit_rxon(priv);
  5911. /* RXON Timing */
  5912. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5913. iwl3945_setup_rxon_timing(priv);
  5914. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5915. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5916. if (rc)
  5917. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5918. "Attempting to continue.\n");
  5919. /* FIXME: what should be the assoc_id for AP? */
  5920. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5921. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5922. priv->staging_rxon.flags |=
  5923. RXON_FLG_SHORT_PREAMBLE_MSK;
  5924. else
  5925. priv->staging_rxon.flags &=
  5926. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5927. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5928. if (priv->assoc_capability &
  5929. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5930. priv->staging_rxon.flags |=
  5931. RXON_FLG_SHORT_SLOT_MSK;
  5932. else
  5933. priv->staging_rxon.flags &=
  5934. ~RXON_FLG_SHORT_SLOT_MSK;
  5935. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5936. priv->staging_rxon.flags &=
  5937. ~RXON_FLG_SHORT_SLOT_MSK;
  5938. }
  5939. /* restore RXON assoc */
  5940. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5941. iwl3945_commit_rxon(priv);
  5942. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5943. }
  5944. iwl3945_send_beacon_cmd(priv);
  5945. /* FIXME - we need to add code here to detect a totally new
  5946. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5947. * clear sta table, add BCAST sta... */
  5948. }
  5949. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5950. struct ieee80211_vif *vif,
  5951. struct ieee80211_if_conf *conf)
  5952. {
  5953. struct iwl3945_priv *priv = hw->priv;
  5954. DECLARE_MAC_BUF(mac);
  5955. unsigned long flags;
  5956. int rc;
  5957. if (conf == NULL)
  5958. return -EIO;
  5959. /* XXX: this MUST use conf->mac_addr */
  5960. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5961. (!conf->beacon || !conf->ssid_len)) {
  5962. IWL_DEBUG_MAC80211
  5963. ("Leaving in AP mode because HostAPD is not ready.\n");
  5964. return 0;
  5965. }
  5966. if (!iwl3945_is_alive(priv))
  5967. return -EAGAIN;
  5968. mutex_lock(&priv->mutex);
  5969. if (conf->bssid)
  5970. IWL_DEBUG_MAC80211("bssid: %s\n",
  5971. print_mac(mac, conf->bssid));
  5972. /*
  5973. * very dubious code was here; the probe filtering flag is never set:
  5974. *
  5975. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5976. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5977. */
  5978. if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
  5979. IWL_DEBUG_MAC80211("leave - scanning\n");
  5980. mutex_unlock(&priv->mutex);
  5981. return 0;
  5982. }
  5983. if (priv->vif != vif) {
  5984. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5985. mutex_unlock(&priv->mutex);
  5986. return 0;
  5987. }
  5988. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5989. if (!conf->bssid) {
  5990. conf->bssid = priv->mac_addr;
  5991. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5992. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5993. print_mac(mac, conf->bssid));
  5994. }
  5995. if (priv->ibss_beacon)
  5996. dev_kfree_skb(priv->ibss_beacon);
  5997. priv->ibss_beacon = conf->beacon;
  5998. }
  5999. if (iwl3945_is_rfkill(priv))
  6000. goto done;
  6001. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  6002. !is_multicast_ether_addr(conf->bssid)) {
  6003. /* If there is currently a HW scan going on in the background
  6004. * then we need to cancel it else the RXON below will fail. */
  6005. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  6006. IWL_WARNING("Aborted scan still in progress "
  6007. "after 100ms\n");
  6008. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  6009. mutex_unlock(&priv->mutex);
  6010. return -EAGAIN;
  6011. }
  6012. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  6013. /* TODO: Audit driver for usage of these members and see
  6014. * if mac80211 deprecates them (priv->bssid looks like it
  6015. * shouldn't be there, but I haven't scanned the IBSS code
  6016. * to verify) - jpk */
  6017. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  6018. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6019. iwl3945_config_ap(priv);
  6020. else {
  6021. rc = iwl3945_commit_rxon(priv);
  6022. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  6023. iwl3945_add_station(priv,
  6024. priv->active_rxon.bssid_addr, 1, 0);
  6025. }
  6026. } else {
  6027. iwl3945_scan_cancel_timeout(priv, 100);
  6028. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6029. iwl3945_commit_rxon(priv);
  6030. }
  6031. done:
  6032. spin_lock_irqsave(&priv->lock, flags);
  6033. if (!conf->ssid_len)
  6034. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6035. else
  6036. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  6037. priv->essid_len = conf->ssid_len;
  6038. spin_unlock_irqrestore(&priv->lock, flags);
  6039. IWL_DEBUG_MAC80211("leave\n");
  6040. mutex_unlock(&priv->mutex);
  6041. return 0;
  6042. }
  6043. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  6044. unsigned int changed_flags,
  6045. unsigned int *total_flags,
  6046. int mc_count, struct dev_addr_list *mc_list)
  6047. {
  6048. /*
  6049. * XXX: dummy
  6050. * see also iwl3945_connection_init_rx_config
  6051. */
  6052. *total_flags = 0;
  6053. }
  6054. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  6055. struct ieee80211_if_init_conf *conf)
  6056. {
  6057. struct iwl3945_priv *priv = hw->priv;
  6058. IWL_DEBUG_MAC80211("enter\n");
  6059. mutex_lock(&priv->mutex);
  6060. if (iwl3945_is_ready_rf(priv)) {
  6061. iwl3945_scan_cancel_timeout(priv, 100);
  6062. cancel_delayed_work(&priv->post_associate);
  6063. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6064. iwl3945_commit_rxon(priv);
  6065. }
  6066. if (priv->vif == conf->vif) {
  6067. priv->vif = NULL;
  6068. memset(priv->bssid, 0, ETH_ALEN);
  6069. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  6070. priv->essid_len = 0;
  6071. }
  6072. mutex_unlock(&priv->mutex);
  6073. IWL_DEBUG_MAC80211("leave\n");
  6074. }
  6075. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  6076. {
  6077. int rc = 0;
  6078. unsigned long flags;
  6079. struct iwl3945_priv *priv = hw->priv;
  6080. IWL_DEBUG_MAC80211("enter\n");
  6081. mutex_lock(&priv->mutex);
  6082. spin_lock_irqsave(&priv->lock, flags);
  6083. if (!iwl3945_is_ready_rf(priv)) {
  6084. rc = -EIO;
  6085. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  6086. goto out_unlock;
  6087. }
  6088. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  6089. rc = -EIO;
  6090. IWL_ERROR("ERROR: APs don't scan\n");
  6091. goto out_unlock;
  6092. }
  6093. /* we don't schedule scan within next_scan_jiffies period */
  6094. if (priv->next_scan_jiffies &&
  6095. time_after(priv->next_scan_jiffies, jiffies)) {
  6096. rc = -EAGAIN;
  6097. goto out_unlock;
  6098. }
  6099. /* if we just finished scan ask for delay */
  6100. if (priv->last_scan_jiffies && time_after(priv->last_scan_jiffies +
  6101. IWL_DELAY_NEXT_SCAN, jiffies)) {
  6102. rc = -EAGAIN;
  6103. goto out_unlock;
  6104. }
  6105. if (len) {
  6106. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  6107. iwl3945_escape_essid(ssid, len), (int)len);
  6108. priv->one_direct_scan = 1;
  6109. priv->direct_ssid_len = (u8)
  6110. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  6111. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  6112. } else
  6113. priv->one_direct_scan = 0;
  6114. rc = iwl3945_scan_initiate(priv);
  6115. IWL_DEBUG_MAC80211("leave\n");
  6116. out_unlock:
  6117. spin_unlock_irqrestore(&priv->lock, flags);
  6118. mutex_unlock(&priv->mutex);
  6119. return rc;
  6120. }
  6121. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  6122. const u8 *local_addr, const u8 *addr,
  6123. struct ieee80211_key_conf *key)
  6124. {
  6125. struct iwl3945_priv *priv = hw->priv;
  6126. int rc = 0;
  6127. u8 sta_id;
  6128. IWL_DEBUG_MAC80211("enter\n");
  6129. if (!iwl3945_param_hwcrypto) {
  6130. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  6131. return -EOPNOTSUPP;
  6132. }
  6133. if (is_zero_ether_addr(addr))
  6134. /* only support pairwise keys */
  6135. return -EOPNOTSUPP;
  6136. sta_id = iwl3945_hw_find_station(priv, addr);
  6137. if (sta_id == IWL_INVALID_STATION) {
  6138. DECLARE_MAC_BUF(mac);
  6139. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  6140. print_mac(mac, addr));
  6141. return -EINVAL;
  6142. }
  6143. mutex_lock(&priv->mutex);
  6144. iwl3945_scan_cancel_timeout(priv, 100);
  6145. switch (cmd) {
  6146. case SET_KEY:
  6147. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  6148. if (!rc) {
  6149. iwl3945_set_rxon_hwcrypto(priv, 1);
  6150. iwl3945_commit_rxon(priv);
  6151. key->hw_key_idx = sta_id;
  6152. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  6153. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  6154. }
  6155. break;
  6156. case DISABLE_KEY:
  6157. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  6158. if (!rc) {
  6159. iwl3945_set_rxon_hwcrypto(priv, 0);
  6160. iwl3945_commit_rxon(priv);
  6161. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  6162. }
  6163. break;
  6164. default:
  6165. rc = -EINVAL;
  6166. }
  6167. IWL_DEBUG_MAC80211("leave\n");
  6168. mutex_unlock(&priv->mutex);
  6169. return rc;
  6170. }
  6171. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, int queue,
  6172. const struct ieee80211_tx_queue_params *params)
  6173. {
  6174. struct iwl3945_priv *priv = hw->priv;
  6175. unsigned long flags;
  6176. int q;
  6177. IWL_DEBUG_MAC80211("enter\n");
  6178. if (!iwl3945_is_ready_rf(priv)) {
  6179. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6180. return -EIO;
  6181. }
  6182. if (queue >= AC_NUM) {
  6183. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  6184. return 0;
  6185. }
  6186. if (!priv->qos_data.qos_enable) {
  6187. priv->qos_data.qos_active = 0;
  6188. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  6189. return 0;
  6190. }
  6191. q = AC_NUM - 1 - queue;
  6192. spin_lock_irqsave(&priv->lock, flags);
  6193. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  6194. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  6195. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  6196. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  6197. cpu_to_le16((params->txop * 32));
  6198. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  6199. priv->qos_data.qos_active = 1;
  6200. spin_unlock_irqrestore(&priv->lock, flags);
  6201. mutex_lock(&priv->mutex);
  6202. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  6203. iwl3945_activate_qos(priv, 1);
  6204. else if (priv->assoc_id && iwl3945_is_associated(priv))
  6205. iwl3945_activate_qos(priv, 0);
  6206. mutex_unlock(&priv->mutex);
  6207. IWL_DEBUG_MAC80211("leave\n");
  6208. return 0;
  6209. }
  6210. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  6211. struct ieee80211_tx_queue_stats *stats)
  6212. {
  6213. struct iwl3945_priv *priv = hw->priv;
  6214. int i, avail;
  6215. struct iwl3945_tx_queue *txq;
  6216. struct iwl3945_queue *q;
  6217. unsigned long flags;
  6218. IWL_DEBUG_MAC80211("enter\n");
  6219. if (!iwl3945_is_ready_rf(priv)) {
  6220. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6221. return -EIO;
  6222. }
  6223. spin_lock_irqsave(&priv->lock, flags);
  6224. for (i = 0; i < AC_NUM; i++) {
  6225. txq = &priv->txq[i];
  6226. q = &txq->q;
  6227. avail = iwl3945_queue_space(q);
  6228. stats->data[i].len = q->n_window - avail;
  6229. stats->data[i].limit = q->n_window - q->high_mark;
  6230. stats->data[i].count = q->n_window;
  6231. }
  6232. spin_unlock_irqrestore(&priv->lock, flags);
  6233. IWL_DEBUG_MAC80211("leave\n");
  6234. return 0;
  6235. }
  6236. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6237. struct ieee80211_low_level_stats *stats)
  6238. {
  6239. IWL_DEBUG_MAC80211("enter\n");
  6240. IWL_DEBUG_MAC80211("leave\n");
  6241. return 0;
  6242. }
  6243. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6244. {
  6245. IWL_DEBUG_MAC80211("enter\n");
  6246. IWL_DEBUG_MAC80211("leave\n");
  6247. return 0;
  6248. }
  6249. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6250. {
  6251. struct iwl3945_priv *priv = hw->priv;
  6252. unsigned long flags;
  6253. mutex_lock(&priv->mutex);
  6254. IWL_DEBUG_MAC80211("enter\n");
  6255. iwl3945_reset_qos(priv);
  6256. cancel_delayed_work(&priv->post_associate);
  6257. spin_lock_irqsave(&priv->lock, flags);
  6258. priv->assoc_id = 0;
  6259. priv->assoc_capability = 0;
  6260. priv->call_post_assoc_from_beacon = 0;
  6261. /* new association get rid of ibss beacon skb */
  6262. if (priv->ibss_beacon)
  6263. dev_kfree_skb(priv->ibss_beacon);
  6264. priv->ibss_beacon = NULL;
  6265. priv->beacon_int = priv->hw->conf.beacon_int;
  6266. priv->timestamp1 = 0;
  6267. priv->timestamp0 = 0;
  6268. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6269. priv->beacon_int = 0;
  6270. spin_unlock_irqrestore(&priv->lock, flags);
  6271. if (!iwl3945_is_ready_rf(priv)) {
  6272. IWL_DEBUG_MAC80211("leave - not ready\n");
  6273. mutex_unlock(&priv->mutex);
  6274. return;
  6275. }
  6276. /* we are restarting association process
  6277. * clear RXON_FILTER_ASSOC_MSK bit
  6278. */
  6279. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6280. iwl3945_scan_cancel_timeout(priv, 100);
  6281. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6282. iwl3945_commit_rxon(priv);
  6283. }
  6284. /* Per mac80211.h: This is only used in IBSS mode... */
  6285. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6286. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6287. mutex_unlock(&priv->mutex);
  6288. return;
  6289. }
  6290. priv->only_active_channel = 0;
  6291. iwl3945_set_rate(priv);
  6292. mutex_unlock(&priv->mutex);
  6293. IWL_DEBUG_MAC80211("leave\n");
  6294. }
  6295. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
  6296. struct ieee80211_tx_control *control)
  6297. {
  6298. struct iwl3945_priv *priv = hw->priv;
  6299. unsigned long flags;
  6300. mutex_lock(&priv->mutex);
  6301. IWL_DEBUG_MAC80211("enter\n");
  6302. if (!iwl3945_is_ready_rf(priv)) {
  6303. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6304. mutex_unlock(&priv->mutex);
  6305. return -EIO;
  6306. }
  6307. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6308. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6309. mutex_unlock(&priv->mutex);
  6310. return -EIO;
  6311. }
  6312. spin_lock_irqsave(&priv->lock, flags);
  6313. if (priv->ibss_beacon)
  6314. dev_kfree_skb(priv->ibss_beacon);
  6315. priv->ibss_beacon = skb;
  6316. priv->assoc_id = 0;
  6317. IWL_DEBUG_MAC80211("leave\n");
  6318. spin_unlock_irqrestore(&priv->lock, flags);
  6319. iwl3945_reset_qos(priv);
  6320. queue_work(priv->workqueue, &priv->post_associate.work);
  6321. mutex_unlock(&priv->mutex);
  6322. return 0;
  6323. }
  6324. /*****************************************************************************
  6325. *
  6326. * sysfs attributes
  6327. *
  6328. *****************************************************************************/
  6329. #ifdef CONFIG_IWL3945_DEBUG
  6330. /*
  6331. * The following adds a new attribute to the sysfs representation
  6332. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6333. * used for controlling the debug level.
  6334. *
  6335. * See the level definitions in iwl for details.
  6336. */
  6337. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6338. {
  6339. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6340. }
  6341. static ssize_t store_debug_level(struct device_driver *d,
  6342. const char *buf, size_t count)
  6343. {
  6344. char *p = (char *)buf;
  6345. u32 val;
  6346. val = simple_strtoul(p, &p, 0);
  6347. if (p == buf)
  6348. printk(KERN_INFO DRV_NAME
  6349. ": %s is not in hex or decimal form.\n", buf);
  6350. else
  6351. iwl3945_debug_level = val;
  6352. return strnlen(buf, count);
  6353. }
  6354. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6355. show_debug_level, store_debug_level);
  6356. #endif /* CONFIG_IWL3945_DEBUG */
  6357. static ssize_t show_rf_kill(struct device *d,
  6358. struct device_attribute *attr, char *buf)
  6359. {
  6360. /*
  6361. * 0 - RF kill not enabled
  6362. * 1 - SW based RF kill active (sysfs)
  6363. * 2 - HW based RF kill active
  6364. * 3 - Both HW and SW based RF kill active
  6365. */
  6366. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6367. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6368. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6369. return sprintf(buf, "%i\n", val);
  6370. }
  6371. static ssize_t store_rf_kill(struct device *d,
  6372. struct device_attribute *attr,
  6373. const char *buf, size_t count)
  6374. {
  6375. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6376. mutex_lock(&priv->mutex);
  6377. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6378. mutex_unlock(&priv->mutex);
  6379. return count;
  6380. }
  6381. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6382. static ssize_t show_temperature(struct device *d,
  6383. struct device_attribute *attr, char *buf)
  6384. {
  6385. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6386. if (!iwl3945_is_alive(priv))
  6387. return -EAGAIN;
  6388. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6389. }
  6390. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6391. static ssize_t show_rs_window(struct device *d,
  6392. struct device_attribute *attr,
  6393. char *buf)
  6394. {
  6395. struct iwl3945_priv *priv = d->driver_data;
  6396. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6397. }
  6398. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6399. static ssize_t show_tx_power(struct device *d,
  6400. struct device_attribute *attr, char *buf)
  6401. {
  6402. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6403. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6404. }
  6405. static ssize_t store_tx_power(struct device *d,
  6406. struct device_attribute *attr,
  6407. const char *buf, size_t count)
  6408. {
  6409. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6410. char *p = (char *)buf;
  6411. u32 val;
  6412. val = simple_strtoul(p, &p, 10);
  6413. if (p == buf)
  6414. printk(KERN_INFO DRV_NAME
  6415. ": %s is not in decimal form.\n", buf);
  6416. else
  6417. iwl3945_hw_reg_set_txpower(priv, val);
  6418. return count;
  6419. }
  6420. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6421. static ssize_t show_flags(struct device *d,
  6422. struct device_attribute *attr, char *buf)
  6423. {
  6424. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6425. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6426. }
  6427. static ssize_t store_flags(struct device *d,
  6428. struct device_attribute *attr,
  6429. const char *buf, size_t count)
  6430. {
  6431. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6432. u32 flags = simple_strtoul(buf, NULL, 0);
  6433. mutex_lock(&priv->mutex);
  6434. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6435. /* Cancel any currently running scans... */
  6436. if (iwl3945_scan_cancel_timeout(priv, 100))
  6437. IWL_WARNING("Could not cancel scan.\n");
  6438. else {
  6439. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6440. flags);
  6441. priv->staging_rxon.flags = cpu_to_le32(flags);
  6442. iwl3945_commit_rxon(priv);
  6443. }
  6444. }
  6445. mutex_unlock(&priv->mutex);
  6446. return count;
  6447. }
  6448. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6449. static ssize_t show_filter_flags(struct device *d,
  6450. struct device_attribute *attr, char *buf)
  6451. {
  6452. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6453. return sprintf(buf, "0x%04X\n",
  6454. le32_to_cpu(priv->active_rxon.filter_flags));
  6455. }
  6456. static ssize_t store_filter_flags(struct device *d,
  6457. struct device_attribute *attr,
  6458. const char *buf, size_t count)
  6459. {
  6460. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6461. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6462. mutex_lock(&priv->mutex);
  6463. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6464. /* Cancel any currently running scans... */
  6465. if (iwl3945_scan_cancel_timeout(priv, 100))
  6466. IWL_WARNING("Could not cancel scan.\n");
  6467. else {
  6468. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6469. "0x%04X\n", filter_flags);
  6470. priv->staging_rxon.filter_flags =
  6471. cpu_to_le32(filter_flags);
  6472. iwl3945_commit_rxon(priv);
  6473. }
  6474. }
  6475. mutex_unlock(&priv->mutex);
  6476. return count;
  6477. }
  6478. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6479. store_filter_flags);
  6480. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6481. static ssize_t show_measurement(struct device *d,
  6482. struct device_attribute *attr, char *buf)
  6483. {
  6484. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6485. struct iwl3945_spectrum_notification measure_report;
  6486. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6487. u8 *data = (u8 *) & measure_report;
  6488. unsigned long flags;
  6489. spin_lock_irqsave(&priv->lock, flags);
  6490. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6491. spin_unlock_irqrestore(&priv->lock, flags);
  6492. return 0;
  6493. }
  6494. memcpy(&measure_report, &priv->measure_report, size);
  6495. priv->measurement_status = 0;
  6496. spin_unlock_irqrestore(&priv->lock, flags);
  6497. while (size && (PAGE_SIZE - len)) {
  6498. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6499. PAGE_SIZE - len, 1);
  6500. len = strlen(buf);
  6501. if (PAGE_SIZE - len)
  6502. buf[len++] = '\n';
  6503. ofs += 16;
  6504. size -= min(size, 16U);
  6505. }
  6506. return len;
  6507. }
  6508. static ssize_t store_measurement(struct device *d,
  6509. struct device_attribute *attr,
  6510. const char *buf, size_t count)
  6511. {
  6512. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6513. struct ieee80211_measurement_params params = {
  6514. .channel = le16_to_cpu(priv->active_rxon.channel),
  6515. .start_time = cpu_to_le64(priv->last_tsf),
  6516. .duration = cpu_to_le16(1),
  6517. };
  6518. u8 type = IWL_MEASURE_BASIC;
  6519. u8 buffer[32];
  6520. u8 channel;
  6521. if (count) {
  6522. char *p = buffer;
  6523. strncpy(buffer, buf, min(sizeof(buffer), count));
  6524. channel = simple_strtoul(p, NULL, 0);
  6525. if (channel)
  6526. params.channel = channel;
  6527. p = buffer;
  6528. while (*p && *p != ' ')
  6529. p++;
  6530. if (*p)
  6531. type = simple_strtoul(p + 1, NULL, 0);
  6532. }
  6533. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6534. "channel %d (for '%s')\n", type, params.channel, buf);
  6535. iwl3945_get_measurement(priv, &params, type);
  6536. return count;
  6537. }
  6538. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6539. show_measurement, store_measurement);
  6540. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6541. static ssize_t show_rate(struct device *d,
  6542. struct device_attribute *attr, char *buf)
  6543. {
  6544. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6545. unsigned long flags;
  6546. int i;
  6547. spin_lock_irqsave(&priv->sta_lock, flags);
  6548. if (priv->iw_mode == IEEE80211_IF_TYPE_STA)
  6549. i = priv->stations[IWL_AP_ID].current_rate.s.rate;
  6550. else
  6551. i = priv->stations[IWL_STA_ID].current_rate.s.rate;
  6552. spin_unlock_irqrestore(&priv->sta_lock, flags);
  6553. i = iwl3945_rate_index_from_plcp(i);
  6554. if (i == -1)
  6555. return sprintf(buf, "0\n");
  6556. return sprintf(buf, "%d%s\n",
  6557. (iwl3945_rates[i].ieee >> 1),
  6558. (iwl3945_rates[i].ieee & 0x1) ? ".5" : "");
  6559. }
  6560. static DEVICE_ATTR(rate, S_IRUSR, show_rate, NULL);
  6561. static ssize_t store_retry_rate(struct device *d,
  6562. struct device_attribute *attr,
  6563. const char *buf, size_t count)
  6564. {
  6565. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6566. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6567. if (priv->retry_rate <= 0)
  6568. priv->retry_rate = 1;
  6569. return count;
  6570. }
  6571. static ssize_t show_retry_rate(struct device *d,
  6572. struct device_attribute *attr, char *buf)
  6573. {
  6574. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6575. return sprintf(buf, "%d", priv->retry_rate);
  6576. }
  6577. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6578. store_retry_rate);
  6579. static ssize_t store_power_level(struct device *d,
  6580. struct device_attribute *attr,
  6581. const char *buf, size_t count)
  6582. {
  6583. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6584. int rc;
  6585. int mode;
  6586. mode = simple_strtoul(buf, NULL, 0);
  6587. mutex_lock(&priv->mutex);
  6588. if (!iwl3945_is_ready(priv)) {
  6589. rc = -EAGAIN;
  6590. goto out;
  6591. }
  6592. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6593. mode = IWL_POWER_AC;
  6594. else
  6595. mode |= IWL_POWER_ENABLED;
  6596. if (mode != priv->power_mode) {
  6597. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6598. if (rc) {
  6599. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6600. goto out;
  6601. }
  6602. priv->power_mode = mode;
  6603. }
  6604. rc = count;
  6605. out:
  6606. mutex_unlock(&priv->mutex);
  6607. return rc;
  6608. }
  6609. #define MAX_WX_STRING 80
  6610. /* Values are in microsecond */
  6611. static const s32 timeout_duration[] = {
  6612. 350000,
  6613. 250000,
  6614. 75000,
  6615. 37000,
  6616. 25000,
  6617. };
  6618. static const s32 period_duration[] = {
  6619. 400000,
  6620. 700000,
  6621. 1000000,
  6622. 1000000,
  6623. 1000000
  6624. };
  6625. static ssize_t show_power_level(struct device *d,
  6626. struct device_attribute *attr, char *buf)
  6627. {
  6628. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6629. int level = IWL_POWER_LEVEL(priv->power_mode);
  6630. char *p = buf;
  6631. p += sprintf(p, "%d ", level);
  6632. switch (level) {
  6633. case IWL_POWER_MODE_CAM:
  6634. case IWL_POWER_AC:
  6635. p += sprintf(p, "(AC)");
  6636. break;
  6637. case IWL_POWER_BATTERY:
  6638. p += sprintf(p, "(BATTERY)");
  6639. break;
  6640. default:
  6641. p += sprintf(p,
  6642. "(Timeout %dms, Period %dms)",
  6643. timeout_duration[level - 1] / 1000,
  6644. period_duration[level - 1] / 1000);
  6645. }
  6646. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6647. p += sprintf(p, " OFF\n");
  6648. else
  6649. p += sprintf(p, " \n");
  6650. return (p - buf + 1);
  6651. }
  6652. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6653. store_power_level);
  6654. static ssize_t show_channels(struct device *d,
  6655. struct device_attribute *attr, char *buf)
  6656. {
  6657. /* all this shit doesn't belong into sysfs anyway */
  6658. return 0;
  6659. }
  6660. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6661. static ssize_t show_statistics(struct device *d,
  6662. struct device_attribute *attr, char *buf)
  6663. {
  6664. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6665. u32 size = sizeof(struct iwl3945_notif_statistics);
  6666. u32 len = 0, ofs = 0;
  6667. u8 *data = (u8 *) & priv->statistics;
  6668. int rc = 0;
  6669. if (!iwl3945_is_alive(priv))
  6670. return -EAGAIN;
  6671. mutex_lock(&priv->mutex);
  6672. rc = iwl3945_send_statistics_request(priv);
  6673. mutex_unlock(&priv->mutex);
  6674. if (rc) {
  6675. len = sprintf(buf,
  6676. "Error sending statistics request: 0x%08X\n", rc);
  6677. return len;
  6678. }
  6679. while (size && (PAGE_SIZE - len)) {
  6680. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6681. PAGE_SIZE - len, 1);
  6682. len = strlen(buf);
  6683. if (PAGE_SIZE - len)
  6684. buf[len++] = '\n';
  6685. ofs += 16;
  6686. size -= min(size, 16U);
  6687. }
  6688. return len;
  6689. }
  6690. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6691. static ssize_t show_antenna(struct device *d,
  6692. struct device_attribute *attr, char *buf)
  6693. {
  6694. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6695. if (!iwl3945_is_alive(priv))
  6696. return -EAGAIN;
  6697. return sprintf(buf, "%d\n", priv->antenna);
  6698. }
  6699. static ssize_t store_antenna(struct device *d,
  6700. struct device_attribute *attr,
  6701. const char *buf, size_t count)
  6702. {
  6703. int ant;
  6704. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6705. if (count == 0)
  6706. return 0;
  6707. if (sscanf(buf, "%1i", &ant) != 1) {
  6708. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6709. return count;
  6710. }
  6711. if ((ant >= 0) && (ant <= 2)) {
  6712. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6713. priv->antenna = (enum iwl3945_antenna)ant;
  6714. } else
  6715. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6716. return count;
  6717. }
  6718. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6719. static ssize_t show_status(struct device *d,
  6720. struct device_attribute *attr, char *buf)
  6721. {
  6722. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6723. if (!iwl3945_is_alive(priv))
  6724. return -EAGAIN;
  6725. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6726. }
  6727. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6728. static ssize_t dump_error_log(struct device *d,
  6729. struct device_attribute *attr,
  6730. const char *buf, size_t count)
  6731. {
  6732. char *p = (char *)buf;
  6733. if (p[0] == '1')
  6734. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6735. return strnlen(buf, count);
  6736. }
  6737. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6738. static ssize_t dump_event_log(struct device *d,
  6739. struct device_attribute *attr,
  6740. const char *buf, size_t count)
  6741. {
  6742. char *p = (char *)buf;
  6743. if (p[0] == '1')
  6744. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6745. return strnlen(buf, count);
  6746. }
  6747. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6748. /*****************************************************************************
  6749. *
  6750. * driver setup and teardown
  6751. *
  6752. *****************************************************************************/
  6753. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6754. {
  6755. priv->workqueue = create_workqueue(DRV_NAME);
  6756. init_waitqueue_head(&priv->wait_command_queue);
  6757. INIT_WORK(&priv->up, iwl3945_bg_up);
  6758. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6759. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6760. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6761. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6762. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6763. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6764. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6765. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6766. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6767. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6768. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6769. iwl3945_hw_setup_deferred_work(priv);
  6770. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6771. iwl3945_irq_tasklet, (unsigned long)priv);
  6772. }
  6773. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6774. {
  6775. iwl3945_hw_cancel_deferred_work(priv);
  6776. cancel_delayed_work_sync(&priv->init_alive_start);
  6777. cancel_delayed_work(&priv->scan_check);
  6778. cancel_delayed_work(&priv->alive_start);
  6779. cancel_delayed_work(&priv->post_associate);
  6780. cancel_work_sync(&priv->beacon_update);
  6781. }
  6782. static struct attribute *iwl3945_sysfs_entries[] = {
  6783. &dev_attr_antenna.attr,
  6784. &dev_attr_channels.attr,
  6785. &dev_attr_dump_errors.attr,
  6786. &dev_attr_dump_events.attr,
  6787. &dev_attr_flags.attr,
  6788. &dev_attr_filter_flags.attr,
  6789. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6790. &dev_attr_measurement.attr,
  6791. #endif
  6792. &dev_attr_power_level.attr,
  6793. &dev_attr_rate.attr,
  6794. &dev_attr_retry_rate.attr,
  6795. &dev_attr_rf_kill.attr,
  6796. &dev_attr_rs_window.attr,
  6797. &dev_attr_statistics.attr,
  6798. &dev_attr_status.attr,
  6799. &dev_attr_temperature.attr,
  6800. &dev_attr_tx_power.attr,
  6801. NULL
  6802. };
  6803. static struct attribute_group iwl3945_attribute_group = {
  6804. .name = NULL, /* put in device directory */
  6805. .attrs = iwl3945_sysfs_entries,
  6806. };
  6807. static struct ieee80211_ops iwl3945_hw_ops = {
  6808. .tx = iwl3945_mac_tx,
  6809. .start = iwl3945_mac_start,
  6810. .stop = iwl3945_mac_stop,
  6811. .add_interface = iwl3945_mac_add_interface,
  6812. .remove_interface = iwl3945_mac_remove_interface,
  6813. .config = iwl3945_mac_config,
  6814. .config_interface = iwl3945_mac_config_interface,
  6815. .configure_filter = iwl3945_configure_filter,
  6816. .set_key = iwl3945_mac_set_key,
  6817. .get_stats = iwl3945_mac_get_stats,
  6818. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6819. .conf_tx = iwl3945_mac_conf_tx,
  6820. .get_tsf = iwl3945_mac_get_tsf,
  6821. .reset_tsf = iwl3945_mac_reset_tsf,
  6822. .beacon_update = iwl3945_mac_beacon_update,
  6823. .hw_scan = iwl3945_mac_hw_scan
  6824. };
  6825. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6826. {
  6827. int err = 0;
  6828. u32 pci_id;
  6829. struct iwl3945_priv *priv;
  6830. struct ieee80211_hw *hw;
  6831. int i;
  6832. DECLARE_MAC_BUF(mac);
  6833. /* Disabling hardware scan means that mac80211 will perform scans
  6834. * "the hard way", rather than using device's scan. */
  6835. if (iwl3945_param_disable_hw_scan) {
  6836. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6837. iwl3945_hw_ops.hw_scan = NULL;
  6838. }
  6839. if ((iwl3945_param_queues_num > IWL_MAX_NUM_QUEUES) ||
  6840. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6841. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6842. IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
  6843. err = -EINVAL;
  6844. goto out;
  6845. }
  6846. /* mac80211 allocates memory for this device instance, including
  6847. * space for this driver's private structure */
  6848. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6849. if (hw == NULL) {
  6850. IWL_ERROR("Can not allocate network device\n");
  6851. err = -ENOMEM;
  6852. goto out;
  6853. }
  6854. SET_IEEE80211_DEV(hw, &pdev->dev);
  6855. hw->rate_control_algorithm = "iwl-3945-rs";
  6856. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6857. priv = hw->priv;
  6858. priv->hw = hw;
  6859. priv->pci_dev = pdev;
  6860. /* Select antenna (may be helpful if only one antenna is connected) */
  6861. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6862. #ifdef CONFIG_IWL3945_DEBUG
  6863. iwl3945_debug_level = iwl3945_param_debug;
  6864. atomic_set(&priv->restrict_refcnt, 0);
  6865. #endif
  6866. priv->retry_rate = 1;
  6867. priv->ibss_beacon = NULL;
  6868. /* Tell mac80211 and its clients (e.g. Wireless Extensions)
  6869. * the range of signal quality values that we'll provide.
  6870. * Negative values for level/noise indicate that we'll provide dBm.
  6871. * For WE, at least, non-0 values here *enable* display of values
  6872. * in app (iwconfig). */
  6873. hw->max_rssi = -20; /* signal level, negative indicates dBm */
  6874. hw->max_noise = -20; /* noise level, negative indicates dBm */
  6875. hw->max_signal = 100; /* link quality indication (%) */
  6876. /* Tell mac80211 our Tx characteristics */
  6877. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
  6878. /* 4 EDCA QOS priorities */
  6879. hw->queues = 4;
  6880. spin_lock_init(&priv->lock);
  6881. spin_lock_init(&priv->power_data.lock);
  6882. spin_lock_init(&priv->sta_lock);
  6883. spin_lock_init(&priv->hcmd_lock);
  6884. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6885. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6886. INIT_LIST_HEAD(&priv->free_frames);
  6887. mutex_init(&priv->mutex);
  6888. if (pci_enable_device(pdev)) {
  6889. err = -ENODEV;
  6890. goto out_ieee80211_free_hw;
  6891. }
  6892. pci_set_master(pdev);
  6893. /* Clear the driver's (not device's) station table */
  6894. iwl3945_clear_stations_table(priv);
  6895. priv->data_retry_limit = -1;
  6896. priv->ieee_channels = NULL;
  6897. priv->ieee_rates = NULL;
  6898. priv->band = IEEE80211_BAND_2GHZ;
  6899. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6900. if (!err)
  6901. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6902. if (err) {
  6903. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6904. goto out_pci_disable_device;
  6905. }
  6906. pci_set_drvdata(pdev, priv);
  6907. err = pci_request_regions(pdev, DRV_NAME);
  6908. if (err)
  6909. goto out_pci_disable_device;
  6910. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6911. * PCI Tx retries from interfering with C3 CPU state */
  6912. pci_write_config_byte(pdev, 0x41, 0x00);
  6913. priv->hw_base = pci_iomap(pdev, 0, 0);
  6914. if (!priv->hw_base) {
  6915. err = -ENODEV;
  6916. goto out_pci_release_regions;
  6917. }
  6918. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6919. (unsigned long long) pci_resource_len(pdev, 0));
  6920. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6921. /* Initialize module parameter values here */
  6922. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6923. if (iwl3945_param_disable) {
  6924. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6925. IWL_DEBUG_INFO("Radio disabled.\n");
  6926. }
  6927. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6928. pci_id =
  6929. (priv->pci_dev->device << 16) | priv->pci_dev->subsystem_device;
  6930. switch (pci_id) {
  6931. case 0x42221005: /* 0x4222 0x8086 0x1005 is BG SKU */
  6932. case 0x42221034: /* 0x4222 0x8086 0x1034 is BG SKU */
  6933. case 0x42271014: /* 0x4227 0x8086 0x1014 is BG SKU */
  6934. case 0x42221044: /* 0x4222 0x8086 0x1044 is BG SKU */
  6935. priv->is_abg = 0;
  6936. break;
  6937. /*
  6938. * Rest are assumed ABG SKU -- if this is not the
  6939. * case then the card will get the wrong 'Detected'
  6940. * line in the kernel log however the code that
  6941. * initializes the GEO table will detect no A-band
  6942. * channels and remove the is_abg mask.
  6943. */
  6944. default:
  6945. priv->is_abg = 1;
  6946. break;
  6947. }
  6948. printk(KERN_INFO DRV_NAME
  6949. ": Detected Intel PRO/Wireless 3945%sBG Network Connection\n",
  6950. priv->is_abg ? "A" : "");
  6951. /* Device-specific setup */
  6952. if (iwl3945_hw_set_hw_setting(priv)) {
  6953. IWL_ERROR("failed to set hw settings\n");
  6954. goto out_iounmap;
  6955. }
  6956. if (iwl3945_param_qos_enable)
  6957. priv->qos_data.qos_enable = 1;
  6958. iwl3945_reset_qos(priv);
  6959. priv->qos_data.qos_active = 0;
  6960. priv->qos_data.qos_cap.val = 0;
  6961. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6962. iwl3945_setup_deferred_work(priv);
  6963. iwl3945_setup_rx_handlers(priv);
  6964. priv->rates_mask = IWL_RATES_MASK;
  6965. /* If power management is turned on, default to AC mode */
  6966. priv->power_mode = IWL_POWER_AC;
  6967. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6968. iwl3945_disable_interrupts(priv);
  6969. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6970. if (err) {
  6971. IWL_ERROR("failed to create sysfs device attributes\n");
  6972. goto out_release_irq;
  6973. }
  6974. /* nic init */
  6975. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6976. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6977. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6978. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6979. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6980. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6981. if (err < 0) {
  6982. IWL_DEBUG_INFO("Failed to init the card\n");
  6983. goto out_remove_sysfs;
  6984. }
  6985. /* Read the EEPROM */
  6986. err = iwl3945_eeprom_init(priv);
  6987. if (err) {
  6988. IWL_ERROR("Unable to init EEPROM\n");
  6989. goto out_remove_sysfs;
  6990. }
  6991. /* MAC Address location in EEPROM same for 3945/4965 */
  6992. get_eeprom_mac(priv, priv->mac_addr);
  6993. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6994. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6995. err = iwl3945_init_channel_map(priv);
  6996. if (err) {
  6997. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6998. goto out_remove_sysfs;
  6999. }
  7000. err = iwl3945_init_geos(priv);
  7001. if (err) {
  7002. IWL_ERROR("initializing geos failed: %d\n", err);
  7003. goto out_free_channel_map;
  7004. }
  7005. iwl3945_rate_control_register(priv->hw);
  7006. err = ieee80211_register_hw(priv->hw);
  7007. if (err) {
  7008. IWL_ERROR("Failed to register network device (error %d)\n", err);
  7009. goto out_free_geos;
  7010. }
  7011. priv->hw->conf.beacon_int = 100;
  7012. priv->mac80211_registered = 1;
  7013. pci_save_state(pdev);
  7014. pci_disable_device(pdev);
  7015. return 0;
  7016. out_free_geos:
  7017. iwl3945_free_geos(priv);
  7018. out_free_channel_map:
  7019. iwl3945_free_channel_map(priv);
  7020. out_remove_sysfs:
  7021. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7022. out_release_irq:
  7023. destroy_workqueue(priv->workqueue);
  7024. priv->workqueue = NULL;
  7025. iwl3945_unset_hw_setting(priv);
  7026. out_iounmap:
  7027. pci_iounmap(pdev, priv->hw_base);
  7028. out_pci_release_regions:
  7029. pci_release_regions(pdev);
  7030. out_pci_disable_device:
  7031. pci_disable_device(pdev);
  7032. pci_set_drvdata(pdev, NULL);
  7033. out_ieee80211_free_hw:
  7034. ieee80211_free_hw(priv->hw);
  7035. out:
  7036. return err;
  7037. }
  7038. static void iwl3945_pci_remove(struct pci_dev *pdev)
  7039. {
  7040. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7041. struct list_head *p, *q;
  7042. int i;
  7043. if (!priv)
  7044. return;
  7045. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  7046. set_bit(STATUS_EXIT_PENDING, &priv->status);
  7047. iwl3945_down(priv);
  7048. /* Free MAC hash list for ADHOC */
  7049. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  7050. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  7051. list_del(p);
  7052. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  7053. }
  7054. }
  7055. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  7056. iwl3945_dealloc_ucode_pci(priv);
  7057. if (priv->rxq.bd)
  7058. iwl3945_rx_queue_free(priv, &priv->rxq);
  7059. iwl3945_hw_txq_ctx_free(priv);
  7060. iwl3945_unset_hw_setting(priv);
  7061. iwl3945_clear_stations_table(priv);
  7062. if (priv->mac80211_registered) {
  7063. ieee80211_unregister_hw(priv->hw);
  7064. iwl3945_rate_control_unregister(priv->hw);
  7065. }
  7066. /*netif_stop_queue(dev); */
  7067. flush_workqueue(priv->workqueue);
  7068. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  7069. * priv->workqueue... so we can't take down the workqueue
  7070. * until now... */
  7071. destroy_workqueue(priv->workqueue);
  7072. priv->workqueue = NULL;
  7073. pci_iounmap(pdev, priv->hw_base);
  7074. pci_release_regions(pdev);
  7075. pci_disable_device(pdev);
  7076. pci_set_drvdata(pdev, NULL);
  7077. iwl3945_free_channel_map(priv);
  7078. iwl3945_free_geos(priv);
  7079. if (priv->ibss_beacon)
  7080. dev_kfree_skb(priv->ibss_beacon);
  7081. ieee80211_free_hw(priv->hw);
  7082. }
  7083. #ifdef CONFIG_PM
  7084. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  7085. {
  7086. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7087. if (priv->is_open) {
  7088. set_bit(STATUS_IN_SUSPEND, &priv->status);
  7089. iwl3945_mac_stop(priv->hw);
  7090. priv->is_open = 1;
  7091. }
  7092. pci_set_power_state(pdev, PCI_D3hot);
  7093. return 0;
  7094. }
  7095. static int iwl3945_pci_resume(struct pci_dev *pdev)
  7096. {
  7097. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  7098. pci_set_power_state(pdev, PCI_D0);
  7099. if (priv->is_open)
  7100. iwl3945_mac_start(priv->hw);
  7101. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  7102. return 0;
  7103. }
  7104. #endif /* CONFIG_PM */
  7105. /*****************************************************************************
  7106. *
  7107. * driver and module entry point
  7108. *
  7109. *****************************************************************************/
  7110. static struct pci_driver iwl3945_driver = {
  7111. .name = DRV_NAME,
  7112. .id_table = iwl3945_hw_card_ids,
  7113. .probe = iwl3945_pci_probe,
  7114. .remove = __devexit_p(iwl3945_pci_remove),
  7115. #ifdef CONFIG_PM
  7116. .suspend = iwl3945_pci_suspend,
  7117. .resume = iwl3945_pci_resume,
  7118. #endif
  7119. };
  7120. static int __init iwl3945_init(void)
  7121. {
  7122. int ret;
  7123. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  7124. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  7125. ret = pci_register_driver(&iwl3945_driver);
  7126. if (ret) {
  7127. IWL_ERROR("Unable to initialize PCI module\n");
  7128. return ret;
  7129. }
  7130. #ifdef CONFIG_IWL3945_DEBUG
  7131. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7132. if (ret) {
  7133. IWL_ERROR("Unable to create driver sysfs file\n");
  7134. pci_unregister_driver(&iwl3945_driver);
  7135. return ret;
  7136. }
  7137. #endif
  7138. return ret;
  7139. }
  7140. static void __exit iwl3945_exit(void)
  7141. {
  7142. #ifdef CONFIG_IWL3945_DEBUG
  7143. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  7144. #endif
  7145. pci_unregister_driver(&iwl3945_driver);
  7146. }
  7147. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  7148. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  7149. module_param_named(disable, iwl3945_param_disable, int, 0444);
  7150. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  7151. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  7152. MODULE_PARM_DESC(hwcrypto,
  7153. "using hardware crypto engine (default 0 [software])\n");
  7154. module_param_named(debug, iwl3945_param_debug, int, 0444);
  7155. MODULE_PARM_DESC(debug, "debug output mask");
  7156. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  7157. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  7158. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  7159. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  7160. /* QoS */
  7161. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  7162. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  7163. module_exit(iwl3945_exit);
  7164. module_init(iwl3945_init);