i7core_edac.c 50 KB

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  1. /* Intel 7 core Memory Controller kernel module (Nehalem)
  2. *
  3. * This file may be distributed under the terms of the
  4. * GNU General Public License version 2 only.
  5. *
  6. * Copyright (c) 2009 by:
  7. * Mauro Carvalho Chehab <mchehab@redhat.com>
  8. *
  9. * Red Hat Inc. http://www.redhat.com
  10. *
  11. * Forked and adapted from the i5400_edac driver
  12. *
  13. * Based on the following public Intel datasheets:
  14. * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
  15. * Datasheet, Volume 2:
  16. * http://download.intel.com/design/processor/datashts/320835.pdf
  17. * Intel Xeon Processor 5500 Series Datasheet Volume 2
  18. * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
  19. * also available at:
  20. * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  21. */
  22. #include <linux/module.h>
  23. #include <linux/init.h>
  24. #include <linux/pci.h>
  25. #include <linux/pci_ids.h>
  26. #include <linux/slab.h>
  27. #include <linux/edac.h>
  28. #include <linux/mmzone.h>
  29. #include <linux/edac_mce.h>
  30. #include <linux/smp.h>
  31. #include <asm/processor.h>
  32. #include "edac_core.h"
  33. /*
  34. * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
  35. * registers start at bus 255, and are not reported by BIOS.
  36. * We currently find devices with only 2 sockets. In order to support more QPI
  37. * Quick Path Interconnect, just increment this number.
  38. */
  39. #define MAX_SOCKET_BUSES 2
  40. /*
  41. * Alter this version for the module when modifications are made
  42. */
  43. #define I7CORE_REVISION " Ver: 1.0.0 " __DATE__
  44. #define EDAC_MOD_STR "i7core_edac"
  45. /*
  46. * Debug macros
  47. */
  48. #define i7core_printk(level, fmt, arg...) \
  49. edac_printk(level, "i7core", fmt, ##arg)
  50. #define i7core_mc_printk(mci, level, fmt, arg...) \
  51. edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
  52. /*
  53. * i7core Memory Controller Registers
  54. */
  55. /* OFFSETS for Device 0 Function 0 */
  56. #define MC_CFG_CONTROL 0x90
  57. /* OFFSETS for Device 3 Function 0 */
  58. #define MC_CONTROL 0x48
  59. #define MC_STATUS 0x4c
  60. #define MC_MAX_DOD 0x64
  61. /*
  62. * OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
  63. * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  64. */
  65. #define MC_TEST_ERR_RCV1 0x60
  66. #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
  67. #define MC_TEST_ERR_RCV0 0x64
  68. #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
  69. #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
  70. /* OFFSETS for Device 3 Function 2, as inicated on Xeon 5500 datasheet */
  71. #define MC_COR_ECC_CNT_0 0x80
  72. #define MC_COR_ECC_CNT_1 0x84
  73. #define MC_COR_ECC_CNT_2 0x88
  74. #define MC_COR_ECC_CNT_3 0x8c
  75. #define MC_COR_ECC_CNT_4 0x90
  76. #define MC_COR_ECC_CNT_5 0x94
  77. #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
  78. #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
  79. /* OFFSETS for Devices 4,5 and 6 Function 0 */
  80. #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
  81. #define THREE_DIMMS_PRESENT (1 << 24)
  82. #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
  83. #define QUAD_RANK_PRESENT (1 << 22)
  84. #define REGISTERED_DIMM (1 << 15)
  85. #define MC_CHANNEL_MAPPER 0x60
  86. #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
  87. #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
  88. #define MC_CHANNEL_RANK_PRESENT 0x7c
  89. #define RANK_PRESENT_MASK 0xffff
  90. #define MC_CHANNEL_ADDR_MATCH 0xf0
  91. #define MC_CHANNEL_ERROR_MASK 0xf8
  92. #define MC_CHANNEL_ERROR_INJECT 0xfc
  93. #define INJECT_ADDR_PARITY 0x10
  94. #define INJECT_ECC 0x08
  95. #define MASK_CACHELINE 0x06
  96. #define MASK_FULL_CACHELINE 0x06
  97. #define MASK_MSB32_CACHELINE 0x04
  98. #define MASK_LSB32_CACHELINE 0x02
  99. #define NO_MASK_CACHELINE 0x00
  100. #define REPEAT_EN 0x01
  101. /* OFFSETS for Devices 4,5 and 6 Function 1 */
  102. #define MC_DOD_CH_DIMM0 0x48
  103. #define MC_DOD_CH_DIMM1 0x4c
  104. #define MC_DOD_CH_DIMM2 0x50
  105. #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
  106. #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
  107. #define DIMM_PRESENT_MASK (1 << 9)
  108. #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
  109. #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
  110. #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
  111. #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
  112. #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
  113. #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
  114. #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
  115. #define MC_DOD_NUMCOL_MASK 3
  116. #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
  117. #define MC_RANK_PRESENT 0x7c
  118. #define MC_SAG_CH_0 0x80
  119. #define MC_SAG_CH_1 0x84
  120. #define MC_SAG_CH_2 0x88
  121. #define MC_SAG_CH_3 0x8c
  122. #define MC_SAG_CH_4 0x90
  123. #define MC_SAG_CH_5 0x94
  124. #define MC_SAG_CH_6 0x98
  125. #define MC_SAG_CH_7 0x9c
  126. #define MC_RIR_LIMIT_CH_0 0x40
  127. #define MC_RIR_LIMIT_CH_1 0x44
  128. #define MC_RIR_LIMIT_CH_2 0x48
  129. #define MC_RIR_LIMIT_CH_3 0x4C
  130. #define MC_RIR_LIMIT_CH_4 0x50
  131. #define MC_RIR_LIMIT_CH_5 0x54
  132. #define MC_RIR_LIMIT_CH_6 0x58
  133. #define MC_RIR_LIMIT_CH_7 0x5C
  134. #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
  135. #define MC_RIR_WAY_CH 0x80
  136. #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
  137. #define MC_RIR_WAY_RANK_MASK 0x7
  138. /*
  139. * i7core structs
  140. */
  141. #define NUM_CHANS 3
  142. #define MAX_DIMMS 3 /* Max DIMMS per channel */
  143. #define MAX_MCR_FUNC 4
  144. #define MAX_CHAN_FUNC 3
  145. struct i7core_info {
  146. u32 mc_control;
  147. u32 mc_status;
  148. u32 max_dod;
  149. u32 ch_map;
  150. };
  151. struct i7core_inject {
  152. int enable;
  153. u32 section;
  154. u32 type;
  155. u32 eccmask;
  156. /* Error address mask */
  157. int channel, dimm, rank, bank, page, col;
  158. };
  159. struct i7core_channel {
  160. u32 ranks;
  161. u32 dimms;
  162. };
  163. struct pci_id_descr {
  164. int dev;
  165. int func;
  166. int dev_id;
  167. };
  168. struct i7core_dev {
  169. struct list_head list;
  170. u8 socket;
  171. struct pci_dev **pdev;
  172. struct mem_ctl_info *mci;
  173. };
  174. struct i7core_pvt {
  175. struct pci_dev *pci_noncore;
  176. struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
  177. struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
  178. struct i7core_dev *i7core_dev;
  179. struct i7core_info info;
  180. struct i7core_inject inject;
  181. struct i7core_channel channel[NUM_CHANS];
  182. int channels; /* Number of active channels */
  183. int ce_count_available;
  184. int csrow_map[NUM_CHANS][MAX_DIMMS];
  185. /* ECC corrected errors counts per udimm */
  186. unsigned long udimm_ce_count[MAX_DIMMS];
  187. int udimm_last_ce_count[MAX_DIMMS];
  188. /* ECC corrected errors counts per rdimm */
  189. unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
  190. int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
  191. unsigned int is_registered;
  192. /* mcelog glue */
  193. struct edac_mce edac_mce;
  194. /* Fifo double buffers */
  195. struct mce mce_entry[MCE_LOG_LEN];
  196. struct mce mce_outentry[MCE_LOG_LEN];
  197. /* Fifo in/out counters */
  198. unsigned mce_in, mce_out;
  199. /* Count indicator to show errors not got */
  200. unsigned mce_overrun;
  201. };
  202. /* Static vars */
  203. static LIST_HEAD(i7core_edac_list);
  204. static DEFINE_MUTEX(i7core_edac_lock);
  205. #define PCI_DESCR(device, function, device_id) \
  206. .dev = (device), \
  207. .func = (function), \
  208. .dev_id = (device_id)
  209. struct pci_id_descr pci_dev_descr[] = {
  210. /* Memory controller */
  211. { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
  212. { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
  213. { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS) }, /* if RDIMM */
  214. { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
  215. /* Channel 0 */
  216. { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
  217. { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
  218. { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
  219. { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
  220. /* Channel 1 */
  221. { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
  222. { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
  223. { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
  224. { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
  225. /* Channel 2 */
  226. { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
  227. { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
  228. { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
  229. { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
  230. /* Generic Non-core registers */
  231. /*
  232. * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
  233. * On Xeon 55xx, however, it has a different id (8086:2c40). So,
  234. * the probing code needs to test for the other address in case of
  235. * failure of this one
  236. */
  237. { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NOCORE) },
  238. };
  239. #define N_DEVS ARRAY_SIZE(pci_dev_descr)
  240. /*
  241. * pci_device_id table for which devices we are looking for
  242. */
  243. static const struct pci_device_id i7core_pci_tbl[] __devinitdata = {
  244. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
  245. {0,} /* 0 terminated list. */
  246. };
  247. static struct edac_pci_ctl_info *i7core_pci;
  248. /****************************************************************************
  249. Anciliary status routines
  250. ****************************************************************************/
  251. /* MC_CONTROL bits */
  252. #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
  253. #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
  254. /* MC_STATUS bits */
  255. #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
  256. #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
  257. /* MC_MAX_DOD read functions */
  258. static inline int numdimms(u32 dimms)
  259. {
  260. return (dimms & 0x3) + 1;
  261. }
  262. static inline int numrank(u32 rank)
  263. {
  264. static int ranks[4] = { 1, 2, 4, -EINVAL };
  265. return ranks[rank & 0x3];
  266. }
  267. static inline int numbank(u32 bank)
  268. {
  269. static int banks[4] = { 4, 8, 16, -EINVAL };
  270. return banks[bank & 0x3];
  271. }
  272. static inline int numrow(u32 row)
  273. {
  274. static int rows[8] = {
  275. 1 << 12, 1 << 13, 1 << 14, 1 << 15,
  276. 1 << 16, -EINVAL, -EINVAL, -EINVAL,
  277. };
  278. return rows[row & 0x7];
  279. }
  280. static inline int numcol(u32 col)
  281. {
  282. static int cols[8] = {
  283. 1 << 10, 1 << 11, 1 << 12, -EINVAL,
  284. };
  285. return cols[col & 0x3];
  286. }
  287. static struct i7core_dev *get_i7core_dev(u8 socket)
  288. {
  289. struct i7core_dev *i7core_dev;
  290. list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
  291. if (i7core_dev->socket == socket)
  292. return i7core_dev;
  293. }
  294. return NULL;
  295. }
  296. /****************************************************************************
  297. Memory check routines
  298. ****************************************************************************/
  299. static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
  300. unsigned func)
  301. {
  302. struct i7core_dev *i7core_dev = get_i7core_dev(socket);
  303. int i;
  304. if (!i7core_dev)
  305. return NULL;
  306. for (i = 0; i < N_DEVS; i++) {
  307. if (!i7core_dev->pdev[i])
  308. continue;
  309. if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
  310. PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
  311. return i7core_dev->pdev[i];
  312. }
  313. }
  314. return NULL;
  315. }
  316. /**
  317. * i7core_get_active_channels() - gets the number of channels and csrows
  318. * @socket: Quick Path Interconnect socket
  319. * @channels: Number of channels that will be returned
  320. * @csrows: Number of csrows found
  321. *
  322. * Since EDAC core needs to know in advance the number of available channels
  323. * and csrows, in order to allocate memory for csrows/channels, it is needed
  324. * to run two similar steps. At the first step, implemented on this function,
  325. * it checks the number of csrows/channels present at one socket.
  326. * this is used in order to properly allocate the size of mci components.
  327. *
  328. * It should be noticed that none of the current available datasheets explain
  329. * or even mention how csrows are seen by the memory controller. So, we need
  330. * to add a fake description for csrows.
  331. * So, this driver is attributing one DIMM memory for one csrow.
  332. */
  333. static int i7core_get_active_channels(u8 socket, unsigned *channels,
  334. unsigned *csrows)
  335. {
  336. struct pci_dev *pdev = NULL;
  337. int i, j;
  338. u32 status, control;
  339. *channels = 0;
  340. *csrows = 0;
  341. pdev = get_pdev_slot_func(socket, 3, 0);
  342. if (!pdev) {
  343. i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
  344. socket);
  345. return -ENODEV;
  346. }
  347. /* Device 3 function 0 reads */
  348. pci_read_config_dword(pdev, MC_STATUS, &status);
  349. pci_read_config_dword(pdev, MC_CONTROL, &control);
  350. for (i = 0; i < NUM_CHANS; i++) {
  351. u32 dimm_dod[3];
  352. /* Check if the channel is active */
  353. if (!(control & (1 << (8 + i))))
  354. continue;
  355. /* Check if the channel is disabled */
  356. if (status & (1 << i))
  357. continue;
  358. pdev = get_pdev_slot_func(socket, i + 4, 1);
  359. if (!pdev) {
  360. i7core_printk(KERN_ERR, "Couldn't find socket %d "
  361. "fn %d.%d!!!\n",
  362. socket, i + 4, 1);
  363. return -ENODEV;
  364. }
  365. /* Devices 4-6 function 1 */
  366. pci_read_config_dword(pdev,
  367. MC_DOD_CH_DIMM0, &dimm_dod[0]);
  368. pci_read_config_dword(pdev,
  369. MC_DOD_CH_DIMM1, &dimm_dod[1]);
  370. pci_read_config_dword(pdev,
  371. MC_DOD_CH_DIMM2, &dimm_dod[2]);
  372. (*channels)++;
  373. for (j = 0; j < 3; j++) {
  374. if (!DIMM_PRESENT(dimm_dod[j]))
  375. continue;
  376. (*csrows)++;
  377. }
  378. }
  379. debugf0("Number of active channels on socket %d: %d\n",
  380. socket, *channels);
  381. return 0;
  382. }
  383. static int get_dimm_config(struct mem_ctl_info *mci, int *csrow)
  384. {
  385. struct i7core_pvt *pvt = mci->pvt_info;
  386. struct csrow_info *csr;
  387. struct pci_dev *pdev;
  388. int i, j;
  389. unsigned long last_page = 0;
  390. enum edac_type mode;
  391. enum mem_type mtype;
  392. /* Get data from the MC register, function 0 */
  393. pdev = pvt->pci_mcr[0];
  394. if (!pdev)
  395. return -ENODEV;
  396. /* Device 3 function 0 reads */
  397. pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
  398. pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
  399. pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
  400. pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
  401. debugf0("QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
  402. pvt->i7core_dev->socket, pvt->info.mc_control, pvt->info.mc_status,
  403. pvt->info.max_dod, pvt->info.ch_map);
  404. if (ECC_ENABLED(pvt)) {
  405. debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
  406. if (ECCx8(pvt))
  407. mode = EDAC_S8ECD8ED;
  408. else
  409. mode = EDAC_S4ECD4ED;
  410. } else {
  411. debugf0("ECC disabled\n");
  412. mode = EDAC_NONE;
  413. }
  414. /* FIXME: need to handle the error codes */
  415. debugf0("DOD Max limits: DIMMS: %d, %d-ranked, %d-banked "
  416. "x%x x 0x%x\n",
  417. numdimms(pvt->info.max_dod),
  418. numrank(pvt->info.max_dod >> 2),
  419. numbank(pvt->info.max_dod >> 4),
  420. numrow(pvt->info.max_dod >> 6),
  421. numcol(pvt->info.max_dod >> 9));
  422. for (i = 0; i < NUM_CHANS; i++) {
  423. u32 data, dimm_dod[3], value[8];
  424. if (!CH_ACTIVE(pvt, i)) {
  425. debugf0("Channel %i is not active\n", i);
  426. continue;
  427. }
  428. if (CH_DISABLED(pvt, i)) {
  429. debugf0("Channel %i is disabled\n", i);
  430. continue;
  431. }
  432. /* Devices 4-6 function 0 */
  433. pci_read_config_dword(pvt->pci_ch[i][0],
  434. MC_CHANNEL_DIMM_INIT_PARAMS, &data);
  435. pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ?
  436. 4 : 2;
  437. if (data & REGISTERED_DIMM)
  438. mtype = MEM_RDDR3;
  439. else
  440. mtype = MEM_DDR3;
  441. #if 0
  442. if (data & THREE_DIMMS_PRESENT)
  443. pvt->channel[i].dimms = 3;
  444. else if (data & SINGLE_QUAD_RANK_PRESENT)
  445. pvt->channel[i].dimms = 1;
  446. else
  447. pvt->channel[i].dimms = 2;
  448. #endif
  449. /* Devices 4-6 function 1 */
  450. pci_read_config_dword(pvt->pci_ch[i][1],
  451. MC_DOD_CH_DIMM0, &dimm_dod[0]);
  452. pci_read_config_dword(pvt->pci_ch[i][1],
  453. MC_DOD_CH_DIMM1, &dimm_dod[1]);
  454. pci_read_config_dword(pvt->pci_ch[i][1],
  455. MC_DOD_CH_DIMM2, &dimm_dod[2]);
  456. debugf0("Ch%d phy rd%d, wr%d (0x%08x): "
  457. "%d ranks, %cDIMMs\n",
  458. i,
  459. RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
  460. data,
  461. pvt->channel[i].ranks,
  462. (data & REGISTERED_DIMM) ? 'R' : 'U');
  463. for (j = 0; j < 3; j++) {
  464. u32 banks, ranks, rows, cols;
  465. u32 size, npages;
  466. if (!DIMM_PRESENT(dimm_dod[j]))
  467. continue;
  468. banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
  469. ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
  470. rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
  471. cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
  472. /* DDR3 has 8 I/O banks */
  473. size = (rows * cols * banks * ranks) >> (20 - 3);
  474. pvt->channel[i].dimms++;
  475. debugf0("\tdimm %d %d Mb offset: %x, "
  476. "bank: %d, rank: %d, row: %#x, col: %#x\n",
  477. j, size,
  478. RANKOFFSET(dimm_dod[j]),
  479. banks, ranks, rows, cols);
  480. #if PAGE_SHIFT > 20
  481. npages = size >> (PAGE_SHIFT - 20);
  482. #else
  483. npages = size << (20 - PAGE_SHIFT);
  484. #endif
  485. csr = &mci->csrows[*csrow];
  486. csr->first_page = last_page + 1;
  487. last_page += npages;
  488. csr->last_page = last_page;
  489. csr->nr_pages = npages;
  490. csr->page_mask = 0;
  491. csr->grain = 8;
  492. csr->csrow_idx = *csrow;
  493. csr->nr_channels = 1;
  494. csr->channels[0].chan_idx = i;
  495. csr->channels[0].ce_count = 0;
  496. pvt->csrow_map[i][j] = *csrow;
  497. switch (banks) {
  498. case 4:
  499. csr->dtype = DEV_X4;
  500. break;
  501. case 8:
  502. csr->dtype = DEV_X8;
  503. break;
  504. case 16:
  505. csr->dtype = DEV_X16;
  506. break;
  507. default:
  508. csr->dtype = DEV_UNKNOWN;
  509. }
  510. csr->edac_mode = mode;
  511. csr->mtype = mtype;
  512. (*csrow)++;
  513. }
  514. pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
  515. pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
  516. pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
  517. pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
  518. pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
  519. pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
  520. pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
  521. pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
  522. debugf1("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
  523. for (j = 0; j < 8; j++)
  524. debugf1("\t\t%#x\t%#x\t%#x\n",
  525. (value[j] >> 27) & 0x1,
  526. (value[j] >> 24) & 0x7,
  527. (value[j] && ((1 << 24) - 1)));
  528. }
  529. return 0;
  530. }
  531. /****************************************************************************
  532. Error insertion routines
  533. ****************************************************************************/
  534. /* The i7core has independent error injection features per channel.
  535. However, to have a simpler code, we don't allow enabling error injection
  536. on more than one channel.
  537. Also, since a change at an inject parameter will be applied only at enable,
  538. we're disabling error injection on all write calls to the sysfs nodes that
  539. controls the error code injection.
  540. */
  541. static int disable_inject(struct mem_ctl_info *mci)
  542. {
  543. struct i7core_pvt *pvt = mci->pvt_info;
  544. pvt->inject.enable = 0;
  545. if (!pvt->pci_ch[pvt->inject.channel][0])
  546. return -ENODEV;
  547. pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
  548. MC_CHANNEL_ERROR_INJECT, 0);
  549. return 0;
  550. }
  551. /*
  552. * i7core inject inject.section
  553. *
  554. * accept and store error injection inject.section value
  555. * bit 0 - refers to the lower 32-byte half cacheline
  556. * bit 1 - refers to the upper 32-byte half cacheline
  557. */
  558. static ssize_t i7core_inject_section_store(struct mem_ctl_info *mci,
  559. const char *data, size_t count)
  560. {
  561. struct i7core_pvt *pvt = mci->pvt_info;
  562. unsigned long value;
  563. int rc;
  564. if (pvt->inject.enable)
  565. disable_inject(mci);
  566. rc = strict_strtoul(data, 10, &value);
  567. if ((rc < 0) || (value > 3))
  568. return -EIO;
  569. pvt->inject.section = (u32) value;
  570. return count;
  571. }
  572. static ssize_t i7core_inject_section_show(struct mem_ctl_info *mci,
  573. char *data)
  574. {
  575. struct i7core_pvt *pvt = mci->pvt_info;
  576. return sprintf(data, "0x%08x\n", pvt->inject.section);
  577. }
  578. /*
  579. * i7core inject.type
  580. *
  581. * accept and store error injection inject.section value
  582. * bit 0 - repeat enable - Enable error repetition
  583. * bit 1 - inject ECC error
  584. * bit 2 - inject parity error
  585. */
  586. static ssize_t i7core_inject_type_store(struct mem_ctl_info *mci,
  587. const char *data, size_t count)
  588. {
  589. struct i7core_pvt *pvt = mci->pvt_info;
  590. unsigned long value;
  591. int rc;
  592. if (pvt->inject.enable)
  593. disable_inject(mci);
  594. rc = strict_strtoul(data, 10, &value);
  595. if ((rc < 0) || (value > 7))
  596. return -EIO;
  597. pvt->inject.type = (u32) value;
  598. return count;
  599. }
  600. static ssize_t i7core_inject_type_show(struct mem_ctl_info *mci,
  601. char *data)
  602. {
  603. struct i7core_pvt *pvt = mci->pvt_info;
  604. return sprintf(data, "0x%08x\n", pvt->inject.type);
  605. }
  606. /*
  607. * i7core_inject_inject.eccmask_store
  608. *
  609. * The type of error (UE/CE) will depend on the inject.eccmask value:
  610. * Any bits set to a 1 will flip the corresponding ECC bit
  611. * Correctable errors can be injected by flipping 1 bit or the bits within
  612. * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
  613. * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
  614. * uncorrectable error to be injected.
  615. */
  616. static ssize_t i7core_inject_eccmask_store(struct mem_ctl_info *mci,
  617. const char *data, size_t count)
  618. {
  619. struct i7core_pvt *pvt = mci->pvt_info;
  620. unsigned long value;
  621. int rc;
  622. if (pvt->inject.enable)
  623. disable_inject(mci);
  624. rc = strict_strtoul(data, 10, &value);
  625. if (rc < 0)
  626. return -EIO;
  627. pvt->inject.eccmask = (u32) value;
  628. return count;
  629. }
  630. static ssize_t i7core_inject_eccmask_show(struct mem_ctl_info *mci,
  631. char *data)
  632. {
  633. struct i7core_pvt *pvt = mci->pvt_info;
  634. return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
  635. }
  636. /*
  637. * i7core_addrmatch
  638. *
  639. * The type of error (UE/CE) will depend on the inject.eccmask value:
  640. * Any bits set to a 1 will flip the corresponding ECC bit
  641. * Correctable errors can be injected by flipping 1 bit or the bits within
  642. * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
  643. * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
  644. * uncorrectable error to be injected.
  645. */
  646. #define DECLARE_ADDR_MATCH(param, limit) \
  647. static ssize_t i7core_inject_store_##param( \
  648. struct mem_ctl_info *mci, \
  649. const char *data, size_t count) \
  650. { \
  651. struct i7core_pvt *pvt; \
  652. long value; \
  653. int rc; \
  654. \
  655. debugf1("%s()\n", __func__); \
  656. pvt = mci->pvt_info; \
  657. \
  658. if (pvt->inject.enable) \
  659. disable_inject(mci); \
  660. \
  661. if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
  662. value = -1; \
  663. else { \
  664. rc = strict_strtoul(data, 10, &value); \
  665. if ((rc < 0) || (value >= limit)) \
  666. return -EIO; \
  667. } \
  668. \
  669. pvt->inject.param = value; \
  670. \
  671. return count; \
  672. } \
  673. \
  674. static ssize_t i7core_inject_show_##param( \
  675. struct mem_ctl_info *mci, \
  676. char *data) \
  677. { \
  678. struct i7core_pvt *pvt; \
  679. \
  680. pvt = mci->pvt_info; \
  681. debugf1("%s() pvt=%p\n", __func__, pvt); \
  682. if (pvt->inject.param < 0) \
  683. return sprintf(data, "any\n"); \
  684. else \
  685. return sprintf(data, "%d\n", pvt->inject.param);\
  686. }
  687. #define ATTR_ADDR_MATCH(param) \
  688. { \
  689. .attr = { \
  690. .name = #param, \
  691. .mode = (S_IRUGO | S_IWUSR) \
  692. }, \
  693. .show = i7core_inject_show_##param, \
  694. .store = i7core_inject_store_##param, \
  695. }
  696. DECLARE_ADDR_MATCH(channel, 3);
  697. DECLARE_ADDR_MATCH(dimm, 3);
  698. DECLARE_ADDR_MATCH(rank, 4);
  699. DECLARE_ADDR_MATCH(bank, 32);
  700. DECLARE_ADDR_MATCH(page, 0x10000);
  701. DECLARE_ADDR_MATCH(col, 0x4000);
  702. static int write_and_test(struct pci_dev *dev, int where, u32 val)
  703. {
  704. u32 read;
  705. int count;
  706. debugf0("setting pci %02x:%02x.%x reg=%02x value=%08x\n",
  707. dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
  708. where, val);
  709. for (count = 0; count < 10; count++) {
  710. if (count)
  711. msleep(100);
  712. pci_write_config_dword(dev, where, val);
  713. pci_read_config_dword(dev, where, &read);
  714. if (read == val)
  715. return 0;
  716. }
  717. i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
  718. "write=%08x. Read=%08x\n",
  719. dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
  720. where, val, read);
  721. return -EINVAL;
  722. }
  723. /*
  724. * This routine prepares the Memory Controller for error injection.
  725. * The error will be injected when some process tries to write to the
  726. * memory that matches the given criteria.
  727. * The criteria can be set in terms of a mask where dimm, rank, bank, page
  728. * and col can be specified.
  729. * A -1 value for any of the mask items will make the MCU to ignore
  730. * that matching criteria for error injection.
  731. *
  732. * It should be noticed that the error will only happen after a write operation
  733. * on a memory that matches the condition. if REPEAT_EN is not enabled at
  734. * inject mask, then it will produce just one error. Otherwise, it will repeat
  735. * until the injectmask would be cleaned.
  736. *
  737. * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
  738. * is reliable enough to check if the MC is using the
  739. * three channels. However, this is not clear at the datasheet.
  740. */
  741. static ssize_t i7core_inject_enable_store(struct mem_ctl_info *mci,
  742. const char *data, size_t count)
  743. {
  744. struct i7core_pvt *pvt = mci->pvt_info;
  745. u32 injectmask;
  746. u64 mask = 0;
  747. int rc;
  748. long enable;
  749. if (!pvt->pci_ch[pvt->inject.channel][0])
  750. return 0;
  751. rc = strict_strtoul(data, 10, &enable);
  752. if ((rc < 0))
  753. return 0;
  754. if (enable) {
  755. pvt->inject.enable = 1;
  756. } else {
  757. disable_inject(mci);
  758. return count;
  759. }
  760. /* Sets pvt->inject.dimm mask */
  761. if (pvt->inject.dimm < 0)
  762. mask |= 1L << 41;
  763. else {
  764. if (pvt->channel[pvt->inject.channel].dimms > 2)
  765. mask |= (pvt->inject.dimm & 0x3L) << 35;
  766. else
  767. mask |= (pvt->inject.dimm & 0x1L) << 36;
  768. }
  769. /* Sets pvt->inject.rank mask */
  770. if (pvt->inject.rank < 0)
  771. mask |= 1L << 40;
  772. else {
  773. if (pvt->channel[pvt->inject.channel].dimms > 2)
  774. mask |= (pvt->inject.rank & 0x1L) << 34;
  775. else
  776. mask |= (pvt->inject.rank & 0x3L) << 34;
  777. }
  778. /* Sets pvt->inject.bank mask */
  779. if (pvt->inject.bank < 0)
  780. mask |= 1L << 39;
  781. else
  782. mask |= (pvt->inject.bank & 0x15L) << 30;
  783. /* Sets pvt->inject.page mask */
  784. if (pvt->inject.page < 0)
  785. mask |= 1L << 38;
  786. else
  787. mask |= (pvt->inject.page & 0xffffL) << 14;
  788. /* Sets pvt->inject.column mask */
  789. if (pvt->inject.col < 0)
  790. mask |= 1L << 37;
  791. else
  792. mask |= (pvt->inject.col & 0x3fffL);
  793. /*
  794. * bit 0: REPEAT_EN
  795. * bits 1-2: MASK_HALF_CACHELINE
  796. * bit 3: INJECT_ECC
  797. * bit 4: INJECT_ADDR_PARITY
  798. */
  799. injectmask = (pvt->inject.type & 1) |
  800. (pvt->inject.section & 0x3) << 1 |
  801. (pvt->inject.type & 0x6) << (3 - 1);
  802. /* Unlock writes to registers - this register is write only */
  803. pci_write_config_dword(pvt->pci_noncore,
  804. MC_CFG_CONTROL, 0x2);
  805. write_and_test(pvt->pci_ch[pvt->inject.channel][0],
  806. MC_CHANNEL_ADDR_MATCH, mask);
  807. write_and_test(pvt->pci_ch[pvt->inject.channel][0],
  808. MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
  809. write_and_test(pvt->pci_ch[pvt->inject.channel][0],
  810. MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
  811. write_and_test(pvt->pci_ch[pvt->inject.channel][0],
  812. MC_CHANNEL_ERROR_INJECT, injectmask);
  813. /*
  814. * This is something undocumented, based on my tests
  815. * Without writing 8 to this register, errors aren't injected. Not sure
  816. * why.
  817. */
  818. pci_write_config_dword(pvt->pci_noncore,
  819. MC_CFG_CONTROL, 8);
  820. debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
  821. " inject 0x%08x\n",
  822. mask, pvt->inject.eccmask, injectmask);
  823. return count;
  824. }
  825. static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
  826. char *data)
  827. {
  828. struct i7core_pvt *pvt = mci->pvt_info;
  829. u32 injectmask;
  830. pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
  831. MC_CHANNEL_ERROR_INJECT, &injectmask);
  832. debugf0("Inject error read: 0x%018x\n", injectmask);
  833. if (injectmask & 0x0c)
  834. pvt->inject.enable = 1;
  835. return sprintf(data, "%d\n", pvt->inject.enable);
  836. }
  837. #define DECLARE_COUNTER(param) \
  838. static ssize_t i7core_show_counter_##param( \
  839. struct mem_ctl_info *mci, \
  840. char *data) \
  841. { \
  842. struct i7core_pvt *pvt = mci->pvt_info; \
  843. \
  844. debugf1("%s() \n", __func__); \
  845. if (!pvt->ce_count_available || (pvt->is_registered)) \
  846. return sprintf(data, "data unavailable\n"); \
  847. return sprintf(data, "%lu\n", \
  848. pvt->udimm_ce_count[param]); \
  849. }
  850. #define ATTR_COUNTER(param) \
  851. { \
  852. .attr = { \
  853. .name = __stringify(udimm##param), \
  854. .mode = (S_IRUGO | S_IWUSR) \
  855. }, \
  856. .show = i7core_show_counter_##param \
  857. }
  858. DECLARE_COUNTER(0);
  859. DECLARE_COUNTER(1);
  860. DECLARE_COUNTER(2);
  861. /*
  862. * Sysfs struct
  863. */
  864. static struct mcidev_sysfs_attribute i7core_addrmatch_attrs[] = {
  865. ATTR_ADDR_MATCH(channel),
  866. ATTR_ADDR_MATCH(dimm),
  867. ATTR_ADDR_MATCH(rank),
  868. ATTR_ADDR_MATCH(bank),
  869. ATTR_ADDR_MATCH(page),
  870. ATTR_ADDR_MATCH(col),
  871. { .attr = { .name = NULL } }
  872. };
  873. static struct mcidev_sysfs_group i7core_inject_addrmatch = {
  874. .name = "inject_addrmatch",
  875. .mcidev_attr = i7core_addrmatch_attrs,
  876. };
  877. static struct mcidev_sysfs_attribute i7core_udimm_counters_attrs[] = {
  878. ATTR_COUNTER(0),
  879. ATTR_COUNTER(1),
  880. ATTR_COUNTER(2),
  881. };
  882. static struct mcidev_sysfs_group i7core_udimm_counters = {
  883. .name = "all_channel_counts",
  884. .mcidev_attr = i7core_udimm_counters_attrs,
  885. };
  886. static struct mcidev_sysfs_attribute i7core_sysfs_attrs[] = {
  887. {
  888. .attr = {
  889. .name = "inject_section",
  890. .mode = (S_IRUGO | S_IWUSR)
  891. },
  892. .show = i7core_inject_section_show,
  893. .store = i7core_inject_section_store,
  894. }, {
  895. .attr = {
  896. .name = "inject_type",
  897. .mode = (S_IRUGO | S_IWUSR)
  898. },
  899. .show = i7core_inject_type_show,
  900. .store = i7core_inject_type_store,
  901. }, {
  902. .attr = {
  903. .name = "inject_eccmask",
  904. .mode = (S_IRUGO | S_IWUSR)
  905. },
  906. .show = i7core_inject_eccmask_show,
  907. .store = i7core_inject_eccmask_store,
  908. }, {
  909. .grp = &i7core_inject_addrmatch,
  910. }, {
  911. .attr = {
  912. .name = "inject_enable",
  913. .mode = (S_IRUGO | S_IWUSR)
  914. },
  915. .show = i7core_inject_enable_show,
  916. .store = i7core_inject_enable_store,
  917. },
  918. { .attr = { .name = NULL } }, /* Reserved for udimm counters */
  919. { .attr = { .name = NULL } }
  920. };
  921. /****************************************************************************
  922. Device initialization routines: put/get, init/exit
  923. ****************************************************************************/
  924. /*
  925. * i7core_put_devices 'put' all the devices that we have
  926. * reserved via 'get'
  927. */
  928. static void i7core_put_devices(struct i7core_dev *i7core_dev)
  929. {
  930. int i;
  931. debugf0(__FILE__ ": %s()\n", __func__);
  932. for (i = 0; i < N_DEVS; i++) {
  933. struct pci_dev *pdev = i7core_dev->pdev[i];
  934. if (!pdev)
  935. continue;
  936. debugf0("Removing dev %02x:%02x.%d\n",
  937. pdev->bus->number,
  938. PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
  939. pci_dev_put(pdev);
  940. }
  941. kfree(i7core_dev->pdev);
  942. list_del(&i7core_dev->list);
  943. kfree(i7core_dev);
  944. }
  945. static void i7core_put_all_devices(void)
  946. {
  947. struct i7core_dev *i7core_dev, *tmp;
  948. list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list)
  949. i7core_put_devices(i7core_dev);
  950. }
  951. static void i7core_xeon_pci_fixup(void)
  952. {
  953. struct pci_dev *pdev = NULL;
  954. int i;
  955. /*
  956. * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core pci buses
  957. * aren't announced by acpi. So, we need to use a legacy scan probing
  958. * to detect them
  959. */
  960. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  961. pci_dev_descr[0].dev_id, NULL);
  962. if (unlikely(!pdev)) {
  963. for (i = 0; i < MAX_SOCKET_BUSES; i++)
  964. pcibios_scan_specific_bus(255-i);
  965. }
  966. }
  967. /*
  968. * i7core_get_devices Find and perform 'get' operation on the MCH's
  969. * device/functions we want to reference for this driver
  970. *
  971. * Need to 'get' device 16 func 1 and func 2
  972. */
  973. int i7core_get_onedevice(struct pci_dev **prev, int devno)
  974. {
  975. struct i7core_dev *i7core_dev;
  976. struct pci_dev *pdev = NULL;
  977. u8 bus = 0;
  978. u8 socket = 0;
  979. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  980. pci_dev_descr[devno].dev_id, *prev);
  981. /*
  982. * On Xeon 55xx, the Intel Quckpath Arch Generic Non-core regs
  983. * is at addr 8086:2c40, instead of 8086:2c41. So, we need
  984. * to probe for the alternate address in case of failure
  985. */
  986. if (pci_dev_descr[devno].dev_id == PCI_DEVICE_ID_INTEL_I7_NOCORE && !pdev)
  987. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  988. PCI_DEVICE_ID_INTEL_I7_NOCORE_ALT, *prev);
  989. if (!pdev) {
  990. if (*prev) {
  991. *prev = pdev;
  992. return 0;
  993. }
  994. /*
  995. * Dev 3 function 2 only exists on chips with RDIMMs
  996. * so, it is ok to not found it
  997. */
  998. if ((pci_dev_descr[devno].dev == 3) && (pci_dev_descr[devno].func == 2)) {
  999. *prev = pdev;
  1000. return 0;
  1001. }
  1002. i7core_printk(KERN_ERR,
  1003. "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
  1004. pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
  1005. PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
  1006. /* End of list, leave */
  1007. return -ENODEV;
  1008. }
  1009. bus = pdev->bus->number;
  1010. if (bus == 0x3f)
  1011. socket = 0;
  1012. else
  1013. socket = 255 - bus;
  1014. i7core_dev = get_i7core_dev(socket);
  1015. if (!i7core_dev) {
  1016. i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
  1017. if (!i7core_dev)
  1018. return -ENOMEM;
  1019. i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * N_DEVS,
  1020. GFP_KERNEL);
  1021. if (!i7core_dev->pdev)
  1022. return -ENOMEM;
  1023. i7core_dev->socket = socket;
  1024. list_add_tail(&i7core_dev->list, &i7core_edac_list);
  1025. }
  1026. if (i7core_dev->pdev[devno]) {
  1027. i7core_printk(KERN_ERR,
  1028. "Duplicated device for "
  1029. "dev %02x:%02x.%d PCI ID %04x:%04x\n",
  1030. bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
  1031. PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
  1032. pci_dev_put(pdev);
  1033. return -ENODEV;
  1034. }
  1035. i7core_dev->pdev[devno] = pdev;
  1036. /* Sanity check */
  1037. if (unlikely(PCI_SLOT(pdev->devfn) != pci_dev_descr[devno].dev ||
  1038. PCI_FUNC(pdev->devfn) != pci_dev_descr[devno].func)) {
  1039. i7core_printk(KERN_ERR,
  1040. "Device PCI ID %04x:%04x "
  1041. "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
  1042. PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id,
  1043. bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
  1044. bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func);
  1045. return -ENODEV;
  1046. }
  1047. /* Be sure that the device is enabled */
  1048. if (unlikely(pci_enable_device(pdev) < 0)) {
  1049. i7core_printk(KERN_ERR,
  1050. "Couldn't enable "
  1051. "dev %02x:%02x.%d PCI ID %04x:%04x\n",
  1052. bus, pci_dev_descr[devno].dev, pci_dev_descr[devno].func,
  1053. PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
  1054. return -ENODEV;
  1055. }
  1056. debugf0("Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
  1057. socket, bus, pci_dev_descr[devno].dev,
  1058. pci_dev_descr[devno].func,
  1059. PCI_VENDOR_ID_INTEL, pci_dev_descr[devno].dev_id);
  1060. *prev = pdev;
  1061. return 0;
  1062. }
  1063. static int i7core_get_devices(void)
  1064. {
  1065. int i;
  1066. struct pci_dev *pdev = NULL;
  1067. for (i = 0; i < N_DEVS; i++) {
  1068. pdev = NULL;
  1069. do {
  1070. if (i7core_get_onedevice(&pdev, i) < 0) {
  1071. i7core_put_all_devices();
  1072. return -ENODEV;
  1073. }
  1074. } while (pdev);
  1075. }
  1076. return 0;
  1077. }
  1078. static int mci_bind_devs(struct mem_ctl_info *mci,
  1079. struct i7core_dev *i7core_dev)
  1080. {
  1081. struct i7core_pvt *pvt = mci->pvt_info;
  1082. struct pci_dev *pdev;
  1083. int i, func, slot;
  1084. /* Associates i7core_dev and mci for future usage */
  1085. pvt->i7core_dev = i7core_dev;
  1086. i7core_dev->mci = mci;
  1087. pvt->is_registered = 0;
  1088. for (i = 0; i < N_DEVS; i++) {
  1089. pdev = i7core_dev->pdev[i];
  1090. if (!pdev)
  1091. continue;
  1092. func = PCI_FUNC(pdev->devfn);
  1093. slot = PCI_SLOT(pdev->devfn);
  1094. if (slot == 3) {
  1095. if (unlikely(func > MAX_MCR_FUNC))
  1096. goto error;
  1097. pvt->pci_mcr[func] = pdev;
  1098. } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
  1099. if (unlikely(func > MAX_CHAN_FUNC))
  1100. goto error;
  1101. pvt->pci_ch[slot - 4][func] = pdev;
  1102. } else if (!slot && !func)
  1103. pvt->pci_noncore = pdev;
  1104. else
  1105. goto error;
  1106. debugf0("Associated fn %d.%d, dev = %p, socket %d\n",
  1107. PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
  1108. pdev, i7core_dev->socket);
  1109. if (PCI_SLOT(pdev->devfn) == 3 &&
  1110. PCI_FUNC(pdev->devfn) == 2)
  1111. pvt->is_registered = 1;
  1112. }
  1113. /*
  1114. * Add extra nodes to count errors on udimm
  1115. * For registered memory, this is not needed, since the counters
  1116. * are already displayed at the standard locations
  1117. */
  1118. if (!pvt->is_registered)
  1119. i7core_sysfs_attrs[ARRAY_SIZE(i7core_sysfs_attrs)-2].grp =
  1120. &i7core_udimm_counters;
  1121. return 0;
  1122. error:
  1123. i7core_printk(KERN_ERR, "Device %d, function %d "
  1124. "is out of the expected range\n",
  1125. slot, func);
  1126. return -EINVAL;
  1127. }
  1128. /****************************************************************************
  1129. Error check routines
  1130. ****************************************************************************/
  1131. static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
  1132. int chan, int dimm, int add)
  1133. {
  1134. char *msg;
  1135. struct i7core_pvt *pvt = mci->pvt_info;
  1136. int row = pvt->csrow_map[chan][dimm], i;
  1137. for (i = 0; i < add; i++) {
  1138. msg = kasprintf(GFP_KERNEL, "Corrected error "
  1139. "(Socket=%d channel=%d dimm=%d)",
  1140. pvt->i7core_dev->socket, chan, dimm);
  1141. edac_mc_handle_fbd_ce(mci, row, 0, msg);
  1142. kfree (msg);
  1143. }
  1144. }
  1145. static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
  1146. int chan, int new0, int new1, int new2)
  1147. {
  1148. struct i7core_pvt *pvt = mci->pvt_info;
  1149. int add0 = 0, add1 = 0, add2 = 0;
  1150. /* Updates CE counters if it is not the first time here */
  1151. if (pvt->ce_count_available) {
  1152. /* Updates CE counters */
  1153. add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
  1154. add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
  1155. add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
  1156. if (add2 < 0)
  1157. add2 += 0x7fff;
  1158. pvt->rdimm_ce_count[chan][2] += add2;
  1159. if (add1 < 0)
  1160. add1 += 0x7fff;
  1161. pvt->rdimm_ce_count[chan][1] += add1;
  1162. if (add0 < 0)
  1163. add0 += 0x7fff;
  1164. pvt->rdimm_ce_count[chan][0] += add0;
  1165. } else
  1166. pvt->ce_count_available = 1;
  1167. /* Store the new values */
  1168. pvt->rdimm_last_ce_count[chan][2] = new2;
  1169. pvt->rdimm_last_ce_count[chan][1] = new1;
  1170. pvt->rdimm_last_ce_count[chan][0] = new0;
  1171. /*updated the edac core */
  1172. if (add0 != 0)
  1173. i7core_rdimm_update_csrow(mci, chan, 0, add0);
  1174. if (add1 != 0)
  1175. i7core_rdimm_update_csrow(mci, chan, 1, add1);
  1176. if (add2 != 0)
  1177. i7core_rdimm_update_csrow(mci, chan, 2, add2);
  1178. }
  1179. static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
  1180. {
  1181. struct i7core_pvt *pvt = mci->pvt_info;
  1182. u32 rcv[3][2];
  1183. int i, new0, new1, new2;
  1184. /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
  1185. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
  1186. &rcv[0][0]);
  1187. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
  1188. &rcv[0][1]);
  1189. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
  1190. &rcv[1][0]);
  1191. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
  1192. &rcv[1][1]);
  1193. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
  1194. &rcv[2][0]);
  1195. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
  1196. &rcv[2][1]);
  1197. for (i = 0 ; i < 3; i++) {
  1198. debugf3("MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
  1199. (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
  1200. /*if the channel has 3 dimms*/
  1201. if (pvt->channel[i].dimms > 2) {
  1202. new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
  1203. new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
  1204. new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
  1205. } else {
  1206. new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
  1207. DIMM_BOT_COR_ERR(rcv[i][0]);
  1208. new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
  1209. DIMM_BOT_COR_ERR(rcv[i][1]);
  1210. new2 = 0;
  1211. }
  1212. i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
  1213. }
  1214. }
  1215. /* This function is based on the device 3 function 4 registers as described on:
  1216. * Intel Xeon Processor 5500 Series Datasheet Volume 2
  1217. * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
  1218. * also available at:
  1219. * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  1220. */
  1221. static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
  1222. {
  1223. struct i7core_pvt *pvt = mci->pvt_info;
  1224. u32 rcv1, rcv0;
  1225. int new0, new1, new2;
  1226. if (!pvt->pci_mcr[4]) {
  1227. debugf0("%s MCR registers not found\n", __func__);
  1228. return;
  1229. }
  1230. /* Corrected test errors */
  1231. pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
  1232. pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
  1233. /* Store the new values */
  1234. new2 = DIMM2_COR_ERR(rcv1);
  1235. new1 = DIMM1_COR_ERR(rcv0);
  1236. new0 = DIMM0_COR_ERR(rcv0);
  1237. /* Updates CE counters if it is not the first time here */
  1238. if (pvt->ce_count_available) {
  1239. /* Updates CE counters */
  1240. int add0, add1, add2;
  1241. add2 = new2 - pvt->udimm_last_ce_count[2];
  1242. add1 = new1 - pvt->udimm_last_ce_count[1];
  1243. add0 = new0 - pvt->udimm_last_ce_count[0];
  1244. if (add2 < 0)
  1245. add2 += 0x7fff;
  1246. pvt->udimm_ce_count[2] += add2;
  1247. if (add1 < 0)
  1248. add1 += 0x7fff;
  1249. pvt->udimm_ce_count[1] += add1;
  1250. if (add0 < 0)
  1251. add0 += 0x7fff;
  1252. pvt->udimm_ce_count[0] += add0;
  1253. if (add0 | add1 | add2)
  1254. i7core_printk(KERN_ERR, "New Corrected error(s): "
  1255. "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
  1256. add0, add1, add2);
  1257. } else
  1258. pvt->ce_count_available = 1;
  1259. /* Store the new values */
  1260. pvt->udimm_last_ce_count[2] = new2;
  1261. pvt->udimm_last_ce_count[1] = new1;
  1262. pvt->udimm_last_ce_count[0] = new0;
  1263. }
  1264. /*
  1265. * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
  1266. * Architectures Software Developer’s Manual Volume 3B.
  1267. * Nehalem are defined as family 0x06, model 0x1a
  1268. *
  1269. * The MCA registers used here are the following ones:
  1270. * struct mce field MCA Register
  1271. * m->status MSR_IA32_MC8_STATUS
  1272. * m->addr MSR_IA32_MC8_ADDR
  1273. * m->misc MSR_IA32_MC8_MISC
  1274. * In the case of Nehalem, the error information is masked at .status and .misc
  1275. * fields
  1276. */
  1277. static void i7core_mce_output_error(struct mem_ctl_info *mci,
  1278. struct mce *m)
  1279. {
  1280. struct i7core_pvt *pvt = mci->pvt_info;
  1281. char *type, *optype, *err, *msg;
  1282. unsigned long error = m->status & 0x1ff0000l;
  1283. u32 optypenum = (m->status >> 4) & 0x07;
  1284. u32 core_err_cnt = (m->status >> 38) && 0x7fff;
  1285. u32 dimm = (m->misc >> 16) & 0x3;
  1286. u32 channel = (m->misc >> 18) & 0x3;
  1287. u32 syndrome = m->misc >> 32;
  1288. u32 errnum = find_first_bit(&error, 32);
  1289. int csrow;
  1290. if (m->mcgstatus & 1)
  1291. type = "FATAL";
  1292. else
  1293. type = "NON_FATAL";
  1294. switch (optypenum) {
  1295. case 0:
  1296. optype = "generic undef request";
  1297. break;
  1298. case 1:
  1299. optype = "read error";
  1300. break;
  1301. case 2:
  1302. optype = "write error";
  1303. break;
  1304. case 3:
  1305. optype = "addr/cmd error";
  1306. break;
  1307. case 4:
  1308. optype = "scrubbing error";
  1309. break;
  1310. default:
  1311. optype = "reserved";
  1312. break;
  1313. }
  1314. switch (errnum) {
  1315. case 16:
  1316. err = "read ECC error";
  1317. break;
  1318. case 17:
  1319. err = "RAS ECC error";
  1320. break;
  1321. case 18:
  1322. err = "write parity error";
  1323. break;
  1324. case 19:
  1325. err = "redundacy loss";
  1326. break;
  1327. case 20:
  1328. err = "reserved";
  1329. break;
  1330. case 21:
  1331. err = "memory range error";
  1332. break;
  1333. case 22:
  1334. err = "RTID out of range";
  1335. break;
  1336. case 23:
  1337. err = "address parity error";
  1338. break;
  1339. case 24:
  1340. err = "byte enable parity error";
  1341. break;
  1342. default:
  1343. err = "unknown";
  1344. }
  1345. /* FIXME: should convert addr into bank and rank information */
  1346. msg = kasprintf(GFP_ATOMIC,
  1347. "%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
  1348. "syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
  1349. type, (long long) m->addr, m->cpu, dimm, channel,
  1350. syndrome, core_err_cnt, (long long)m->status,
  1351. (long long)m->misc, optype, err);
  1352. debugf0("%s", msg);
  1353. csrow = pvt->csrow_map[channel][dimm];
  1354. /* Call the helper to output message */
  1355. if (m->mcgstatus & 1)
  1356. edac_mc_handle_fbd_ue(mci, csrow, 0,
  1357. 0 /* FIXME: should be channel here */, msg);
  1358. else if (!pvt->is_registered)
  1359. edac_mc_handle_fbd_ce(mci, csrow,
  1360. 0 /* FIXME: should be channel here */, msg);
  1361. kfree(msg);
  1362. }
  1363. /*
  1364. * i7core_check_error Retrieve and process errors reported by the
  1365. * hardware. Called by the Core module.
  1366. */
  1367. static void i7core_check_error(struct mem_ctl_info *mci)
  1368. {
  1369. struct i7core_pvt *pvt = mci->pvt_info;
  1370. int i;
  1371. unsigned count = 0;
  1372. struct mce *m;
  1373. /*
  1374. * MCE first step: Copy all mce errors into a temporary buffer
  1375. * We use a double buffering here, to reduce the risk of
  1376. * loosing an error.
  1377. */
  1378. smp_rmb();
  1379. count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
  1380. % MCE_LOG_LEN;
  1381. if (!count)
  1382. return;
  1383. m = pvt->mce_outentry;
  1384. if (pvt->mce_in + count > MCE_LOG_LEN) {
  1385. unsigned l = MCE_LOG_LEN - pvt->mce_in;
  1386. memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
  1387. smp_wmb();
  1388. pvt->mce_in = 0;
  1389. count -= l;
  1390. m += l;
  1391. }
  1392. memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
  1393. smp_wmb();
  1394. pvt->mce_in += count;
  1395. smp_rmb();
  1396. if (pvt->mce_overrun) {
  1397. i7core_printk(KERN_ERR, "Lost %d memory errors\n",
  1398. pvt->mce_overrun);
  1399. smp_wmb();
  1400. pvt->mce_overrun = 0;
  1401. }
  1402. /*
  1403. * MCE second step: parse errors and display
  1404. */
  1405. for (i = 0; i < count; i++)
  1406. i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
  1407. /*
  1408. * Now, let's increment CE error counts
  1409. */
  1410. if (!pvt->is_registered)
  1411. i7core_udimm_check_mc_ecc_err(mci);
  1412. else
  1413. i7core_rdimm_check_mc_ecc_err(mci);
  1414. }
  1415. /*
  1416. * i7core_mce_check_error Replicates mcelog routine to get errors
  1417. * This routine simply queues mcelog errors, and
  1418. * return. The error itself should be handled later
  1419. * by i7core_check_error.
  1420. * WARNING: As this routine should be called at NMI time, extra care should
  1421. * be taken to avoid deadlocks, and to be as fast as possible.
  1422. */
  1423. static int i7core_mce_check_error(void *priv, struct mce *mce)
  1424. {
  1425. struct mem_ctl_info *mci = priv;
  1426. struct i7core_pvt *pvt = mci->pvt_info;
  1427. /*
  1428. * Just let mcelog handle it if the error is
  1429. * outside the memory controller
  1430. */
  1431. if (((mce->status & 0xffff) >> 7) != 1)
  1432. return 0;
  1433. /* Bank 8 registers are the only ones that we know how to handle */
  1434. if (mce->bank != 8)
  1435. return 0;
  1436. /* Only handle if it is the right mc controller */
  1437. if (cpu_data(mce->cpu).phys_proc_id != pvt->i7core_dev->socket)
  1438. return 0;
  1439. smp_rmb();
  1440. if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
  1441. smp_wmb();
  1442. pvt->mce_overrun++;
  1443. return 0;
  1444. }
  1445. /* Copy memory error at the ringbuffer */
  1446. memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
  1447. smp_wmb();
  1448. pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
  1449. /* Handle fatal errors immediately */
  1450. if (mce->mcgstatus & 1)
  1451. i7core_check_error(mci);
  1452. /* Advice mcelog that the error were handled */
  1453. return 1;
  1454. }
  1455. static int i7core_register_mci(struct i7core_dev *i7core_dev,
  1456. int num_channels, int num_csrows)
  1457. {
  1458. struct mem_ctl_info *mci;
  1459. struct i7core_pvt *pvt;
  1460. int csrow = 0;
  1461. int rc;
  1462. /* allocate a new MC control structure */
  1463. mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels,
  1464. i7core_dev->socket);
  1465. if (unlikely(!mci))
  1466. return -ENOMEM;
  1467. debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
  1468. /* record ptr to the generic device */
  1469. mci->dev = &i7core_dev->pdev[0]->dev;
  1470. pvt = mci->pvt_info;
  1471. memset(pvt, 0, sizeof(*pvt));
  1472. /*
  1473. * FIXME: how to handle RDDR3 at MCI level? It is possible to have
  1474. * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
  1475. * memory channels
  1476. */
  1477. mci->mtype_cap = MEM_FLAG_DDR3;
  1478. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  1479. mci->edac_cap = EDAC_FLAG_NONE;
  1480. mci->mod_name = "i7core_edac.c";
  1481. mci->mod_ver = I7CORE_REVISION;
  1482. mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
  1483. i7core_dev->socket);
  1484. mci->dev_name = pci_name(i7core_dev->pdev[0]);
  1485. mci->ctl_page_to_phys = NULL;
  1486. mci->mc_driver_sysfs_attributes = i7core_sysfs_attrs;
  1487. /* Set the function pointer to an actual operation function */
  1488. mci->edac_check = i7core_check_error;
  1489. /* Store pci devices at mci for faster access */
  1490. rc = mci_bind_devs(mci, i7core_dev);
  1491. if (unlikely(rc < 0))
  1492. goto fail;
  1493. /* Get dimm basic config */
  1494. get_dimm_config(mci, &csrow);
  1495. /* add this new MC control structure to EDAC's list of MCs */
  1496. if (unlikely(edac_mc_add_mc(mci))) {
  1497. debugf0("MC: " __FILE__
  1498. ": %s(): failed edac_mc_add_mc()\n", __func__);
  1499. /* FIXME: perhaps some code should go here that disables error
  1500. * reporting if we just enabled it
  1501. */
  1502. rc = -EINVAL;
  1503. goto fail;
  1504. }
  1505. /* allocating generic PCI control info */
  1506. i7core_pci = edac_pci_create_generic_ctl(&i7core_dev->pdev[0]->dev,
  1507. EDAC_MOD_STR);
  1508. if (unlikely(!i7core_pci)) {
  1509. printk(KERN_WARNING
  1510. "%s(): Unable to create PCI control\n",
  1511. __func__);
  1512. printk(KERN_WARNING
  1513. "%s(): PCI error report via EDAC not setup\n",
  1514. __func__);
  1515. }
  1516. /* Default error mask is any memory */
  1517. pvt->inject.channel = 0;
  1518. pvt->inject.dimm = -1;
  1519. pvt->inject.rank = -1;
  1520. pvt->inject.bank = -1;
  1521. pvt->inject.page = -1;
  1522. pvt->inject.col = -1;
  1523. /* Registers on edac_mce in order to receive memory errors */
  1524. pvt->edac_mce.priv = mci;
  1525. pvt->edac_mce.check_error = i7core_mce_check_error;
  1526. rc = edac_mce_register(&pvt->edac_mce);
  1527. if (unlikely(rc < 0)) {
  1528. debugf0("MC: " __FILE__
  1529. ": %s(): failed edac_mce_register()\n", __func__);
  1530. }
  1531. fail:
  1532. edac_mc_free(mci);
  1533. return rc;
  1534. }
  1535. /*
  1536. * i7core_probe Probe for ONE instance of device to see if it is
  1537. * present.
  1538. * return:
  1539. * 0 for FOUND a device
  1540. * < 0 for error code
  1541. */
  1542. static int __devinit i7core_probe(struct pci_dev *pdev,
  1543. const struct pci_device_id *id)
  1544. {
  1545. int dev_idx = id->driver_data;
  1546. int rc;
  1547. struct i7core_dev *i7core_dev;
  1548. /*
  1549. * All memory controllers are allocated at the first pass.
  1550. */
  1551. if (unlikely(dev_idx >= 1))
  1552. return -EINVAL;
  1553. /* get the pci devices we want to reserve for our use */
  1554. mutex_lock(&i7core_edac_lock);
  1555. rc = i7core_get_devices();
  1556. if (unlikely(rc < 0))
  1557. goto fail0;
  1558. list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
  1559. int channels;
  1560. int csrows;
  1561. /* Check the number of active and not disabled channels */
  1562. rc = i7core_get_active_channels(i7core_dev->socket,
  1563. &channels, &csrows);
  1564. if (unlikely(rc < 0))
  1565. goto fail1;
  1566. rc = i7core_register_mci(i7core_dev, channels, csrows);
  1567. if (unlikely(rc < 0))
  1568. goto fail1;
  1569. }
  1570. i7core_printk(KERN_INFO, "Driver loaded.\n");
  1571. mutex_unlock(&i7core_edac_lock);
  1572. return 0;
  1573. fail1:
  1574. i7core_put_all_devices();
  1575. fail0:
  1576. mutex_unlock(&i7core_edac_lock);
  1577. return rc;
  1578. }
  1579. /*
  1580. * i7core_remove destructor for one instance of device
  1581. *
  1582. */
  1583. static void __devexit i7core_remove(struct pci_dev *pdev)
  1584. {
  1585. struct mem_ctl_info *mci;
  1586. struct i7core_dev *i7core_dev, *tmp;
  1587. debugf0(__FILE__ ": %s()\n", __func__);
  1588. if (i7core_pci)
  1589. edac_pci_release_generic_ctl(i7core_pci);
  1590. /*
  1591. * we have a trouble here: pdev value for removal will be wrong, since
  1592. * it will point to the X58 register used to detect that the machine
  1593. * is a Nehalem or upper design. However, due to the way several PCI
  1594. * devices are grouped together to provide MC functionality, we need
  1595. * to use a different method for releasing the devices
  1596. */
  1597. mutex_lock(&i7core_edac_lock);
  1598. list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
  1599. mci = edac_mc_del_mc(&i7core_dev->pdev[0]->dev);
  1600. if (mci) {
  1601. struct i7core_pvt *pvt = mci->pvt_info;
  1602. i7core_dev = pvt->i7core_dev;
  1603. edac_mce_unregister(&pvt->edac_mce);
  1604. kfree(mci->ctl_name);
  1605. edac_mc_free(mci);
  1606. i7core_put_devices(i7core_dev);
  1607. } else {
  1608. i7core_printk(KERN_ERR,
  1609. "Couldn't find mci for socket %d\n",
  1610. i7core_dev->socket);
  1611. }
  1612. }
  1613. mutex_unlock(&i7core_edac_lock);
  1614. }
  1615. MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
  1616. /*
  1617. * i7core_driver pci_driver structure for this module
  1618. *
  1619. */
  1620. static struct pci_driver i7core_driver = {
  1621. .name = "i7core_edac",
  1622. .probe = i7core_probe,
  1623. .remove = __devexit_p(i7core_remove),
  1624. .id_table = i7core_pci_tbl,
  1625. };
  1626. /*
  1627. * i7core_init Module entry function
  1628. * Try to initialize this module for its devices
  1629. */
  1630. static int __init i7core_init(void)
  1631. {
  1632. int pci_rc;
  1633. debugf2("MC: " __FILE__ ": %s()\n", __func__);
  1634. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  1635. opstate_init();
  1636. i7core_xeon_pci_fixup();
  1637. pci_rc = pci_register_driver(&i7core_driver);
  1638. if (pci_rc >= 0)
  1639. return 0;
  1640. i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
  1641. pci_rc);
  1642. return pci_rc;
  1643. }
  1644. /*
  1645. * i7core_exit() Module exit function
  1646. * Unregister the driver
  1647. */
  1648. static void __exit i7core_exit(void)
  1649. {
  1650. debugf2("MC: " __FILE__ ": %s()\n", __func__);
  1651. pci_unregister_driver(&i7core_driver);
  1652. }
  1653. module_init(i7core_init);
  1654. module_exit(i7core_exit);
  1655. MODULE_LICENSE("GPL");
  1656. MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
  1657. MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
  1658. MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
  1659. I7CORE_REVISION);
  1660. module_param(edac_op_state, int, 0444);
  1661. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");