tg3.c 440 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559756075617562756375647565756675677568756975707571757275737574757575767577757875797580758175827583758475857586758775887589759075917592759375947595759675977598759976007601760276037604760576067607760876097610761176127613761476157616761776187619762076217622762376247625762676277628762976307631763276337634763576367637763876397640764176427643764476457646764776487649765076517652765376547655765676577658765976607661766276637664766576667667766876697670767176727673767476757676767776787679768076817682768376847685768676877688768976907691769276937694769576967697769876997700770177027703770477057706770777087709771077117712771377147715771677177718771977207721772277237724772577267727772877297730773177327733773477357736773777387739774077417742774377447745774677477748774977507751775277537754775577567757775877597760776177627763776477657766776777687769777077717772777377747775777677777778777977807781778277837784778577867787778877897790779177927793779477957796779777987799780078017802780378047805780678077808780978107811781278137814781578167817781878197820782178227823782478257826782778287829783078317832783378347835783678377838783978407841784278437844784578467847784878497850785178527853785478557856785778587859786078617862786378647865786678677868786978707871787278737874787578767877787878797880788178827883788478857886788778887889789078917892789378947895789678977898789979007901790279037904790579067907790879097910791179127913791479157916791779187919792079217922792379247925792679277928792979307931793279337934793579367937793879397940794179427943794479457946794779487949795079517952795379547955795679577958795979607961796279637964796579667967796879697970797179727973797479757976797779787979798079817982798379847985798679877988798979907991799279937994799579967997799879998000800180028003800480058006800780088009801080118012801380148015801680178018801980208021802280238024802580268027802880298030803180328033803480358036803780388039804080418042804380448045804680478048804980508051805280538054805580568057805880598060806180628063806480658066806780688069807080718072807380748075807680778078807980808081808280838084808580868087808880898090809180928093809480958096809780988099810081018102810381048105810681078108810981108111811281138114811581168117811881198120812181228123812481258126812781288129813081318132813381348135813681378138813981408141814281438144814581468147814881498150815181528153815481558156815781588159816081618162816381648165816681678168816981708171817281738174817581768177817881798180818181828183818481858186818781888189819081918192819381948195819681978198819982008201820282038204820582068207820882098210821182128213821482158216821782188219822082218222822382248225822682278228822982308231823282338234823582368237823882398240824182428243824482458246824782488249825082518252825382548255825682578258825982608261826282638264826582668267826882698270827182728273827482758276827782788279828082818282828382848285828682878288828982908291829282938294829582968297829882998300830183028303830483058306830783088309831083118312831383148315831683178318831983208321832283238324832583268327832883298330833183328333833483358336833783388339834083418342834383448345834683478348834983508351835283538354835583568357835883598360836183628363836483658366836783688369837083718372837383748375837683778378837983808381838283838384838583868387838883898390839183928393839483958396839783988399840084018402840384048405840684078408840984108411841284138414841584168417841884198420842184228423842484258426842784288429843084318432843384348435843684378438843984408441844284438444844584468447844884498450845184528453845484558456845784588459846084618462846384648465846684678468846984708471847284738474847584768477847884798480848184828483848484858486848784888489849084918492849384948495849684978498849985008501850285038504850585068507850885098510851185128513851485158516851785188519852085218522852385248525852685278528852985308531853285338534853585368537853885398540854185428543854485458546854785488549855085518552855385548555855685578558855985608561856285638564856585668567856885698570857185728573857485758576857785788579858085818582858385848585858685878588858985908591859285938594859585968597859885998600860186028603860486058606860786088609861086118612861386148615861686178618861986208621862286238624862586268627862886298630863186328633863486358636863786388639864086418642864386448645864686478648864986508651865286538654865586568657865886598660866186628663866486658666866786688669867086718672867386748675867686778678867986808681868286838684868586868687868886898690869186928693869486958696869786988699870087018702870387048705870687078708870987108711871287138714871587168717871887198720872187228723872487258726872787288729873087318732873387348735873687378738873987408741874287438744874587468747874887498750875187528753875487558756875787588759876087618762876387648765876687678768876987708771877287738774877587768777877887798780878187828783878487858786878787888789879087918792879387948795879687978798879988008801880288038804880588068807880888098810881188128813881488158816881788188819882088218822882388248825882688278828882988308831883288338834883588368837883888398840884188428843884488458846884788488849885088518852885388548855885688578858885988608861886288638864886588668867886888698870887188728873887488758876887788788879888088818882888388848885888688878888888988908891889288938894889588968897889888998900890189028903890489058906890789088909891089118912891389148915891689178918891989208921892289238924892589268927892889298930893189328933893489358936893789388939894089418942894389448945894689478948894989508951895289538954895589568957895889598960896189628963896489658966896789688969897089718972897389748975897689778978897989808981898289838984898589868987898889898990899189928993899489958996899789988999900090019002900390049005900690079008900990109011901290139014901590169017901890199020902190229023902490259026902790289029903090319032903390349035903690379038903990409041904290439044904590469047904890499050905190529053905490559056905790589059906090619062906390649065906690679068906990709071907290739074907590769077907890799080908190829083908490859086908790889089909090919092909390949095909690979098909991009101910291039104910591069107910891099110911191129113911491159116911791189119912091219122912391249125912691279128912991309131913291339134913591369137913891399140914191429143914491459146914791489149915091519152915391549155915691579158915991609161916291639164916591669167916891699170917191729173917491759176917791789179918091819182918391849185918691879188918991909191919291939194919591969197919891999200920192029203920492059206920792089209921092119212921392149215921692179218921992209221922292239224922592269227922892299230923192329233923492359236923792389239924092419242924392449245924692479248924992509251925292539254925592569257925892599260926192629263926492659266926792689269927092719272927392749275927692779278927992809281928292839284928592869287928892899290929192929293929492959296929792989299930093019302930393049305930693079308930993109311931293139314931593169317931893199320932193229323932493259326932793289329933093319332933393349335933693379338933993409341934293439344934593469347934893499350935193529353935493559356935793589359936093619362936393649365936693679368936993709371937293739374937593769377937893799380938193829383938493859386938793889389939093919392939393949395939693979398939994009401940294039404940594069407940894099410941194129413941494159416941794189419942094219422942394249425942694279428942994309431943294339434943594369437943894399440944194429443944494459446944794489449945094519452945394549455945694579458945994609461946294639464946594669467946894699470947194729473947494759476947794789479948094819482948394849485948694879488948994909491949294939494949594969497949894999500950195029503950495059506950795089509951095119512951395149515951695179518951995209521952295239524952595269527952895299530953195329533953495359536953795389539954095419542954395449545954695479548954995509551955295539554955595569557955895599560956195629563956495659566956795689569957095719572957395749575957695779578957995809581958295839584958595869587958895899590959195929593959495959596959795989599960096019602960396049605960696079608960996109611961296139614961596169617961896199620962196229623962496259626962796289629963096319632963396349635963696379638963996409641964296439644964596469647964896499650965196529653965496559656965796589659966096619662966396649665966696679668966996709671967296739674967596769677967896799680968196829683968496859686968796889689969096919692969396949695969696979698969997009701970297039704970597069707970897099710971197129713971497159716971797189719972097219722972397249725972697279728972997309731973297339734973597369737973897399740974197429743974497459746974797489749975097519752975397549755975697579758975997609761976297639764976597669767976897699770977197729773977497759776977797789779978097819782978397849785978697879788978997909791979297939794979597969797979897999800980198029803980498059806980798089809981098119812981398149815981698179818981998209821982298239824982598269827982898299830983198329833983498359836983798389839984098419842984398449845984698479848984998509851985298539854985598569857985898599860986198629863986498659866986798689869987098719872987398749875987698779878987998809881988298839884988598869887988898899890989198929893989498959896989798989899990099019902990399049905990699079908990999109911991299139914991599169917991899199920992199229923992499259926992799289929993099319932993399349935993699379938993999409941994299439944994599469947994899499950995199529953995499559956995799589959996099619962996399649965996699679968996999709971997299739974997599769977997899799980998199829983998499859986998799889989999099919992999399949995999699979998999910000100011000210003100041000510006100071000810009100101001110012100131001410015100161001710018100191002010021100221002310024100251002610027100281002910030100311003210033100341003510036100371003810039100401004110042100431004410045100461004710048100491005010051100521005310054100551005610057100581005910060100611006210063100641006510066100671006810069100701007110072100731007410075100761007710078100791008010081100821008310084100851008610087100881008910090100911009210093100941009510096100971009810099101001010110102101031010410105101061010710108101091011010111101121011310114101151011610117101181011910120101211012210123101241012510126101271012810129101301013110132101331013410135101361013710138101391014010141101421014310144101451014610147101481014910150101511015210153101541015510156101571015810159101601016110162101631016410165101661016710168101691017010171101721017310174101751017610177101781017910180101811018210183101841018510186101871018810189101901019110192101931019410195101961019710198101991020010201102021020310204102051020610207102081020910210102111021210213102141021510216102171021810219102201022110222102231022410225102261022710228102291023010231102321023310234102351023610237102381023910240102411024210243102441024510246102471024810249102501025110252102531025410255102561025710258102591026010261102621026310264102651026610267102681026910270102711027210273102741027510276102771027810279102801028110282102831028410285102861028710288102891029010291102921029310294102951029610297102981029910300103011030210303103041030510306103071030810309103101031110312103131031410315103161031710318103191032010321103221032310324103251032610327103281032910330103311033210333103341033510336103371033810339103401034110342103431034410345103461034710348103491035010351103521035310354103551035610357103581035910360103611036210363103641036510366103671036810369103701037110372103731037410375103761037710378103791038010381103821038310384103851038610387103881038910390103911039210393103941039510396103971039810399104001040110402104031040410405104061040710408104091041010411104121041310414104151041610417104181041910420104211042210423104241042510426104271042810429104301043110432104331043410435104361043710438104391044010441104421044310444104451044610447104481044910450104511045210453104541045510456104571045810459104601046110462104631046410465104661046710468104691047010471104721047310474104751047610477104781047910480104811048210483104841048510486104871048810489104901049110492104931049410495104961049710498104991050010501105021050310504105051050610507105081050910510105111051210513105141051510516105171051810519105201052110522105231052410525105261052710528105291053010531105321053310534105351053610537105381053910540105411054210543105441054510546105471054810549105501055110552105531055410555105561055710558105591056010561105621056310564105651056610567105681056910570105711057210573105741057510576105771057810579105801058110582105831058410585105861058710588105891059010591105921059310594105951059610597105981059910600106011060210603106041060510606106071060810609106101061110612106131061410615106161061710618106191062010621106221062310624106251062610627106281062910630106311063210633106341063510636106371063810639106401064110642106431064410645106461064710648106491065010651106521065310654106551065610657106581065910660106611066210663106641066510666106671066810669106701067110672106731067410675106761067710678106791068010681106821068310684106851068610687106881068910690106911069210693106941069510696106971069810699107001070110702107031070410705107061070710708107091071010711107121071310714107151071610717107181071910720107211072210723107241072510726107271072810729107301073110732107331073410735107361073710738107391074010741107421074310744107451074610747107481074910750107511075210753107541075510756107571075810759107601076110762107631076410765107661076710768107691077010771107721077310774107751077610777107781077910780107811078210783107841078510786107871078810789107901079110792107931079410795107961079710798107991080010801108021080310804108051080610807108081080910810108111081210813108141081510816108171081810819108201082110822108231082410825108261082710828108291083010831108321083310834108351083610837108381083910840108411084210843108441084510846108471084810849108501085110852108531085410855108561085710858108591086010861108621086310864108651086610867108681086910870108711087210873108741087510876108771087810879108801088110882108831088410885108861088710888108891089010891108921089310894108951089610897108981089910900109011090210903109041090510906109071090810909109101091110912109131091410915109161091710918109191092010921109221092310924109251092610927109281092910930109311093210933109341093510936109371093810939109401094110942109431094410945109461094710948109491095010951109521095310954109551095610957109581095910960109611096210963109641096510966109671096810969109701097110972109731097410975109761097710978109791098010981109821098310984109851098610987109881098910990109911099210993109941099510996109971099810999110001100111002110031100411005110061100711008110091101011011110121101311014110151101611017110181101911020110211102211023110241102511026110271102811029110301103111032110331103411035110361103711038110391104011041110421104311044110451104611047110481104911050110511105211053110541105511056110571105811059110601106111062110631106411065110661106711068110691107011071110721107311074110751107611077110781107911080110811108211083110841108511086110871108811089110901109111092110931109411095110961109711098110991110011101111021110311104111051110611107111081110911110111111111211113111141111511116111171111811119111201112111122111231112411125111261112711128111291113011131111321113311134111351113611137111381113911140111411114211143111441114511146111471114811149111501115111152111531115411155111561115711158111591116011161111621116311164111651116611167111681116911170111711117211173111741117511176111771117811179111801118111182111831118411185111861118711188111891119011191111921119311194111951119611197111981119911200112011120211203112041120511206112071120811209112101121111212112131121411215112161121711218112191122011221112221122311224112251122611227112281122911230112311123211233112341123511236112371123811239112401124111242112431124411245112461124711248112491125011251112521125311254112551125611257112581125911260112611126211263112641126511266112671126811269112701127111272112731127411275112761127711278112791128011281112821128311284112851128611287112881128911290112911129211293112941129511296112971129811299113001130111302113031130411305113061130711308113091131011311113121131311314113151131611317113181131911320113211132211323113241132511326113271132811329113301133111332113331133411335113361133711338113391134011341113421134311344113451134611347113481134911350113511135211353113541135511356113571135811359113601136111362113631136411365113661136711368113691137011371113721137311374113751137611377113781137911380113811138211383113841138511386113871138811389113901139111392113931139411395113961139711398113991140011401114021140311404114051140611407114081140911410114111141211413114141141511416114171141811419114201142111422114231142411425114261142711428114291143011431114321143311434114351143611437114381143911440114411144211443114441144511446114471144811449114501145111452114531145411455114561145711458114591146011461114621146311464114651146611467114681146911470114711147211473114741147511476114771147811479114801148111482114831148411485114861148711488114891149011491114921149311494114951149611497114981149911500115011150211503115041150511506115071150811509115101151111512115131151411515115161151711518115191152011521115221152311524115251152611527115281152911530115311153211533115341153511536115371153811539115401154111542115431154411545115461154711548115491155011551115521155311554115551155611557115581155911560115611156211563115641156511566115671156811569115701157111572115731157411575115761157711578115791158011581115821158311584115851158611587115881158911590115911159211593115941159511596115971159811599116001160111602116031160411605116061160711608116091161011611116121161311614116151161611617116181161911620116211162211623116241162511626116271162811629116301163111632116331163411635116361163711638116391164011641116421164311644116451164611647116481164911650116511165211653116541165511656116571165811659116601166111662116631166411665116661166711668116691167011671116721167311674116751167611677116781167911680116811168211683116841168511686116871168811689116901169111692116931169411695116961169711698116991170011701117021170311704117051170611707117081170911710117111171211713117141171511716117171171811719117201172111722117231172411725117261172711728117291173011731117321173311734117351173611737117381173911740117411174211743117441174511746117471174811749117501175111752117531175411755117561175711758117591176011761117621176311764117651176611767117681176911770117711177211773117741177511776117771177811779117801178111782117831178411785117861178711788117891179011791117921179311794117951179611797117981179911800118011180211803118041180511806118071180811809118101181111812118131181411815118161181711818118191182011821118221182311824118251182611827118281182911830118311183211833118341183511836118371183811839118401184111842118431184411845118461184711848118491185011851118521185311854118551185611857118581185911860118611186211863118641186511866118671186811869118701187111872118731187411875118761187711878118791188011881118821188311884118851188611887118881188911890118911189211893118941189511896118971189811899119001190111902119031190411905119061190711908119091191011911119121191311914119151191611917119181191911920119211192211923119241192511926119271192811929119301193111932119331193411935119361193711938119391194011941119421194311944119451194611947119481194911950119511195211953119541195511956119571195811959119601196111962119631196411965119661196711968119691197011971119721197311974119751197611977119781197911980119811198211983119841198511986119871198811989119901199111992119931199411995119961199711998119991200012001120021200312004120051200612007120081200912010120111201212013120141201512016120171201812019120201202112022120231202412025120261202712028120291203012031120321203312034120351203612037120381203912040120411204212043120441204512046120471204812049120501205112052120531205412055120561205712058120591206012061120621206312064120651206612067120681206912070120711207212073120741207512076120771207812079120801208112082120831208412085120861208712088120891209012091120921209312094120951209612097120981209912100121011210212103121041210512106121071210812109121101211112112121131211412115121161211712118121191212012121121221212312124121251212612127121281212912130121311213212133121341213512136121371213812139121401214112142121431214412145121461214712148121491215012151121521215312154121551215612157121581215912160121611216212163121641216512166121671216812169121701217112172121731217412175121761217712178121791218012181121821218312184121851218612187121881218912190121911219212193121941219512196121971219812199122001220112202122031220412205122061220712208122091221012211122121221312214122151221612217122181221912220122211222212223122241222512226122271222812229122301223112232122331223412235122361223712238122391224012241122421224312244122451224612247122481224912250122511225212253122541225512256122571225812259122601226112262122631226412265122661226712268122691227012271122721227312274122751227612277122781227912280122811228212283122841228512286122871228812289122901229112292122931229412295122961229712298122991230012301123021230312304123051230612307123081230912310123111231212313123141231512316123171231812319123201232112322123231232412325123261232712328123291233012331123321233312334123351233612337123381233912340123411234212343123441234512346123471234812349123501235112352123531235412355123561235712358123591236012361123621236312364123651236612367123681236912370123711237212373123741237512376123771237812379123801238112382123831238412385123861238712388123891239012391123921239312394123951239612397123981239912400124011240212403124041240512406124071240812409124101241112412124131241412415124161241712418124191242012421124221242312424124251242612427124281242912430124311243212433124341243512436124371243812439124401244112442124431244412445124461244712448124491245012451124521245312454124551245612457124581245912460124611246212463124641246512466124671246812469124701247112472124731247412475124761247712478124791248012481124821248312484124851248612487124881248912490124911249212493124941249512496124971249812499125001250112502125031250412505125061250712508125091251012511125121251312514125151251612517125181251912520125211252212523125241252512526125271252812529125301253112532125331253412535125361253712538125391254012541125421254312544125451254612547125481254912550125511255212553125541255512556125571255812559125601256112562125631256412565125661256712568125691257012571125721257312574125751257612577125781257912580125811258212583125841258512586125871258812589125901259112592125931259412595125961259712598125991260012601126021260312604126051260612607126081260912610126111261212613126141261512616126171261812619126201262112622126231262412625126261262712628126291263012631126321263312634126351263612637126381263912640126411264212643126441264512646126471264812649126501265112652126531265412655126561265712658126591266012661126621266312664126651266612667126681266912670126711267212673126741267512676126771267812679126801268112682126831268412685126861268712688126891269012691126921269312694126951269612697126981269912700127011270212703127041270512706127071270812709127101271112712127131271412715127161271712718127191272012721127221272312724127251272612727127281272912730127311273212733127341273512736127371273812739127401274112742127431274412745127461274712748127491275012751127521275312754127551275612757127581275912760127611276212763127641276512766127671276812769127701277112772127731277412775127761277712778127791278012781127821278312784127851278612787127881278912790127911279212793127941279512796127971279812799128001280112802128031280412805128061280712808128091281012811128121281312814128151281612817128181281912820128211282212823128241282512826128271282812829128301283112832128331283412835128361283712838128391284012841128421284312844128451284612847128481284912850128511285212853128541285512856128571285812859128601286112862128631286412865128661286712868128691287012871128721287312874128751287612877128781287912880128811288212883128841288512886128871288812889128901289112892128931289412895128961289712898128991290012901129021290312904129051290612907129081290912910129111291212913129141291512916129171291812919129201292112922129231292412925129261292712928129291293012931129321293312934129351293612937129381293912940129411294212943129441294512946129471294812949129501295112952129531295412955129561295712958129591296012961129621296312964129651296612967129681296912970129711297212973129741297512976129771297812979129801298112982129831298412985129861298712988129891299012991129921299312994129951299612997129981299913000130011300213003130041300513006130071300813009130101301113012130131301413015130161301713018130191302013021130221302313024130251302613027130281302913030130311303213033130341303513036130371303813039130401304113042130431304413045130461304713048130491305013051130521305313054130551305613057130581305913060130611306213063130641306513066130671306813069130701307113072130731307413075130761307713078130791308013081130821308313084130851308613087130881308913090130911309213093130941309513096130971309813099131001310113102131031310413105131061310713108131091311013111131121311313114131151311613117131181311913120131211312213123131241312513126131271312813129131301313113132131331313413135131361313713138131391314013141131421314313144131451314613147131481314913150131511315213153131541315513156131571315813159131601316113162131631316413165131661316713168131691317013171131721317313174131751317613177131781317913180131811318213183131841318513186131871318813189131901319113192131931319413195131961319713198131991320013201132021320313204132051320613207132081320913210132111321213213132141321513216132171321813219132201322113222132231322413225132261322713228132291323013231132321323313234132351323613237132381323913240132411324213243132441324513246132471324813249132501325113252132531325413255132561325713258132591326013261132621326313264132651326613267132681326913270132711327213273132741327513276132771327813279132801328113282132831328413285132861328713288132891329013291132921329313294132951329613297132981329913300133011330213303133041330513306133071330813309133101331113312133131331413315133161331713318133191332013321133221332313324133251332613327133281332913330133311333213333133341333513336133371333813339133401334113342133431334413345133461334713348133491335013351133521335313354133551335613357133581335913360133611336213363133641336513366133671336813369133701337113372133731337413375133761337713378133791338013381133821338313384133851338613387133881338913390133911339213393133941339513396133971339813399134001340113402134031340413405134061340713408134091341013411134121341313414134151341613417134181341913420134211342213423134241342513426134271342813429134301343113432134331343413435134361343713438134391344013441134421344313444134451344613447134481344913450134511345213453134541345513456134571345813459134601346113462134631346413465134661346713468134691347013471134721347313474134751347613477134781347913480134811348213483134841348513486134871348813489134901349113492134931349413495134961349713498134991350013501135021350313504135051350613507135081350913510135111351213513135141351513516135171351813519135201352113522135231352413525135261352713528135291353013531135321353313534135351353613537135381353913540135411354213543135441354513546135471354813549135501355113552135531355413555135561355713558135591356013561135621356313564135651356613567135681356913570135711357213573135741357513576135771357813579135801358113582135831358413585135861358713588135891359013591135921359313594135951359613597135981359913600136011360213603136041360513606136071360813609136101361113612136131361413615136161361713618136191362013621136221362313624136251362613627136281362913630136311363213633136341363513636136371363813639136401364113642136431364413645136461364713648136491365013651136521365313654136551365613657136581365913660136611366213663136641366513666136671366813669136701367113672136731367413675136761367713678136791368013681136821368313684136851368613687136881368913690136911369213693136941369513696136971369813699137001370113702137031370413705137061370713708137091371013711137121371313714137151371613717137181371913720137211372213723137241372513726137271372813729137301373113732137331373413735137361373713738137391374013741137421374313744137451374613747137481374913750137511375213753137541375513756137571375813759137601376113762137631376413765137661376713768137691377013771137721377313774137751377613777137781377913780137811378213783137841378513786137871378813789137901379113792137931379413795137961379713798137991380013801138021380313804138051380613807138081380913810138111381213813138141381513816138171381813819138201382113822138231382413825138261382713828138291383013831138321383313834138351383613837138381383913840138411384213843138441384513846138471384813849138501385113852138531385413855138561385713858138591386013861138621386313864138651386613867138681386913870138711387213873138741387513876138771387813879138801388113882138831388413885138861388713888138891389013891138921389313894138951389613897138981389913900139011390213903139041390513906139071390813909139101391113912139131391413915139161391713918139191392013921139221392313924139251392613927139281392913930139311393213933139341393513936139371393813939139401394113942139431394413945139461394713948139491395013951139521395313954139551395613957139581395913960139611396213963139641396513966139671396813969139701397113972139731397413975139761397713978139791398013981139821398313984139851398613987139881398913990139911399213993139941399513996139971399813999140001400114002140031400414005140061400714008140091401014011140121401314014140151401614017140181401914020140211402214023140241402514026140271402814029140301403114032140331403414035140361403714038140391404014041140421404314044140451404614047140481404914050140511405214053140541405514056140571405814059140601406114062140631406414065140661406714068140691407014071140721407314074140751407614077140781407914080140811408214083140841408514086140871408814089140901409114092140931409414095140961409714098140991410014101141021410314104141051410614107141081410914110141111411214113141141411514116141171411814119141201412114122141231412414125141261412714128141291413014131141321413314134141351413614137141381413914140141411414214143141441414514146141471414814149141501415114152141531415414155141561415714158141591416014161141621416314164141651416614167141681416914170141711417214173141741417514176141771417814179141801418114182141831418414185141861418714188141891419014191141921419314194141951419614197141981419914200142011420214203142041420514206142071420814209142101421114212142131421414215142161421714218142191422014221142221422314224142251422614227142281422914230142311423214233142341423514236142371423814239142401424114242142431424414245142461424714248142491425014251142521425314254142551425614257142581425914260142611426214263142641426514266142671426814269142701427114272142731427414275142761427714278142791428014281142821428314284142851428614287142881428914290142911429214293142941429514296142971429814299143001430114302143031430414305143061430714308143091431014311143121431314314143151431614317143181431914320143211432214323143241432514326143271432814329143301433114332143331433414335143361433714338143391434014341143421434314344143451434614347143481434914350143511435214353143541435514356143571435814359143601436114362143631436414365143661436714368143691437014371143721437314374143751437614377143781437914380143811438214383143841438514386143871438814389143901439114392143931439414395143961439714398143991440014401144021440314404144051440614407144081440914410144111441214413144141441514416144171441814419144201442114422144231442414425144261442714428144291443014431144321443314434144351443614437144381443914440144411444214443144441444514446144471444814449144501445114452144531445414455144561445714458144591446014461144621446314464144651446614467144681446914470144711447214473144741447514476144771447814479144801448114482144831448414485144861448714488144891449014491144921449314494144951449614497144981449914500145011450214503145041450514506145071450814509145101451114512145131451414515145161451714518145191452014521145221452314524145251452614527145281452914530145311453214533145341453514536145371453814539145401454114542145431454414545145461454714548145491455014551145521455314554145551455614557145581455914560145611456214563145641456514566145671456814569145701457114572145731457414575145761457714578145791458014581145821458314584145851458614587145881458914590145911459214593145941459514596145971459814599146001460114602146031460414605146061460714608146091461014611146121461314614146151461614617146181461914620146211462214623146241462514626146271462814629146301463114632146331463414635146361463714638146391464014641146421464314644146451464614647146481464914650146511465214653146541465514656146571465814659146601466114662146631466414665146661466714668146691467014671146721467314674146751467614677146781467914680146811468214683146841468514686146871468814689146901469114692146931469414695146961469714698146991470014701147021470314704147051470614707147081470914710147111471214713147141471514716147171471814719147201472114722147231472414725147261472714728147291473014731147321473314734147351473614737147381473914740147411474214743147441474514746147471474814749147501475114752147531475414755147561475714758147591476014761147621476314764147651476614767147681476914770147711477214773147741477514776147771477814779147801478114782147831478414785147861478714788147891479014791147921479314794147951479614797147981479914800148011480214803148041480514806148071480814809148101481114812148131481414815148161481714818148191482014821148221482314824148251482614827148281482914830148311483214833148341483514836148371483814839148401484114842148431484414845148461484714848148491485014851148521485314854148551485614857148581485914860148611486214863148641486514866148671486814869148701487114872148731487414875148761487714878148791488014881148821488314884148851488614887148881488914890148911489214893148941489514896148971489814899149001490114902149031490414905149061490714908149091491014911149121491314914149151491614917149181491914920149211492214923149241492514926149271492814929149301493114932149331493414935149361493714938149391494014941149421494314944149451494614947149481494914950149511495214953149541495514956149571495814959149601496114962149631496414965149661496714968149691497014971149721497314974149751497614977149781497914980149811498214983149841498514986149871498814989149901499114992149931499414995149961499714998149991500015001150021500315004150051500615007150081500915010150111501215013150141501515016150171501815019150201502115022150231502415025150261502715028150291503015031150321503315034150351503615037150381503915040150411504215043150441504515046150471504815049150501505115052150531505415055150561505715058150591506015061150621506315064150651506615067150681506915070150711507215073150741507515076150771507815079150801508115082150831508415085150861508715088150891509015091150921509315094150951509615097150981509915100151011510215103151041510515106151071510815109151101511115112151131511415115151161511715118151191512015121151221512315124151251512615127151281512915130151311513215133151341513515136151371513815139151401514115142151431514415145151461514715148151491515015151151521515315154151551515615157151581515915160151611516215163151641516515166151671516815169151701517115172151731517415175151761517715178151791518015181151821518315184151851518615187151881518915190151911519215193151941519515196151971519815199152001520115202152031520415205152061520715208152091521015211152121521315214152151521615217152181521915220152211522215223152241522515226152271522815229152301523115232152331523415235152361523715238152391524015241152421524315244152451524615247152481524915250152511525215253152541525515256152571525815259152601526115262152631526415265152661526715268152691527015271152721527315274152751527615277152781527915280152811528215283152841528515286152871528815289152901529115292152931529415295152961529715298152991530015301153021530315304153051530615307153081530915310153111531215313153141531515316153171531815319153201532115322153231532415325153261532715328153291533015331153321533315334153351533615337153381533915340153411534215343153441534515346153471534815349153501535115352153531535415355153561535715358153591536015361153621536315364153651536615367153681536915370153711537215373153741537515376153771537815379153801538115382153831538415385153861538715388153891539015391153921539315394153951539615397153981539915400154011540215403154041540515406154071540815409154101541115412154131541415415154161541715418154191542015421154221542315424154251542615427154281542915430154311543215433154341543515436154371543815439154401544115442154431544415445154461544715448154491545015451154521545315454154551545615457154581545915460154611546215463154641546515466154671546815469154701547115472154731547415475154761547715478154791548015481154821548315484154851548615487154881548915490154911549215493154941549515496154971549815499155001550115502155031550415505155061550715508155091551015511155121551315514155151551615517155181551915520155211552215523155241552515526155271552815529155301553115532155331553415535155361553715538155391554015541155421554315544155451554615547155481554915550155511555215553155541555515556155571555815559155601556115562155631556415565155661556715568155691557015571155721557315574155751557615577155781557915580155811558215583155841558515586155871558815589155901559115592155931559415595155961559715598155991560015601156021560315604156051560615607156081560915610156111561215613156141561515616156171561815619156201562115622156231562415625156261562715628156291563015631156321563315634156351563615637156381563915640156411564215643156441564515646156471564815649156501565115652156531565415655156561565715658156591566015661156621566315664156651566615667156681566915670156711567215673156741567515676156771567815679156801568115682156831568415685156861568715688156891569015691156921569315694156951569615697156981569915700157011570215703157041570515706157071570815709157101571115712157131571415715157161571715718157191572015721157221572315724157251572615727157281572915730157311573215733157341573515736157371573815739157401574115742157431574415745157461574715748157491575015751157521575315754157551575615757157581575915760157611576215763157641576515766157671576815769157701577115772157731577415775157761577715778157791578015781157821578315784157851578615787157881578915790157911579215793157941579515796157971579815799158001580115802158031580415805158061580715808158091581015811158121581315814158151581615817158181581915820158211582215823158241582515826158271582815829158301583115832158331583415835158361583715838158391584015841158421584315844158451584615847158481584915850158511585215853158541585515856158571585815859158601586115862158631586415865158661586715868158691587015871158721587315874158751587615877158781587915880158811588215883158841588515886158871588815889158901589115892158931589415895158961589715898158991590015901159021590315904159051590615907159081590915910159111591215913159141591515916159171591815919159201592115922159231592415925159261592715928159291593015931159321593315934159351593615937159381593915940159411594215943159441594515946159471594815949159501595115952159531595415955159561595715958159591596015961159621596315964159651596615967159681596915970159711597215973159741597515976159771597815979159801598115982159831598415985159861598715988159891599015991159921599315994159951599615997159981599916000160011600216003160041600516006160071600816009160101601116012160131601416015160161601716018160191602016021160221602316024160251602616027160281602916030160311603216033160341603516036160371603816039160401604116042160431604416045160461604716048160491605016051160521605316054160551605616057160581605916060160611606216063160641606516066160671606816069160701607116072160731607416075160761607716078160791608016081160821608316084160851608616087160881608916090160911609216093160941609516096160971609816099161001610116102161031610416105161061610716108161091611016111161121611316114161151611616117161181611916120161211612216123161241612516126161271612816129161301613116132161331613416135161361613716138161391614016141161421614316144161451614616147161481614916150161511615216153161541615516156161571615816159161601616116162161631616416165161661616716168161691617016171161721617316174161751617616177161781617916180161811618216183161841618516186161871618816189161901619116192161931619416195161961619716198161991620016201162021620316204162051620616207162081620916210162111621216213162141621516216162171621816219162201622116222162231622416225162261622716228162291623016231162321623316234162351623616237162381623916240162411624216243162441624516246162471624816249162501625116252162531625416255162561625716258162591626016261162621626316264162651626616267162681626916270162711627216273162741627516276162771627816279162801628116282162831628416285162861628716288162891629016291162921629316294162951629616297162981629916300163011630216303163041630516306163071630816309163101631116312163131631416315163161631716318163191632016321163221632316324163251632616327163281632916330163311633216333163341633516336163371633816339163401634116342163431634416345163461634716348163491635016351163521635316354163551635616357163581635916360163611636216363163641636516366163671636816369163701637116372163731637416375163761637716378163791638016381163821638316384163851638616387163881638916390163911639216393163941639516396163971639816399164001640116402164031640416405164061640716408164091641016411164121641316414164151641616417164181641916420164211642216423164241642516426164271642816429164301643116432164331643416435164361643716438164391644016441164421644316444164451644616447164481644916450164511645216453164541645516456164571645816459164601646116462164631646416465164661646716468164691647016471164721647316474164751647616477164781647916480164811648216483164841648516486164871648816489164901649116492164931649416495164961649716498164991650016501165021650316504165051650616507165081650916510165111651216513165141651516516165171651816519165201652116522165231652416525165261652716528165291653016531165321653316534165351653616537165381653916540165411654216543165441654516546165471654816549165501655116552165531655416555165561655716558165591656016561165621656316564165651656616567165681656916570165711657216573165741657516576165771657816579165801658116582165831658416585165861658716588165891659016591165921659316594165951659616597165981659916600166011660216603166041660516606166071660816609166101661116612166131661416615166161661716618166191662016621166221662316624166251662616627166281662916630166311663216633166341663516636166371663816639166401664116642166431664416645166461664716648166491665016651166521665316654166551665616657166581665916660166611666216663166641666516666166671666816669166701667116672166731667416675166761667716678166791668016681166821668316684166851668616687166881668916690166911669216693166941669516696166971669816699167001670116702167031670416705167061670716708167091671016711167121671316714167151671616717167181671916720167211672216723167241672516726167271672816729167301673116732167331673416735167361673716738167391674016741167421674316744167451674616747167481674916750167511675216753167541675516756167571675816759167601676116762167631676416765167661676716768167691677016771167721677316774167751677616777167781677916780167811678216783167841678516786167871678816789167901679116792167931679416795167961679716798167991680016801168021680316804168051680616807168081680916810168111681216813168141681516816168171681816819168201682116822168231682416825168261682716828168291683016831168321683316834168351683616837168381683916840168411684216843168441684516846168471684816849168501685116852168531685416855168561685716858168591686016861168621686316864168651686616867168681686916870168711687216873168741687516876168771687816879168801688116882168831688416885168861688716888168891689016891168921689316894168951689616897168981689916900169011690216903169041690516906169071690816909169101691116912169131691416915169161691716918169191692016921169221692316924169251692616927169281692916930169311693216933169341693516936169371693816939169401694116942169431694416945169461694716948169491695016951169521695316954169551695616957169581695916960169611696216963169641696516966169671696816969169701697116972169731697416975169761697716978169791698016981169821698316984169851698616987169881698916990169911699216993169941699516996169971699816999170001700117002170031700417005170061700717008170091701017011170121701317014170151701617017170181701917020170211702217023170241702517026170271702817029170301703117032170331703417035170361703717038170391704017041170421704317044170451704617047170481704917050170511705217053170541705517056170571705817059170601706117062170631706417065170661706717068170691707017071170721707317074170751707617077170781707917080170811708217083170841708517086170871708817089170901709117092170931709417095170961709717098170991710017101171021710317104171051710617107171081710917110171111711217113171141711517116171171711817119171201712117122171231712417125171261712717128171291713017131171321713317134171351713617137171381713917140171411714217143171441714517146171471714817149171501715117152171531715417155171561715717158171591716017161171621716317164171651716617167171681716917170171711717217173171741717517176171771717817179171801718117182171831718417185171861718717188171891719017191171921719317194171951719617197171981719917200172011720217203172041720517206172071720817209172101721117212172131721417215172161721717218172191722017221172221722317224172251722617227172281722917230172311723217233172341723517236172371723817239172401724117242172431724417245172461724717248172491725017251172521725317254172551725617257172581725917260
  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2013 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/stringify.h>
  20. #include <linux/kernel.h>
  21. #include <linux/types.h>
  22. #include <linux/compiler.h>
  23. #include <linux/slab.h>
  24. #include <linux/delay.h>
  25. #include <linux/in.h>
  26. #include <linux/init.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/ioport.h>
  29. #include <linux/pci.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/ethtool.h>
  34. #include <linux/mdio.h>
  35. #include <linux/mii.h>
  36. #include <linux/phy.h>
  37. #include <linux/brcmphy.h>
  38. #include <linux/if_vlan.h>
  39. #include <linux/ip.h>
  40. #include <linux/tcp.h>
  41. #include <linux/workqueue.h>
  42. #include <linux/prefetch.h>
  43. #include <linux/dma-mapping.h>
  44. #include <linux/firmware.h>
  45. #include <linux/ssb/ssb_driver_gige.h>
  46. #include <linux/hwmon.h>
  47. #include <linux/hwmon-sysfs.h>
  48. #include <net/checksum.h>
  49. #include <net/ip.h>
  50. #include <linux/io.h>
  51. #include <asm/byteorder.h>
  52. #include <linux/uaccess.h>
  53. #include <uapi/linux/net_tstamp.h>
  54. #include <linux/ptp_clock_kernel.h>
  55. #ifdef CONFIG_SPARC
  56. #include <asm/idprom.h>
  57. #include <asm/prom.h>
  58. #endif
  59. #define BAR_0 0
  60. #define BAR_2 2
  61. #include "tg3.h"
  62. /* Functions & macros to verify TG3_FLAGS types */
  63. static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
  64. {
  65. return test_bit(flag, bits);
  66. }
  67. static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
  68. {
  69. set_bit(flag, bits);
  70. }
  71. static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
  72. {
  73. clear_bit(flag, bits);
  74. }
  75. #define tg3_flag(tp, flag) \
  76. _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
  77. #define tg3_flag_set(tp, flag) \
  78. _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
  79. #define tg3_flag_clear(tp, flag) \
  80. _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
  81. #define DRV_MODULE_NAME "tg3"
  82. #define TG3_MAJ_NUM 3
  83. #define TG3_MIN_NUM 130
  84. #define DRV_MODULE_VERSION \
  85. __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  86. #define DRV_MODULE_RELDATE "February 14, 2013"
  87. #define RESET_KIND_SHUTDOWN 0
  88. #define RESET_KIND_INIT 1
  89. #define RESET_KIND_SUSPEND 2
  90. #define TG3_DEF_RX_MODE 0
  91. #define TG3_DEF_TX_MODE 0
  92. #define TG3_DEF_MSG_ENABLE \
  93. (NETIF_MSG_DRV | \
  94. NETIF_MSG_PROBE | \
  95. NETIF_MSG_LINK | \
  96. NETIF_MSG_TIMER | \
  97. NETIF_MSG_IFDOWN | \
  98. NETIF_MSG_IFUP | \
  99. NETIF_MSG_RX_ERR | \
  100. NETIF_MSG_TX_ERR)
  101. #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
  102. /* length of time before we decide the hardware is borked,
  103. * and dev->tx_timeout() should be called to fix the problem
  104. */
  105. #define TG3_TX_TIMEOUT (5 * HZ)
  106. /* hardware minimum and maximum for a single frame's data payload */
  107. #define TG3_MIN_MTU 60
  108. #define TG3_MAX_MTU(tp) \
  109. (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
  110. /* These numbers seem to be hard coded in the NIC firmware somehow.
  111. * You can't change the ring sizes, but you can change where you place
  112. * them in the NIC onboard memory.
  113. */
  114. #define TG3_RX_STD_RING_SIZE(tp) \
  115. (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
  116. TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
  117. #define TG3_DEF_RX_RING_PENDING 200
  118. #define TG3_RX_JMB_RING_SIZE(tp) \
  119. (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
  120. TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
  121. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  122. /* Do not place this n-ring entries value into the tp struct itself,
  123. * we really want to expose these constants to GCC so that modulo et
  124. * al. operations are done with shifts and masks instead of with
  125. * hw multiply/modulo instructions. Another solution would be to
  126. * replace things like '% foo' with '& (foo - 1)'.
  127. */
  128. #define TG3_TX_RING_SIZE 512
  129. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  130. #define TG3_RX_STD_RING_BYTES(tp) \
  131. (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
  132. #define TG3_RX_JMB_RING_BYTES(tp) \
  133. (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
  134. #define TG3_RX_RCB_RING_BYTES(tp) \
  135. (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
  136. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  137. TG3_TX_RING_SIZE)
  138. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  139. #define TG3_DMA_BYTE_ENAB 64
  140. #define TG3_RX_STD_DMA_SZ 1536
  141. #define TG3_RX_JMB_DMA_SZ 9046
  142. #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
  143. #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
  144. #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
  145. #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
  146. (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
  147. #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
  148. (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
  149. /* Due to a hardware bug, the 5701 can only DMA to memory addresses
  150. * that are at least dword aligned when used in PCIX mode. The driver
  151. * works around this bug by double copying the packet. This workaround
  152. * is built into the normal double copy length check for efficiency.
  153. *
  154. * However, the double copy is only necessary on those architectures
  155. * where unaligned memory accesses are inefficient. For those architectures
  156. * where unaligned memory accesses incur little penalty, we can reintegrate
  157. * the 5701 in the normal rx path. Doing so saves a device structure
  158. * dereference by hardcoding the double copy threshold in place.
  159. */
  160. #define TG3_RX_COPY_THRESHOLD 256
  161. #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
  162. #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
  163. #else
  164. #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
  165. #endif
  166. #if (NET_IP_ALIGN != 0)
  167. #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
  168. #else
  169. #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
  170. #endif
  171. /* minimum number of free TX descriptors required to wake up TX process */
  172. #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
  173. #define TG3_TX_BD_DMA_MAX_2K 2048
  174. #define TG3_TX_BD_DMA_MAX_4K 4096
  175. #define TG3_RAW_IP_ALIGN 2
  176. #define TG3_FW_UPDATE_TIMEOUT_SEC 5
  177. #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
  178. #define FIRMWARE_TG3 "tigon/tg3.bin"
  179. #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
  180. #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
  181. static char version[] =
  182. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
  183. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  184. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  185. MODULE_LICENSE("GPL");
  186. MODULE_VERSION(DRV_MODULE_VERSION);
  187. MODULE_FIRMWARE(FIRMWARE_TG3);
  188. MODULE_FIRMWARE(FIRMWARE_TG3TSO);
  189. MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
  190. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  191. module_param(tg3_debug, int, 0);
  192. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  193. #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
  194. #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
  195. static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
  196. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  197. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  198. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  199. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  200. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  201. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  202. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  203. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  204. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  205. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  206. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  207. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  208. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  209. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  210. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  211. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  212. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  213. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  214. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
  215. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  216. TG3_DRV_DATA_FLAG_5705_10_100},
  217. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
  218. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  219. TG3_DRV_DATA_FLAG_5705_10_100},
  220. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  221. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
  222. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
  223. TG3_DRV_DATA_FLAG_5705_10_100},
  224. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  225. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  226. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  227. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  228. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  229. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
  230. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  231. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  232. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  233. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  234. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  235. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
  236. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  237. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  238. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  239. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  240. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  241. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  242. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  243. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  244. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
  245. PCI_VENDOR_ID_LENOVO,
  246. TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
  247. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  248. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  249. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
  250. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  251. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  252. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  253. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  254. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  255. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  256. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  257. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  258. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  259. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  260. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  261. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  262. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
  263. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
  264. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
  265. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
  266. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
  267. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
  268. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
  269. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
  270. PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
  271. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  272. {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
  273. PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
  274. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  275. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
  276. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
  277. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
  278. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  279. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
  280. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
  281. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
  282. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
  283. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
  284. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
  285. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
  286. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
  287. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
  288. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  289. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
  290. .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
  291. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
  292. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
  293. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
  294. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
  295. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
  296. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
  297. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
  298. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  299. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  300. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  301. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  302. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  303. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  304. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  305. {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
  306. {}
  307. };
  308. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  309. static const struct {
  310. const char string[ETH_GSTRING_LEN];
  311. } ethtool_stats_keys[] = {
  312. { "rx_octets" },
  313. { "rx_fragments" },
  314. { "rx_ucast_packets" },
  315. { "rx_mcast_packets" },
  316. { "rx_bcast_packets" },
  317. { "rx_fcs_errors" },
  318. { "rx_align_errors" },
  319. { "rx_xon_pause_rcvd" },
  320. { "rx_xoff_pause_rcvd" },
  321. { "rx_mac_ctrl_rcvd" },
  322. { "rx_xoff_entered" },
  323. { "rx_frame_too_long_errors" },
  324. { "rx_jabbers" },
  325. { "rx_undersize_packets" },
  326. { "rx_in_length_errors" },
  327. { "rx_out_length_errors" },
  328. { "rx_64_or_less_octet_packets" },
  329. { "rx_65_to_127_octet_packets" },
  330. { "rx_128_to_255_octet_packets" },
  331. { "rx_256_to_511_octet_packets" },
  332. { "rx_512_to_1023_octet_packets" },
  333. { "rx_1024_to_1522_octet_packets" },
  334. { "rx_1523_to_2047_octet_packets" },
  335. { "rx_2048_to_4095_octet_packets" },
  336. { "rx_4096_to_8191_octet_packets" },
  337. { "rx_8192_to_9022_octet_packets" },
  338. { "tx_octets" },
  339. { "tx_collisions" },
  340. { "tx_xon_sent" },
  341. { "tx_xoff_sent" },
  342. { "tx_flow_control" },
  343. { "tx_mac_errors" },
  344. { "tx_single_collisions" },
  345. { "tx_mult_collisions" },
  346. { "tx_deferred" },
  347. { "tx_excessive_collisions" },
  348. { "tx_late_collisions" },
  349. { "tx_collide_2times" },
  350. { "tx_collide_3times" },
  351. { "tx_collide_4times" },
  352. { "tx_collide_5times" },
  353. { "tx_collide_6times" },
  354. { "tx_collide_7times" },
  355. { "tx_collide_8times" },
  356. { "tx_collide_9times" },
  357. { "tx_collide_10times" },
  358. { "tx_collide_11times" },
  359. { "tx_collide_12times" },
  360. { "tx_collide_13times" },
  361. { "tx_collide_14times" },
  362. { "tx_collide_15times" },
  363. { "tx_ucast_packets" },
  364. { "tx_mcast_packets" },
  365. { "tx_bcast_packets" },
  366. { "tx_carrier_sense_errors" },
  367. { "tx_discards" },
  368. { "tx_errors" },
  369. { "dma_writeq_full" },
  370. { "dma_write_prioq_full" },
  371. { "rxbds_empty" },
  372. { "rx_discards" },
  373. { "rx_errors" },
  374. { "rx_threshold_hit" },
  375. { "dma_readq_full" },
  376. { "dma_read_prioq_full" },
  377. { "tx_comp_queue_full" },
  378. { "ring_set_send_prod_index" },
  379. { "ring_status_update" },
  380. { "nic_irqs" },
  381. { "nic_avoided_irqs" },
  382. { "nic_tx_threshold_hit" },
  383. { "mbuf_lwm_thresh_hit" },
  384. };
  385. #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
  386. #define TG3_NVRAM_TEST 0
  387. #define TG3_LINK_TEST 1
  388. #define TG3_REGISTER_TEST 2
  389. #define TG3_MEMORY_TEST 3
  390. #define TG3_MAC_LOOPB_TEST 4
  391. #define TG3_PHY_LOOPB_TEST 5
  392. #define TG3_EXT_LOOPB_TEST 6
  393. #define TG3_INTERRUPT_TEST 7
  394. static const struct {
  395. const char string[ETH_GSTRING_LEN];
  396. } ethtool_test_keys[] = {
  397. [TG3_NVRAM_TEST] = { "nvram test (online) " },
  398. [TG3_LINK_TEST] = { "link test (online) " },
  399. [TG3_REGISTER_TEST] = { "register test (offline)" },
  400. [TG3_MEMORY_TEST] = { "memory test (offline)" },
  401. [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
  402. [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
  403. [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
  404. [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
  405. };
  406. #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
  407. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  408. {
  409. writel(val, tp->regs + off);
  410. }
  411. static u32 tg3_read32(struct tg3 *tp, u32 off)
  412. {
  413. return readl(tp->regs + off);
  414. }
  415. static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
  416. {
  417. writel(val, tp->aperegs + off);
  418. }
  419. static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
  420. {
  421. return readl(tp->aperegs + off);
  422. }
  423. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  424. {
  425. unsigned long flags;
  426. spin_lock_irqsave(&tp->indirect_lock, flags);
  427. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  428. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  429. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  430. }
  431. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  432. {
  433. writel(val, tp->regs + off);
  434. readl(tp->regs + off);
  435. }
  436. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  437. {
  438. unsigned long flags;
  439. u32 val;
  440. spin_lock_irqsave(&tp->indirect_lock, flags);
  441. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  442. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  443. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  444. return val;
  445. }
  446. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  447. {
  448. unsigned long flags;
  449. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  450. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  451. TG3_64BIT_REG_LOW, val);
  452. return;
  453. }
  454. if (off == TG3_RX_STD_PROD_IDX_REG) {
  455. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  456. TG3_64BIT_REG_LOW, val);
  457. return;
  458. }
  459. spin_lock_irqsave(&tp->indirect_lock, flags);
  460. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  461. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  462. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  463. /* In indirect mode when disabling interrupts, we also need
  464. * to clear the interrupt bit in the GRC local ctrl register.
  465. */
  466. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  467. (val == 0x1)) {
  468. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  469. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  470. }
  471. }
  472. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  473. {
  474. unsigned long flags;
  475. u32 val;
  476. spin_lock_irqsave(&tp->indirect_lock, flags);
  477. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  478. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  479. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  480. return val;
  481. }
  482. /* usec_wait specifies the wait time in usec when writing to certain registers
  483. * where it is unsafe to read back the register without some delay.
  484. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  485. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  486. */
  487. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  488. {
  489. if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
  490. /* Non-posted methods */
  491. tp->write32(tp, off, val);
  492. else {
  493. /* Posted method */
  494. tg3_write32(tp, off, val);
  495. if (usec_wait)
  496. udelay(usec_wait);
  497. tp->read32(tp, off);
  498. }
  499. /* Wait again after the read for the posted method to guarantee that
  500. * the wait time is met.
  501. */
  502. if (usec_wait)
  503. udelay(usec_wait);
  504. }
  505. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  506. {
  507. tp->write32_mbox(tp, off, val);
  508. if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
  509. (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
  510. !tg3_flag(tp, ICH_WORKAROUND)))
  511. tp->read32_mbox(tp, off);
  512. }
  513. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  514. {
  515. void __iomem *mbox = tp->regs + off;
  516. writel(val, mbox);
  517. if (tg3_flag(tp, TXD_MBOX_HWBUG))
  518. writel(val, mbox);
  519. if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
  520. tg3_flag(tp, FLUSH_POSTED_WRITES))
  521. readl(mbox);
  522. }
  523. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  524. {
  525. return readl(tp->regs + off + GRCMBOX_BASE);
  526. }
  527. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  528. {
  529. writel(val, tp->regs + off + GRCMBOX_BASE);
  530. }
  531. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  532. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  533. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  534. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  535. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  536. #define tw32(reg, val) tp->write32(tp, reg, val)
  537. #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
  538. #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
  539. #define tr32(reg) tp->read32(tp, reg)
  540. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  541. {
  542. unsigned long flags;
  543. if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
  544. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  545. return;
  546. spin_lock_irqsave(&tp->indirect_lock, flags);
  547. if (tg3_flag(tp, SRAM_USE_CONFIG)) {
  548. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  549. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  550. /* Always leave this as zero. */
  551. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  552. } else {
  553. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  554. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  555. /* Always leave this as zero. */
  556. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  557. }
  558. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  559. }
  560. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  561. {
  562. unsigned long flags;
  563. if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
  564. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  565. *val = 0;
  566. return;
  567. }
  568. spin_lock_irqsave(&tp->indirect_lock, flags);
  569. if (tg3_flag(tp, SRAM_USE_CONFIG)) {
  570. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  571. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  572. /* Always leave this as zero. */
  573. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  574. } else {
  575. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  576. *val = tr32(TG3PCI_MEM_WIN_DATA);
  577. /* Always leave this as zero. */
  578. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  579. }
  580. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  581. }
  582. static void tg3_ape_lock_init(struct tg3 *tp)
  583. {
  584. int i;
  585. u32 regbase, bit;
  586. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  587. regbase = TG3_APE_LOCK_GRANT;
  588. else
  589. regbase = TG3_APE_PER_LOCK_GRANT;
  590. /* Make sure the driver hasn't any stale locks. */
  591. for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
  592. switch (i) {
  593. case TG3_APE_LOCK_PHY0:
  594. case TG3_APE_LOCK_PHY1:
  595. case TG3_APE_LOCK_PHY2:
  596. case TG3_APE_LOCK_PHY3:
  597. bit = APE_LOCK_GRANT_DRIVER;
  598. break;
  599. default:
  600. if (!tp->pci_fn)
  601. bit = APE_LOCK_GRANT_DRIVER;
  602. else
  603. bit = 1 << tp->pci_fn;
  604. }
  605. tg3_ape_write32(tp, regbase + 4 * i, bit);
  606. }
  607. }
  608. static int tg3_ape_lock(struct tg3 *tp, int locknum)
  609. {
  610. int i, off;
  611. int ret = 0;
  612. u32 status, req, gnt, bit;
  613. if (!tg3_flag(tp, ENABLE_APE))
  614. return 0;
  615. switch (locknum) {
  616. case TG3_APE_LOCK_GPIO:
  617. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  618. return 0;
  619. case TG3_APE_LOCK_GRC:
  620. case TG3_APE_LOCK_MEM:
  621. if (!tp->pci_fn)
  622. bit = APE_LOCK_REQ_DRIVER;
  623. else
  624. bit = 1 << tp->pci_fn;
  625. break;
  626. case TG3_APE_LOCK_PHY0:
  627. case TG3_APE_LOCK_PHY1:
  628. case TG3_APE_LOCK_PHY2:
  629. case TG3_APE_LOCK_PHY3:
  630. bit = APE_LOCK_REQ_DRIVER;
  631. break;
  632. default:
  633. return -EINVAL;
  634. }
  635. if (tg3_asic_rev(tp) == ASIC_REV_5761) {
  636. req = TG3_APE_LOCK_REQ;
  637. gnt = TG3_APE_LOCK_GRANT;
  638. } else {
  639. req = TG3_APE_PER_LOCK_REQ;
  640. gnt = TG3_APE_PER_LOCK_GRANT;
  641. }
  642. off = 4 * locknum;
  643. tg3_ape_write32(tp, req + off, bit);
  644. /* Wait for up to 1 millisecond to acquire lock. */
  645. for (i = 0; i < 100; i++) {
  646. status = tg3_ape_read32(tp, gnt + off);
  647. if (status == bit)
  648. break;
  649. udelay(10);
  650. }
  651. if (status != bit) {
  652. /* Revoke the lock request. */
  653. tg3_ape_write32(tp, gnt + off, bit);
  654. ret = -EBUSY;
  655. }
  656. return ret;
  657. }
  658. static void tg3_ape_unlock(struct tg3 *tp, int locknum)
  659. {
  660. u32 gnt, bit;
  661. if (!tg3_flag(tp, ENABLE_APE))
  662. return;
  663. switch (locknum) {
  664. case TG3_APE_LOCK_GPIO:
  665. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  666. return;
  667. case TG3_APE_LOCK_GRC:
  668. case TG3_APE_LOCK_MEM:
  669. if (!tp->pci_fn)
  670. bit = APE_LOCK_GRANT_DRIVER;
  671. else
  672. bit = 1 << tp->pci_fn;
  673. break;
  674. case TG3_APE_LOCK_PHY0:
  675. case TG3_APE_LOCK_PHY1:
  676. case TG3_APE_LOCK_PHY2:
  677. case TG3_APE_LOCK_PHY3:
  678. bit = APE_LOCK_GRANT_DRIVER;
  679. break;
  680. default:
  681. return;
  682. }
  683. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  684. gnt = TG3_APE_LOCK_GRANT;
  685. else
  686. gnt = TG3_APE_PER_LOCK_GRANT;
  687. tg3_ape_write32(tp, gnt + 4 * locknum, bit);
  688. }
  689. static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
  690. {
  691. u32 apedata;
  692. while (timeout_us) {
  693. if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
  694. return -EBUSY;
  695. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  696. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  697. break;
  698. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  699. udelay(10);
  700. timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
  701. }
  702. return timeout_us ? 0 : -EBUSY;
  703. }
  704. static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
  705. {
  706. u32 i, apedata;
  707. for (i = 0; i < timeout_us / 10; i++) {
  708. apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
  709. if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
  710. break;
  711. udelay(10);
  712. }
  713. return i == timeout_us / 10;
  714. }
  715. static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
  716. u32 len)
  717. {
  718. int err;
  719. u32 i, bufoff, msgoff, maxlen, apedata;
  720. if (!tg3_flag(tp, APE_HAS_NCSI))
  721. return 0;
  722. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  723. if (apedata != APE_SEG_SIG_MAGIC)
  724. return -ENODEV;
  725. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  726. if (!(apedata & APE_FW_STATUS_READY))
  727. return -EAGAIN;
  728. bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
  729. TG3_APE_SHMEM_BASE;
  730. msgoff = bufoff + 2 * sizeof(u32);
  731. maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
  732. while (len) {
  733. u32 length;
  734. /* Cap xfer sizes to scratchpad limits. */
  735. length = (len > maxlen) ? maxlen : len;
  736. len -= length;
  737. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  738. if (!(apedata & APE_FW_STATUS_READY))
  739. return -EAGAIN;
  740. /* Wait for up to 1 msec for APE to service previous event. */
  741. err = tg3_ape_event_lock(tp, 1000);
  742. if (err)
  743. return err;
  744. apedata = APE_EVENT_STATUS_DRIVER_EVNT |
  745. APE_EVENT_STATUS_SCRTCHPD_READ |
  746. APE_EVENT_STATUS_EVENT_PENDING;
  747. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
  748. tg3_ape_write32(tp, bufoff, base_off);
  749. tg3_ape_write32(tp, bufoff + sizeof(u32), length);
  750. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  751. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  752. base_off += length;
  753. if (tg3_ape_wait_for_event(tp, 30000))
  754. return -EAGAIN;
  755. for (i = 0; length; i += 4, length -= 4) {
  756. u32 val = tg3_ape_read32(tp, msgoff + i);
  757. memcpy(data, &val, sizeof(u32));
  758. data++;
  759. }
  760. }
  761. return 0;
  762. }
  763. static int tg3_ape_send_event(struct tg3 *tp, u32 event)
  764. {
  765. int err;
  766. u32 apedata;
  767. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  768. if (apedata != APE_SEG_SIG_MAGIC)
  769. return -EAGAIN;
  770. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  771. if (!(apedata & APE_FW_STATUS_READY))
  772. return -EAGAIN;
  773. /* Wait for up to 1 millisecond for APE to service previous event. */
  774. err = tg3_ape_event_lock(tp, 1000);
  775. if (err)
  776. return err;
  777. tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
  778. event | APE_EVENT_STATUS_EVENT_PENDING);
  779. tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
  780. tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
  781. return 0;
  782. }
  783. static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
  784. {
  785. u32 event;
  786. u32 apedata;
  787. if (!tg3_flag(tp, ENABLE_APE))
  788. return;
  789. switch (kind) {
  790. case RESET_KIND_INIT:
  791. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
  792. APE_HOST_SEG_SIG_MAGIC);
  793. tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
  794. APE_HOST_SEG_LEN_MAGIC);
  795. apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
  796. tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
  797. tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
  798. APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
  799. tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
  800. APE_HOST_BEHAV_NO_PHYLOCK);
  801. tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
  802. TG3_APE_HOST_DRVR_STATE_START);
  803. event = APE_EVENT_STATUS_STATE_START;
  804. break;
  805. case RESET_KIND_SHUTDOWN:
  806. /* With the interface we are currently using,
  807. * APE does not track driver state. Wiping
  808. * out the HOST SEGMENT SIGNATURE forces
  809. * the APE to assume OS absent status.
  810. */
  811. tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
  812. if (device_may_wakeup(&tp->pdev->dev) &&
  813. tg3_flag(tp, WOL_ENABLE)) {
  814. tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
  815. TG3_APE_HOST_WOL_SPEED_AUTO);
  816. apedata = TG3_APE_HOST_DRVR_STATE_WOL;
  817. } else
  818. apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
  819. tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
  820. event = APE_EVENT_STATUS_STATE_UNLOAD;
  821. break;
  822. case RESET_KIND_SUSPEND:
  823. event = APE_EVENT_STATUS_STATE_SUSPEND;
  824. break;
  825. default:
  826. return;
  827. }
  828. event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
  829. tg3_ape_send_event(tp, event);
  830. }
  831. static void tg3_disable_ints(struct tg3 *tp)
  832. {
  833. int i;
  834. tw32(TG3PCI_MISC_HOST_CTRL,
  835. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  836. for (i = 0; i < tp->irq_max; i++)
  837. tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
  838. }
  839. static void tg3_enable_ints(struct tg3 *tp)
  840. {
  841. int i;
  842. tp->irq_sync = 0;
  843. wmb();
  844. tw32(TG3PCI_MISC_HOST_CTRL,
  845. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  846. tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
  847. for (i = 0; i < tp->irq_cnt; i++) {
  848. struct tg3_napi *tnapi = &tp->napi[i];
  849. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  850. if (tg3_flag(tp, 1SHOT_MSI))
  851. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  852. tp->coal_now |= tnapi->coal_now;
  853. }
  854. /* Force an initial interrupt */
  855. if (!tg3_flag(tp, TAGGED_STATUS) &&
  856. (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
  857. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  858. else
  859. tw32(HOSTCC_MODE, tp->coal_now);
  860. tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
  861. }
  862. static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
  863. {
  864. struct tg3 *tp = tnapi->tp;
  865. struct tg3_hw_status *sblk = tnapi->hw_status;
  866. unsigned int work_exists = 0;
  867. /* check for phy events */
  868. if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
  869. if (sblk->status & SD_STATUS_LINK_CHG)
  870. work_exists = 1;
  871. }
  872. /* check for TX work to do */
  873. if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
  874. work_exists = 1;
  875. /* check for RX work to do */
  876. if (tnapi->rx_rcb_prod_idx &&
  877. *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  878. work_exists = 1;
  879. return work_exists;
  880. }
  881. /* tg3_int_reenable
  882. * similar to tg3_enable_ints, but it accurately determines whether there
  883. * is new work pending and can return without flushing the PIO write
  884. * which reenables interrupts
  885. */
  886. static void tg3_int_reenable(struct tg3_napi *tnapi)
  887. {
  888. struct tg3 *tp = tnapi->tp;
  889. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  890. mmiowb();
  891. /* When doing tagged status, this work check is unnecessary.
  892. * The last_tag we write above tells the chip which piece of
  893. * work we've completed.
  894. */
  895. if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
  896. tw32(HOSTCC_MODE, tp->coalesce_mode |
  897. HOSTCC_MODE_ENABLE | tnapi->coal_now);
  898. }
  899. static void tg3_switch_clocks(struct tg3 *tp)
  900. {
  901. u32 clock_ctrl;
  902. u32 orig_clock_ctrl;
  903. if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
  904. return;
  905. clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  906. orig_clock_ctrl = clock_ctrl;
  907. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  908. CLOCK_CTRL_CLKRUN_OENABLE |
  909. 0x1f);
  910. tp->pci_clock_ctrl = clock_ctrl;
  911. if (tg3_flag(tp, 5705_PLUS)) {
  912. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  913. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  914. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  915. }
  916. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  917. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  918. clock_ctrl |
  919. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  920. 40);
  921. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  922. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  923. 40);
  924. }
  925. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  926. }
  927. #define PHY_BUSY_LOOPS 5000
  928. static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
  929. u32 *val)
  930. {
  931. u32 frame_val;
  932. unsigned int loops;
  933. int ret;
  934. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  935. tw32_f(MAC_MI_MODE,
  936. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  937. udelay(80);
  938. }
  939. tg3_ape_lock(tp, tp->phy_ape_lock);
  940. *val = 0x0;
  941. frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  942. MI_COM_PHY_ADDR_MASK);
  943. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  944. MI_COM_REG_ADDR_MASK);
  945. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  946. tw32_f(MAC_MI_COM, frame_val);
  947. loops = PHY_BUSY_LOOPS;
  948. while (loops != 0) {
  949. udelay(10);
  950. frame_val = tr32(MAC_MI_COM);
  951. if ((frame_val & MI_COM_BUSY) == 0) {
  952. udelay(5);
  953. frame_val = tr32(MAC_MI_COM);
  954. break;
  955. }
  956. loops -= 1;
  957. }
  958. ret = -EBUSY;
  959. if (loops != 0) {
  960. *val = frame_val & MI_COM_DATA_MASK;
  961. ret = 0;
  962. }
  963. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  964. tw32_f(MAC_MI_MODE, tp->mi_mode);
  965. udelay(80);
  966. }
  967. tg3_ape_unlock(tp, tp->phy_ape_lock);
  968. return ret;
  969. }
  970. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  971. {
  972. return __tg3_readphy(tp, tp->phy_addr, reg, val);
  973. }
  974. static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
  975. u32 val)
  976. {
  977. u32 frame_val;
  978. unsigned int loops;
  979. int ret;
  980. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  981. (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
  982. return 0;
  983. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  984. tw32_f(MAC_MI_MODE,
  985. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  986. udelay(80);
  987. }
  988. tg3_ape_lock(tp, tp->phy_ape_lock);
  989. frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
  990. MI_COM_PHY_ADDR_MASK);
  991. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  992. MI_COM_REG_ADDR_MASK);
  993. frame_val |= (val & MI_COM_DATA_MASK);
  994. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  995. tw32_f(MAC_MI_COM, frame_val);
  996. loops = PHY_BUSY_LOOPS;
  997. while (loops != 0) {
  998. udelay(10);
  999. frame_val = tr32(MAC_MI_COM);
  1000. if ((frame_val & MI_COM_BUSY) == 0) {
  1001. udelay(5);
  1002. frame_val = tr32(MAC_MI_COM);
  1003. break;
  1004. }
  1005. loops -= 1;
  1006. }
  1007. ret = -EBUSY;
  1008. if (loops != 0)
  1009. ret = 0;
  1010. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  1011. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1012. udelay(80);
  1013. }
  1014. tg3_ape_unlock(tp, tp->phy_ape_lock);
  1015. return ret;
  1016. }
  1017. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  1018. {
  1019. return __tg3_writephy(tp, tp->phy_addr, reg, val);
  1020. }
  1021. static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
  1022. {
  1023. int err;
  1024. err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
  1025. if (err)
  1026. goto done;
  1027. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
  1028. if (err)
  1029. goto done;
  1030. err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
  1031. MII_TG3_MMD_CTRL_DATA_NOINC | devad);
  1032. if (err)
  1033. goto done;
  1034. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
  1035. done:
  1036. return err;
  1037. }
  1038. static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
  1039. {
  1040. int err;
  1041. err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
  1042. if (err)
  1043. goto done;
  1044. err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
  1045. if (err)
  1046. goto done;
  1047. err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
  1048. MII_TG3_MMD_CTRL_DATA_NOINC | devad);
  1049. if (err)
  1050. goto done;
  1051. err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
  1052. done:
  1053. return err;
  1054. }
  1055. static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
  1056. {
  1057. int err;
  1058. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1059. if (!err)
  1060. err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
  1061. return err;
  1062. }
  1063. static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
  1064. {
  1065. int err;
  1066. err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
  1067. if (!err)
  1068. err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
  1069. return err;
  1070. }
  1071. static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
  1072. {
  1073. int err;
  1074. err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
  1075. (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
  1076. MII_TG3_AUXCTL_SHDWSEL_MISC);
  1077. if (!err)
  1078. err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
  1079. return err;
  1080. }
  1081. static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
  1082. {
  1083. if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
  1084. set |= MII_TG3_AUXCTL_MISC_WREN;
  1085. return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
  1086. }
  1087. static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
  1088. {
  1089. u32 val;
  1090. int err;
  1091. err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  1092. if (err)
  1093. return err;
  1094. if (enable)
  1095. val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
  1096. else
  1097. val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
  1098. err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  1099. val | MII_TG3_AUXCTL_ACTL_TX_6DB);
  1100. return err;
  1101. }
  1102. static int tg3_bmcr_reset(struct tg3 *tp)
  1103. {
  1104. u32 phy_control;
  1105. int limit, err;
  1106. /* OK, reset it, and poll the BMCR_RESET bit until it
  1107. * clears or we time out.
  1108. */
  1109. phy_control = BMCR_RESET;
  1110. err = tg3_writephy(tp, MII_BMCR, phy_control);
  1111. if (err != 0)
  1112. return -EBUSY;
  1113. limit = 5000;
  1114. while (limit--) {
  1115. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  1116. if (err != 0)
  1117. return -EBUSY;
  1118. if ((phy_control & BMCR_RESET) == 0) {
  1119. udelay(40);
  1120. break;
  1121. }
  1122. udelay(10);
  1123. }
  1124. if (limit < 0)
  1125. return -EBUSY;
  1126. return 0;
  1127. }
  1128. static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
  1129. {
  1130. struct tg3 *tp = bp->priv;
  1131. u32 val;
  1132. spin_lock_bh(&tp->lock);
  1133. if (tg3_readphy(tp, reg, &val))
  1134. val = -EIO;
  1135. spin_unlock_bh(&tp->lock);
  1136. return val;
  1137. }
  1138. static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
  1139. {
  1140. struct tg3 *tp = bp->priv;
  1141. u32 ret = 0;
  1142. spin_lock_bh(&tp->lock);
  1143. if (tg3_writephy(tp, reg, val))
  1144. ret = -EIO;
  1145. spin_unlock_bh(&tp->lock);
  1146. return ret;
  1147. }
  1148. static int tg3_mdio_reset(struct mii_bus *bp)
  1149. {
  1150. return 0;
  1151. }
  1152. static void tg3_mdio_config_5785(struct tg3 *tp)
  1153. {
  1154. u32 val;
  1155. struct phy_device *phydev;
  1156. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1157. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  1158. case PHY_ID_BCM50610:
  1159. case PHY_ID_BCM50610M:
  1160. val = MAC_PHYCFG2_50610_LED_MODES;
  1161. break;
  1162. case PHY_ID_BCMAC131:
  1163. val = MAC_PHYCFG2_AC131_LED_MODES;
  1164. break;
  1165. case PHY_ID_RTL8211C:
  1166. val = MAC_PHYCFG2_RTL8211C_LED_MODES;
  1167. break;
  1168. case PHY_ID_RTL8201E:
  1169. val = MAC_PHYCFG2_RTL8201E_LED_MODES;
  1170. break;
  1171. default:
  1172. return;
  1173. }
  1174. if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
  1175. tw32(MAC_PHYCFG2, val);
  1176. val = tr32(MAC_PHYCFG1);
  1177. val &= ~(MAC_PHYCFG1_RGMII_INT |
  1178. MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
  1179. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
  1180. tw32(MAC_PHYCFG1, val);
  1181. return;
  1182. }
  1183. if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
  1184. val |= MAC_PHYCFG2_EMODE_MASK_MASK |
  1185. MAC_PHYCFG2_FMODE_MASK_MASK |
  1186. MAC_PHYCFG2_GMODE_MASK_MASK |
  1187. MAC_PHYCFG2_ACT_MASK_MASK |
  1188. MAC_PHYCFG2_QUAL_MASK_MASK |
  1189. MAC_PHYCFG2_INBAND_ENABLE;
  1190. tw32(MAC_PHYCFG2, val);
  1191. val = tr32(MAC_PHYCFG1);
  1192. val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
  1193. MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
  1194. if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
  1195. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1196. val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
  1197. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1198. val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
  1199. }
  1200. val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
  1201. MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
  1202. tw32(MAC_PHYCFG1, val);
  1203. val = tr32(MAC_EXT_RGMII_MODE);
  1204. val &= ~(MAC_RGMII_MODE_RX_INT_B |
  1205. MAC_RGMII_MODE_RX_QUALITY |
  1206. MAC_RGMII_MODE_RX_ACTIVITY |
  1207. MAC_RGMII_MODE_RX_ENG_DET |
  1208. MAC_RGMII_MODE_TX_ENABLE |
  1209. MAC_RGMII_MODE_TX_LOWPWR |
  1210. MAC_RGMII_MODE_TX_RESET);
  1211. if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
  1212. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1213. val |= MAC_RGMII_MODE_RX_INT_B |
  1214. MAC_RGMII_MODE_RX_QUALITY |
  1215. MAC_RGMII_MODE_RX_ACTIVITY |
  1216. MAC_RGMII_MODE_RX_ENG_DET;
  1217. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1218. val |= MAC_RGMII_MODE_TX_ENABLE |
  1219. MAC_RGMII_MODE_TX_LOWPWR |
  1220. MAC_RGMII_MODE_TX_RESET;
  1221. }
  1222. tw32(MAC_EXT_RGMII_MODE, val);
  1223. }
  1224. static void tg3_mdio_start(struct tg3 *tp)
  1225. {
  1226. tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
  1227. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1228. udelay(80);
  1229. if (tg3_flag(tp, MDIOBUS_INITED) &&
  1230. tg3_asic_rev(tp) == ASIC_REV_5785)
  1231. tg3_mdio_config_5785(tp);
  1232. }
  1233. static int tg3_mdio_init(struct tg3 *tp)
  1234. {
  1235. int i;
  1236. u32 reg;
  1237. struct phy_device *phydev;
  1238. if (tg3_flag(tp, 5717_PLUS)) {
  1239. u32 is_serdes;
  1240. tp->phy_addr = tp->pci_fn + 1;
  1241. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
  1242. is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
  1243. else
  1244. is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
  1245. TG3_CPMU_PHY_STRAP_IS_SERDES;
  1246. if (is_serdes)
  1247. tp->phy_addr += 7;
  1248. } else
  1249. tp->phy_addr = TG3_PHY_MII_ADDR;
  1250. tg3_mdio_start(tp);
  1251. if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
  1252. return 0;
  1253. tp->mdio_bus = mdiobus_alloc();
  1254. if (tp->mdio_bus == NULL)
  1255. return -ENOMEM;
  1256. tp->mdio_bus->name = "tg3 mdio bus";
  1257. snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
  1258. (tp->pdev->bus->number << 8) | tp->pdev->devfn);
  1259. tp->mdio_bus->priv = tp;
  1260. tp->mdio_bus->parent = &tp->pdev->dev;
  1261. tp->mdio_bus->read = &tg3_mdio_read;
  1262. tp->mdio_bus->write = &tg3_mdio_write;
  1263. tp->mdio_bus->reset = &tg3_mdio_reset;
  1264. tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
  1265. tp->mdio_bus->irq = &tp->mdio_irq[0];
  1266. for (i = 0; i < PHY_MAX_ADDR; i++)
  1267. tp->mdio_bus->irq[i] = PHY_POLL;
  1268. /* The bus registration will look for all the PHYs on the mdio bus.
  1269. * Unfortunately, it does not ensure the PHY is powered up before
  1270. * accessing the PHY ID registers. A chip reset is the
  1271. * quickest way to bring the device back to an operational state..
  1272. */
  1273. if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
  1274. tg3_bmcr_reset(tp);
  1275. i = mdiobus_register(tp->mdio_bus);
  1276. if (i) {
  1277. dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
  1278. mdiobus_free(tp->mdio_bus);
  1279. return i;
  1280. }
  1281. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1282. if (!phydev || !phydev->drv) {
  1283. dev_warn(&tp->pdev->dev, "No PHY devices\n");
  1284. mdiobus_unregister(tp->mdio_bus);
  1285. mdiobus_free(tp->mdio_bus);
  1286. return -ENODEV;
  1287. }
  1288. switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
  1289. case PHY_ID_BCM57780:
  1290. phydev->interface = PHY_INTERFACE_MODE_GMII;
  1291. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1292. break;
  1293. case PHY_ID_BCM50610:
  1294. case PHY_ID_BCM50610M:
  1295. phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
  1296. PHY_BRCM_RX_REFCLK_UNUSED |
  1297. PHY_BRCM_DIS_TXCRXC_NOENRGY |
  1298. PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1299. if (tg3_flag(tp, RGMII_INBAND_DISABLE))
  1300. phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
  1301. if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
  1302. phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
  1303. if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
  1304. phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
  1305. /* fallthru */
  1306. case PHY_ID_RTL8211C:
  1307. phydev->interface = PHY_INTERFACE_MODE_RGMII;
  1308. break;
  1309. case PHY_ID_RTL8201E:
  1310. case PHY_ID_BCMAC131:
  1311. phydev->interface = PHY_INTERFACE_MODE_MII;
  1312. phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
  1313. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  1314. break;
  1315. }
  1316. tg3_flag_set(tp, MDIOBUS_INITED);
  1317. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  1318. tg3_mdio_config_5785(tp);
  1319. return 0;
  1320. }
  1321. static void tg3_mdio_fini(struct tg3 *tp)
  1322. {
  1323. if (tg3_flag(tp, MDIOBUS_INITED)) {
  1324. tg3_flag_clear(tp, MDIOBUS_INITED);
  1325. mdiobus_unregister(tp->mdio_bus);
  1326. mdiobus_free(tp->mdio_bus);
  1327. }
  1328. }
  1329. /* tp->lock is held. */
  1330. static inline void tg3_generate_fw_event(struct tg3 *tp)
  1331. {
  1332. u32 val;
  1333. val = tr32(GRC_RX_CPU_EVENT);
  1334. val |= GRC_RX_CPU_DRIVER_EVENT;
  1335. tw32_f(GRC_RX_CPU_EVENT, val);
  1336. tp->last_event_jiffies = jiffies;
  1337. }
  1338. #define TG3_FW_EVENT_TIMEOUT_USEC 2500
  1339. /* tp->lock is held. */
  1340. static void tg3_wait_for_event_ack(struct tg3 *tp)
  1341. {
  1342. int i;
  1343. unsigned int delay_cnt;
  1344. long time_remain;
  1345. /* If enough time has passed, no wait is necessary. */
  1346. time_remain = (long)(tp->last_event_jiffies + 1 +
  1347. usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
  1348. (long)jiffies;
  1349. if (time_remain < 0)
  1350. return;
  1351. /* Check if we can shorten the wait time. */
  1352. delay_cnt = jiffies_to_usecs(time_remain);
  1353. if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
  1354. delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
  1355. delay_cnt = (delay_cnt >> 3) + 1;
  1356. for (i = 0; i < delay_cnt; i++) {
  1357. if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
  1358. break;
  1359. udelay(8);
  1360. }
  1361. }
  1362. /* tp->lock is held. */
  1363. static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
  1364. {
  1365. u32 reg, val;
  1366. val = 0;
  1367. if (!tg3_readphy(tp, MII_BMCR, &reg))
  1368. val = reg << 16;
  1369. if (!tg3_readphy(tp, MII_BMSR, &reg))
  1370. val |= (reg & 0xffff);
  1371. *data++ = val;
  1372. val = 0;
  1373. if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
  1374. val = reg << 16;
  1375. if (!tg3_readphy(tp, MII_LPA, &reg))
  1376. val |= (reg & 0xffff);
  1377. *data++ = val;
  1378. val = 0;
  1379. if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
  1380. if (!tg3_readphy(tp, MII_CTRL1000, &reg))
  1381. val = reg << 16;
  1382. if (!tg3_readphy(tp, MII_STAT1000, &reg))
  1383. val |= (reg & 0xffff);
  1384. }
  1385. *data++ = val;
  1386. if (!tg3_readphy(tp, MII_PHYADDR, &reg))
  1387. val = reg << 16;
  1388. else
  1389. val = 0;
  1390. *data++ = val;
  1391. }
  1392. /* tp->lock is held. */
  1393. static void tg3_ump_link_report(struct tg3 *tp)
  1394. {
  1395. u32 data[4];
  1396. if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
  1397. return;
  1398. tg3_phy_gather_ump_data(tp, data);
  1399. tg3_wait_for_event_ack(tp);
  1400. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
  1401. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
  1402. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
  1403. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
  1404. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
  1405. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
  1406. tg3_generate_fw_event(tp);
  1407. }
  1408. /* tp->lock is held. */
  1409. static void tg3_stop_fw(struct tg3 *tp)
  1410. {
  1411. if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
  1412. /* Wait for RX cpu to ACK the previous event. */
  1413. tg3_wait_for_event_ack(tp);
  1414. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  1415. tg3_generate_fw_event(tp);
  1416. /* Wait for RX cpu to ACK this event. */
  1417. tg3_wait_for_event_ack(tp);
  1418. }
  1419. }
  1420. /* tp->lock is held. */
  1421. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  1422. {
  1423. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  1424. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  1425. if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
  1426. switch (kind) {
  1427. case RESET_KIND_INIT:
  1428. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1429. DRV_STATE_START);
  1430. break;
  1431. case RESET_KIND_SHUTDOWN:
  1432. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1433. DRV_STATE_UNLOAD);
  1434. break;
  1435. case RESET_KIND_SUSPEND:
  1436. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1437. DRV_STATE_SUSPEND);
  1438. break;
  1439. default:
  1440. break;
  1441. }
  1442. }
  1443. if (kind == RESET_KIND_INIT ||
  1444. kind == RESET_KIND_SUSPEND)
  1445. tg3_ape_driver_state_change(tp, kind);
  1446. }
  1447. /* tp->lock is held. */
  1448. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  1449. {
  1450. if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
  1451. switch (kind) {
  1452. case RESET_KIND_INIT:
  1453. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1454. DRV_STATE_START_DONE);
  1455. break;
  1456. case RESET_KIND_SHUTDOWN:
  1457. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1458. DRV_STATE_UNLOAD_DONE);
  1459. break;
  1460. default:
  1461. break;
  1462. }
  1463. }
  1464. if (kind == RESET_KIND_SHUTDOWN)
  1465. tg3_ape_driver_state_change(tp, kind);
  1466. }
  1467. /* tp->lock is held. */
  1468. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  1469. {
  1470. if (tg3_flag(tp, ENABLE_ASF)) {
  1471. switch (kind) {
  1472. case RESET_KIND_INIT:
  1473. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1474. DRV_STATE_START);
  1475. break;
  1476. case RESET_KIND_SHUTDOWN:
  1477. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1478. DRV_STATE_UNLOAD);
  1479. break;
  1480. case RESET_KIND_SUSPEND:
  1481. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  1482. DRV_STATE_SUSPEND);
  1483. break;
  1484. default:
  1485. break;
  1486. }
  1487. }
  1488. }
  1489. static int tg3_poll_fw(struct tg3 *tp)
  1490. {
  1491. int i;
  1492. u32 val;
  1493. if (tg3_flag(tp, IS_SSB_CORE)) {
  1494. /* We don't use firmware. */
  1495. return 0;
  1496. }
  1497. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  1498. /* Wait up to 20ms for init done. */
  1499. for (i = 0; i < 200; i++) {
  1500. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  1501. return 0;
  1502. udelay(100);
  1503. }
  1504. return -ENODEV;
  1505. }
  1506. /* Wait for firmware initialization to complete. */
  1507. for (i = 0; i < 100000; i++) {
  1508. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  1509. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1510. break;
  1511. udelay(10);
  1512. }
  1513. /* Chip might not be fitted with firmware. Some Sun onboard
  1514. * parts are configured like that. So don't signal the timeout
  1515. * of the above loop as an error, but do report the lack of
  1516. * running firmware once.
  1517. */
  1518. if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
  1519. tg3_flag_set(tp, NO_FWARE_REPORTED);
  1520. netdev_info(tp->dev, "No firmware running\n");
  1521. }
  1522. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
  1523. /* The 57765 A0 needs a little more
  1524. * time to do some important work.
  1525. */
  1526. mdelay(10);
  1527. }
  1528. return 0;
  1529. }
  1530. static void tg3_link_report(struct tg3 *tp)
  1531. {
  1532. if (!netif_carrier_ok(tp->dev)) {
  1533. netif_info(tp, link, tp->dev, "Link is down\n");
  1534. tg3_ump_link_report(tp);
  1535. } else if (netif_msg_link(tp)) {
  1536. netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
  1537. (tp->link_config.active_speed == SPEED_1000 ?
  1538. 1000 :
  1539. (tp->link_config.active_speed == SPEED_100 ?
  1540. 100 : 10)),
  1541. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1542. "full" : "half"));
  1543. netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
  1544. (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
  1545. "on" : "off",
  1546. (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
  1547. "on" : "off");
  1548. if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
  1549. netdev_info(tp->dev, "EEE is %s\n",
  1550. tp->setlpicnt ? "enabled" : "disabled");
  1551. tg3_ump_link_report(tp);
  1552. }
  1553. tp->link_up = netif_carrier_ok(tp->dev);
  1554. }
  1555. static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
  1556. {
  1557. u16 miireg;
  1558. if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
  1559. miireg = ADVERTISE_1000XPAUSE;
  1560. else if (flow_ctrl & FLOW_CTRL_TX)
  1561. miireg = ADVERTISE_1000XPSE_ASYM;
  1562. else if (flow_ctrl & FLOW_CTRL_RX)
  1563. miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  1564. else
  1565. miireg = 0;
  1566. return miireg;
  1567. }
  1568. static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
  1569. {
  1570. u8 cap = 0;
  1571. if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
  1572. cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
  1573. } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
  1574. if (lcladv & ADVERTISE_1000XPAUSE)
  1575. cap = FLOW_CTRL_RX;
  1576. if (rmtadv & ADVERTISE_1000XPAUSE)
  1577. cap = FLOW_CTRL_TX;
  1578. }
  1579. return cap;
  1580. }
  1581. static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
  1582. {
  1583. u8 autoneg;
  1584. u8 flowctrl = 0;
  1585. u32 old_rx_mode = tp->rx_mode;
  1586. u32 old_tx_mode = tp->tx_mode;
  1587. if (tg3_flag(tp, USE_PHYLIB))
  1588. autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
  1589. else
  1590. autoneg = tp->link_config.autoneg;
  1591. if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
  1592. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  1593. flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
  1594. else
  1595. flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  1596. } else
  1597. flowctrl = tp->link_config.flowctrl;
  1598. tp->link_config.active_flowctrl = flowctrl;
  1599. if (flowctrl & FLOW_CTRL_RX)
  1600. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1601. else
  1602. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1603. if (old_rx_mode != tp->rx_mode)
  1604. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1605. if (flowctrl & FLOW_CTRL_TX)
  1606. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1607. else
  1608. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1609. if (old_tx_mode != tp->tx_mode)
  1610. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1611. }
  1612. static void tg3_adjust_link(struct net_device *dev)
  1613. {
  1614. u8 oldflowctrl, linkmesg = 0;
  1615. u32 mac_mode, lcl_adv, rmt_adv;
  1616. struct tg3 *tp = netdev_priv(dev);
  1617. struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1618. spin_lock_bh(&tp->lock);
  1619. mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
  1620. MAC_MODE_HALF_DUPLEX);
  1621. oldflowctrl = tp->link_config.active_flowctrl;
  1622. if (phydev->link) {
  1623. lcl_adv = 0;
  1624. rmt_adv = 0;
  1625. if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
  1626. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1627. else if (phydev->speed == SPEED_1000 ||
  1628. tg3_asic_rev(tp) != ASIC_REV_5785)
  1629. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1630. else
  1631. mac_mode |= MAC_MODE_PORT_MODE_MII;
  1632. if (phydev->duplex == DUPLEX_HALF)
  1633. mac_mode |= MAC_MODE_HALF_DUPLEX;
  1634. else {
  1635. lcl_adv = mii_advertise_flowctrl(
  1636. tp->link_config.flowctrl);
  1637. if (phydev->pause)
  1638. rmt_adv = LPA_PAUSE_CAP;
  1639. if (phydev->asym_pause)
  1640. rmt_adv |= LPA_PAUSE_ASYM;
  1641. }
  1642. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  1643. } else
  1644. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1645. if (mac_mode != tp->mac_mode) {
  1646. tp->mac_mode = mac_mode;
  1647. tw32_f(MAC_MODE, tp->mac_mode);
  1648. udelay(40);
  1649. }
  1650. if (tg3_asic_rev(tp) == ASIC_REV_5785) {
  1651. if (phydev->speed == SPEED_10)
  1652. tw32(MAC_MI_STAT,
  1653. MAC_MI_STAT_10MBPS_MODE |
  1654. MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1655. else
  1656. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  1657. }
  1658. if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
  1659. tw32(MAC_TX_LENGTHS,
  1660. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1661. (6 << TX_LENGTHS_IPG_SHIFT) |
  1662. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1663. else
  1664. tw32(MAC_TX_LENGTHS,
  1665. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  1666. (6 << TX_LENGTHS_IPG_SHIFT) |
  1667. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  1668. if (phydev->link != tp->old_link ||
  1669. phydev->speed != tp->link_config.active_speed ||
  1670. phydev->duplex != tp->link_config.active_duplex ||
  1671. oldflowctrl != tp->link_config.active_flowctrl)
  1672. linkmesg = 1;
  1673. tp->old_link = phydev->link;
  1674. tp->link_config.active_speed = phydev->speed;
  1675. tp->link_config.active_duplex = phydev->duplex;
  1676. spin_unlock_bh(&tp->lock);
  1677. if (linkmesg)
  1678. tg3_link_report(tp);
  1679. }
  1680. static int tg3_phy_init(struct tg3 *tp)
  1681. {
  1682. struct phy_device *phydev;
  1683. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
  1684. return 0;
  1685. /* Bring the PHY back to a known state. */
  1686. tg3_bmcr_reset(tp);
  1687. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1688. /* Attach the MAC to the PHY. */
  1689. phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
  1690. tg3_adjust_link, phydev->interface);
  1691. if (IS_ERR(phydev)) {
  1692. dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
  1693. return PTR_ERR(phydev);
  1694. }
  1695. /* Mask with MAC supported features. */
  1696. switch (phydev->interface) {
  1697. case PHY_INTERFACE_MODE_GMII:
  1698. case PHY_INTERFACE_MODE_RGMII:
  1699. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  1700. phydev->supported &= (PHY_GBIT_FEATURES |
  1701. SUPPORTED_Pause |
  1702. SUPPORTED_Asym_Pause);
  1703. break;
  1704. }
  1705. /* fallthru */
  1706. case PHY_INTERFACE_MODE_MII:
  1707. phydev->supported &= (PHY_BASIC_FEATURES |
  1708. SUPPORTED_Pause |
  1709. SUPPORTED_Asym_Pause);
  1710. break;
  1711. default:
  1712. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1713. return -EINVAL;
  1714. }
  1715. tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
  1716. phydev->advertising = phydev->supported;
  1717. return 0;
  1718. }
  1719. static void tg3_phy_start(struct tg3 *tp)
  1720. {
  1721. struct phy_device *phydev;
  1722. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1723. return;
  1724. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  1725. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  1726. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  1727. phydev->speed = tp->link_config.speed;
  1728. phydev->duplex = tp->link_config.duplex;
  1729. phydev->autoneg = tp->link_config.autoneg;
  1730. phydev->advertising = tp->link_config.advertising;
  1731. }
  1732. phy_start(phydev);
  1733. phy_start_aneg(phydev);
  1734. }
  1735. static void tg3_phy_stop(struct tg3 *tp)
  1736. {
  1737. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  1738. return;
  1739. phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1740. }
  1741. static void tg3_phy_fini(struct tg3 *tp)
  1742. {
  1743. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  1744. phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  1745. tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
  1746. }
  1747. }
  1748. static int tg3_phy_set_extloopbk(struct tg3 *tp)
  1749. {
  1750. int err;
  1751. u32 val;
  1752. if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  1753. return 0;
  1754. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  1755. /* Cannot do read-modify-write on 5401 */
  1756. err = tg3_phy_auxctl_write(tp,
  1757. MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  1758. MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
  1759. 0x4c20);
  1760. goto done;
  1761. }
  1762. err = tg3_phy_auxctl_read(tp,
  1763. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  1764. if (err)
  1765. return err;
  1766. val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
  1767. err = tg3_phy_auxctl_write(tp,
  1768. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
  1769. done:
  1770. return err;
  1771. }
  1772. static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
  1773. {
  1774. u32 phytest;
  1775. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  1776. u32 phy;
  1777. tg3_writephy(tp, MII_TG3_FET_TEST,
  1778. phytest | MII_TG3_FET_SHADOW_EN);
  1779. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
  1780. if (enable)
  1781. phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1782. else
  1783. phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
  1784. tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
  1785. }
  1786. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  1787. }
  1788. }
  1789. static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
  1790. {
  1791. u32 reg;
  1792. if (!tg3_flag(tp, 5705_PLUS) ||
  1793. (tg3_flag(tp, 5717_PLUS) &&
  1794. (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
  1795. return;
  1796. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1797. tg3_phy_fet_toggle_apd(tp, enable);
  1798. return;
  1799. }
  1800. reg = MII_TG3_MISC_SHDW_WREN |
  1801. MII_TG3_MISC_SHDW_SCR5_SEL |
  1802. MII_TG3_MISC_SHDW_SCR5_LPED |
  1803. MII_TG3_MISC_SHDW_SCR5_DLPTLM |
  1804. MII_TG3_MISC_SHDW_SCR5_SDTL |
  1805. MII_TG3_MISC_SHDW_SCR5_C125OE;
  1806. if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
  1807. reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
  1808. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1809. reg = MII_TG3_MISC_SHDW_WREN |
  1810. MII_TG3_MISC_SHDW_APD_SEL |
  1811. MII_TG3_MISC_SHDW_APD_WKTM_84MS;
  1812. if (enable)
  1813. reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
  1814. tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
  1815. }
  1816. static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
  1817. {
  1818. u32 phy;
  1819. if (!tg3_flag(tp, 5705_PLUS) ||
  1820. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  1821. return;
  1822. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  1823. u32 ephy;
  1824. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
  1825. u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
  1826. tg3_writephy(tp, MII_TG3_FET_TEST,
  1827. ephy | MII_TG3_FET_SHADOW_EN);
  1828. if (!tg3_readphy(tp, reg, &phy)) {
  1829. if (enable)
  1830. phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1831. else
  1832. phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
  1833. tg3_writephy(tp, reg, phy);
  1834. }
  1835. tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
  1836. }
  1837. } else {
  1838. int ret;
  1839. ret = tg3_phy_auxctl_read(tp,
  1840. MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
  1841. if (!ret) {
  1842. if (enable)
  1843. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1844. else
  1845. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  1846. tg3_phy_auxctl_write(tp,
  1847. MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
  1848. }
  1849. }
  1850. }
  1851. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  1852. {
  1853. int ret;
  1854. u32 val;
  1855. if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
  1856. return;
  1857. ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
  1858. if (!ret)
  1859. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
  1860. val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
  1861. }
  1862. static void tg3_phy_apply_otp(struct tg3 *tp)
  1863. {
  1864. u32 otp, phy;
  1865. if (!tp->phy_otp)
  1866. return;
  1867. otp = tp->phy_otp;
  1868. if (tg3_phy_toggle_auxctl_smdsp(tp, true))
  1869. return;
  1870. phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
  1871. phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
  1872. tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
  1873. phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
  1874. ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
  1875. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
  1876. phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
  1877. phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
  1878. tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
  1879. phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
  1880. tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
  1881. phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
  1882. tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
  1883. phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
  1884. ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
  1885. tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
  1886. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1887. }
  1888. static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
  1889. {
  1890. u32 val;
  1891. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  1892. return;
  1893. tp->setlpicnt = 0;
  1894. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  1895. current_link_up == 1 &&
  1896. tp->link_config.active_duplex == DUPLEX_FULL &&
  1897. (tp->link_config.active_speed == SPEED_100 ||
  1898. tp->link_config.active_speed == SPEED_1000)) {
  1899. u32 eeectl;
  1900. if (tp->link_config.active_speed == SPEED_1000)
  1901. eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
  1902. else
  1903. eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
  1904. tw32(TG3_CPMU_EEE_CTRL, eeectl);
  1905. tg3_phy_cl45_read(tp, MDIO_MMD_AN,
  1906. TG3_CL45_D7_EEERES_STAT, &val);
  1907. if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
  1908. val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
  1909. tp->setlpicnt = 2;
  1910. }
  1911. if (!tp->setlpicnt) {
  1912. if (current_link_up == 1 &&
  1913. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  1914. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
  1915. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1916. }
  1917. val = tr32(TG3_CPMU_EEE_MODE);
  1918. tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
  1919. }
  1920. }
  1921. static void tg3_phy_eee_enable(struct tg3 *tp)
  1922. {
  1923. u32 val;
  1924. if (tp->link_config.active_speed == SPEED_1000 &&
  1925. (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  1926. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  1927. tg3_flag(tp, 57765_CLASS)) &&
  1928. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  1929. val = MII_TG3_DSP_TAP26_ALNOKO |
  1930. MII_TG3_DSP_TAP26_RMRXSTO;
  1931. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
  1932. tg3_phy_toggle_auxctl_smdsp(tp, false);
  1933. }
  1934. val = tr32(TG3_CPMU_EEE_MODE);
  1935. tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
  1936. }
  1937. static int tg3_wait_macro_done(struct tg3 *tp)
  1938. {
  1939. int limit = 100;
  1940. while (limit--) {
  1941. u32 tmp32;
  1942. if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
  1943. if ((tmp32 & 0x1000) == 0)
  1944. break;
  1945. }
  1946. }
  1947. if (limit < 0)
  1948. return -EBUSY;
  1949. return 0;
  1950. }
  1951. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  1952. {
  1953. static const u32 test_pat[4][6] = {
  1954. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  1955. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  1956. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  1957. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  1958. };
  1959. int chan;
  1960. for (chan = 0; chan < 4; chan++) {
  1961. int i;
  1962. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1963. (chan * 0x2000) | 0x0200);
  1964. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  1965. for (i = 0; i < 6; i++)
  1966. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  1967. test_pat[chan][i]);
  1968. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  1969. if (tg3_wait_macro_done(tp)) {
  1970. *resetp = 1;
  1971. return -EBUSY;
  1972. }
  1973. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  1974. (chan * 0x2000) | 0x0200);
  1975. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
  1976. if (tg3_wait_macro_done(tp)) {
  1977. *resetp = 1;
  1978. return -EBUSY;
  1979. }
  1980. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
  1981. if (tg3_wait_macro_done(tp)) {
  1982. *resetp = 1;
  1983. return -EBUSY;
  1984. }
  1985. for (i = 0; i < 6; i += 2) {
  1986. u32 low, high;
  1987. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  1988. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  1989. tg3_wait_macro_done(tp)) {
  1990. *resetp = 1;
  1991. return -EBUSY;
  1992. }
  1993. low &= 0x7fff;
  1994. high &= 0x000f;
  1995. if (low != test_pat[chan][i] ||
  1996. high != test_pat[chan][i+1]) {
  1997. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  1998. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  1999. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  2000. return -EBUSY;
  2001. }
  2002. }
  2003. }
  2004. return 0;
  2005. }
  2006. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  2007. {
  2008. int chan;
  2009. for (chan = 0; chan < 4; chan++) {
  2010. int i;
  2011. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  2012. (chan * 0x2000) | 0x0200);
  2013. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
  2014. for (i = 0; i < 6; i++)
  2015. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  2016. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
  2017. if (tg3_wait_macro_done(tp))
  2018. return -EBUSY;
  2019. }
  2020. return 0;
  2021. }
  2022. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  2023. {
  2024. u32 reg32, phy9_orig;
  2025. int retries, do_phy_reset, err;
  2026. retries = 10;
  2027. do_phy_reset = 1;
  2028. do {
  2029. if (do_phy_reset) {
  2030. err = tg3_bmcr_reset(tp);
  2031. if (err)
  2032. return err;
  2033. do_phy_reset = 0;
  2034. }
  2035. /* Disable transmitter and interrupt. */
  2036. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  2037. continue;
  2038. reg32 |= 0x3000;
  2039. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  2040. /* Set full-duplex, 1000 mbps. */
  2041. tg3_writephy(tp, MII_BMCR,
  2042. BMCR_FULLDPLX | BMCR_SPEED1000);
  2043. /* Set to master mode. */
  2044. if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
  2045. continue;
  2046. tg3_writephy(tp, MII_CTRL1000,
  2047. CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
  2048. err = tg3_phy_toggle_auxctl_smdsp(tp, true);
  2049. if (err)
  2050. return err;
  2051. /* Block the PHY control access. */
  2052. tg3_phydsp_write(tp, 0x8005, 0x0800);
  2053. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  2054. if (!err)
  2055. break;
  2056. } while (--retries);
  2057. err = tg3_phy_reset_chanpat(tp);
  2058. if (err)
  2059. return err;
  2060. tg3_phydsp_write(tp, 0x8005, 0x0000);
  2061. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  2062. tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
  2063. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2064. tg3_writephy(tp, MII_CTRL1000, phy9_orig);
  2065. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  2066. reg32 &= ~0x3000;
  2067. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  2068. } else if (!err)
  2069. err = -EBUSY;
  2070. return err;
  2071. }
  2072. static void tg3_carrier_off(struct tg3 *tp)
  2073. {
  2074. netif_carrier_off(tp->dev);
  2075. tp->link_up = false;
  2076. }
  2077. /* This will reset the tigon3 PHY if there is no valid
  2078. * link unless the FORCE argument is non-zero.
  2079. */
  2080. static int tg3_phy_reset(struct tg3 *tp)
  2081. {
  2082. u32 val, cpmuctrl;
  2083. int err;
  2084. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2085. val = tr32(GRC_MISC_CFG);
  2086. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  2087. udelay(40);
  2088. }
  2089. err = tg3_readphy(tp, MII_BMSR, &val);
  2090. err |= tg3_readphy(tp, MII_BMSR, &val);
  2091. if (err != 0)
  2092. return -EBUSY;
  2093. if (netif_running(tp->dev) && tp->link_up) {
  2094. netif_carrier_off(tp->dev);
  2095. tg3_link_report(tp);
  2096. }
  2097. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  2098. tg3_asic_rev(tp) == ASIC_REV_5704 ||
  2099. tg3_asic_rev(tp) == ASIC_REV_5705) {
  2100. err = tg3_phy_reset_5703_4_5(tp);
  2101. if (err)
  2102. return err;
  2103. goto out;
  2104. }
  2105. cpmuctrl = 0;
  2106. if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  2107. tg3_chip_rev(tp) != CHIPREV_5784_AX) {
  2108. cpmuctrl = tr32(TG3_CPMU_CTRL);
  2109. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
  2110. tw32(TG3_CPMU_CTRL,
  2111. cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
  2112. }
  2113. err = tg3_bmcr_reset(tp);
  2114. if (err)
  2115. return err;
  2116. if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
  2117. val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
  2118. tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
  2119. tw32(TG3_CPMU_CTRL, cpmuctrl);
  2120. }
  2121. if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
  2122. tg3_chip_rev(tp) == CHIPREV_5761_AX) {
  2123. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  2124. if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
  2125. CPMU_LSPD_1000MB_MACCLK_12_5) {
  2126. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  2127. udelay(40);
  2128. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  2129. }
  2130. }
  2131. if (tg3_flag(tp, 5717_PLUS) &&
  2132. (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
  2133. return 0;
  2134. tg3_phy_apply_otp(tp);
  2135. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  2136. tg3_phy_toggle_apd(tp, true);
  2137. else
  2138. tg3_phy_toggle_apd(tp, false);
  2139. out:
  2140. if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
  2141. !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2142. tg3_phydsp_write(tp, 0x201f, 0x2aaa);
  2143. tg3_phydsp_write(tp, 0x000a, 0x0323);
  2144. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2145. }
  2146. if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
  2147. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  2148. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  2149. }
  2150. if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
  2151. if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2152. tg3_phydsp_write(tp, 0x000a, 0x310b);
  2153. tg3_phydsp_write(tp, 0x201f, 0x9506);
  2154. tg3_phydsp_write(tp, 0x401f, 0x14e2);
  2155. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2156. }
  2157. } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
  2158. if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
  2159. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  2160. if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
  2161. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  2162. tg3_writephy(tp, MII_TG3_TEST1,
  2163. MII_TG3_TEST1_TRIM_EN | 0x4);
  2164. } else
  2165. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  2166. tg3_phy_toggle_auxctl_smdsp(tp, false);
  2167. }
  2168. }
  2169. /* Set Extended packet length bit (bit 14) on all chips that */
  2170. /* support jumbo frames */
  2171. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  2172. /* Cannot do read-modify-write on 5401 */
  2173. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
  2174. } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
  2175. /* Set bit 14 with read-modify-write to preserve other bits */
  2176. err = tg3_phy_auxctl_read(tp,
  2177. MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
  2178. if (!err)
  2179. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
  2180. val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
  2181. }
  2182. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  2183. * jumbo frames transmission.
  2184. */
  2185. if (tg3_flag(tp, JUMBO_CAPABLE)) {
  2186. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
  2187. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2188. val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  2189. }
  2190. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2191. /* adjust output voltage */
  2192. tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
  2193. }
  2194. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
  2195. tg3_phydsp_write(tp, 0xffb, 0x4000);
  2196. tg3_phy_toggle_automdix(tp, 1);
  2197. tg3_phy_set_wirespeed(tp);
  2198. return 0;
  2199. }
  2200. #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
  2201. #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
  2202. #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
  2203. TG3_GPIO_MSG_NEED_VAUX)
  2204. #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
  2205. ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
  2206. (TG3_GPIO_MSG_DRVR_PRES << 4) | \
  2207. (TG3_GPIO_MSG_DRVR_PRES << 8) | \
  2208. (TG3_GPIO_MSG_DRVR_PRES << 12))
  2209. #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
  2210. ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
  2211. (TG3_GPIO_MSG_NEED_VAUX << 4) | \
  2212. (TG3_GPIO_MSG_NEED_VAUX << 8) | \
  2213. (TG3_GPIO_MSG_NEED_VAUX << 12))
  2214. static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
  2215. {
  2216. u32 status, shift;
  2217. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2218. tg3_asic_rev(tp) == ASIC_REV_5719)
  2219. status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
  2220. else
  2221. status = tr32(TG3_CPMU_DRV_STATUS);
  2222. shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
  2223. status &= ~(TG3_GPIO_MSG_MASK << shift);
  2224. status |= (newstat << shift);
  2225. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2226. tg3_asic_rev(tp) == ASIC_REV_5719)
  2227. tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
  2228. else
  2229. tw32(TG3_CPMU_DRV_STATUS, status);
  2230. return status >> TG3_APE_GPIO_MSG_SHIFT;
  2231. }
  2232. static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
  2233. {
  2234. if (!tg3_flag(tp, IS_NIC))
  2235. return 0;
  2236. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2237. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  2238. tg3_asic_rev(tp) == ASIC_REV_5720) {
  2239. if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
  2240. return -EIO;
  2241. tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
  2242. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
  2243. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2244. tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
  2245. } else {
  2246. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
  2247. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2248. }
  2249. return 0;
  2250. }
  2251. static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
  2252. {
  2253. u32 grc_local_ctrl;
  2254. if (!tg3_flag(tp, IS_NIC) ||
  2255. tg3_asic_rev(tp) == ASIC_REV_5700 ||
  2256. tg3_asic_rev(tp) == ASIC_REV_5701)
  2257. return;
  2258. grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
  2259. tw32_wait_f(GRC_LOCAL_CTRL,
  2260. grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
  2261. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2262. tw32_wait_f(GRC_LOCAL_CTRL,
  2263. grc_local_ctrl,
  2264. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2265. tw32_wait_f(GRC_LOCAL_CTRL,
  2266. grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
  2267. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2268. }
  2269. static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
  2270. {
  2271. if (!tg3_flag(tp, IS_NIC))
  2272. return;
  2273. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  2274. tg3_asic_rev(tp) == ASIC_REV_5701) {
  2275. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  2276. (GRC_LCLCTRL_GPIO_OE0 |
  2277. GRC_LCLCTRL_GPIO_OE1 |
  2278. GRC_LCLCTRL_GPIO_OE2 |
  2279. GRC_LCLCTRL_GPIO_OUTPUT0 |
  2280. GRC_LCLCTRL_GPIO_OUTPUT1),
  2281. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2282. } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  2283. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  2284. /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
  2285. u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
  2286. GRC_LCLCTRL_GPIO_OE1 |
  2287. GRC_LCLCTRL_GPIO_OE2 |
  2288. GRC_LCLCTRL_GPIO_OUTPUT0 |
  2289. GRC_LCLCTRL_GPIO_OUTPUT1 |
  2290. tp->grc_local_ctrl;
  2291. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2292. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2293. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
  2294. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2295. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2296. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
  2297. tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
  2298. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2299. } else {
  2300. u32 no_gpio2;
  2301. u32 grc_local_ctrl = 0;
  2302. /* Workaround to prevent overdrawing Amps. */
  2303. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  2304. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  2305. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  2306. grc_local_ctrl,
  2307. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2308. }
  2309. /* On 5753 and variants, GPIO2 cannot be used. */
  2310. no_gpio2 = tp->nic_sram_data_cfg &
  2311. NIC_SRAM_DATA_CFG_NO_GPIO2;
  2312. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  2313. GRC_LCLCTRL_GPIO_OE1 |
  2314. GRC_LCLCTRL_GPIO_OE2 |
  2315. GRC_LCLCTRL_GPIO_OUTPUT1 |
  2316. GRC_LCLCTRL_GPIO_OUTPUT2;
  2317. if (no_gpio2) {
  2318. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  2319. GRC_LCLCTRL_GPIO_OUTPUT2);
  2320. }
  2321. tw32_wait_f(GRC_LOCAL_CTRL,
  2322. tp->grc_local_ctrl | grc_local_ctrl,
  2323. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2324. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  2325. tw32_wait_f(GRC_LOCAL_CTRL,
  2326. tp->grc_local_ctrl | grc_local_ctrl,
  2327. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2328. if (!no_gpio2) {
  2329. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  2330. tw32_wait_f(GRC_LOCAL_CTRL,
  2331. tp->grc_local_ctrl | grc_local_ctrl,
  2332. TG3_GRC_LCLCTL_PWRSW_DELAY);
  2333. }
  2334. }
  2335. }
  2336. static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
  2337. {
  2338. u32 msg = 0;
  2339. /* Serialize power state transitions */
  2340. if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
  2341. return;
  2342. if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
  2343. msg = TG3_GPIO_MSG_NEED_VAUX;
  2344. msg = tg3_set_function_status(tp, msg);
  2345. if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
  2346. goto done;
  2347. if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
  2348. tg3_pwrsrc_switch_to_vaux(tp);
  2349. else
  2350. tg3_pwrsrc_die_with_vmain(tp);
  2351. done:
  2352. tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
  2353. }
  2354. static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
  2355. {
  2356. bool need_vaux = false;
  2357. /* The GPIOs do something completely different on 57765. */
  2358. if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
  2359. return;
  2360. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  2361. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  2362. tg3_asic_rev(tp) == ASIC_REV_5720) {
  2363. tg3_frob_aux_power_5717(tp, include_wol ?
  2364. tg3_flag(tp, WOL_ENABLE) != 0 : 0);
  2365. return;
  2366. }
  2367. if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
  2368. struct net_device *dev_peer;
  2369. dev_peer = pci_get_drvdata(tp->pdev_peer);
  2370. /* remove_one() may have been run on the peer. */
  2371. if (dev_peer) {
  2372. struct tg3 *tp_peer = netdev_priv(dev_peer);
  2373. if (tg3_flag(tp_peer, INIT_COMPLETE))
  2374. return;
  2375. if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
  2376. tg3_flag(tp_peer, ENABLE_ASF))
  2377. need_vaux = true;
  2378. }
  2379. }
  2380. if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
  2381. tg3_flag(tp, ENABLE_ASF))
  2382. need_vaux = true;
  2383. if (need_vaux)
  2384. tg3_pwrsrc_switch_to_vaux(tp);
  2385. else
  2386. tg3_pwrsrc_die_with_vmain(tp);
  2387. }
  2388. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  2389. {
  2390. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  2391. return 1;
  2392. else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
  2393. if (speed != SPEED_10)
  2394. return 1;
  2395. } else if (speed == SPEED_10)
  2396. return 1;
  2397. return 0;
  2398. }
  2399. static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
  2400. {
  2401. u32 val;
  2402. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  2403. if (tg3_asic_rev(tp) == ASIC_REV_5704) {
  2404. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2405. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  2406. sg_dig_ctrl |=
  2407. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  2408. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  2409. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  2410. }
  2411. return;
  2412. }
  2413. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2414. tg3_bmcr_reset(tp);
  2415. val = tr32(GRC_MISC_CFG);
  2416. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  2417. udelay(40);
  2418. return;
  2419. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  2420. u32 phytest;
  2421. if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
  2422. u32 phy;
  2423. tg3_writephy(tp, MII_ADVERTISE, 0);
  2424. tg3_writephy(tp, MII_BMCR,
  2425. BMCR_ANENABLE | BMCR_ANRESTART);
  2426. tg3_writephy(tp, MII_TG3_FET_TEST,
  2427. phytest | MII_TG3_FET_SHADOW_EN);
  2428. if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
  2429. phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
  2430. tg3_writephy(tp,
  2431. MII_TG3_FET_SHDW_AUXMODE4,
  2432. phy);
  2433. }
  2434. tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
  2435. }
  2436. return;
  2437. } else if (do_low_power) {
  2438. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  2439. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  2440. val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  2441. MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
  2442. MII_TG3_AUXCTL_PCTL_VREG_11V;
  2443. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
  2444. }
  2445. /* The PHY should not be powered down on some chips because
  2446. * of bugs.
  2447. */
  2448. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  2449. tg3_asic_rev(tp) == ASIC_REV_5704 ||
  2450. (tg3_asic_rev(tp) == ASIC_REV_5780 &&
  2451. (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
  2452. (tg3_asic_rev(tp) == ASIC_REV_5717 &&
  2453. !tp->pci_fn))
  2454. return;
  2455. if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
  2456. tg3_chip_rev(tp) == CHIPREV_5761_AX) {
  2457. val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
  2458. val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
  2459. val |= CPMU_LSPD_1000MB_MACCLK_12_5;
  2460. tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
  2461. }
  2462. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  2463. }
  2464. /* tp->lock is held. */
  2465. static int tg3_nvram_lock(struct tg3 *tp)
  2466. {
  2467. if (tg3_flag(tp, NVRAM)) {
  2468. int i;
  2469. if (tp->nvram_lock_cnt == 0) {
  2470. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  2471. for (i = 0; i < 8000; i++) {
  2472. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  2473. break;
  2474. udelay(20);
  2475. }
  2476. if (i == 8000) {
  2477. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  2478. return -ENODEV;
  2479. }
  2480. }
  2481. tp->nvram_lock_cnt++;
  2482. }
  2483. return 0;
  2484. }
  2485. /* tp->lock is held. */
  2486. static void tg3_nvram_unlock(struct tg3 *tp)
  2487. {
  2488. if (tg3_flag(tp, NVRAM)) {
  2489. if (tp->nvram_lock_cnt > 0)
  2490. tp->nvram_lock_cnt--;
  2491. if (tp->nvram_lock_cnt == 0)
  2492. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  2493. }
  2494. }
  2495. /* tp->lock is held. */
  2496. static void tg3_enable_nvram_access(struct tg3 *tp)
  2497. {
  2498. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
  2499. u32 nvaccess = tr32(NVRAM_ACCESS);
  2500. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  2501. }
  2502. }
  2503. /* tp->lock is held. */
  2504. static void tg3_disable_nvram_access(struct tg3 *tp)
  2505. {
  2506. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
  2507. u32 nvaccess = tr32(NVRAM_ACCESS);
  2508. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  2509. }
  2510. }
  2511. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  2512. u32 offset, u32 *val)
  2513. {
  2514. u32 tmp;
  2515. int i;
  2516. if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
  2517. return -EINVAL;
  2518. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  2519. EEPROM_ADDR_DEVID_MASK |
  2520. EEPROM_ADDR_READ);
  2521. tw32(GRC_EEPROM_ADDR,
  2522. tmp |
  2523. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  2524. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  2525. EEPROM_ADDR_ADDR_MASK) |
  2526. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  2527. for (i = 0; i < 1000; i++) {
  2528. tmp = tr32(GRC_EEPROM_ADDR);
  2529. if (tmp & EEPROM_ADDR_COMPLETE)
  2530. break;
  2531. msleep(1);
  2532. }
  2533. if (!(tmp & EEPROM_ADDR_COMPLETE))
  2534. return -EBUSY;
  2535. tmp = tr32(GRC_EEPROM_DATA);
  2536. /*
  2537. * The data will always be opposite the native endian
  2538. * format. Perform a blind byteswap to compensate.
  2539. */
  2540. *val = swab32(tmp);
  2541. return 0;
  2542. }
  2543. #define NVRAM_CMD_TIMEOUT 10000
  2544. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  2545. {
  2546. int i;
  2547. tw32(NVRAM_CMD, nvram_cmd);
  2548. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  2549. udelay(10);
  2550. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  2551. udelay(10);
  2552. break;
  2553. }
  2554. }
  2555. if (i == NVRAM_CMD_TIMEOUT)
  2556. return -EBUSY;
  2557. return 0;
  2558. }
  2559. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  2560. {
  2561. if (tg3_flag(tp, NVRAM) &&
  2562. tg3_flag(tp, NVRAM_BUFFERED) &&
  2563. tg3_flag(tp, FLASH) &&
  2564. !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
  2565. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2566. addr = ((addr / tp->nvram_pagesize) <<
  2567. ATMEL_AT45DB0X1B_PAGE_POS) +
  2568. (addr % tp->nvram_pagesize);
  2569. return addr;
  2570. }
  2571. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  2572. {
  2573. if (tg3_flag(tp, NVRAM) &&
  2574. tg3_flag(tp, NVRAM_BUFFERED) &&
  2575. tg3_flag(tp, FLASH) &&
  2576. !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
  2577. (tp->nvram_jedecnum == JEDEC_ATMEL))
  2578. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  2579. tp->nvram_pagesize) +
  2580. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  2581. return addr;
  2582. }
  2583. /* NOTE: Data read in from NVRAM is byteswapped according to
  2584. * the byteswapping settings for all other register accesses.
  2585. * tg3 devices are BE devices, so on a BE machine, the data
  2586. * returned will be exactly as it is seen in NVRAM. On a LE
  2587. * machine, the 32-bit value will be byteswapped.
  2588. */
  2589. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  2590. {
  2591. int ret;
  2592. if (!tg3_flag(tp, NVRAM))
  2593. return tg3_nvram_read_using_eeprom(tp, offset, val);
  2594. offset = tg3_nvram_phys_addr(tp, offset);
  2595. if (offset > NVRAM_ADDR_MSK)
  2596. return -EINVAL;
  2597. ret = tg3_nvram_lock(tp);
  2598. if (ret)
  2599. return ret;
  2600. tg3_enable_nvram_access(tp);
  2601. tw32(NVRAM_ADDR, offset);
  2602. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  2603. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  2604. if (ret == 0)
  2605. *val = tr32(NVRAM_RDDATA);
  2606. tg3_disable_nvram_access(tp);
  2607. tg3_nvram_unlock(tp);
  2608. return ret;
  2609. }
  2610. /* Ensures NVRAM data is in bytestream format. */
  2611. static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
  2612. {
  2613. u32 v;
  2614. int res = tg3_nvram_read(tp, offset, &v);
  2615. if (!res)
  2616. *val = cpu_to_be32(v);
  2617. return res;
  2618. }
  2619. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  2620. u32 offset, u32 len, u8 *buf)
  2621. {
  2622. int i, j, rc = 0;
  2623. u32 val;
  2624. for (i = 0; i < len; i += 4) {
  2625. u32 addr;
  2626. __be32 data;
  2627. addr = offset + i;
  2628. memcpy(&data, buf + i, 4);
  2629. /*
  2630. * The SEEPROM interface expects the data to always be opposite
  2631. * the native endian format. We accomplish this by reversing
  2632. * all the operations that would have been performed on the
  2633. * data from a call to tg3_nvram_read_be32().
  2634. */
  2635. tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
  2636. val = tr32(GRC_EEPROM_ADDR);
  2637. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  2638. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  2639. EEPROM_ADDR_READ);
  2640. tw32(GRC_EEPROM_ADDR, val |
  2641. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  2642. (addr & EEPROM_ADDR_ADDR_MASK) |
  2643. EEPROM_ADDR_START |
  2644. EEPROM_ADDR_WRITE);
  2645. for (j = 0; j < 1000; j++) {
  2646. val = tr32(GRC_EEPROM_ADDR);
  2647. if (val & EEPROM_ADDR_COMPLETE)
  2648. break;
  2649. msleep(1);
  2650. }
  2651. if (!(val & EEPROM_ADDR_COMPLETE)) {
  2652. rc = -EBUSY;
  2653. break;
  2654. }
  2655. }
  2656. return rc;
  2657. }
  2658. /* offset and length are dword aligned */
  2659. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  2660. u8 *buf)
  2661. {
  2662. int ret = 0;
  2663. u32 pagesize = tp->nvram_pagesize;
  2664. u32 pagemask = pagesize - 1;
  2665. u32 nvram_cmd;
  2666. u8 *tmp;
  2667. tmp = kmalloc(pagesize, GFP_KERNEL);
  2668. if (tmp == NULL)
  2669. return -ENOMEM;
  2670. while (len) {
  2671. int j;
  2672. u32 phy_addr, page_off, size;
  2673. phy_addr = offset & ~pagemask;
  2674. for (j = 0; j < pagesize; j += 4) {
  2675. ret = tg3_nvram_read_be32(tp, phy_addr + j,
  2676. (__be32 *) (tmp + j));
  2677. if (ret)
  2678. break;
  2679. }
  2680. if (ret)
  2681. break;
  2682. page_off = offset & pagemask;
  2683. size = pagesize;
  2684. if (len < size)
  2685. size = len;
  2686. len -= size;
  2687. memcpy(tmp + page_off, buf, size);
  2688. offset = offset + (pagesize - page_off);
  2689. tg3_enable_nvram_access(tp);
  2690. /*
  2691. * Before we can erase the flash page, we need
  2692. * to issue a special "write enable" command.
  2693. */
  2694. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2695. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2696. break;
  2697. /* Erase the target page */
  2698. tw32(NVRAM_ADDR, phy_addr);
  2699. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  2700. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  2701. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2702. break;
  2703. /* Issue another write enable to start the write. */
  2704. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2705. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  2706. break;
  2707. for (j = 0; j < pagesize; j += 4) {
  2708. __be32 data;
  2709. data = *((__be32 *) (tmp + j));
  2710. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  2711. tw32(NVRAM_ADDR, phy_addr + j);
  2712. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  2713. NVRAM_CMD_WR;
  2714. if (j == 0)
  2715. nvram_cmd |= NVRAM_CMD_FIRST;
  2716. else if (j == (pagesize - 4))
  2717. nvram_cmd |= NVRAM_CMD_LAST;
  2718. ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
  2719. if (ret)
  2720. break;
  2721. }
  2722. if (ret)
  2723. break;
  2724. }
  2725. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2726. tg3_nvram_exec_cmd(tp, nvram_cmd);
  2727. kfree(tmp);
  2728. return ret;
  2729. }
  2730. /* offset and length are dword aligned */
  2731. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  2732. u8 *buf)
  2733. {
  2734. int i, ret = 0;
  2735. for (i = 0; i < len; i += 4, offset += 4) {
  2736. u32 page_off, phy_addr, nvram_cmd;
  2737. __be32 data;
  2738. memcpy(&data, buf + i, 4);
  2739. tw32(NVRAM_WRDATA, be32_to_cpu(data));
  2740. page_off = offset % tp->nvram_pagesize;
  2741. phy_addr = tg3_nvram_phys_addr(tp, offset);
  2742. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  2743. if (page_off == 0 || i == 0)
  2744. nvram_cmd |= NVRAM_CMD_FIRST;
  2745. if (page_off == (tp->nvram_pagesize - 4))
  2746. nvram_cmd |= NVRAM_CMD_LAST;
  2747. if (i == (len - 4))
  2748. nvram_cmd |= NVRAM_CMD_LAST;
  2749. if ((nvram_cmd & NVRAM_CMD_FIRST) ||
  2750. !tg3_flag(tp, FLASH) ||
  2751. !tg3_flag(tp, 57765_PLUS))
  2752. tw32(NVRAM_ADDR, phy_addr);
  2753. if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
  2754. !tg3_flag(tp, 5755_PLUS) &&
  2755. (tp->nvram_jedecnum == JEDEC_ST) &&
  2756. (nvram_cmd & NVRAM_CMD_FIRST)) {
  2757. u32 cmd;
  2758. cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  2759. ret = tg3_nvram_exec_cmd(tp, cmd);
  2760. if (ret)
  2761. break;
  2762. }
  2763. if (!tg3_flag(tp, FLASH)) {
  2764. /* We always do complete word writes to eeprom. */
  2765. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  2766. }
  2767. ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
  2768. if (ret)
  2769. break;
  2770. }
  2771. return ret;
  2772. }
  2773. /* offset and length are dword aligned */
  2774. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  2775. {
  2776. int ret;
  2777. if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
  2778. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  2779. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  2780. udelay(40);
  2781. }
  2782. if (!tg3_flag(tp, NVRAM)) {
  2783. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  2784. } else {
  2785. u32 grc_mode;
  2786. ret = tg3_nvram_lock(tp);
  2787. if (ret)
  2788. return ret;
  2789. tg3_enable_nvram_access(tp);
  2790. if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
  2791. tw32(NVRAM_WRITE1, 0x406);
  2792. grc_mode = tr32(GRC_MODE);
  2793. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  2794. if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
  2795. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  2796. buf);
  2797. } else {
  2798. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  2799. buf);
  2800. }
  2801. grc_mode = tr32(GRC_MODE);
  2802. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  2803. tg3_disable_nvram_access(tp);
  2804. tg3_nvram_unlock(tp);
  2805. }
  2806. if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
  2807. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  2808. udelay(40);
  2809. }
  2810. return ret;
  2811. }
  2812. #define RX_CPU_SCRATCH_BASE 0x30000
  2813. #define RX_CPU_SCRATCH_SIZE 0x04000
  2814. #define TX_CPU_SCRATCH_BASE 0x34000
  2815. #define TX_CPU_SCRATCH_SIZE 0x04000
  2816. /* tp->lock is held. */
  2817. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  2818. {
  2819. int i;
  2820. BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
  2821. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  2822. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  2823. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  2824. return 0;
  2825. }
  2826. if (offset == RX_CPU_BASE) {
  2827. for (i = 0; i < 10000; i++) {
  2828. tw32(offset + CPU_STATE, 0xffffffff);
  2829. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  2830. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  2831. break;
  2832. }
  2833. tw32(offset + CPU_STATE, 0xffffffff);
  2834. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  2835. udelay(10);
  2836. } else {
  2837. /*
  2838. * There is only an Rx CPU for the 5750 derivative in the
  2839. * BCM4785.
  2840. */
  2841. if (tg3_flag(tp, IS_SSB_CORE))
  2842. return 0;
  2843. for (i = 0; i < 10000; i++) {
  2844. tw32(offset + CPU_STATE, 0xffffffff);
  2845. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  2846. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  2847. break;
  2848. }
  2849. }
  2850. if (i >= 10000) {
  2851. netdev_err(tp->dev, "%s timed out, %s CPU\n",
  2852. __func__, offset == RX_CPU_BASE ? "RX" : "TX");
  2853. return -ENODEV;
  2854. }
  2855. /* Clear firmware's nvram arbitration. */
  2856. if (tg3_flag(tp, NVRAM))
  2857. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  2858. return 0;
  2859. }
  2860. struct fw_info {
  2861. unsigned int fw_base;
  2862. unsigned int fw_len;
  2863. const __be32 *fw_data;
  2864. };
  2865. /* tp->lock is held. */
  2866. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
  2867. u32 cpu_scratch_base, int cpu_scratch_size,
  2868. struct fw_info *info)
  2869. {
  2870. int err, lock_err, i;
  2871. void (*write_op)(struct tg3 *, u32, u32);
  2872. if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
  2873. netdev_err(tp->dev,
  2874. "%s: Trying to load TX cpu firmware which is 5705\n",
  2875. __func__);
  2876. return -EINVAL;
  2877. }
  2878. if (tg3_flag(tp, 5705_PLUS))
  2879. write_op = tg3_write_mem;
  2880. else
  2881. write_op = tg3_write_indirect_reg32;
  2882. /* It is possible that bootcode is still loading at this point.
  2883. * Get the nvram lock first before halting the cpu.
  2884. */
  2885. lock_err = tg3_nvram_lock(tp);
  2886. err = tg3_halt_cpu(tp, cpu_base);
  2887. if (!lock_err)
  2888. tg3_nvram_unlock(tp);
  2889. if (err)
  2890. goto out;
  2891. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  2892. write_op(tp, cpu_scratch_base + i, 0);
  2893. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2894. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  2895. for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
  2896. write_op(tp, (cpu_scratch_base +
  2897. (info->fw_base & 0xffff) +
  2898. (i * sizeof(u32))),
  2899. be32_to_cpu(info->fw_data[i]));
  2900. err = 0;
  2901. out:
  2902. return err;
  2903. }
  2904. /* tp->lock is held. */
  2905. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  2906. {
  2907. struct fw_info info;
  2908. const __be32 *fw_data;
  2909. int err, i;
  2910. fw_data = (void *)tp->fw->data;
  2911. /* Firmware blob starts with version numbers, followed by
  2912. start address and length. We are setting complete length.
  2913. length = end_address_of_bss - start_address_of_text.
  2914. Remainder is the blob to be loaded contiguously
  2915. from start address. */
  2916. info.fw_base = be32_to_cpu(fw_data[1]);
  2917. info.fw_len = tp->fw->size - 12;
  2918. info.fw_data = &fw_data[3];
  2919. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  2920. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  2921. &info);
  2922. if (err)
  2923. return err;
  2924. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  2925. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  2926. &info);
  2927. if (err)
  2928. return err;
  2929. /* Now startup only the RX cpu. */
  2930. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2931. tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
  2932. for (i = 0; i < 5; i++) {
  2933. if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
  2934. break;
  2935. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2936. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  2937. tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
  2938. udelay(1000);
  2939. }
  2940. if (i >= 5) {
  2941. netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
  2942. "should be %08x\n", __func__,
  2943. tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
  2944. return -ENODEV;
  2945. }
  2946. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  2947. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  2948. return 0;
  2949. }
  2950. /* tp->lock is held. */
  2951. static int tg3_load_tso_firmware(struct tg3 *tp)
  2952. {
  2953. struct fw_info info;
  2954. const __be32 *fw_data;
  2955. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  2956. int err, i;
  2957. if (tg3_flag(tp, HW_TSO_1) ||
  2958. tg3_flag(tp, HW_TSO_2) ||
  2959. tg3_flag(tp, HW_TSO_3))
  2960. return 0;
  2961. fw_data = (void *)tp->fw->data;
  2962. /* Firmware blob starts with version numbers, followed by
  2963. start address and length. We are setting complete length.
  2964. length = end_address_of_bss - start_address_of_text.
  2965. Remainder is the blob to be loaded contiguously
  2966. from start address. */
  2967. info.fw_base = be32_to_cpu(fw_data[1]);
  2968. cpu_scratch_size = tp->fw_len;
  2969. info.fw_len = tp->fw->size - 12;
  2970. info.fw_data = &fw_data[3];
  2971. if (tg3_asic_rev(tp) == ASIC_REV_5705) {
  2972. cpu_base = RX_CPU_BASE;
  2973. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  2974. } else {
  2975. cpu_base = TX_CPU_BASE;
  2976. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  2977. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  2978. }
  2979. err = tg3_load_firmware_cpu(tp, cpu_base,
  2980. cpu_scratch_base, cpu_scratch_size,
  2981. &info);
  2982. if (err)
  2983. return err;
  2984. /* Now startup the cpu. */
  2985. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2986. tw32_f(cpu_base + CPU_PC, info.fw_base);
  2987. for (i = 0; i < 5; i++) {
  2988. if (tr32(cpu_base + CPU_PC) == info.fw_base)
  2989. break;
  2990. tw32(cpu_base + CPU_STATE, 0xffffffff);
  2991. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  2992. tw32_f(cpu_base + CPU_PC, info.fw_base);
  2993. udelay(1000);
  2994. }
  2995. if (i >= 5) {
  2996. netdev_err(tp->dev,
  2997. "%s fails to set CPU PC, is %08x should be %08x\n",
  2998. __func__, tr32(cpu_base + CPU_PC), info.fw_base);
  2999. return -ENODEV;
  3000. }
  3001. tw32(cpu_base + CPU_STATE, 0xffffffff);
  3002. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  3003. return 0;
  3004. }
  3005. /* tp->lock is held. */
  3006. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  3007. {
  3008. u32 addr_high, addr_low;
  3009. int i;
  3010. addr_high = ((tp->dev->dev_addr[0] << 8) |
  3011. tp->dev->dev_addr[1]);
  3012. addr_low = ((tp->dev->dev_addr[2] << 24) |
  3013. (tp->dev->dev_addr[3] << 16) |
  3014. (tp->dev->dev_addr[4] << 8) |
  3015. (tp->dev->dev_addr[5] << 0));
  3016. for (i = 0; i < 4; i++) {
  3017. if (i == 1 && skip_mac_1)
  3018. continue;
  3019. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  3020. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  3021. }
  3022. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  3023. tg3_asic_rev(tp) == ASIC_REV_5704) {
  3024. for (i = 0; i < 12; i++) {
  3025. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  3026. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  3027. }
  3028. }
  3029. addr_high = (tp->dev->dev_addr[0] +
  3030. tp->dev->dev_addr[1] +
  3031. tp->dev->dev_addr[2] +
  3032. tp->dev->dev_addr[3] +
  3033. tp->dev->dev_addr[4] +
  3034. tp->dev->dev_addr[5]) &
  3035. TX_BACKOFF_SEED_MASK;
  3036. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  3037. }
  3038. static void tg3_enable_register_access(struct tg3 *tp)
  3039. {
  3040. /*
  3041. * Make sure register accesses (indirect or otherwise) will function
  3042. * correctly.
  3043. */
  3044. pci_write_config_dword(tp->pdev,
  3045. TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
  3046. }
  3047. static int tg3_power_up(struct tg3 *tp)
  3048. {
  3049. int err;
  3050. tg3_enable_register_access(tp);
  3051. err = pci_set_power_state(tp->pdev, PCI_D0);
  3052. if (!err) {
  3053. /* Switch out of Vaux if it is a NIC */
  3054. tg3_pwrsrc_switch_to_vmain(tp);
  3055. } else {
  3056. netdev_err(tp->dev, "Transition to D0 failed\n");
  3057. }
  3058. return err;
  3059. }
  3060. static int tg3_setup_phy(struct tg3 *, int);
  3061. static int tg3_power_down_prepare(struct tg3 *tp)
  3062. {
  3063. u32 misc_host_ctrl;
  3064. bool device_should_wake, do_low_power;
  3065. tg3_enable_register_access(tp);
  3066. /* Restore the CLKREQ setting. */
  3067. if (tg3_flag(tp, CLKREQ_BUG))
  3068. pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
  3069. PCI_EXP_LNKCTL_CLKREQ_EN);
  3070. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  3071. tw32(TG3PCI_MISC_HOST_CTRL,
  3072. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  3073. device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
  3074. tg3_flag(tp, WOL_ENABLE);
  3075. if (tg3_flag(tp, USE_PHYLIB)) {
  3076. do_low_power = false;
  3077. if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
  3078. !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  3079. struct phy_device *phydev;
  3080. u32 phyid, advertising;
  3081. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  3082. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  3083. tp->link_config.speed = phydev->speed;
  3084. tp->link_config.duplex = phydev->duplex;
  3085. tp->link_config.autoneg = phydev->autoneg;
  3086. tp->link_config.advertising = phydev->advertising;
  3087. advertising = ADVERTISED_TP |
  3088. ADVERTISED_Pause |
  3089. ADVERTISED_Autoneg |
  3090. ADVERTISED_10baseT_Half;
  3091. if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
  3092. if (tg3_flag(tp, WOL_SPEED_100MB))
  3093. advertising |=
  3094. ADVERTISED_100baseT_Half |
  3095. ADVERTISED_100baseT_Full |
  3096. ADVERTISED_10baseT_Full;
  3097. else
  3098. advertising |= ADVERTISED_10baseT_Full;
  3099. }
  3100. phydev->advertising = advertising;
  3101. phy_start_aneg(phydev);
  3102. phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
  3103. if (phyid != PHY_ID_BCMAC131) {
  3104. phyid &= PHY_BCM_OUI_MASK;
  3105. if (phyid == PHY_BCM_OUI_1 ||
  3106. phyid == PHY_BCM_OUI_2 ||
  3107. phyid == PHY_BCM_OUI_3)
  3108. do_low_power = true;
  3109. }
  3110. }
  3111. } else {
  3112. do_low_power = true;
  3113. if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
  3114. tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
  3115. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  3116. tg3_setup_phy(tp, 0);
  3117. }
  3118. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  3119. u32 val;
  3120. val = tr32(GRC_VCPU_EXT_CTRL);
  3121. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  3122. } else if (!tg3_flag(tp, ENABLE_ASF)) {
  3123. int i;
  3124. u32 val;
  3125. for (i = 0; i < 200; i++) {
  3126. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  3127. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  3128. break;
  3129. msleep(1);
  3130. }
  3131. }
  3132. if (tg3_flag(tp, WOL_CAP))
  3133. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  3134. WOL_DRV_STATE_SHUTDOWN |
  3135. WOL_DRV_WOL |
  3136. WOL_SET_MAGIC_PKT);
  3137. if (device_should_wake) {
  3138. u32 mac_mode;
  3139. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  3140. if (do_low_power &&
  3141. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  3142. tg3_phy_auxctl_write(tp,
  3143. MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
  3144. MII_TG3_AUXCTL_PCTL_WOL_EN |
  3145. MII_TG3_AUXCTL_PCTL_100TX_LPWR |
  3146. MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
  3147. udelay(40);
  3148. }
  3149. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  3150. mac_mode = MAC_MODE_PORT_MODE_GMII;
  3151. else
  3152. mac_mode = MAC_MODE_PORT_MODE_MII;
  3153. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  3154. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  3155. u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
  3156. SPEED_100 : SPEED_10;
  3157. if (tg3_5700_link_polarity(tp, speed))
  3158. mac_mode |= MAC_MODE_LINK_POLARITY;
  3159. else
  3160. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  3161. }
  3162. } else {
  3163. mac_mode = MAC_MODE_PORT_MODE_TBI;
  3164. }
  3165. if (!tg3_flag(tp, 5750_PLUS))
  3166. tw32(MAC_LED_CTRL, tp->led_ctrl);
  3167. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  3168. if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
  3169. (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
  3170. mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
  3171. if (tg3_flag(tp, ENABLE_APE))
  3172. mac_mode |= MAC_MODE_APE_TX_EN |
  3173. MAC_MODE_APE_RX_EN |
  3174. MAC_MODE_TDE_ENABLE;
  3175. tw32_f(MAC_MODE, mac_mode);
  3176. udelay(100);
  3177. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  3178. udelay(10);
  3179. }
  3180. if (!tg3_flag(tp, WOL_SPEED_100MB) &&
  3181. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3182. tg3_asic_rev(tp) == ASIC_REV_5701)) {
  3183. u32 base_val;
  3184. base_val = tp->pci_clock_ctrl;
  3185. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  3186. CLOCK_CTRL_TXCLK_DISABLE);
  3187. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  3188. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  3189. } else if (tg3_flag(tp, 5780_CLASS) ||
  3190. tg3_flag(tp, CPMU_PRESENT) ||
  3191. tg3_asic_rev(tp) == ASIC_REV_5906) {
  3192. /* do nothing */
  3193. } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
  3194. u32 newbits1, newbits2;
  3195. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3196. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3197. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  3198. CLOCK_CTRL_TXCLK_DISABLE |
  3199. CLOCK_CTRL_ALTCLK);
  3200. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  3201. } else if (tg3_flag(tp, 5705_PLUS)) {
  3202. newbits1 = CLOCK_CTRL_625_CORE;
  3203. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  3204. } else {
  3205. newbits1 = CLOCK_CTRL_ALTCLK;
  3206. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  3207. }
  3208. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  3209. 40);
  3210. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  3211. 40);
  3212. if (!tg3_flag(tp, 5705_PLUS)) {
  3213. u32 newbits3;
  3214. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3215. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3216. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  3217. CLOCK_CTRL_TXCLK_DISABLE |
  3218. CLOCK_CTRL_44MHZ_CORE);
  3219. } else {
  3220. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  3221. }
  3222. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  3223. tp->pci_clock_ctrl | newbits3, 40);
  3224. }
  3225. }
  3226. if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
  3227. tg3_power_down_phy(tp, do_low_power);
  3228. tg3_frob_aux_power(tp, true);
  3229. /* Workaround for unstable PLL clock */
  3230. if ((!tg3_flag(tp, IS_SSB_CORE)) &&
  3231. ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
  3232. (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
  3233. u32 val = tr32(0x7d00);
  3234. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  3235. tw32(0x7d00, val);
  3236. if (!tg3_flag(tp, ENABLE_ASF)) {
  3237. int err;
  3238. err = tg3_nvram_lock(tp);
  3239. tg3_halt_cpu(tp, RX_CPU_BASE);
  3240. if (!err)
  3241. tg3_nvram_unlock(tp);
  3242. }
  3243. }
  3244. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  3245. return 0;
  3246. }
  3247. static void tg3_power_down(struct tg3 *tp)
  3248. {
  3249. tg3_power_down_prepare(tp);
  3250. pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
  3251. pci_set_power_state(tp->pdev, PCI_D3hot);
  3252. }
  3253. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  3254. {
  3255. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  3256. case MII_TG3_AUX_STAT_10HALF:
  3257. *speed = SPEED_10;
  3258. *duplex = DUPLEX_HALF;
  3259. break;
  3260. case MII_TG3_AUX_STAT_10FULL:
  3261. *speed = SPEED_10;
  3262. *duplex = DUPLEX_FULL;
  3263. break;
  3264. case MII_TG3_AUX_STAT_100HALF:
  3265. *speed = SPEED_100;
  3266. *duplex = DUPLEX_HALF;
  3267. break;
  3268. case MII_TG3_AUX_STAT_100FULL:
  3269. *speed = SPEED_100;
  3270. *duplex = DUPLEX_FULL;
  3271. break;
  3272. case MII_TG3_AUX_STAT_1000HALF:
  3273. *speed = SPEED_1000;
  3274. *duplex = DUPLEX_HALF;
  3275. break;
  3276. case MII_TG3_AUX_STAT_1000FULL:
  3277. *speed = SPEED_1000;
  3278. *duplex = DUPLEX_FULL;
  3279. break;
  3280. default:
  3281. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  3282. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  3283. SPEED_10;
  3284. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  3285. DUPLEX_HALF;
  3286. break;
  3287. }
  3288. *speed = SPEED_UNKNOWN;
  3289. *duplex = DUPLEX_UNKNOWN;
  3290. break;
  3291. }
  3292. }
  3293. static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
  3294. {
  3295. int err = 0;
  3296. u32 val, new_adv;
  3297. new_adv = ADVERTISE_CSMA;
  3298. new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
  3299. new_adv |= mii_advertise_flowctrl(flowctrl);
  3300. err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
  3301. if (err)
  3302. goto done;
  3303. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3304. new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
  3305. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3306. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
  3307. new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
  3308. err = tg3_writephy(tp, MII_CTRL1000, new_adv);
  3309. if (err)
  3310. goto done;
  3311. }
  3312. if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
  3313. goto done;
  3314. tw32(TG3_CPMU_EEE_MODE,
  3315. tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
  3316. err = tg3_phy_toggle_auxctl_smdsp(tp, true);
  3317. if (!err) {
  3318. u32 err2;
  3319. val = 0;
  3320. /* Advertise 100-BaseTX EEE ability */
  3321. if (advertise & ADVERTISED_100baseT_Full)
  3322. val |= MDIO_AN_EEE_ADV_100TX;
  3323. /* Advertise 1000-BaseT EEE ability */
  3324. if (advertise & ADVERTISED_1000baseT_Full)
  3325. val |= MDIO_AN_EEE_ADV_1000T;
  3326. err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  3327. if (err)
  3328. val = 0;
  3329. switch (tg3_asic_rev(tp)) {
  3330. case ASIC_REV_5717:
  3331. case ASIC_REV_57765:
  3332. case ASIC_REV_57766:
  3333. case ASIC_REV_5719:
  3334. /* If we advertised any eee advertisements above... */
  3335. if (val)
  3336. val = MII_TG3_DSP_TAP26_ALNOKO |
  3337. MII_TG3_DSP_TAP26_RMRXSTO |
  3338. MII_TG3_DSP_TAP26_OPCSINPT;
  3339. tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
  3340. /* Fall through */
  3341. case ASIC_REV_5720:
  3342. case ASIC_REV_5762:
  3343. if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
  3344. tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
  3345. MII_TG3_DSP_CH34TP2_HIBW01);
  3346. }
  3347. err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
  3348. if (!err)
  3349. err = err2;
  3350. }
  3351. done:
  3352. return err;
  3353. }
  3354. static void tg3_phy_copper_begin(struct tg3 *tp)
  3355. {
  3356. if (tp->link_config.autoneg == AUTONEG_ENABLE ||
  3357. (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  3358. u32 adv, fc;
  3359. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
  3360. adv = ADVERTISED_10baseT_Half |
  3361. ADVERTISED_10baseT_Full;
  3362. if (tg3_flag(tp, WOL_SPEED_100MB))
  3363. adv |= ADVERTISED_100baseT_Half |
  3364. ADVERTISED_100baseT_Full;
  3365. fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
  3366. } else {
  3367. adv = tp->link_config.advertising;
  3368. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  3369. adv &= ~(ADVERTISED_1000baseT_Half |
  3370. ADVERTISED_1000baseT_Full);
  3371. fc = tp->link_config.flowctrl;
  3372. }
  3373. tg3_phy_autoneg_cfg(tp, adv, fc);
  3374. tg3_writephy(tp, MII_BMCR,
  3375. BMCR_ANENABLE | BMCR_ANRESTART);
  3376. } else {
  3377. int i;
  3378. u32 bmcr, orig_bmcr;
  3379. tp->link_config.active_speed = tp->link_config.speed;
  3380. tp->link_config.active_duplex = tp->link_config.duplex;
  3381. bmcr = 0;
  3382. switch (tp->link_config.speed) {
  3383. default:
  3384. case SPEED_10:
  3385. break;
  3386. case SPEED_100:
  3387. bmcr |= BMCR_SPEED100;
  3388. break;
  3389. case SPEED_1000:
  3390. bmcr |= BMCR_SPEED1000;
  3391. break;
  3392. }
  3393. if (tp->link_config.duplex == DUPLEX_FULL)
  3394. bmcr |= BMCR_FULLDPLX;
  3395. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  3396. (bmcr != orig_bmcr)) {
  3397. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  3398. for (i = 0; i < 1500; i++) {
  3399. u32 tmp;
  3400. udelay(10);
  3401. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  3402. tg3_readphy(tp, MII_BMSR, &tmp))
  3403. continue;
  3404. if (!(tmp & BMSR_LSTATUS)) {
  3405. udelay(40);
  3406. break;
  3407. }
  3408. }
  3409. tg3_writephy(tp, MII_BMCR, bmcr);
  3410. udelay(40);
  3411. }
  3412. }
  3413. }
  3414. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  3415. {
  3416. int err;
  3417. /* Turn off tap power management. */
  3418. /* Set Extended packet length bit */
  3419. err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
  3420. err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
  3421. err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
  3422. err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
  3423. err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
  3424. err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
  3425. udelay(40);
  3426. return err;
  3427. }
  3428. static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
  3429. {
  3430. u32 advmsk, tgtadv, advertising;
  3431. advertising = tp->link_config.advertising;
  3432. tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
  3433. advmsk = ADVERTISE_ALL;
  3434. if (tp->link_config.active_duplex == DUPLEX_FULL) {
  3435. tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
  3436. advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3437. }
  3438. if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
  3439. return false;
  3440. if ((*lcladv & advmsk) != tgtadv)
  3441. return false;
  3442. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3443. u32 tg3_ctrl;
  3444. tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
  3445. if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
  3446. return false;
  3447. if (tgtadv &&
  3448. (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3449. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
  3450. tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
  3451. tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
  3452. CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
  3453. } else {
  3454. tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
  3455. }
  3456. if (tg3_ctrl != tgtadv)
  3457. return false;
  3458. }
  3459. return true;
  3460. }
  3461. static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
  3462. {
  3463. u32 lpeth = 0;
  3464. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
  3465. u32 val;
  3466. if (tg3_readphy(tp, MII_STAT1000, &val))
  3467. return false;
  3468. lpeth = mii_stat1000_to_ethtool_lpa_t(val);
  3469. }
  3470. if (tg3_readphy(tp, MII_LPA, rmtadv))
  3471. return false;
  3472. lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
  3473. tp->link_config.rmt_adv = lpeth;
  3474. return true;
  3475. }
  3476. static bool tg3_test_and_report_link_chg(struct tg3 *tp, int curr_link_up)
  3477. {
  3478. if (curr_link_up != tp->link_up) {
  3479. if (curr_link_up) {
  3480. netif_carrier_on(tp->dev);
  3481. } else {
  3482. netif_carrier_off(tp->dev);
  3483. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  3484. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  3485. }
  3486. tg3_link_report(tp);
  3487. return true;
  3488. }
  3489. return false;
  3490. }
  3491. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  3492. {
  3493. int current_link_up;
  3494. u32 bmsr, val;
  3495. u32 lcl_adv, rmt_adv;
  3496. u16 current_speed;
  3497. u8 current_duplex;
  3498. int i, err;
  3499. tw32(MAC_EVENT, 0);
  3500. tw32_f(MAC_STATUS,
  3501. (MAC_STATUS_SYNC_CHANGED |
  3502. MAC_STATUS_CFG_CHANGED |
  3503. MAC_STATUS_MI_COMPLETION |
  3504. MAC_STATUS_LNKSTATE_CHANGED));
  3505. udelay(40);
  3506. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  3507. tw32_f(MAC_MI_MODE,
  3508. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  3509. udelay(80);
  3510. }
  3511. tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
  3512. /* Some third-party PHYs need to be reset on link going
  3513. * down.
  3514. */
  3515. if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
  3516. tg3_asic_rev(tp) == ASIC_REV_5704 ||
  3517. tg3_asic_rev(tp) == ASIC_REV_5705) &&
  3518. tp->link_up) {
  3519. tg3_readphy(tp, MII_BMSR, &bmsr);
  3520. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3521. !(bmsr & BMSR_LSTATUS))
  3522. force_reset = 1;
  3523. }
  3524. if (force_reset)
  3525. tg3_phy_reset(tp);
  3526. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  3527. tg3_readphy(tp, MII_BMSR, &bmsr);
  3528. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  3529. !tg3_flag(tp, INIT_COMPLETE))
  3530. bmsr = 0;
  3531. if (!(bmsr & BMSR_LSTATUS)) {
  3532. err = tg3_init_5401phy_dsp(tp);
  3533. if (err)
  3534. return err;
  3535. tg3_readphy(tp, MII_BMSR, &bmsr);
  3536. for (i = 0; i < 1000; i++) {
  3537. udelay(10);
  3538. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3539. (bmsr & BMSR_LSTATUS)) {
  3540. udelay(40);
  3541. break;
  3542. }
  3543. }
  3544. if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
  3545. TG3_PHY_REV_BCM5401_B0 &&
  3546. !(bmsr & BMSR_LSTATUS) &&
  3547. tp->link_config.active_speed == SPEED_1000) {
  3548. err = tg3_phy_reset(tp);
  3549. if (!err)
  3550. err = tg3_init_5401phy_dsp(tp);
  3551. if (err)
  3552. return err;
  3553. }
  3554. }
  3555. } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  3556. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
  3557. /* 5701 {A0,B0} CRC bug workaround */
  3558. tg3_writephy(tp, 0x15, 0x0a75);
  3559. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  3560. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
  3561. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
  3562. }
  3563. /* Clear pending interrupts... */
  3564. tg3_readphy(tp, MII_TG3_ISTAT, &val);
  3565. tg3_readphy(tp, MII_TG3_ISTAT, &val);
  3566. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
  3567. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  3568. else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
  3569. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  3570. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  3571. tg3_asic_rev(tp) == ASIC_REV_5701) {
  3572. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  3573. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  3574. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  3575. else
  3576. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  3577. }
  3578. current_link_up = 0;
  3579. current_speed = SPEED_UNKNOWN;
  3580. current_duplex = DUPLEX_UNKNOWN;
  3581. tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
  3582. tp->link_config.rmt_adv = 0;
  3583. if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
  3584. err = tg3_phy_auxctl_read(tp,
  3585. MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
  3586. &val);
  3587. if (!err && !(val & (1 << 10))) {
  3588. tg3_phy_auxctl_write(tp,
  3589. MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
  3590. val | (1 << 10));
  3591. goto relink;
  3592. }
  3593. }
  3594. bmsr = 0;
  3595. for (i = 0; i < 100; i++) {
  3596. tg3_readphy(tp, MII_BMSR, &bmsr);
  3597. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  3598. (bmsr & BMSR_LSTATUS))
  3599. break;
  3600. udelay(40);
  3601. }
  3602. if (bmsr & BMSR_LSTATUS) {
  3603. u32 aux_stat, bmcr;
  3604. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  3605. for (i = 0; i < 2000; i++) {
  3606. udelay(10);
  3607. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  3608. aux_stat)
  3609. break;
  3610. }
  3611. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  3612. &current_speed,
  3613. &current_duplex);
  3614. bmcr = 0;
  3615. for (i = 0; i < 200; i++) {
  3616. tg3_readphy(tp, MII_BMCR, &bmcr);
  3617. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  3618. continue;
  3619. if (bmcr && bmcr != 0x7fff)
  3620. break;
  3621. udelay(10);
  3622. }
  3623. lcl_adv = 0;
  3624. rmt_adv = 0;
  3625. tp->link_config.active_speed = current_speed;
  3626. tp->link_config.active_duplex = current_duplex;
  3627. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  3628. if ((bmcr & BMCR_ANENABLE) &&
  3629. tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
  3630. tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
  3631. current_link_up = 1;
  3632. } else {
  3633. if (!(bmcr & BMCR_ANENABLE) &&
  3634. tp->link_config.speed == current_speed &&
  3635. tp->link_config.duplex == current_duplex &&
  3636. tp->link_config.flowctrl ==
  3637. tp->link_config.active_flowctrl) {
  3638. current_link_up = 1;
  3639. }
  3640. }
  3641. if (current_link_up == 1 &&
  3642. tp->link_config.active_duplex == DUPLEX_FULL) {
  3643. u32 reg, bit;
  3644. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  3645. reg = MII_TG3_FET_GEN_STAT;
  3646. bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
  3647. } else {
  3648. reg = MII_TG3_EXT_STAT;
  3649. bit = MII_TG3_EXT_STAT_MDIX;
  3650. }
  3651. if (!tg3_readphy(tp, reg, &val) && (val & bit))
  3652. tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
  3653. tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
  3654. }
  3655. }
  3656. relink:
  3657. if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
  3658. tg3_phy_copper_begin(tp);
  3659. if (tg3_flag(tp, ROBOSWITCH)) {
  3660. current_link_up = 1;
  3661. /* FIXME: when BCM5325 switch is used use 100 MBit/s */
  3662. current_speed = SPEED_1000;
  3663. current_duplex = DUPLEX_FULL;
  3664. tp->link_config.active_speed = current_speed;
  3665. tp->link_config.active_duplex = current_duplex;
  3666. }
  3667. tg3_readphy(tp, MII_BMSR, &bmsr);
  3668. if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
  3669. (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
  3670. current_link_up = 1;
  3671. }
  3672. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  3673. if (current_link_up == 1) {
  3674. if (tp->link_config.active_speed == SPEED_100 ||
  3675. tp->link_config.active_speed == SPEED_10)
  3676. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  3677. else
  3678. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  3679. } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  3680. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  3681. else
  3682. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  3683. /* In order for the 5750 core in BCM4785 chip to work properly
  3684. * in RGMII mode, the Led Control Register must be set up.
  3685. */
  3686. if (tg3_flag(tp, RGMII_MODE)) {
  3687. u32 led_ctrl = tr32(MAC_LED_CTRL);
  3688. led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
  3689. if (tp->link_config.active_speed == SPEED_10)
  3690. led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
  3691. else if (tp->link_config.active_speed == SPEED_100)
  3692. led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
  3693. LED_CTRL_100MBPS_ON);
  3694. else if (tp->link_config.active_speed == SPEED_1000)
  3695. led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
  3696. LED_CTRL_1000MBPS_ON);
  3697. tw32(MAC_LED_CTRL, led_ctrl);
  3698. udelay(40);
  3699. }
  3700. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  3701. if (tp->link_config.active_duplex == DUPLEX_HALF)
  3702. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  3703. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  3704. if (current_link_up == 1 &&
  3705. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  3706. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  3707. else
  3708. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  3709. }
  3710. /* ??? Without this setting Netgear GA302T PHY does not
  3711. * ??? send/receive packets...
  3712. */
  3713. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
  3714. tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
  3715. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  3716. tw32_f(MAC_MI_MODE, tp->mi_mode);
  3717. udelay(80);
  3718. }
  3719. tw32_f(MAC_MODE, tp->mac_mode);
  3720. udelay(40);
  3721. tg3_phy_eee_adjust(tp, current_link_up);
  3722. if (tg3_flag(tp, USE_LINKCHG_REG)) {
  3723. /* Polled via timer. */
  3724. tw32_f(MAC_EVENT, 0);
  3725. } else {
  3726. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  3727. }
  3728. udelay(40);
  3729. if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
  3730. current_link_up == 1 &&
  3731. tp->link_config.active_speed == SPEED_1000 &&
  3732. (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
  3733. udelay(120);
  3734. tw32_f(MAC_STATUS,
  3735. (MAC_STATUS_SYNC_CHANGED |
  3736. MAC_STATUS_CFG_CHANGED));
  3737. udelay(40);
  3738. tg3_write_mem(tp,
  3739. NIC_SRAM_FIRMWARE_MBOX,
  3740. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  3741. }
  3742. /* Prevent send BD corruption. */
  3743. if (tg3_flag(tp, CLKREQ_BUG)) {
  3744. if (tp->link_config.active_speed == SPEED_100 ||
  3745. tp->link_config.active_speed == SPEED_10)
  3746. pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
  3747. PCI_EXP_LNKCTL_CLKREQ_EN);
  3748. else
  3749. pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
  3750. PCI_EXP_LNKCTL_CLKREQ_EN);
  3751. }
  3752. tg3_test_and_report_link_chg(tp, current_link_up);
  3753. return 0;
  3754. }
  3755. struct tg3_fiber_aneginfo {
  3756. int state;
  3757. #define ANEG_STATE_UNKNOWN 0
  3758. #define ANEG_STATE_AN_ENABLE 1
  3759. #define ANEG_STATE_RESTART_INIT 2
  3760. #define ANEG_STATE_RESTART 3
  3761. #define ANEG_STATE_DISABLE_LINK_OK 4
  3762. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  3763. #define ANEG_STATE_ABILITY_DETECT 6
  3764. #define ANEG_STATE_ACK_DETECT_INIT 7
  3765. #define ANEG_STATE_ACK_DETECT 8
  3766. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  3767. #define ANEG_STATE_COMPLETE_ACK 10
  3768. #define ANEG_STATE_IDLE_DETECT_INIT 11
  3769. #define ANEG_STATE_IDLE_DETECT 12
  3770. #define ANEG_STATE_LINK_OK 13
  3771. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  3772. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  3773. u32 flags;
  3774. #define MR_AN_ENABLE 0x00000001
  3775. #define MR_RESTART_AN 0x00000002
  3776. #define MR_AN_COMPLETE 0x00000004
  3777. #define MR_PAGE_RX 0x00000008
  3778. #define MR_NP_LOADED 0x00000010
  3779. #define MR_TOGGLE_TX 0x00000020
  3780. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  3781. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  3782. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  3783. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  3784. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  3785. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  3786. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  3787. #define MR_TOGGLE_RX 0x00002000
  3788. #define MR_NP_RX 0x00004000
  3789. #define MR_LINK_OK 0x80000000
  3790. unsigned long link_time, cur_time;
  3791. u32 ability_match_cfg;
  3792. int ability_match_count;
  3793. char ability_match, idle_match, ack_match;
  3794. u32 txconfig, rxconfig;
  3795. #define ANEG_CFG_NP 0x00000080
  3796. #define ANEG_CFG_ACK 0x00000040
  3797. #define ANEG_CFG_RF2 0x00000020
  3798. #define ANEG_CFG_RF1 0x00000010
  3799. #define ANEG_CFG_PS2 0x00000001
  3800. #define ANEG_CFG_PS1 0x00008000
  3801. #define ANEG_CFG_HD 0x00004000
  3802. #define ANEG_CFG_FD 0x00002000
  3803. #define ANEG_CFG_INVAL 0x00001f06
  3804. };
  3805. #define ANEG_OK 0
  3806. #define ANEG_DONE 1
  3807. #define ANEG_TIMER_ENAB 2
  3808. #define ANEG_FAILED -1
  3809. #define ANEG_STATE_SETTLE_TIME 10000
  3810. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  3811. struct tg3_fiber_aneginfo *ap)
  3812. {
  3813. u16 flowctrl;
  3814. unsigned long delta;
  3815. u32 rx_cfg_reg;
  3816. int ret;
  3817. if (ap->state == ANEG_STATE_UNKNOWN) {
  3818. ap->rxconfig = 0;
  3819. ap->link_time = 0;
  3820. ap->cur_time = 0;
  3821. ap->ability_match_cfg = 0;
  3822. ap->ability_match_count = 0;
  3823. ap->ability_match = 0;
  3824. ap->idle_match = 0;
  3825. ap->ack_match = 0;
  3826. }
  3827. ap->cur_time++;
  3828. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  3829. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  3830. if (rx_cfg_reg != ap->ability_match_cfg) {
  3831. ap->ability_match_cfg = rx_cfg_reg;
  3832. ap->ability_match = 0;
  3833. ap->ability_match_count = 0;
  3834. } else {
  3835. if (++ap->ability_match_count > 1) {
  3836. ap->ability_match = 1;
  3837. ap->ability_match_cfg = rx_cfg_reg;
  3838. }
  3839. }
  3840. if (rx_cfg_reg & ANEG_CFG_ACK)
  3841. ap->ack_match = 1;
  3842. else
  3843. ap->ack_match = 0;
  3844. ap->idle_match = 0;
  3845. } else {
  3846. ap->idle_match = 1;
  3847. ap->ability_match_cfg = 0;
  3848. ap->ability_match_count = 0;
  3849. ap->ability_match = 0;
  3850. ap->ack_match = 0;
  3851. rx_cfg_reg = 0;
  3852. }
  3853. ap->rxconfig = rx_cfg_reg;
  3854. ret = ANEG_OK;
  3855. switch (ap->state) {
  3856. case ANEG_STATE_UNKNOWN:
  3857. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  3858. ap->state = ANEG_STATE_AN_ENABLE;
  3859. /* fallthru */
  3860. case ANEG_STATE_AN_ENABLE:
  3861. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  3862. if (ap->flags & MR_AN_ENABLE) {
  3863. ap->link_time = 0;
  3864. ap->cur_time = 0;
  3865. ap->ability_match_cfg = 0;
  3866. ap->ability_match_count = 0;
  3867. ap->ability_match = 0;
  3868. ap->idle_match = 0;
  3869. ap->ack_match = 0;
  3870. ap->state = ANEG_STATE_RESTART_INIT;
  3871. } else {
  3872. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  3873. }
  3874. break;
  3875. case ANEG_STATE_RESTART_INIT:
  3876. ap->link_time = ap->cur_time;
  3877. ap->flags &= ~(MR_NP_LOADED);
  3878. ap->txconfig = 0;
  3879. tw32(MAC_TX_AUTO_NEG, 0);
  3880. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  3881. tw32_f(MAC_MODE, tp->mac_mode);
  3882. udelay(40);
  3883. ret = ANEG_TIMER_ENAB;
  3884. ap->state = ANEG_STATE_RESTART;
  3885. /* fallthru */
  3886. case ANEG_STATE_RESTART:
  3887. delta = ap->cur_time - ap->link_time;
  3888. if (delta > ANEG_STATE_SETTLE_TIME)
  3889. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  3890. else
  3891. ret = ANEG_TIMER_ENAB;
  3892. break;
  3893. case ANEG_STATE_DISABLE_LINK_OK:
  3894. ret = ANEG_DONE;
  3895. break;
  3896. case ANEG_STATE_ABILITY_DETECT_INIT:
  3897. ap->flags &= ~(MR_TOGGLE_TX);
  3898. ap->txconfig = ANEG_CFG_FD;
  3899. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  3900. if (flowctrl & ADVERTISE_1000XPAUSE)
  3901. ap->txconfig |= ANEG_CFG_PS1;
  3902. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  3903. ap->txconfig |= ANEG_CFG_PS2;
  3904. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  3905. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  3906. tw32_f(MAC_MODE, tp->mac_mode);
  3907. udelay(40);
  3908. ap->state = ANEG_STATE_ABILITY_DETECT;
  3909. break;
  3910. case ANEG_STATE_ABILITY_DETECT:
  3911. if (ap->ability_match != 0 && ap->rxconfig != 0)
  3912. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  3913. break;
  3914. case ANEG_STATE_ACK_DETECT_INIT:
  3915. ap->txconfig |= ANEG_CFG_ACK;
  3916. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  3917. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  3918. tw32_f(MAC_MODE, tp->mac_mode);
  3919. udelay(40);
  3920. ap->state = ANEG_STATE_ACK_DETECT;
  3921. /* fallthru */
  3922. case ANEG_STATE_ACK_DETECT:
  3923. if (ap->ack_match != 0) {
  3924. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  3925. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  3926. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  3927. } else {
  3928. ap->state = ANEG_STATE_AN_ENABLE;
  3929. }
  3930. } else if (ap->ability_match != 0 &&
  3931. ap->rxconfig == 0) {
  3932. ap->state = ANEG_STATE_AN_ENABLE;
  3933. }
  3934. break;
  3935. case ANEG_STATE_COMPLETE_ACK_INIT:
  3936. if (ap->rxconfig & ANEG_CFG_INVAL) {
  3937. ret = ANEG_FAILED;
  3938. break;
  3939. }
  3940. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  3941. MR_LP_ADV_HALF_DUPLEX |
  3942. MR_LP_ADV_SYM_PAUSE |
  3943. MR_LP_ADV_ASYM_PAUSE |
  3944. MR_LP_ADV_REMOTE_FAULT1 |
  3945. MR_LP_ADV_REMOTE_FAULT2 |
  3946. MR_LP_ADV_NEXT_PAGE |
  3947. MR_TOGGLE_RX |
  3948. MR_NP_RX);
  3949. if (ap->rxconfig & ANEG_CFG_FD)
  3950. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  3951. if (ap->rxconfig & ANEG_CFG_HD)
  3952. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  3953. if (ap->rxconfig & ANEG_CFG_PS1)
  3954. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  3955. if (ap->rxconfig & ANEG_CFG_PS2)
  3956. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  3957. if (ap->rxconfig & ANEG_CFG_RF1)
  3958. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  3959. if (ap->rxconfig & ANEG_CFG_RF2)
  3960. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  3961. if (ap->rxconfig & ANEG_CFG_NP)
  3962. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  3963. ap->link_time = ap->cur_time;
  3964. ap->flags ^= (MR_TOGGLE_TX);
  3965. if (ap->rxconfig & 0x0008)
  3966. ap->flags |= MR_TOGGLE_RX;
  3967. if (ap->rxconfig & ANEG_CFG_NP)
  3968. ap->flags |= MR_NP_RX;
  3969. ap->flags |= MR_PAGE_RX;
  3970. ap->state = ANEG_STATE_COMPLETE_ACK;
  3971. ret = ANEG_TIMER_ENAB;
  3972. break;
  3973. case ANEG_STATE_COMPLETE_ACK:
  3974. if (ap->ability_match != 0 &&
  3975. ap->rxconfig == 0) {
  3976. ap->state = ANEG_STATE_AN_ENABLE;
  3977. break;
  3978. }
  3979. delta = ap->cur_time - ap->link_time;
  3980. if (delta > ANEG_STATE_SETTLE_TIME) {
  3981. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  3982. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  3983. } else {
  3984. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  3985. !(ap->flags & MR_NP_RX)) {
  3986. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  3987. } else {
  3988. ret = ANEG_FAILED;
  3989. }
  3990. }
  3991. }
  3992. break;
  3993. case ANEG_STATE_IDLE_DETECT_INIT:
  3994. ap->link_time = ap->cur_time;
  3995. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  3996. tw32_f(MAC_MODE, tp->mac_mode);
  3997. udelay(40);
  3998. ap->state = ANEG_STATE_IDLE_DETECT;
  3999. ret = ANEG_TIMER_ENAB;
  4000. break;
  4001. case ANEG_STATE_IDLE_DETECT:
  4002. if (ap->ability_match != 0 &&
  4003. ap->rxconfig == 0) {
  4004. ap->state = ANEG_STATE_AN_ENABLE;
  4005. break;
  4006. }
  4007. delta = ap->cur_time - ap->link_time;
  4008. if (delta > ANEG_STATE_SETTLE_TIME) {
  4009. /* XXX another gem from the Broadcom driver :( */
  4010. ap->state = ANEG_STATE_LINK_OK;
  4011. }
  4012. break;
  4013. case ANEG_STATE_LINK_OK:
  4014. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  4015. ret = ANEG_DONE;
  4016. break;
  4017. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  4018. /* ??? unimplemented */
  4019. break;
  4020. case ANEG_STATE_NEXT_PAGE_WAIT:
  4021. /* ??? unimplemented */
  4022. break;
  4023. default:
  4024. ret = ANEG_FAILED;
  4025. break;
  4026. }
  4027. return ret;
  4028. }
  4029. static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
  4030. {
  4031. int res = 0;
  4032. struct tg3_fiber_aneginfo aninfo;
  4033. int status = ANEG_FAILED;
  4034. unsigned int tick;
  4035. u32 tmp;
  4036. tw32_f(MAC_TX_AUTO_NEG, 0);
  4037. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  4038. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  4039. udelay(40);
  4040. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  4041. udelay(40);
  4042. memset(&aninfo, 0, sizeof(aninfo));
  4043. aninfo.flags |= MR_AN_ENABLE;
  4044. aninfo.state = ANEG_STATE_UNKNOWN;
  4045. aninfo.cur_time = 0;
  4046. tick = 0;
  4047. while (++tick < 195000) {
  4048. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  4049. if (status == ANEG_DONE || status == ANEG_FAILED)
  4050. break;
  4051. udelay(1);
  4052. }
  4053. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  4054. tw32_f(MAC_MODE, tp->mac_mode);
  4055. udelay(40);
  4056. *txflags = aninfo.txconfig;
  4057. *rxflags = aninfo.flags;
  4058. if (status == ANEG_DONE &&
  4059. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  4060. MR_LP_ADV_FULL_DUPLEX)))
  4061. res = 1;
  4062. return res;
  4063. }
  4064. static void tg3_init_bcm8002(struct tg3 *tp)
  4065. {
  4066. u32 mac_status = tr32(MAC_STATUS);
  4067. int i;
  4068. /* Reset when initting first time or we have a link. */
  4069. if (tg3_flag(tp, INIT_COMPLETE) &&
  4070. !(mac_status & MAC_STATUS_PCS_SYNCED))
  4071. return;
  4072. /* Set PLL lock range. */
  4073. tg3_writephy(tp, 0x16, 0x8007);
  4074. /* SW reset */
  4075. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  4076. /* Wait for reset to complete. */
  4077. /* XXX schedule_timeout() ... */
  4078. for (i = 0; i < 500; i++)
  4079. udelay(10);
  4080. /* Config mode; select PMA/Ch 1 regs. */
  4081. tg3_writephy(tp, 0x10, 0x8411);
  4082. /* Enable auto-lock and comdet, select txclk for tx. */
  4083. tg3_writephy(tp, 0x11, 0x0a10);
  4084. tg3_writephy(tp, 0x18, 0x00a0);
  4085. tg3_writephy(tp, 0x16, 0x41ff);
  4086. /* Assert and deassert POR. */
  4087. tg3_writephy(tp, 0x13, 0x0400);
  4088. udelay(40);
  4089. tg3_writephy(tp, 0x13, 0x0000);
  4090. tg3_writephy(tp, 0x11, 0x0a50);
  4091. udelay(40);
  4092. tg3_writephy(tp, 0x11, 0x0a10);
  4093. /* Wait for signal to stabilize */
  4094. /* XXX schedule_timeout() ... */
  4095. for (i = 0; i < 15000; i++)
  4096. udelay(10);
  4097. /* Deselect the channel register so we can read the PHYID
  4098. * later.
  4099. */
  4100. tg3_writephy(tp, 0x10, 0x8011);
  4101. }
  4102. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  4103. {
  4104. u16 flowctrl;
  4105. u32 sg_dig_ctrl, sg_dig_status;
  4106. u32 serdes_cfg, expected_sg_dig_ctrl;
  4107. int workaround, port_a;
  4108. int current_link_up;
  4109. serdes_cfg = 0;
  4110. expected_sg_dig_ctrl = 0;
  4111. workaround = 0;
  4112. port_a = 1;
  4113. current_link_up = 0;
  4114. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
  4115. tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
  4116. workaround = 1;
  4117. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  4118. port_a = 0;
  4119. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  4120. /* preserve bits 20-23 for voltage regulator */
  4121. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  4122. }
  4123. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  4124. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  4125. if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
  4126. if (workaround) {
  4127. u32 val = serdes_cfg;
  4128. if (port_a)
  4129. val |= 0xc010000;
  4130. else
  4131. val |= 0x4010000;
  4132. tw32_f(MAC_SERDES_CFG, val);
  4133. }
  4134. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  4135. }
  4136. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  4137. tg3_setup_flow_control(tp, 0, 0);
  4138. current_link_up = 1;
  4139. }
  4140. goto out;
  4141. }
  4142. /* Want auto-negotiation. */
  4143. expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
  4144. flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4145. if (flowctrl & ADVERTISE_1000XPAUSE)
  4146. expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
  4147. if (flowctrl & ADVERTISE_1000XPSE_ASYM)
  4148. expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
  4149. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  4150. if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
  4151. tp->serdes_counter &&
  4152. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  4153. MAC_STATUS_RCVD_CFG)) ==
  4154. MAC_STATUS_PCS_SYNCED)) {
  4155. tp->serdes_counter--;
  4156. current_link_up = 1;
  4157. goto out;
  4158. }
  4159. restart_autoneg:
  4160. if (workaround)
  4161. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  4162. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
  4163. udelay(5);
  4164. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  4165. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  4166. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4167. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  4168. MAC_STATUS_SIGNAL_DET)) {
  4169. sg_dig_status = tr32(SG_DIG_STATUS);
  4170. mac_status = tr32(MAC_STATUS);
  4171. if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
  4172. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  4173. u32 local_adv = 0, remote_adv = 0;
  4174. if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
  4175. local_adv |= ADVERTISE_1000XPAUSE;
  4176. if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
  4177. local_adv |= ADVERTISE_1000XPSE_ASYM;
  4178. if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
  4179. remote_adv |= LPA_1000XPAUSE;
  4180. if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
  4181. remote_adv |= LPA_1000XPAUSE_ASYM;
  4182. tp->link_config.rmt_adv =
  4183. mii_adv_to_ethtool_adv_x(remote_adv);
  4184. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4185. current_link_up = 1;
  4186. tp->serdes_counter = 0;
  4187. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4188. } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
  4189. if (tp->serdes_counter)
  4190. tp->serdes_counter--;
  4191. else {
  4192. if (workaround) {
  4193. u32 val = serdes_cfg;
  4194. if (port_a)
  4195. val |= 0xc010000;
  4196. else
  4197. val |= 0x4010000;
  4198. tw32_f(MAC_SERDES_CFG, val);
  4199. }
  4200. tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
  4201. udelay(40);
  4202. /* Link parallel detection - link is up */
  4203. /* only if we have PCS_SYNC and not */
  4204. /* receiving config code words */
  4205. mac_status = tr32(MAC_STATUS);
  4206. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  4207. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  4208. tg3_setup_flow_control(tp, 0, 0);
  4209. current_link_up = 1;
  4210. tp->phy_flags |=
  4211. TG3_PHYFLG_PARALLEL_DETECT;
  4212. tp->serdes_counter =
  4213. SERDES_PARALLEL_DET_TIMEOUT;
  4214. } else
  4215. goto restart_autoneg;
  4216. }
  4217. }
  4218. } else {
  4219. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  4220. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4221. }
  4222. out:
  4223. return current_link_up;
  4224. }
  4225. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  4226. {
  4227. int current_link_up = 0;
  4228. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  4229. goto out;
  4230. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  4231. u32 txflags, rxflags;
  4232. int i;
  4233. if (fiber_autoneg(tp, &txflags, &rxflags)) {
  4234. u32 local_adv = 0, remote_adv = 0;
  4235. if (txflags & ANEG_CFG_PS1)
  4236. local_adv |= ADVERTISE_1000XPAUSE;
  4237. if (txflags & ANEG_CFG_PS2)
  4238. local_adv |= ADVERTISE_1000XPSE_ASYM;
  4239. if (rxflags & MR_LP_ADV_SYM_PAUSE)
  4240. remote_adv |= LPA_1000XPAUSE;
  4241. if (rxflags & MR_LP_ADV_ASYM_PAUSE)
  4242. remote_adv |= LPA_1000XPAUSE_ASYM;
  4243. tp->link_config.rmt_adv =
  4244. mii_adv_to_ethtool_adv_x(remote_adv);
  4245. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4246. current_link_up = 1;
  4247. }
  4248. for (i = 0; i < 30; i++) {
  4249. udelay(20);
  4250. tw32_f(MAC_STATUS,
  4251. (MAC_STATUS_SYNC_CHANGED |
  4252. MAC_STATUS_CFG_CHANGED));
  4253. udelay(40);
  4254. if ((tr32(MAC_STATUS) &
  4255. (MAC_STATUS_SYNC_CHANGED |
  4256. MAC_STATUS_CFG_CHANGED)) == 0)
  4257. break;
  4258. }
  4259. mac_status = tr32(MAC_STATUS);
  4260. if (current_link_up == 0 &&
  4261. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  4262. !(mac_status & MAC_STATUS_RCVD_CFG))
  4263. current_link_up = 1;
  4264. } else {
  4265. tg3_setup_flow_control(tp, 0, 0);
  4266. /* Forcing 1000FD link up. */
  4267. current_link_up = 1;
  4268. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  4269. udelay(40);
  4270. tw32_f(MAC_MODE, tp->mac_mode);
  4271. udelay(40);
  4272. }
  4273. out:
  4274. return current_link_up;
  4275. }
  4276. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  4277. {
  4278. u32 orig_pause_cfg;
  4279. u16 orig_active_speed;
  4280. u8 orig_active_duplex;
  4281. u32 mac_status;
  4282. int current_link_up;
  4283. int i;
  4284. orig_pause_cfg = tp->link_config.active_flowctrl;
  4285. orig_active_speed = tp->link_config.active_speed;
  4286. orig_active_duplex = tp->link_config.active_duplex;
  4287. if (!tg3_flag(tp, HW_AUTONEG) &&
  4288. tp->link_up &&
  4289. tg3_flag(tp, INIT_COMPLETE)) {
  4290. mac_status = tr32(MAC_STATUS);
  4291. mac_status &= (MAC_STATUS_PCS_SYNCED |
  4292. MAC_STATUS_SIGNAL_DET |
  4293. MAC_STATUS_CFG_CHANGED |
  4294. MAC_STATUS_RCVD_CFG);
  4295. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  4296. MAC_STATUS_SIGNAL_DET)) {
  4297. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  4298. MAC_STATUS_CFG_CHANGED));
  4299. return 0;
  4300. }
  4301. }
  4302. tw32_f(MAC_TX_AUTO_NEG, 0);
  4303. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  4304. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  4305. tw32_f(MAC_MODE, tp->mac_mode);
  4306. udelay(40);
  4307. if (tp->phy_id == TG3_PHY_ID_BCM8002)
  4308. tg3_init_bcm8002(tp);
  4309. /* Enable link change event even when serdes polling. */
  4310. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4311. udelay(40);
  4312. current_link_up = 0;
  4313. tp->link_config.rmt_adv = 0;
  4314. mac_status = tr32(MAC_STATUS);
  4315. if (tg3_flag(tp, HW_AUTONEG))
  4316. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  4317. else
  4318. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  4319. tp->napi[0].hw_status->status =
  4320. (SD_STATUS_UPDATED |
  4321. (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
  4322. for (i = 0; i < 100; i++) {
  4323. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  4324. MAC_STATUS_CFG_CHANGED));
  4325. udelay(5);
  4326. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  4327. MAC_STATUS_CFG_CHANGED |
  4328. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  4329. break;
  4330. }
  4331. mac_status = tr32(MAC_STATUS);
  4332. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  4333. current_link_up = 0;
  4334. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  4335. tp->serdes_counter == 0) {
  4336. tw32_f(MAC_MODE, (tp->mac_mode |
  4337. MAC_MODE_SEND_CONFIGS));
  4338. udelay(1);
  4339. tw32_f(MAC_MODE, tp->mac_mode);
  4340. }
  4341. }
  4342. if (current_link_up == 1) {
  4343. tp->link_config.active_speed = SPEED_1000;
  4344. tp->link_config.active_duplex = DUPLEX_FULL;
  4345. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  4346. LED_CTRL_LNKLED_OVERRIDE |
  4347. LED_CTRL_1000MBPS_ON));
  4348. } else {
  4349. tp->link_config.active_speed = SPEED_UNKNOWN;
  4350. tp->link_config.active_duplex = DUPLEX_UNKNOWN;
  4351. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  4352. LED_CTRL_LNKLED_OVERRIDE |
  4353. LED_CTRL_TRAFFIC_OVERRIDE));
  4354. }
  4355. if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
  4356. u32 now_pause_cfg = tp->link_config.active_flowctrl;
  4357. if (orig_pause_cfg != now_pause_cfg ||
  4358. orig_active_speed != tp->link_config.active_speed ||
  4359. orig_active_duplex != tp->link_config.active_duplex)
  4360. tg3_link_report(tp);
  4361. }
  4362. return 0;
  4363. }
  4364. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  4365. {
  4366. int current_link_up, err = 0;
  4367. u32 bmsr, bmcr;
  4368. u16 current_speed;
  4369. u8 current_duplex;
  4370. u32 local_adv, remote_adv;
  4371. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  4372. tw32_f(MAC_MODE, tp->mac_mode);
  4373. udelay(40);
  4374. tw32(MAC_EVENT, 0);
  4375. tw32_f(MAC_STATUS,
  4376. (MAC_STATUS_SYNC_CHANGED |
  4377. MAC_STATUS_CFG_CHANGED |
  4378. MAC_STATUS_MI_COMPLETION |
  4379. MAC_STATUS_LNKSTATE_CHANGED));
  4380. udelay(40);
  4381. if (force_reset)
  4382. tg3_phy_reset(tp);
  4383. current_link_up = 0;
  4384. current_speed = SPEED_UNKNOWN;
  4385. current_duplex = DUPLEX_UNKNOWN;
  4386. tp->link_config.rmt_adv = 0;
  4387. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4388. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4389. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  4390. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  4391. bmsr |= BMSR_LSTATUS;
  4392. else
  4393. bmsr &= ~BMSR_LSTATUS;
  4394. }
  4395. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  4396. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  4397. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  4398. /* do nothing, just check for link up at the end */
  4399. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  4400. u32 adv, newadv;
  4401. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  4402. newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  4403. ADVERTISE_1000XPAUSE |
  4404. ADVERTISE_1000XPSE_ASYM |
  4405. ADVERTISE_SLCT);
  4406. newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
  4407. newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
  4408. if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
  4409. tg3_writephy(tp, MII_ADVERTISE, newadv);
  4410. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  4411. tg3_writephy(tp, MII_BMCR, bmcr);
  4412. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4413. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  4414. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4415. return err;
  4416. }
  4417. } else {
  4418. u32 new_bmcr;
  4419. bmcr &= ~BMCR_SPEED1000;
  4420. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  4421. if (tp->link_config.duplex == DUPLEX_FULL)
  4422. new_bmcr |= BMCR_FULLDPLX;
  4423. if (new_bmcr != bmcr) {
  4424. /* BMCR_SPEED1000 is a reserved bit that needs
  4425. * to be set on write.
  4426. */
  4427. new_bmcr |= BMCR_SPEED1000;
  4428. /* Force a linkdown */
  4429. if (tp->link_up) {
  4430. u32 adv;
  4431. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  4432. adv &= ~(ADVERTISE_1000XFULL |
  4433. ADVERTISE_1000XHALF |
  4434. ADVERTISE_SLCT);
  4435. tg3_writephy(tp, MII_ADVERTISE, adv);
  4436. tg3_writephy(tp, MII_BMCR, bmcr |
  4437. BMCR_ANRESTART |
  4438. BMCR_ANENABLE);
  4439. udelay(10);
  4440. tg3_carrier_off(tp);
  4441. }
  4442. tg3_writephy(tp, MII_BMCR, new_bmcr);
  4443. bmcr = new_bmcr;
  4444. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4445. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  4446. if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  4447. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  4448. bmsr |= BMSR_LSTATUS;
  4449. else
  4450. bmsr &= ~BMSR_LSTATUS;
  4451. }
  4452. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4453. }
  4454. }
  4455. if (bmsr & BMSR_LSTATUS) {
  4456. current_speed = SPEED_1000;
  4457. current_link_up = 1;
  4458. if (bmcr & BMCR_FULLDPLX)
  4459. current_duplex = DUPLEX_FULL;
  4460. else
  4461. current_duplex = DUPLEX_HALF;
  4462. local_adv = 0;
  4463. remote_adv = 0;
  4464. if (bmcr & BMCR_ANENABLE) {
  4465. u32 common;
  4466. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  4467. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  4468. common = local_adv & remote_adv;
  4469. if (common & (ADVERTISE_1000XHALF |
  4470. ADVERTISE_1000XFULL)) {
  4471. if (common & ADVERTISE_1000XFULL)
  4472. current_duplex = DUPLEX_FULL;
  4473. else
  4474. current_duplex = DUPLEX_HALF;
  4475. tp->link_config.rmt_adv =
  4476. mii_adv_to_ethtool_adv_x(remote_adv);
  4477. } else if (!tg3_flag(tp, 5780_CLASS)) {
  4478. /* Link is up via parallel detect */
  4479. } else {
  4480. current_link_up = 0;
  4481. }
  4482. }
  4483. }
  4484. if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
  4485. tg3_setup_flow_control(tp, local_adv, remote_adv);
  4486. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  4487. if (tp->link_config.active_duplex == DUPLEX_HALF)
  4488. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  4489. tw32_f(MAC_MODE, tp->mac_mode);
  4490. udelay(40);
  4491. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  4492. tp->link_config.active_speed = current_speed;
  4493. tp->link_config.active_duplex = current_duplex;
  4494. tg3_test_and_report_link_chg(tp, current_link_up);
  4495. return err;
  4496. }
  4497. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  4498. {
  4499. if (tp->serdes_counter) {
  4500. /* Give autoneg time to complete. */
  4501. tp->serdes_counter--;
  4502. return;
  4503. }
  4504. if (!tp->link_up &&
  4505. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  4506. u32 bmcr;
  4507. tg3_readphy(tp, MII_BMCR, &bmcr);
  4508. if (bmcr & BMCR_ANENABLE) {
  4509. u32 phy1, phy2;
  4510. /* Select shadow register 0x1f */
  4511. tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
  4512. tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
  4513. /* Select expansion interrupt status register */
  4514. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  4515. MII_TG3_DSP_EXP1_INT_STAT);
  4516. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4517. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4518. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  4519. /* We have signal detect and not receiving
  4520. * config code words, link is up by parallel
  4521. * detection.
  4522. */
  4523. bmcr &= ~BMCR_ANENABLE;
  4524. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  4525. tg3_writephy(tp, MII_BMCR, bmcr);
  4526. tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
  4527. }
  4528. }
  4529. } else if (tp->link_up &&
  4530. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  4531. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
  4532. u32 phy2;
  4533. /* Select expansion interrupt status register */
  4534. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  4535. MII_TG3_DSP_EXP1_INT_STAT);
  4536. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
  4537. if (phy2 & 0x20) {
  4538. u32 bmcr;
  4539. /* Config code words received, turn on autoneg. */
  4540. tg3_readphy(tp, MII_BMCR, &bmcr);
  4541. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  4542. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  4543. }
  4544. }
  4545. }
  4546. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  4547. {
  4548. u32 val;
  4549. int err;
  4550. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  4551. err = tg3_setup_fiber_phy(tp, force_reset);
  4552. else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  4553. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  4554. else
  4555. err = tg3_setup_copper_phy(tp, force_reset);
  4556. if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
  4557. u32 scale;
  4558. val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
  4559. if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
  4560. scale = 65;
  4561. else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
  4562. scale = 6;
  4563. else
  4564. scale = 12;
  4565. val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
  4566. val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
  4567. tw32(GRC_MISC_CFG, val);
  4568. }
  4569. val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  4570. (6 << TX_LENGTHS_IPG_SHIFT);
  4571. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  4572. tg3_asic_rev(tp) == ASIC_REV_5762)
  4573. val |= tr32(MAC_TX_LENGTHS) &
  4574. (TX_LENGTHS_JMB_FRM_LEN_MSK |
  4575. TX_LENGTHS_CNT_DWN_VAL_MSK);
  4576. if (tp->link_config.active_speed == SPEED_1000 &&
  4577. tp->link_config.active_duplex == DUPLEX_HALF)
  4578. tw32(MAC_TX_LENGTHS, val |
  4579. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
  4580. else
  4581. tw32(MAC_TX_LENGTHS, val |
  4582. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  4583. if (!tg3_flag(tp, 5705_PLUS)) {
  4584. if (tp->link_up) {
  4585. tw32(HOSTCC_STAT_COAL_TICKS,
  4586. tp->coal.stats_block_coalesce_usecs);
  4587. } else {
  4588. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  4589. }
  4590. }
  4591. if (tg3_flag(tp, ASPM_WORKAROUND)) {
  4592. val = tr32(PCIE_PWR_MGMT_THRESH);
  4593. if (!tp->link_up)
  4594. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  4595. tp->pwrmgmt_thresh;
  4596. else
  4597. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  4598. tw32(PCIE_PWR_MGMT_THRESH, val);
  4599. }
  4600. return err;
  4601. }
  4602. /* tp->lock must be held */
  4603. static u64 tg3_refclk_read(struct tg3 *tp)
  4604. {
  4605. u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
  4606. return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
  4607. }
  4608. /* tp->lock must be held */
  4609. static void tg3_refclk_write(struct tg3 *tp, u64 newval)
  4610. {
  4611. tw32(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_STOP);
  4612. tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
  4613. tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
  4614. tw32_f(TG3_EAV_REF_CLCK_CTL, TG3_EAV_REF_CLCK_CTL_RESUME);
  4615. }
  4616. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
  4617. static inline void tg3_full_unlock(struct tg3 *tp);
  4618. static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
  4619. {
  4620. struct tg3 *tp = netdev_priv(dev);
  4621. info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
  4622. SOF_TIMESTAMPING_RX_SOFTWARE |
  4623. SOF_TIMESTAMPING_SOFTWARE |
  4624. SOF_TIMESTAMPING_TX_HARDWARE |
  4625. SOF_TIMESTAMPING_RX_HARDWARE |
  4626. SOF_TIMESTAMPING_RAW_HARDWARE;
  4627. if (tp->ptp_clock)
  4628. info->phc_index = ptp_clock_index(tp->ptp_clock);
  4629. else
  4630. info->phc_index = -1;
  4631. info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
  4632. info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
  4633. (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
  4634. (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
  4635. (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
  4636. return 0;
  4637. }
  4638. static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
  4639. {
  4640. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  4641. bool neg_adj = false;
  4642. u32 correction = 0;
  4643. if (ppb < 0) {
  4644. neg_adj = true;
  4645. ppb = -ppb;
  4646. }
  4647. /* Frequency adjustment is performed using hardware with a 24 bit
  4648. * accumulator and a programmable correction value. On each clk, the
  4649. * correction value gets added to the accumulator and when it
  4650. * overflows, the time counter is incremented/decremented.
  4651. *
  4652. * So conversion from ppb to correction value is
  4653. * ppb * (1 << 24) / 1000000000
  4654. */
  4655. correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
  4656. TG3_EAV_REF_CLK_CORRECT_MASK;
  4657. tg3_full_lock(tp, 0);
  4658. if (correction)
  4659. tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
  4660. TG3_EAV_REF_CLK_CORRECT_EN |
  4661. (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
  4662. else
  4663. tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
  4664. tg3_full_unlock(tp);
  4665. return 0;
  4666. }
  4667. static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
  4668. {
  4669. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  4670. tg3_full_lock(tp, 0);
  4671. tp->ptp_adjust += delta;
  4672. tg3_full_unlock(tp);
  4673. return 0;
  4674. }
  4675. static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
  4676. {
  4677. u64 ns;
  4678. u32 remainder;
  4679. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  4680. tg3_full_lock(tp, 0);
  4681. ns = tg3_refclk_read(tp);
  4682. ns += tp->ptp_adjust;
  4683. tg3_full_unlock(tp);
  4684. ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
  4685. ts->tv_nsec = remainder;
  4686. return 0;
  4687. }
  4688. static int tg3_ptp_settime(struct ptp_clock_info *ptp,
  4689. const struct timespec *ts)
  4690. {
  4691. u64 ns;
  4692. struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
  4693. ns = timespec_to_ns(ts);
  4694. tg3_full_lock(tp, 0);
  4695. tg3_refclk_write(tp, ns);
  4696. tp->ptp_adjust = 0;
  4697. tg3_full_unlock(tp);
  4698. return 0;
  4699. }
  4700. static int tg3_ptp_enable(struct ptp_clock_info *ptp,
  4701. struct ptp_clock_request *rq, int on)
  4702. {
  4703. return -EOPNOTSUPP;
  4704. }
  4705. static const struct ptp_clock_info tg3_ptp_caps = {
  4706. .owner = THIS_MODULE,
  4707. .name = "tg3 clock",
  4708. .max_adj = 250000000,
  4709. .n_alarm = 0,
  4710. .n_ext_ts = 0,
  4711. .n_per_out = 0,
  4712. .pps = 0,
  4713. .adjfreq = tg3_ptp_adjfreq,
  4714. .adjtime = tg3_ptp_adjtime,
  4715. .gettime = tg3_ptp_gettime,
  4716. .settime = tg3_ptp_settime,
  4717. .enable = tg3_ptp_enable,
  4718. };
  4719. static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
  4720. struct skb_shared_hwtstamps *timestamp)
  4721. {
  4722. memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
  4723. timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
  4724. tp->ptp_adjust);
  4725. }
  4726. /* tp->lock must be held */
  4727. static void tg3_ptp_init(struct tg3 *tp)
  4728. {
  4729. if (!tg3_flag(tp, PTP_CAPABLE))
  4730. return;
  4731. /* Initialize the hardware clock to the system time. */
  4732. tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
  4733. tp->ptp_adjust = 0;
  4734. tp->ptp_info = tg3_ptp_caps;
  4735. }
  4736. /* tp->lock must be held */
  4737. static void tg3_ptp_resume(struct tg3 *tp)
  4738. {
  4739. if (!tg3_flag(tp, PTP_CAPABLE))
  4740. return;
  4741. tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
  4742. tp->ptp_adjust = 0;
  4743. }
  4744. static void tg3_ptp_fini(struct tg3 *tp)
  4745. {
  4746. if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
  4747. return;
  4748. ptp_clock_unregister(tp->ptp_clock);
  4749. tp->ptp_clock = NULL;
  4750. tp->ptp_adjust = 0;
  4751. }
  4752. static inline int tg3_irq_sync(struct tg3 *tp)
  4753. {
  4754. return tp->irq_sync;
  4755. }
  4756. static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
  4757. {
  4758. int i;
  4759. dst = (u32 *)((u8 *)dst + off);
  4760. for (i = 0; i < len; i += sizeof(u32))
  4761. *dst++ = tr32(off + i);
  4762. }
  4763. static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
  4764. {
  4765. tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
  4766. tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
  4767. tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
  4768. tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
  4769. tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
  4770. tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
  4771. tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
  4772. tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
  4773. tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
  4774. tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
  4775. tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
  4776. tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
  4777. tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
  4778. tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
  4779. tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
  4780. tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
  4781. tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
  4782. tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
  4783. tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
  4784. if (tg3_flag(tp, SUPPORT_MSIX))
  4785. tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
  4786. tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
  4787. tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
  4788. tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
  4789. tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
  4790. tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
  4791. tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
  4792. tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
  4793. tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
  4794. if (!tg3_flag(tp, 5705_PLUS)) {
  4795. tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
  4796. tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
  4797. tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
  4798. }
  4799. tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
  4800. tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
  4801. tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
  4802. tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
  4803. tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
  4804. if (tg3_flag(tp, NVRAM))
  4805. tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
  4806. }
  4807. static void tg3_dump_state(struct tg3 *tp)
  4808. {
  4809. int i;
  4810. u32 *regs;
  4811. regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
  4812. if (!regs)
  4813. return;
  4814. if (tg3_flag(tp, PCI_EXPRESS)) {
  4815. /* Read up to but not including private PCI registers */
  4816. for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
  4817. regs[i / sizeof(u32)] = tr32(i);
  4818. } else
  4819. tg3_dump_legacy_regs(tp, regs);
  4820. for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
  4821. if (!regs[i + 0] && !regs[i + 1] &&
  4822. !regs[i + 2] && !regs[i + 3])
  4823. continue;
  4824. netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
  4825. i * 4,
  4826. regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
  4827. }
  4828. kfree(regs);
  4829. for (i = 0; i < tp->irq_cnt; i++) {
  4830. struct tg3_napi *tnapi = &tp->napi[i];
  4831. /* SW status block */
  4832. netdev_err(tp->dev,
  4833. "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  4834. i,
  4835. tnapi->hw_status->status,
  4836. tnapi->hw_status->status_tag,
  4837. tnapi->hw_status->rx_jumbo_consumer,
  4838. tnapi->hw_status->rx_consumer,
  4839. tnapi->hw_status->rx_mini_consumer,
  4840. tnapi->hw_status->idx[0].rx_producer,
  4841. tnapi->hw_status->idx[0].tx_consumer);
  4842. netdev_err(tp->dev,
  4843. "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
  4844. i,
  4845. tnapi->last_tag, tnapi->last_irq_tag,
  4846. tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
  4847. tnapi->rx_rcb_ptr,
  4848. tnapi->prodring.rx_std_prod_idx,
  4849. tnapi->prodring.rx_std_cons_idx,
  4850. tnapi->prodring.rx_jmb_prod_idx,
  4851. tnapi->prodring.rx_jmb_cons_idx);
  4852. }
  4853. }
  4854. /* This is called whenever we suspect that the system chipset is re-
  4855. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  4856. * is bogus tx completions. We try to recover by setting the
  4857. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  4858. * in the workqueue.
  4859. */
  4860. static void tg3_tx_recover(struct tg3 *tp)
  4861. {
  4862. BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
  4863. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  4864. netdev_warn(tp->dev,
  4865. "The system may be re-ordering memory-mapped I/O "
  4866. "cycles to the network device, attempting to recover. "
  4867. "Please report the problem to the driver maintainer "
  4868. "and include system chipset information.\n");
  4869. spin_lock(&tp->lock);
  4870. tg3_flag_set(tp, TX_RECOVERY_PENDING);
  4871. spin_unlock(&tp->lock);
  4872. }
  4873. static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
  4874. {
  4875. /* Tell compiler to fetch tx indices from memory. */
  4876. barrier();
  4877. return tnapi->tx_pending -
  4878. ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
  4879. }
  4880. /* Tigon3 never reports partial packet sends. So we do not
  4881. * need special logic to handle SKBs that have not had all
  4882. * of their frags sent yet, like SunGEM does.
  4883. */
  4884. static void tg3_tx(struct tg3_napi *tnapi)
  4885. {
  4886. struct tg3 *tp = tnapi->tp;
  4887. u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
  4888. u32 sw_idx = tnapi->tx_cons;
  4889. struct netdev_queue *txq;
  4890. int index = tnapi - tp->napi;
  4891. unsigned int pkts_compl = 0, bytes_compl = 0;
  4892. if (tg3_flag(tp, ENABLE_TSS))
  4893. index--;
  4894. txq = netdev_get_tx_queue(tp->dev, index);
  4895. while (sw_idx != hw_idx) {
  4896. struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
  4897. struct sk_buff *skb = ri->skb;
  4898. int i, tx_bug = 0;
  4899. if (unlikely(skb == NULL)) {
  4900. tg3_tx_recover(tp);
  4901. return;
  4902. }
  4903. if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
  4904. struct skb_shared_hwtstamps timestamp;
  4905. u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
  4906. hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
  4907. tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);
  4908. skb_tstamp_tx(skb, &timestamp);
  4909. }
  4910. pci_unmap_single(tp->pdev,
  4911. dma_unmap_addr(ri, mapping),
  4912. skb_headlen(skb),
  4913. PCI_DMA_TODEVICE);
  4914. ri->skb = NULL;
  4915. while (ri->fragmented) {
  4916. ri->fragmented = false;
  4917. sw_idx = NEXT_TX(sw_idx);
  4918. ri = &tnapi->tx_buffers[sw_idx];
  4919. }
  4920. sw_idx = NEXT_TX(sw_idx);
  4921. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  4922. ri = &tnapi->tx_buffers[sw_idx];
  4923. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  4924. tx_bug = 1;
  4925. pci_unmap_page(tp->pdev,
  4926. dma_unmap_addr(ri, mapping),
  4927. skb_frag_size(&skb_shinfo(skb)->frags[i]),
  4928. PCI_DMA_TODEVICE);
  4929. while (ri->fragmented) {
  4930. ri->fragmented = false;
  4931. sw_idx = NEXT_TX(sw_idx);
  4932. ri = &tnapi->tx_buffers[sw_idx];
  4933. }
  4934. sw_idx = NEXT_TX(sw_idx);
  4935. }
  4936. pkts_compl++;
  4937. bytes_compl += skb->len;
  4938. dev_kfree_skb(skb);
  4939. if (unlikely(tx_bug)) {
  4940. tg3_tx_recover(tp);
  4941. return;
  4942. }
  4943. }
  4944. netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
  4945. tnapi->tx_cons = sw_idx;
  4946. /* Need to make the tx_cons update visible to tg3_start_xmit()
  4947. * before checking for netif_queue_stopped(). Without the
  4948. * memory barrier, there is a small possibility that tg3_start_xmit()
  4949. * will miss it and cause the queue to be stopped forever.
  4950. */
  4951. smp_mb();
  4952. if (unlikely(netif_tx_queue_stopped(txq) &&
  4953. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
  4954. __netif_tx_lock(txq, smp_processor_id());
  4955. if (netif_tx_queue_stopped(txq) &&
  4956. (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
  4957. netif_tx_wake_queue(txq);
  4958. __netif_tx_unlock(txq);
  4959. }
  4960. }
  4961. static void tg3_frag_free(bool is_frag, void *data)
  4962. {
  4963. if (is_frag)
  4964. put_page(virt_to_head_page(data));
  4965. else
  4966. kfree(data);
  4967. }
  4968. static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
  4969. {
  4970. unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
  4971. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  4972. if (!ri->data)
  4973. return;
  4974. pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
  4975. map_sz, PCI_DMA_FROMDEVICE);
  4976. tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
  4977. ri->data = NULL;
  4978. }
  4979. /* Returns size of skb allocated or < 0 on error.
  4980. *
  4981. * We only need to fill in the address because the other members
  4982. * of the RX descriptor are invariant, see tg3_init_rings.
  4983. *
  4984. * Note the purposeful assymetry of cpu vs. chip accesses. For
  4985. * posting buffers we only dirty the first cache line of the RX
  4986. * descriptor (containing the address). Whereas for the RX status
  4987. * buffers the cpu only reads the last cacheline of the RX descriptor
  4988. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  4989. */
  4990. static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
  4991. u32 opaque_key, u32 dest_idx_unmasked,
  4992. unsigned int *frag_size)
  4993. {
  4994. struct tg3_rx_buffer_desc *desc;
  4995. struct ring_info *map;
  4996. u8 *data;
  4997. dma_addr_t mapping;
  4998. int skb_size, data_size, dest_idx;
  4999. switch (opaque_key) {
  5000. case RXD_OPAQUE_RING_STD:
  5001. dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
  5002. desc = &tpr->rx_std[dest_idx];
  5003. map = &tpr->rx_std_buffers[dest_idx];
  5004. data_size = tp->rx_pkt_map_sz;
  5005. break;
  5006. case RXD_OPAQUE_RING_JUMBO:
  5007. dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
  5008. desc = &tpr->rx_jmb[dest_idx].std;
  5009. map = &tpr->rx_jmb_buffers[dest_idx];
  5010. data_size = TG3_RX_JMB_MAP_SZ;
  5011. break;
  5012. default:
  5013. return -EINVAL;
  5014. }
  5015. /* Do not overwrite any of the map or rp information
  5016. * until we are sure we can commit to a new buffer.
  5017. *
  5018. * Callers depend upon this behavior and assume that
  5019. * we leave everything unchanged if we fail.
  5020. */
  5021. skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
  5022. SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
  5023. if (skb_size <= PAGE_SIZE) {
  5024. data = netdev_alloc_frag(skb_size);
  5025. *frag_size = skb_size;
  5026. } else {
  5027. data = kmalloc(skb_size, GFP_ATOMIC);
  5028. *frag_size = 0;
  5029. }
  5030. if (!data)
  5031. return -ENOMEM;
  5032. mapping = pci_map_single(tp->pdev,
  5033. data + TG3_RX_OFFSET(tp),
  5034. data_size,
  5035. PCI_DMA_FROMDEVICE);
  5036. if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
  5037. tg3_frag_free(skb_size <= PAGE_SIZE, data);
  5038. return -EIO;
  5039. }
  5040. map->data = data;
  5041. dma_unmap_addr_set(map, mapping, mapping);
  5042. desc->addr_hi = ((u64)mapping >> 32);
  5043. desc->addr_lo = ((u64)mapping & 0xffffffff);
  5044. return data_size;
  5045. }
  5046. /* We only need to move over in the address because the other
  5047. * members of the RX descriptor are invariant. See notes above
  5048. * tg3_alloc_rx_data for full details.
  5049. */
  5050. static void tg3_recycle_rx(struct tg3_napi *tnapi,
  5051. struct tg3_rx_prodring_set *dpr,
  5052. u32 opaque_key, int src_idx,
  5053. u32 dest_idx_unmasked)
  5054. {
  5055. struct tg3 *tp = tnapi->tp;
  5056. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  5057. struct ring_info *src_map, *dest_map;
  5058. struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
  5059. int dest_idx;
  5060. switch (opaque_key) {
  5061. case RXD_OPAQUE_RING_STD:
  5062. dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
  5063. dest_desc = &dpr->rx_std[dest_idx];
  5064. dest_map = &dpr->rx_std_buffers[dest_idx];
  5065. src_desc = &spr->rx_std[src_idx];
  5066. src_map = &spr->rx_std_buffers[src_idx];
  5067. break;
  5068. case RXD_OPAQUE_RING_JUMBO:
  5069. dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
  5070. dest_desc = &dpr->rx_jmb[dest_idx].std;
  5071. dest_map = &dpr->rx_jmb_buffers[dest_idx];
  5072. src_desc = &spr->rx_jmb[src_idx].std;
  5073. src_map = &spr->rx_jmb_buffers[src_idx];
  5074. break;
  5075. default:
  5076. return;
  5077. }
  5078. dest_map->data = src_map->data;
  5079. dma_unmap_addr_set(dest_map, mapping,
  5080. dma_unmap_addr(src_map, mapping));
  5081. dest_desc->addr_hi = src_desc->addr_hi;
  5082. dest_desc->addr_lo = src_desc->addr_lo;
  5083. /* Ensure that the update to the skb happens after the physical
  5084. * addresses have been transferred to the new BD location.
  5085. */
  5086. smp_wmb();
  5087. src_map->data = NULL;
  5088. }
  5089. /* The RX ring scheme is composed of multiple rings which post fresh
  5090. * buffers to the chip, and one special ring the chip uses to report
  5091. * status back to the host.
  5092. *
  5093. * The special ring reports the status of received packets to the
  5094. * host. The chip does not write into the original descriptor the
  5095. * RX buffer was obtained from. The chip simply takes the original
  5096. * descriptor as provided by the host, updates the status and length
  5097. * field, then writes this into the next status ring entry.
  5098. *
  5099. * Each ring the host uses to post buffers to the chip is described
  5100. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  5101. * it is first placed into the on-chip ram. When the packet's length
  5102. * is known, it walks down the TG3_BDINFO entries to select the ring.
  5103. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  5104. * which is within the range of the new packet's length is chosen.
  5105. *
  5106. * The "separate ring for rx status" scheme may sound queer, but it makes
  5107. * sense from a cache coherency perspective. If only the host writes
  5108. * to the buffer post rings, and only the chip writes to the rx status
  5109. * rings, then cache lines never move beyond shared-modified state.
  5110. * If both the host and chip were to write into the same ring, cache line
  5111. * eviction could occur since both entities want it in an exclusive state.
  5112. */
  5113. static int tg3_rx(struct tg3_napi *tnapi, int budget)
  5114. {
  5115. struct tg3 *tp = tnapi->tp;
  5116. u32 work_mask, rx_std_posted = 0;
  5117. u32 std_prod_idx, jmb_prod_idx;
  5118. u32 sw_idx = tnapi->rx_rcb_ptr;
  5119. u16 hw_idx;
  5120. int received;
  5121. struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
  5122. hw_idx = *(tnapi->rx_rcb_prod_idx);
  5123. /*
  5124. * We need to order the read of hw_idx and the read of
  5125. * the opaque cookie.
  5126. */
  5127. rmb();
  5128. work_mask = 0;
  5129. received = 0;
  5130. std_prod_idx = tpr->rx_std_prod_idx;
  5131. jmb_prod_idx = tpr->rx_jmb_prod_idx;
  5132. while (sw_idx != hw_idx && budget > 0) {
  5133. struct ring_info *ri;
  5134. struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
  5135. unsigned int len;
  5136. struct sk_buff *skb;
  5137. dma_addr_t dma_addr;
  5138. u32 opaque_key, desc_idx, *post_ptr;
  5139. u8 *data;
  5140. u64 tstamp = 0;
  5141. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  5142. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  5143. if (opaque_key == RXD_OPAQUE_RING_STD) {
  5144. ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
  5145. dma_addr = dma_unmap_addr(ri, mapping);
  5146. data = ri->data;
  5147. post_ptr = &std_prod_idx;
  5148. rx_std_posted++;
  5149. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  5150. ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
  5151. dma_addr = dma_unmap_addr(ri, mapping);
  5152. data = ri->data;
  5153. post_ptr = &jmb_prod_idx;
  5154. } else
  5155. goto next_pkt_nopost;
  5156. work_mask |= opaque_key;
  5157. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  5158. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  5159. drop_it:
  5160. tg3_recycle_rx(tnapi, tpr, opaque_key,
  5161. desc_idx, *post_ptr);
  5162. drop_it_no_recycle:
  5163. /* Other statistics kept track of by card. */
  5164. tp->rx_dropped++;
  5165. goto next_pkt;
  5166. }
  5167. prefetch(data + TG3_RX_OFFSET(tp));
  5168. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
  5169. ETH_FCS_LEN;
  5170. if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
  5171. RXD_FLAG_PTPSTAT_PTPV1 ||
  5172. (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
  5173. RXD_FLAG_PTPSTAT_PTPV2) {
  5174. tstamp = tr32(TG3_RX_TSTAMP_LSB);
  5175. tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
  5176. }
  5177. if (len > TG3_RX_COPY_THRESH(tp)) {
  5178. int skb_size;
  5179. unsigned int frag_size;
  5180. skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
  5181. *post_ptr, &frag_size);
  5182. if (skb_size < 0)
  5183. goto drop_it;
  5184. pci_unmap_single(tp->pdev, dma_addr, skb_size,
  5185. PCI_DMA_FROMDEVICE);
  5186. skb = build_skb(data, frag_size);
  5187. if (!skb) {
  5188. tg3_frag_free(frag_size != 0, data);
  5189. goto drop_it_no_recycle;
  5190. }
  5191. skb_reserve(skb, TG3_RX_OFFSET(tp));
  5192. /* Ensure that the update to the data happens
  5193. * after the usage of the old DMA mapping.
  5194. */
  5195. smp_wmb();
  5196. ri->data = NULL;
  5197. } else {
  5198. tg3_recycle_rx(tnapi, tpr, opaque_key,
  5199. desc_idx, *post_ptr);
  5200. skb = netdev_alloc_skb(tp->dev,
  5201. len + TG3_RAW_IP_ALIGN);
  5202. if (skb == NULL)
  5203. goto drop_it_no_recycle;
  5204. skb_reserve(skb, TG3_RAW_IP_ALIGN);
  5205. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  5206. memcpy(skb->data,
  5207. data + TG3_RX_OFFSET(tp),
  5208. len);
  5209. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  5210. }
  5211. skb_put(skb, len);
  5212. if (tstamp)
  5213. tg3_hwclock_to_timestamp(tp, tstamp,
  5214. skb_hwtstamps(skb));
  5215. if ((tp->dev->features & NETIF_F_RXCSUM) &&
  5216. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  5217. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  5218. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  5219. skb->ip_summed = CHECKSUM_UNNECESSARY;
  5220. else
  5221. skb_checksum_none_assert(skb);
  5222. skb->protocol = eth_type_trans(skb, tp->dev);
  5223. if (len > (tp->dev->mtu + ETH_HLEN) &&
  5224. skb->protocol != htons(ETH_P_8021Q)) {
  5225. dev_kfree_skb(skb);
  5226. goto drop_it_no_recycle;
  5227. }
  5228. if (desc->type_flags & RXD_FLAG_VLAN &&
  5229. !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
  5230. __vlan_hwaccel_put_tag(skb,
  5231. desc->err_vlan & RXD_VLAN_MASK);
  5232. napi_gro_receive(&tnapi->napi, skb);
  5233. received++;
  5234. budget--;
  5235. next_pkt:
  5236. (*post_ptr)++;
  5237. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  5238. tpr->rx_std_prod_idx = std_prod_idx &
  5239. tp->rx_std_ring_mask;
  5240. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5241. tpr->rx_std_prod_idx);
  5242. work_mask &= ~RXD_OPAQUE_RING_STD;
  5243. rx_std_posted = 0;
  5244. }
  5245. next_pkt_nopost:
  5246. sw_idx++;
  5247. sw_idx &= tp->rx_ret_ring_mask;
  5248. /* Refresh hw_idx to see if there is new work */
  5249. if (sw_idx == hw_idx) {
  5250. hw_idx = *(tnapi->rx_rcb_prod_idx);
  5251. rmb();
  5252. }
  5253. }
  5254. /* ACK the status ring. */
  5255. tnapi->rx_rcb_ptr = sw_idx;
  5256. tw32_rx_mbox(tnapi->consmbox, sw_idx);
  5257. /* Refill RX ring(s). */
  5258. if (!tg3_flag(tp, ENABLE_RSS)) {
  5259. /* Sync BD data before updating mailbox */
  5260. wmb();
  5261. if (work_mask & RXD_OPAQUE_RING_STD) {
  5262. tpr->rx_std_prod_idx = std_prod_idx &
  5263. tp->rx_std_ring_mask;
  5264. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5265. tpr->rx_std_prod_idx);
  5266. }
  5267. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  5268. tpr->rx_jmb_prod_idx = jmb_prod_idx &
  5269. tp->rx_jmb_ring_mask;
  5270. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  5271. tpr->rx_jmb_prod_idx);
  5272. }
  5273. mmiowb();
  5274. } else if (work_mask) {
  5275. /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
  5276. * updated before the producer indices can be updated.
  5277. */
  5278. smp_wmb();
  5279. tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
  5280. tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
  5281. if (tnapi != &tp->napi[1]) {
  5282. tp->rx_refill = true;
  5283. napi_schedule(&tp->napi[1].napi);
  5284. }
  5285. }
  5286. return received;
  5287. }
  5288. static void tg3_poll_link(struct tg3 *tp)
  5289. {
  5290. /* handle link change and other phy events */
  5291. if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
  5292. struct tg3_hw_status *sblk = tp->napi[0].hw_status;
  5293. if (sblk->status & SD_STATUS_LINK_CHG) {
  5294. sblk->status = SD_STATUS_UPDATED |
  5295. (sblk->status & ~SD_STATUS_LINK_CHG);
  5296. spin_lock(&tp->lock);
  5297. if (tg3_flag(tp, USE_PHYLIB)) {
  5298. tw32_f(MAC_STATUS,
  5299. (MAC_STATUS_SYNC_CHANGED |
  5300. MAC_STATUS_CFG_CHANGED |
  5301. MAC_STATUS_MI_COMPLETION |
  5302. MAC_STATUS_LNKSTATE_CHANGED));
  5303. udelay(40);
  5304. } else
  5305. tg3_setup_phy(tp, 0);
  5306. spin_unlock(&tp->lock);
  5307. }
  5308. }
  5309. }
  5310. static int tg3_rx_prodring_xfer(struct tg3 *tp,
  5311. struct tg3_rx_prodring_set *dpr,
  5312. struct tg3_rx_prodring_set *spr)
  5313. {
  5314. u32 si, di, cpycnt, src_prod_idx;
  5315. int i, err = 0;
  5316. while (1) {
  5317. src_prod_idx = spr->rx_std_prod_idx;
  5318. /* Make sure updates to the rx_std_buffers[] entries and the
  5319. * standard producer index are seen in the correct order.
  5320. */
  5321. smp_rmb();
  5322. if (spr->rx_std_cons_idx == src_prod_idx)
  5323. break;
  5324. if (spr->rx_std_cons_idx < src_prod_idx)
  5325. cpycnt = src_prod_idx - spr->rx_std_cons_idx;
  5326. else
  5327. cpycnt = tp->rx_std_ring_mask + 1 -
  5328. spr->rx_std_cons_idx;
  5329. cpycnt = min(cpycnt,
  5330. tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
  5331. si = spr->rx_std_cons_idx;
  5332. di = dpr->rx_std_prod_idx;
  5333. for (i = di; i < di + cpycnt; i++) {
  5334. if (dpr->rx_std_buffers[i].data) {
  5335. cpycnt = i - di;
  5336. err = -ENOSPC;
  5337. break;
  5338. }
  5339. }
  5340. if (!cpycnt)
  5341. break;
  5342. /* Ensure that updates to the rx_std_buffers ring and the
  5343. * shadowed hardware producer ring from tg3_recycle_skb() are
  5344. * ordered correctly WRT the skb check above.
  5345. */
  5346. smp_rmb();
  5347. memcpy(&dpr->rx_std_buffers[di],
  5348. &spr->rx_std_buffers[si],
  5349. cpycnt * sizeof(struct ring_info));
  5350. for (i = 0; i < cpycnt; i++, di++, si++) {
  5351. struct tg3_rx_buffer_desc *sbd, *dbd;
  5352. sbd = &spr->rx_std[si];
  5353. dbd = &dpr->rx_std[di];
  5354. dbd->addr_hi = sbd->addr_hi;
  5355. dbd->addr_lo = sbd->addr_lo;
  5356. }
  5357. spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
  5358. tp->rx_std_ring_mask;
  5359. dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
  5360. tp->rx_std_ring_mask;
  5361. }
  5362. while (1) {
  5363. src_prod_idx = spr->rx_jmb_prod_idx;
  5364. /* Make sure updates to the rx_jmb_buffers[] entries and
  5365. * the jumbo producer index are seen in the correct order.
  5366. */
  5367. smp_rmb();
  5368. if (spr->rx_jmb_cons_idx == src_prod_idx)
  5369. break;
  5370. if (spr->rx_jmb_cons_idx < src_prod_idx)
  5371. cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
  5372. else
  5373. cpycnt = tp->rx_jmb_ring_mask + 1 -
  5374. spr->rx_jmb_cons_idx;
  5375. cpycnt = min(cpycnt,
  5376. tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
  5377. si = spr->rx_jmb_cons_idx;
  5378. di = dpr->rx_jmb_prod_idx;
  5379. for (i = di; i < di + cpycnt; i++) {
  5380. if (dpr->rx_jmb_buffers[i].data) {
  5381. cpycnt = i - di;
  5382. err = -ENOSPC;
  5383. break;
  5384. }
  5385. }
  5386. if (!cpycnt)
  5387. break;
  5388. /* Ensure that updates to the rx_jmb_buffers ring and the
  5389. * shadowed hardware producer ring from tg3_recycle_skb() are
  5390. * ordered correctly WRT the skb check above.
  5391. */
  5392. smp_rmb();
  5393. memcpy(&dpr->rx_jmb_buffers[di],
  5394. &spr->rx_jmb_buffers[si],
  5395. cpycnt * sizeof(struct ring_info));
  5396. for (i = 0; i < cpycnt; i++, di++, si++) {
  5397. struct tg3_rx_buffer_desc *sbd, *dbd;
  5398. sbd = &spr->rx_jmb[si].std;
  5399. dbd = &dpr->rx_jmb[di].std;
  5400. dbd->addr_hi = sbd->addr_hi;
  5401. dbd->addr_lo = sbd->addr_lo;
  5402. }
  5403. spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
  5404. tp->rx_jmb_ring_mask;
  5405. dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
  5406. tp->rx_jmb_ring_mask;
  5407. }
  5408. return err;
  5409. }
  5410. static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
  5411. {
  5412. struct tg3 *tp = tnapi->tp;
  5413. /* run TX completion thread */
  5414. if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
  5415. tg3_tx(tnapi);
  5416. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5417. return work_done;
  5418. }
  5419. if (!tnapi->rx_rcb_prod_idx)
  5420. return work_done;
  5421. /* run RX thread, within the bounds set by NAPI.
  5422. * All RX "locking" is done by ensuring outside
  5423. * code synchronizes with tg3->napi.poll()
  5424. */
  5425. if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
  5426. work_done += tg3_rx(tnapi, budget - work_done);
  5427. if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
  5428. struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
  5429. int i, err = 0;
  5430. u32 std_prod_idx = dpr->rx_std_prod_idx;
  5431. u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
  5432. tp->rx_refill = false;
  5433. for (i = 1; i <= tp->rxq_cnt; i++)
  5434. err |= tg3_rx_prodring_xfer(tp, dpr,
  5435. &tp->napi[i].prodring);
  5436. wmb();
  5437. if (std_prod_idx != dpr->rx_std_prod_idx)
  5438. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
  5439. dpr->rx_std_prod_idx);
  5440. if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
  5441. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
  5442. dpr->rx_jmb_prod_idx);
  5443. mmiowb();
  5444. if (err)
  5445. tw32_f(HOSTCC_MODE, tp->coal_now);
  5446. }
  5447. return work_done;
  5448. }
  5449. static inline void tg3_reset_task_schedule(struct tg3 *tp)
  5450. {
  5451. if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
  5452. schedule_work(&tp->reset_task);
  5453. }
  5454. static inline void tg3_reset_task_cancel(struct tg3 *tp)
  5455. {
  5456. cancel_work_sync(&tp->reset_task);
  5457. tg3_flag_clear(tp, RESET_TASK_PENDING);
  5458. tg3_flag_clear(tp, TX_RECOVERY_PENDING);
  5459. }
  5460. static int tg3_poll_msix(struct napi_struct *napi, int budget)
  5461. {
  5462. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  5463. struct tg3 *tp = tnapi->tp;
  5464. int work_done = 0;
  5465. struct tg3_hw_status *sblk = tnapi->hw_status;
  5466. while (1) {
  5467. work_done = tg3_poll_work(tnapi, work_done, budget);
  5468. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5469. goto tx_recovery;
  5470. if (unlikely(work_done >= budget))
  5471. break;
  5472. /* tp->last_tag is used in tg3_int_reenable() below
  5473. * to tell the hw how much work has been processed,
  5474. * so we must read it before checking for more work.
  5475. */
  5476. tnapi->last_tag = sblk->status_tag;
  5477. tnapi->last_irq_tag = tnapi->last_tag;
  5478. rmb();
  5479. /* check for RX/TX work to do */
  5480. if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
  5481. *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
  5482. /* This test here is not race free, but will reduce
  5483. * the number of interrupts by looping again.
  5484. */
  5485. if (tnapi == &tp->napi[1] && tp->rx_refill)
  5486. continue;
  5487. napi_complete(napi);
  5488. /* Reenable interrupts. */
  5489. tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
  5490. /* This test here is synchronized by napi_schedule()
  5491. * and napi_complete() to close the race condition.
  5492. */
  5493. if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
  5494. tw32(HOSTCC_MODE, tp->coalesce_mode |
  5495. HOSTCC_MODE_ENABLE |
  5496. tnapi->coal_now);
  5497. }
  5498. mmiowb();
  5499. break;
  5500. }
  5501. }
  5502. return work_done;
  5503. tx_recovery:
  5504. /* work_done is guaranteed to be less than budget. */
  5505. napi_complete(napi);
  5506. tg3_reset_task_schedule(tp);
  5507. return work_done;
  5508. }
  5509. static void tg3_process_error(struct tg3 *tp)
  5510. {
  5511. u32 val;
  5512. bool real_error = false;
  5513. if (tg3_flag(tp, ERROR_PROCESSED))
  5514. return;
  5515. /* Check Flow Attention register */
  5516. val = tr32(HOSTCC_FLOW_ATTN);
  5517. if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
  5518. netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
  5519. real_error = true;
  5520. }
  5521. if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
  5522. netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
  5523. real_error = true;
  5524. }
  5525. if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
  5526. netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
  5527. real_error = true;
  5528. }
  5529. if (!real_error)
  5530. return;
  5531. tg3_dump_state(tp);
  5532. tg3_flag_set(tp, ERROR_PROCESSED);
  5533. tg3_reset_task_schedule(tp);
  5534. }
  5535. static int tg3_poll(struct napi_struct *napi, int budget)
  5536. {
  5537. struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
  5538. struct tg3 *tp = tnapi->tp;
  5539. int work_done = 0;
  5540. struct tg3_hw_status *sblk = tnapi->hw_status;
  5541. while (1) {
  5542. if (sblk->status & SD_STATUS_ERROR)
  5543. tg3_process_error(tp);
  5544. tg3_poll_link(tp);
  5545. work_done = tg3_poll_work(tnapi, work_done, budget);
  5546. if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
  5547. goto tx_recovery;
  5548. if (unlikely(work_done >= budget))
  5549. break;
  5550. if (tg3_flag(tp, TAGGED_STATUS)) {
  5551. /* tp->last_tag is used in tg3_int_reenable() below
  5552. * to tell the hw how much work has been processed,
  5553. * so we must read it before checking for more work.
  5554. */
  5555. tnapi->last_tag = sblk->status_tag;
  5556. tnapi->last_irq_tag = tnapi->last_tag;
  5557. rmb();
  5558. } else
  5559. sblk->status &= ~SD_STATUS_UPDATED;
  5560. if (likely(!tg3_has_work(tnapi))) {
  5561. napi_complete(napi);
  5562. tg3_int_reenable(tnapi);
  5563. break;
  5564. }
  5565. }
  5566. return work_done;
  5567. tx_recovery:
  5568. /* work_done is guaranteed to be less than budget. */
  5569. napi_complete(napi);
  5570. tg3_reset_task_schedule(tp);
  5571. return work_done;
  5572. }
  5573. static void tg3_napi_disable(struct tg3 *tp)
  5574. {
  5575. int i;
  5576. for (i = tp->irq_cnt - 1; i >= 0; i--)
  5577. napi_disable(&tp->napi[i].napi);
  5578. }
  5579. static void tg3_napi_enable(struct tg3 *tp)
  5580. {
  5581. int i;
  5582. for (i = 0; i < tp->irq_cnt; i++)
  5583. napi_enable(&tp->napi[i].napi);
  5584. }
  5585. static void tg3_napi_init(struct tg3 *tp)
  5586. {
  5587. int i;
  5588. netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
  5589. for (i = 1; i < tp->irq_cnt; i++)
  5590. netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
  5591. }
  5592. static void tg3_napi_fini(struct tg3 *tp)
  5593. {
  5594. int i;
  5595. for (i = 0; i < tp->irq_cnt; i++)
  5596. netif_napi_del(&tp->napi[i].napi);
  5597. }
  5598. static inline void tg3_netif_stop(struct tg3 *tp)
  5599. {
  5600. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  5601. tg3_napi_disable(tp);
  5602. netif_carrier_off(tp->dev);
  5603. netif_tx_disable(tp->dev);
  5604. }
  5605. /* tp->lock must be held */
  5606. static inline void tg3_netif_start(struct tg3 *tp)
  5607. {
  5608. tg3_ptp_resume(tp);
  5609. /* NOTE: unconditional netif_tx_wake_all_queues is only
  5610. * appropriate so long as all callers are assured to
  5611. * have free tx slots (such as after tg3_init_hw)
  5612. */
  5613. netif_tx_wake_all_queues(tp->dev);
  5614. if (tp->link_up)
  5615. netif_carrier_on(tp->dev);
  5616. tg3_napi_enable(tp);
  5617. tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
  5618. tg3_enable_ints(tp);
  5619. }
  5620. static void tg3_irq_quiesce(struct tg3 *tp)
  5621. {
  5622. int i;
  5623. BUG_ON(tp->irq_sync);
  5624. tp->irq_sync = 1;
  5625. smp_mb();
  5626. for (i = 0; i < tp->irq_cnt; i++)
  5627. synchronize_irq(tp->napi[i].irq_vec);
  5628. }
  5629. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  5630. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  5631. * with as well. Most of the time, this is not necessary except when
  5632. * shutting down the device.
  5633. */
  5634. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  5635. {
  5636. spin_lock_bh(&tp->lock);
  5637. if (irq_sync)
  5638. tg3_irq_quiesce(tp);
  5639. }
  5640. static inline void tg3_full_unlock(struct tg3 *tp)
  5641. {
  5642. spin_unlock_bh(&tp->lock);
  5643. }
  5644. /* One-shot MSI handler - Chip automatically disables interrupt
  5645. * after sending MSI so driver doesn't have to do it.
  5646. */
  5647. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  5648. {
  5649. struct tg3_napi *tnapi = dev_id;
  5650. struct tg3 *tp = tnapi->tp;
  5651. prefetch(tnapi->hw_status);
  5652. if (tnapi->rx_rcb)
  5653. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  5654. if (likely(!tg3_irq_sync(tp)))
  5655. napi_schedule(&tnapi->napi);
  5656. return IRQ_HANDLED;
  5657. }
  5658. /* MSI ISR - No need to check for interrupt sharing and no need to
  5659. * flush status block and interrupt mailbox. PCI ordering rules
  5660. * guarantee that MSI will arrive after the status block.
  5661. */
  5662. static irqreturn_t tg3_msi(int irq, void *dev_id)
  5663. {
  5664. struct tg3_napi *tnapi = dev_id;
  5665. struct tg3 *tp = tnapi->tp;
  5666. prefetch(tnapi->hw_status);
  5667. if (tnapi->rx_rcb)
  5668. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  5669. /*
  5670. * Writing any value to intr-mbox-0 clears PCI INTA# and
  5671. * chip-internal interrupt pending events.
  5672. * Writing non-zero to intr-mbox-0 additional tells the
  5673. * NIC to stop sending us irqs, engaging "in-intr-handler"
  5674. * event coalescing.
  5675. */
  5676. tw32_mailbox(tnapi->int_mbox, 0x00000001);
  5677. if (likely(!tg3_irq_sync(tp)))
  5678. napi_schedule(&tnapi->napi);
  5679. return IRQ_RETVAL(1);
  5680. }
  5681. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  5682. {
  5683. struct tg3_napi *tnapi = dev_id;
  5684. struct tg3 *tp = tnapi->tp;
  5685. struct tg3_hw_status *sblk = tnapi->hw_status;
  5686. unsigned int handled = 1;
  5687. /* In INTx mode, it is possible for the interrupt to arrive at
  5688. * the CPU before the status block posted prior to the interrupt.
  5689. * Reading the PCI State register will confirm whether the
  5690. * interrupt is ours and will flush the status block.
  5691. */
  5692. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  5693. if (tg3_flag(tp, CHIP_RESETTING) ||
  5694. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  5695. handled = 0;
  5696. goto out;
  5697. }
  5698. }
  5699. /*
  5700. * Writing any value to intr-mbox-0 clears PCI INTA# and
  5701. * chip-internal interrupt pending events.
  5702. * Writing non-zero to intr-mbox-0 additional tells the
  5703. * NIC to stop sending us irqs, engaging "in-intr-handler"
  5704. * event coalescing.
  5705. *
  5706. * Flush the mailbox to de-assert the IRQ immediately to prevent
  5707. * spurious interrupts. The flush impacts performance but
  5708. * excessive spurious interrupts can be worse in some cases.
  5709. */
  5710. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  5711. if (tg3_irq_sync(tp))
  5712. goto out;
  5713. sblk->status &= ~SD_STATUS_UPDATED;
  5714. if (likely(tg3_has_work(tnapi))) {
  5715. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  5716. napi_schedule(&tnapi->napi);
  5717. } else {
  5718. /* No work, shared interrupt perhaps? re-enable
  5719. * interrupts, and flush that PCI write
  5720. */
  5721. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  5722. 0x00000000);
  5723. }
  5724. out:
  5725. return IRQ_RETVAL(handled);
  5726. }
  5727. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  5728. {
  5729. struct tg3_napi *tnapi = dev_id;
  5730. struct tg3 *tp = tnapi->tp;
  5731. struct tg3_hw_status *sblk = tnapi->hw_status;
  5732. unsigned int handled = 1;
  5733. /* In INTx mode, it is possible for the interrupt to arrive at
  5734. * the CPU before the status block posted prior to the interrupt.
  5735. * Reading the PCI State register will confirm whether the
  5736. * interrupt is ours and will flush the status block.
  5737. */
  5738. if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
  5739. if (tg3_flag(tp, CHIP_RESETTING) ||
  5740. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  5741. handled = 0;
  5742. goto out;
  5743. }
  5744. }
  5745. /*
  5746. * writing any value to intr-mbox-0 clears PCI INTA# and
  5747. * chip-internal interrupt pending events.
  5748. * writing non-zero to intr-mbox-0 additional tells the
  5749. * NIC to stop sending us irqs, engaging "in-intr-handler"
  5750. * event coalescing.
  5751. *
  5752. * Flush the mailbox to de-assert the IRQ immediately to prevent
  5753. * spurious interrupts. The flush impacts performance but
  5754. * excessive spurious interrupts can be worse in some cases.
  5755. */
  5756. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  5757. /*
  5758. * In a shared interrupt configuration, sometimes other devices'
  5759. * interrupts will scream. We record the current status tag here
  5760. * so that the above check can report that the screaming interrupts
  5761. * are unhandled. Eventually they will be silenced.
  5762. */
  5763. tnapi->last_irq_tag = sblk->status_tag;
  5764. if (tg3_irq_sync(tp))
  5765. goto out;
  5766. prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
  5767. napi_schedule(&tnapi->napi);
  5768. out:
  5769. return IRQ_RETVAL(handled);
  5770. }
  5771. /* ISR for interrupt test */
  5772. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  5773. {
  5774. struct tg3_napi *tnapi = dev_id;
  5775. struct tg3 *tp = tnapi->tp;
  5776. struct tg3_hw_status *sblk = tnapi->hw_status;
  5777. if ((sblk->status & SD_STATUS_UPDATED) ||
  5778. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  5779. tg3_disable_ints(tp);
  5780. return IRQ_RETVAL(1);
  5781. }
  5782. return IRQ_RETVAL(0);
  5783. }
  5784. #ifdef CONFIG_NET_POLL_CONTROLLER
  5785. static void tg3_poll_controller(struct net_device *dev)
  5786. {
  5787. int i;
  5788. struct tg3 *tp = netdev_priv(dev);
  5789. if (tg3_irq_sync(tp))
  5790. return;
  5791. for (i = 0; i < tp->irq_cnt; i++)
  5792. tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
  5793. }
  5794. #endif
  5795. static void tg3_tx_timeout(struct net_device *dev)
  5796. {
  5797. struct tg3 *tp = netdev_priv(dev);
  5798. if (netif_msg_tx_err(tp)) {
  5799. netdev_err(dev, "transmit timed out, resetting\n");
  5800. tg3_dump_state(tp);
  5801. }
  5802. tg3_reset_task_schedule(tp);
  5803. }
  5804. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  5805. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  5806. {
  5807. u32 base = (u32) mapping & 0xffffffff;
  5808. return (base > 0xffffdcc0) && (base + len + 8 < base);
  5809. }
  5810. /* Test for DMA addresses > 40-bit */
  5811. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  5812. int len)
  5813. {
  5814. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  5815. if (tg3_flag(tp, 40BIT_DMA_BUG))
  5816. return ((u64) mapping + len) > DMA_BIT_MASK(40);
  5817. return 0;
  5818. #else
  5819. return 0;
  5820. #endif
  5821. }
  5822. static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
  5823. dma_addr_t mapping, u32 len, u32 flags,
  5824. u32 mss, u32 vlan)
  5825. {
  5826. txbd->addr_hi = ((u64) mapping >> 32);
  5827. txbd->addr_lo = ((u64) mapping & 0xffffffff);
  5828. txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
  5829. txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
  5830. }
  5831. static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
  5832. dma_addr_t map, u32 len, u32 flags,
  5833. u32 mss, u32 vlan)
  5834. {
  5835. struct tg3 *tp = tnapi->tp;
  5836. bool hwbug = false;
  5837. if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
  5838. hwbug = true;
  5839. if (tg3_4g_overflow_test(map, len))
  5840. hwbug = true;
  5841. if (tg3_40bit_overflow_test(tp, map, len))
  5842. hwbug = true;
  5843. if (tp->dma_limit) {
  5844. u32 prvidx = *entry;
  5845. u32 tmp_flag = flags & ~TXD_FLAG_END;
  5846. while (len > tp->dma_limit && *budget) {
  5847. u32 frag_len = tp->dma_limit;
  5848. len -= tp->dma_limit;
  5849. /* Avoid the 8byte DMA problem */
  5850. if (len <= 8) {
  5851. len += tp->dma_limit / 2;
  5852. frag_len = tp->dma_limit / 2;
  5853. }
  5854. tnapi->tx_buffers[*entry].fragmented = true;
  5855. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  5856. frag_len, tmp_flag, mss, vlan);
  5857. *budget -= 1;
  5858. prvidx = *entry;
  5859. *entry = NEXT_TX(*entry);
  5860. map += frag_len;
  5861. }
  5862. if (len) {
  5863. if (*budget) {
  5864. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  5865. len, flags, mss, vlan);
  5866. *budget -= 1;
  5867. *entry = NEXT_TX(*entry);
  5868. } else {
  5869. hwbug = true;
  5870. tnapi->tx_buffers[prvidx].fragmented = false;
  5871. }
  5872. }
  5873. } else {
  5874. tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
  5875. len, flags, mss, vlan);
  5876. *entry = NEXT_TX(*entry);
  5877. }
  5878. return hwbug;
  5879. }
  5880. static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
  5881. {
  5882. int i;
  5883. struct sk_buff *skb;
  5884. struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
  5885. skb = txb->skb;
  5886. txb->skb = NULL;
  5887. pci_unmap_single(tnapi->tp->pdev,
  5888. dma_unmap_addr(txb, mapping),
  5889. skb_headlen(skb),
  5890. PCI_DMA_TODEVICE);
  5891. while (txb->fragmented) {
  5892. txb->fragmented = false;
  5893. entry = NEXT_TX(entry);
  5894. txb = &tnapi->tx_buffers[entry];
  5895. }
  5896. for (i = 0; i <= last; i++) {
  5897. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  5898. entry = NEXT_TX(entry);
  5899. txb = &tnapi->tx_buffers[entry];
  5900. pci_unmap_page(tnapi->tp->pdev,
  5901. dma_unmap_addr(txb, mapping),
  5902. skb_frag_size(frag), PCI_DMA_TODEVICE);
  5903. while (txb->fragmented) {
  5904. txb->fragmented = false;
  5905. entry = NEXT_TX(entry);
  5906. txb = &tnapi->tx_buffers[entry];
  5907. }
  5908. }
  5909. }
  5910. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  5911. static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
  5912. struct sk_buff **pskb,
  5913. u32 *entry, u32 *budget,
  5914. u32 base_flags, u32 mss, u32 vlan)
  5915. {
  5916. struct tg3 *tp = tnapi->tp;
  5917. struct sk_buff *new_skb, *skb = *pskb;
  5918. dma_addr_t new_addr = 0;
  5919. int ret = 0;
  5920. if (tg3_asic_rev(tp) != ASIC_REV_5701)
  5921. new_skb = skb_copy(skb, GFP_ATOMIC);
  5922. else {
  5923. int more_headroom = 4 - ((unsigned long)skb->data & 3);
  5924. new_skb = skb_copy_expand(skb,
  5925. skb_headroom(skb) + more_headroom,
  5926. skb_tailroom(skb), GFP_ATOMIC);
  5927. }
  5928. if (!new_skb) {
  5929. ret = -1;
  5930. } else {
  5931. /* New SKB is guaranteed to be linear. */
  5932. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  5933. PCI_DMA_TODEVICE);
  5934. /* Make sure the mapping succeeded */
  5935. if (pci_dma_mapping_error(tp->pdev, new_addr)) {
  5936. dev_kfree_skb(new_skb);
  5937. ret = -1;
  5938. } else {
  5939. u32 save_entry = *entry;
  5940. base_flags |= TXD_FLAG_END;
  5941. tnapi->tx_buffers[*entry].skb = new_skb;
  5942. dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
  5943. mapping, new_addr);
  5944. if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
  5945. new_skb->len, base_flags,
  5946. mss, vlan)) {
  5947. tg3_tx_skb_unmap(tnapi, save_entry, -1);
  5948. dev_kfree_skb(new_skb);
  5949. ret = -1;
  5950. }
  5951. }
  5952. }
  5953. dev_kfree_skb(skb);
  5954. *pskb = new_skb;
  5955. return ret;
  5956. }
  5957. static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
  5958. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  5959. * TSO header is greater than 80 bytes.
  5960. */
  5961. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  5962. {
  5963. struct sk_buff *segs, *nskb;
  5964. u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
  5965. /* Estimate the number of fragments in the worst case */
  5966. if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
  5967. netif_stop_queue(tp->dev);
  5968. /* netif_tx_stop_queue() must be done before checking
  5969. * checking tx index in tg3_tx_avail() below, because in
  5970. * tg3_tx(), we update tx index before checking for
  5971. * netif_tx_queue_stopped().
  5972. */
  5973. smp_mb();
  5974. if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
  5975. return NETDEV_TX_BUSY;
  5976. netif_wake_queue(tp->dev);
  5977. }
  5978. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  5979. if (IS_ERR(segs))
  5980. goto tg3_tso_bug_end;
  5981. do {
  5982. nskb = segs;
  5983. segs = segs->next;
  5984. nskb->next = NULL;
  5985. tg3_start_xmit(nskb, tp->dev);
  5986. } while (segs);
  5987. tg3_tso_bug_end:
  5988. dev_kfree_skb(skb);
  5989. return NETDEV_TX_OK;
  5990. }
  5991. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  5992. * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
  5993. */
  5994. static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  5995. {
  5996. struct tg3 *tp = netdev_priv(dev);
  5997. u32 len, entry, base_flags, mss, vlan = 0;
  5998. u32 budget;
  5999. int i = -1, would_hit_hwbug;
  6000. dma_addr_t mapping;
  6001. struct tg3_napi *tnapi;
  6002. struct netdev_queue *txq;
  6003. unsigned int last;
  6004. txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
  6005. tnapi = &tp->napi[skb_get_queue_mapping(skb)];
  6006. if (tg3_flag(tp, ENABLE_TSS))
  6007. tnapi++;
  6008. budget = tg3_tx_avail(tnapi);
  6009. /* We are running in BH disabled context with netif_tx_lock
  6010. * and TX reclaim runs via tp->napi.poll inside of a software
  6011. * interrupt. Furthermore, IRQ processing runs lockless so we have
  6012. * no IRQ context deadlocks to worry about either. Rejoice!
  6013. */
  6014. if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
  6015. if (!netif_tx_queue_stopped(txq)) {
  6016. netif_tx_stop_queue(txq);
  6017. /* This is a hard error, log it. */
  6018. netdev_err(dev,
  6019. "BUG! Tx Ring full when queue awake!\n");
  6020. }
  6021. return NETDEV_TX_BUSY;
  6022. }
  6023. entry = tnapi->tx_prod;
  6024. base_flags = 0;
  6025. if (skb->ip_summed == CHECKSUM_PARTIAL)
  6026. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  6027. mss = skb_shinfo(skb)->gso_size;
  6028. if (mss) {
  6029. struct iphdr *iph;
  6030. u32 tcp_opt_len, hdr_len;
  6031. if (skb_header_cloned(skb) &&
  6032. pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
  6033. goto drop;
  6034. iph = ip_hdr(skb);
  6035. tcp_opt_len = tcp_optlen(skb);
  6036. hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
  6037. if (!skb_is_gso_v6(skb)) {
  6038. iph->check = 0;
  6039. iph->tot_len = htons(mss + hdr_len);
  6040. }
  6041. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  6042. tg3_flag(tp, TSO_BUG))
  6043. return tg3_tso_bug(tp, skb);
  6044. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  6045. TXD_FLAG_CPU_POST_DMA);
  6046. if (tg3_flag(tp, HW_TSO_1) ||
  6047. tg3_flag(tp, HW_TSO_2) ||
  6048. tg3_flag(tp, HW_TSO_3)) {
  6049. tcp_hdr(skb)->check = 0;
  6050. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  6051. } else
  6052. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  6053. iph->daddr, 0,
  6054. IPPROTO_TCP,
  6055. 0);
  6056. if (tg3_flag(tp, HW_TSO_3)) {
  6057. mss |= (hdr_len & 0xc) << 12;
  6058. if (hdr_len & 0x10)
  6059. base_flags |= 0x00000010;
  6060. base_flags |= (hdr_len & 0x3e0) << 5;
  6061. } else if (tg3_flag(tp, HW_TSO_2))
  6062. mss |= hdr_len << 9;
  6063. else if (tg3_flag(tp, HW_TSO_1) ||
  6064. tg3_asic_rev(tp) == ASIC_REV_5705) {
  6065. if (tcp_opt_len || iph->ihl > 5) {
  6066. int tsflags;
  6067. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  6068. mss |= (tsflags << 11);
  6069. }
  6070. } else {
  6071. if (tcp_opt_len || iph->ihl > 5) {
  6072. int tsflags;
  6073. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  6074. base_flags |= tsflags << 12;
  6075. }
  6076. }
  6077. }
  6078. if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
  6079. !mss && skb->len > VLAN_ETH_FRAME_LEN)
  6080. base_flags |= TXD_FLAG_JMB_PKT;
  6081. if (vlan_tx_tag_present(skb)) {
  6082. base_flags |= TXD_FLAG_VLAN;
  6083. vlan = vlan_tx_tag_get(skb);
  6084. }
  6085. if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
  6086. tg3_flag(tp, TX_TSTAMP_EN)) {
  6087. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  6088. base_flags |= TXD_FLAG_HWTSTAMP;
  6089. }
  6090. len = skb_headlen(skb);
  6091. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  6092. if (pci_dma_mapping_error(tp->pdev, mapping))
  6093. goto drop;
  6094. tnapi->tx_buffers[entry].skb = skb;
  6095. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
  6096. would_hit_hwbug = 0;
  6097. if (tg3_flag(tp, 5701_DMA_BUG))
  6098. would_hit_hwbug = 1;
  6099. if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
  6100. ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
  6101. mss, vlan)) {
  6102. would_hit_hwbug = 1;
  6103. } else if (skb_shinfo(skb)->nr_frags > 0) {
  6104. u32 tmp_mss = mss;
  6105. if (!tg3_flag(tp, HW_TSO_1) &&
  6106. !tg3_flag(tp, HW_TSO_2) &&
  6107. !tg3_flag(tp, HW_TSO_3))
  6108. tmp_mss = 0;
  6109. /* Now loop through additional data
  6110. * fragments, and queue them.
  6111. */
  6112. last = skb_shinfo(skb)->nr_frags - 1;
  6113. for (i = 0; i <= last; i++) {
  6114. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  6115. len = skb_frag_size(frag);
  6116. mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
  6117. len, DMA_TO_DEVICE);
  6118. tnapi->tx_buffers[entry].skb = NULL;
  6119. dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
  6120. mapping);
  6121. if (dma_mapping_error(&tp->pdev->dev, mapping))
  6122. goto dma_error;
  6123. if (!budget ||
  6124. tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
  6125. len, base_flags |
  6126. ((i == last) ? TXD_FLAG_END : 0),
  6127. tmp_mss, vlan)) {
  6128. would_hit_hwbug = 1;
  6129. break;
  6130. }
  6131. }
  6132. }
  6133. if (would_hit_hwbug) {
  6134. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
  6135. /* If the workaround fails due to memory/mapping
  6136. * failure, silently drop this packet.
  6137. */
  6138. entry = tnapi->tx_prod;
  6139. budget = tg3_tx_avail(tnapi);
  6140. if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
  6141. base_flags, mss, vlan))
  6142. goto drop_nofree;
  6143. }
  6144. skb_tx_timestamp(skb);
  6145. netdev_tx_sent_queue(txq, skb->len);
  6146. /* Sync BD data before updating mailbox */
  6147. wmb();
  6148. /* Packets are ready, update Tx producer idx local and on card. */
  6149. tw32_tx_mbox(tnapi->prodmbox, entry);
  6150. tnapi->tx_prod = entry;
  6151. if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
  6152. netif_tx_stop_queue(txq);
  6153. /* netif_tx_stop_queue() must be done before checking
  6154. * checking tx index in tg3_tx_avail() below, because in
  6155. * tg3_tx(), we update tx index before checking for
  6156. * netif_tx_queue_stopped().
  6157. */
  6158. smp_mb();
  6159. if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
  6160. netif_tx_wake_queue(txq);
  6161. }
  6162. mmiowb();
  6163. return NETDEV_TX_OK;
  6164. dma_error:
  6165. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
  6166. tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
  6167. drop:
  6168. dev_kfree_skb(skb);
  6169. drop_nofree:
  6170. tp->tx_dropped++;
  6171. return NETDEV_TX_OK;
  6172. }
  6173. static void tg3_mac_loopback(struct tg3 *tp, bool enable)
  6174. {
  6175. if (enable) {
  6176. tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
  6177. MAC_MODE_PORT_MODE_MASK);
  6178. tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
  6179. if (!tg3_flag(tp, 5705_PLUS))
  6180. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  6181. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  6182. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  6183. else
  6184. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  6185. } else {
  6186. tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
  6187. if (tg3_flag(tp, 5705_PLUS) ||
  6188. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
  6189. tg3_asic_rev(tp) == ASIC_REV_5700)
  6190. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  6191. }
  6192. tw32(MAC_MODE, tp->mac_mode);
  6193. udelay(40);
  6194. }
  6195. static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
  6196. {
  6197. u32 val, bmcr, mac_mode, ptest = 0;
  6198. tg3_phy_toggle_apd(tp, false);
  6199. tg3_phy_toggle_automdix(tp, 0);
  6200. if (extlpbk && tg3_phy_set_extloopbk(tp))
  6201. return -EIO;
  6202. bmcr = BMCR_FULLDPLX;
  6203. switch (speed) {
  6204. case SPEED_10:
  6205. break;
  6206. case SPEED_100:
  6207. bmcr |= BMCR_SPEED100;
  6208. break;
  6209. case SPEED_1000:
  6210. default:
  6211. if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
  6212. speed = SPEED_100;
  6213. bmcr |= BMCR_SPEED100;
  6214. } else {
  6215. speed = SPEED_1000;
  6216. bmcr |= BMCR_SPEED1000;
  6217. }
  6218. }
  6219. if (extlpbk) {
  6220. if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  6221. tg3_readphy(tp, MII_CTRL1000, &val);
  6222. val |= CTL1000_AS_MASTER |
  6223. CTL1000_ENABLE_MASTER;
  6224. tg3_writephy(tp, MII_CTRL1000, val);
  6225. } else {
  6226. ptest = MII_TG3_FET_PTEST_TRIM_SEL |
  6227. MII_TG3_FET_PTEST_TRIM_2;
  6228. tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
  6229. }
  6230. } else
  6231. bmcr |= BMCR_LOOPBACK;
  6232. tg3_writephy(tp, MII_BMCR, bmcr);
  6233. /* The write needs to be flushed for the FETs */
  6234. if (tp->phy_flags & TG3_PHYFLG_IS_FET)
  6235. tg3_readphy(tp, MII_BMCR, &bmcr);
  6236. udelay(40);
  6237. if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  6238. tg3_asic_rev(tp) == ASIC_REV_5785) {
  6239. tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
  6240. MII_TG3_FET_PTEST_FRC_TX_LINK |
  6241. MII_TG3_FET_PTEST_FRC_TX_LOCK);
  6242. /* The write needs to be flushed for the AC131 */
  6243. tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
  6244. }
  6245. /* Reset to prevent losing 1st rx packet intermittently */
  6246. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  6247. tg3_flag(tp, 5780_CLASS)) {
  6248. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  6249. udelay(10);
  6250. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6251. }
  6252. mac_mode = tp->mac_mode &
  6253. ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  6254. if (speed == SPEED_1000)
  6255. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  6256. else
  6257. mac_mode |= MAC_MODE_PORT_MODE_MII;
  6258. if (tg3_asic_rev(tp) == ASIC_REV_5700) {
  6259. u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
  6260. if (masked_phy_id == TG3_PHY_ID_BCM5401)
  6261. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  6262. else if (masked_phy_id == TG3_PHY_ID_BCM5411)
  6263. mac_mode |= MAC_MODE_LINK_POLARITY;
  6264. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  6265. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  6266. }
  6267. tw32(MAC_MODE, mac_mode);
  6268. udelay(40);
  6269. return 0;
  6270. }
  6271. static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
  6272. {
  6273. struct tg3 *tp = netdev_priv(dev);
  6274. if (features & NETIF_F_LOOPBACK) {
  6275. if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
  6276. return;
  6277. spin_lock_bh(&tp->lock);
  6278. tg3_mac_loopback(tp, true);
  6279. netif_carrier_on(tp->dev);
  6280. spin_unlock_bh(&tp->lock);
  6281. netdev_info(dev, "Internal MAC loopback mode enabled.\n");
  6282. } else {
  6283. if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
  6284. return;
  6285. spin_lock_bh(&tp->lock);
  6286. tg3_mac_loopback(tp, false);
  6287. /* Force link status check */
  6288. tg3_setup_phy(tp, 1);
  6289. spin_unlock_bh(&tp->lock);
  6290. netdev_info(dev, "Internal MAC loopback mode disabled.\n");
  6291. }
  6292. }
  6293. static netdev_features_t tg3_fix_features(struct net_device *dev,
  6294. netdev_features_t features)
  6295. {
  6296. struct tg3 *tp = netdev_priv(dev);
  6297. if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
  6298. features &= ~NETIF_F_ALL_TSO;
  6299. return features;
  6300. }
  6301. static int tg3_set_features(struct net_device *dev, netdev_features_t features)
  6302. {
  6303. netdev_features_t changed = dev->features ^ features;
  6304. if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
  6305. tg3_set_loopback(dev, features);
  6306. return 0;
  6307. }
  6308. static void tg3_rx_prodring_free(struct tg3 *tp,
  6309. struct tg3_rx_prodring_set *tpr)
  6310. {
  6311. int i;
  6312. if (tpr != &tp->napi[0].prodring) {
  6313. for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
  6314. i = (i + 1) & tp->rx_std_ring_mask)
  6315. tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
  6316. tp->rx_pkt_map_sz);
  6317. if (tg3_flag(tp, JUMBO_CAPABLE)) {
  6318. for (i = tpr->rx_jmb_cons_idx;
  6319. i != tpr->rx_jmb_prod_idx;
  6320. i = (i + 1) & tp->rx_jmb_ring_mask) {
  6321. tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
  6322. TG3_RX_JMB_MAP_SZ);
  6323. }
  6324. }
  6325. return;
  6326. }
  6327. for (i = 0; i <= tp->rx_std_ring_mask; i++)
  6328. tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
  6329. tp->rx_pkt_map_sz);
  6330. if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
  6331. for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
  6332. tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
  6333. TG3_RX_JMB_MAP_SZ);
  6334. }
  6335. }
  6336. /* Initialize rx rings for packet processing.
  6337. *
  6338. * The chip has been shut down and the driver detached from
  6339. * the networking, so no interrupts or new tx packets will
  6340. * end up in the driver. tp->{tx,}lock are held and thus
  6341. * we may not sleep.
  6342. */
  6343. static int tg3_rx_prodring_alloc(struct tg3 *tp,
  6344. struct tg3_rx_prodring_set *tpr)
  6345. {
  6346. u32 i, rx_pkt_dma_sz;
  6347. tpr->rx_std_cons_idx = 0;
  6348. tpr->rx_std_prod_idx = 0;
  6349. tpr->rx_jmb_cons_idx = 0;
  6350. tpr->rx_jmb_prod_idx = 0;
  6351. if (tpr != &tp->napi[0].prodring) {
  6352. memset(&tpr->rx_std_buffers[0], 0,
  6353. TG3_RX_STD_BUFF_RING_SIZE(tp));
  6354. if (tpr->rx_jmb_buffers)
  6355. memset(&tpr->rx_jmb_buffers[0], 0,
  6356. TG3_RX_JMB_BUFF_RING_SIZE(tp));
  6357. goto done;
  6358. }
  6359. /* Zero out all descriptors. */
  6360. memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
  6361. rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
  6362. if (tg3_flag(tp, 5780_CLASS) &&
  6363. tp->dev->mtu > ETH_DATA_LEN)
  6364. rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
  6365. tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
  6366. /* Initialize invariants of the rings, we only set this
  6367. * stuff once. This works because the card does not
  6368. * write into the rx buffer posting rings.
  6369. */
  6370. for (i = 0; i <= tp->rx_std_ring_mask; i++) {
  6371. struct tg3_rx_buffer_desc *rxd;
  6372. rxd = &tpr->rx_std[i];
  6373. rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
  6374. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  6375. rxd->opaque = (RXD_OPAQUE_RING_STD |
  6376. (i << RXD_OPAQUE_INDEX_SHIFT));
  6377. }
  6378. /* Now allocate fresh SKBs for each rx ring. */
  6379. for (i = 0; i < tp->rx_pending; i++) {
  6380. unsigned int frag_size;
  6381. if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
  6382. &frag_size) < 0) {
  6383. netdev_warn(tp->dev,
  6384. "Using a smaller RX standard ring. Only "
  6385. "%d out of %d buffers were allocated "
  6386. "successfully\n", i, tp->rx_pending);
  6387. if (i == 0)
  6388. goto initfail;
  6389. tp->rx_pending = i;
  6390. break;
  6391. }
  6392. }
  6393. if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
  6394. goto done;
  6395. memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
  6396. if (!tg3_flag(tp, JUMBO_RING_ENABLE))
  6397. goto done;
  6398. for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
  6399. struct tg3_rx_buffer_desc *rxd;
  6400. rxd = &tpr->rx_jmb[i].std;
  6401. rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
  6402. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  6403. RXD_FLAG_JUMBO;
  6404. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  6405. (i << RXD_OPAQUE_INDEX_SHIFT));
  6406. }
  6407. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  6408. unsigned int frag_size;
  6409. if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
  6410. &frag_size) < 0) {
  6411. netdev_warn(tp->dev,
  6412. "Using a smaller RX jumbo ring. Only %d "
  6413. "out of %d buffers were allocated "
  6414. "successfully\n", i, tp->rx_jumbo_pending);
  6415. if (i == 0)
  6416. goto initfail;
  6417. tp->rx_jumbo_pending = i;
  6418. break;
  6419. }
  6420. }
  6421. done:
  6422. return 0;
  6423. initfail:
  6424. tg3_rx_prodring_free(tp, tpr);
  6425. return -ENOMEM;
  6426. }
  6427. static void tg3_rx_prodring_fini(struct tg3 *tp,
  6428. struct tg3_rx_prodring_set *tpr)
  6429. {
  6430. kfree(tpr->rx_std_buffers);
  6431. tpr->rx_std_buffers = NULL;
  6432. kfree(tpr->rx_jmb_buffers);
  6433. tpr->rx_jmb_buffers = NULL;
  6434. if (tpr->rx_std) {
  6435. dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
  6436. tpr->rx_std, tpr->rx_std_mapping);
  6437. tpr->rx_std = NULL;
  6438. }
  6439. if (tpr->rx_jmb) {
  6440. dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
  6441. tpr->rx_jmb, tpr->rx_jmb_mapping);
  6442. tpr->rx_jmb = NULL;
  6443. }
  6444. }
  6445. static int tg3_rx_prodring_init(struct tg3 *tp,
  6446. struct tg3_rx_prodring_set *tpr)
  6447. {
  6448. tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
  6449. GFP_KERNEL);
  6450. if (!tpr->rx_std_buffers)
  6451. return -ENOMEM;
  6452. tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
  6453. TG3_RX_STD_RING_BYTES(tp),
  6454. &tpr->rx_std_mapping,
  6455. GFP_KERNEL);
  6456. if (!tpr->rx_std)
  6457. goto err_out;
  6458. if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
  6459. tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
  6460. GFP_KERNEL);
  6461. if (!tpr->rx_jmb_buffers)
  6462. goto err_out;
  6463. tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
  6464. TG3_RX_JMB_RING_BYTES(tp),
  6465. &tpr->rx_jmb_mapping,
  6466. GFP_KERNEL);
  6467. if (!tpr->rx_jmb)
  6468. goto err_out;
  6469. }
  6470. return 0;
  6471. err_out:
  6472. tg3_rx_prodring_fini(tp, tpr);
  6473. return -ENOMEM;
  6474. }
  6475. /* Free up pending packets in all rx/tx rings.
  6476. *
  6477. * The chip has been shut down and the driver detached from
  6478. * the networking, so no interrupts or new tx packets will
  6479. * end up in the driver. tp->{tx,}lock is not held and we are not
  6480. * in an interrupt context and thus may sleep.
  6481. */
  6482. static void tg3_free_rings(struct tg3 *tp)
  6483. {
  6484. int i, j;
  6485. for (j = 0; j < tp->irq_cnt; j++) {
  6486. struct tg3_napi *tnapi = &tp->napi[j];
  6487. tg3_rx_prodring_free(tp, &tnapi->prodring);
  6488. if (!tnapi->tx_buffers)
  6489. continue;
  6490. for (i = 0; i < TG3_TX_RING_SIZE; i++) {
  6491. struct sk_buff *skb = tnapi->tx_buffers[i].skb;
  6492. if (!skb)
  6493. continue;
  6494. tg3_tx_skb_unmap(tnapi, i,
  6495. skb_shinfo(skb)->nr_frags - 1);
  6496. dev_kfree_skb_any(skb);
  6497. }
  6498. netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
  6499. }
  6500. }
  6501. /* Initialize tx/rx rings for packet processing.
  6502. *
  6503. * The chip has been shut down and the driver detached from
  6504. * the networking, so no interrupts or new tx packets will
  6505. * end up in the driver. tp->{tx,}lock are held and thus
  6506. * we may not sleep.
  6507. */
  6508. static int tg3_init_rings(struct tg3 *tp)
  6509. {
  6510. int i;
  6511. /* Free up all the SKBs. */
  6512. tg3_free_rings(tp);
  6513. for (i = 0; i < tp->irq_cnt; i++) {
  6514. struct tg3_napi *tnapi = &tp->napi[i];
  6515. tnapi->last_tag = 0;
  6516. tnapi->last_irq_tag = 0;
  6517. tnapi->hw_status->status = 0;
  6518. tnapi->hw_status->status_tag = 0;
  6519. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6520. tnapi->tx_prod = 0;
  6521. tnapi->tx_cons = 0;
  6522. if (tnapi->tx_ring)
  6523. memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
  6524. tnapi->rx_rcb_ptr = 0;
  6525. if (tnapi->rx_rcb)
  6526. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  6527. if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
  6528. tg3_free_rings(tp);
  6529. return -ENOMEM;
  6530. }
  6531. }
  6532. return 0;
  6533. }
  6534. static void tg3_mem_tx_release(struct tg3 *tp)
  6535. {
  6536. int i;
  6537. for (i = 0; i < tp->irq_max; i++) {
  6538. struct tg3_napi *tnapi = &tp->napi[i];
  6539. if (tnapi->tx_ring) {
  6540. dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
  6541. tnapi->tx_ring, tnapi->tx_desc_mapping);
  6542. tnapi->tx_ring = NULL;
  6543. }
  6544. kfree(tnapi->tx_buffers);
  6545. tnapi->tx_buffers = NULL;
  6546. }
  6547. }
  6548. static int tg3_mem_tx_acquire(struct tg3 *tp)
  6549. {
  6550. int i;
  6551. struct tg3_napi *tnapi = &tp->napi[0];
  6552. /* If multivector TSS is enabled, vector 0 does not handle
  6553. * tx interrupts. Don't allocate any resources for it.
  6554. */
  6555. if (tg3_flag(tp, ENABLE_TSS))
  6556. tnapi++;
  6557. for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
  6558. tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
  6559. TG3_TX_RING_SIZE, GFP_KERNEL);
  6560. if (!tnapi->tx_buffers)
  6561. goto err_out;
  6562. tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
  6563. TG3_TX_RING_BYTES,
  6564. &tnapi->tx_desc_mapping,
  6565. GFP_KERNEL);
  6566. if (!tnapi->tx_ring)
  6567. goto err_out;
  6568. }
  6569. return 0;
  6570. err_out:
  6571. tg3_mem_tx_release(tp);
  6572. return -ENOMEM;
  6573. }
  6574. static void tg3_mem_rx_release(struct tg3 *tp)
  6575. {
  6576. int i;
  6577. for (i = 0; i < tp->irq_max; i++) {
  6578. struct tg3_napi *tnapi = &tp->napi[i];
  6579. tg3_rx_prodring_fini(tp, &tnapi->prodring);
  6580. if (!tnapi->rx_rcb)
  6581. continue;
  6582. dma_free_coherent(&tp->pdev->dev,
  6583. TG3_RX_RCB_RING_BYTES(tp),
  6584. tnapi->rx_rcb,
  6585. tnapi->rx_rcb_mapping);
  6586. tnapi->rx_rcb = NULL;
  6587. }
  6588. }
  6589. static int tg3_mem_rx_acquire(struct tg3 *tp)
  6590. {
  6591. unsigned int i, limit;
  6592. limit = tp->rxq_cnt;
  6593. /* If RSS is enabled, we need a (dummy) producer ring
  6594. * set on vector zero. This is the true hw prodring.
  6595. */
  6596. if (tg3_flag(tp, ENABLE_RSS))
  6597. limit++;
  6598. for (i = 0; i < limit; i++) {
  6599. struct tg3_napi *tnapi = &tp->napi[i];
  6600. if (tg3_rx_prodring_init(tp, &tnapi->prodring))
  6601. goto err_out;
  6602. /* If multivector RSS is enabled, vector 0
  6603. * does not handle rx or tx interrupts.
  6604. * Don't allocate any resources for it.
  6605. */
  6606. if (!i && tg3_flag(tp, ENABLE_RSS))
  6607. continue;
  6608. tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
  6609. TG3_RX_RCB_RING_BYTES(tp),
  6610. &tnapi->rx_rcb_mapping,
  6611. GFP_KERNEL);
  6612. if (!tnapi->rx_rcb)
  6613. goto err_out;
  6614. memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  6615. }
  6616. return 0;
  6617. err_out:
  6618. tg3_mem_rx_release(tp);
  6619. return -ENOMEM;
  6620. }
  6621. /*
  6622. * Must not be invoked with interrupt sources disabled and
  6623. * the hardware shutdown down.
  6624. */
  6625. static void tg3_free_consistent(struct tg3 *tp)
  6626. {
  6627. int i;
  6628. for (i = 0; i < tp->irq_cnt; i++) {
  6629. struct tg3_napi *tnapi = &tp->napi[i];
  6630. if (tnapi->hw_status) {
  6631. dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
  6632. tnapi->hw_status,
  6633. tnapi->status_mapping);
  6634. tnapi->hw_status = NULL;
  6635. }
  6636. }
  6637. tg3_mem_rx_release(tp);
  6638. tg3_mem_tx_release(tp);
  6639. if (tp->hw_stats) {
  6640. dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
  6641. tp->hw_stats, tp->stats_mapping);
  6642. tp->hw_stats = NULL;
  6643. }
  6644. }
  6645. /*
  6646. * Must not be invoked with interrupt sources disabled and
  6647. * the hardware shutdown down. Can sleep.
  6648. */
  6649. static int tg3_alloc_consistent(struct tg3 *tp)
  6650. {
  6651. int i;
  6652. tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
  6653. sizeof(struct tg3_hw_stats),
  6654. &tp->stats_mapping,
  6655. GFP_KERNEL);
  6656. if (!tp->hw_stats)
  6657. goto err_out;
  6658. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  6659. for (i = 0; i < tp->irq_cnt; i++) {
  6660. struct tg3_napi *tnapi = &tp->napi[i];
  6661. struct tg3_hw_status *sblk;
  6662. tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
  6663. TG3_HW_STATUS_SIZE,
  6664. &tnapi->status_mapping,
  6665. GFP_KERNEL);
  6666. if (!tnapi->hw_status)
  6667. goto err_out;
  6668. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6669. sblk = tnapi->hw_status;
  6670. if (tg3_flag(tp, ENABLE_RSS)) {
  6671. u16 *prodptr = NULL;
  6672. /*
  6673. * When RSS is enabled, the status block format changes
  6674. * slightly. The "rx_jumbo_consumer", "reserved",
  6675. * and "rx_mini_consumer" members get mapped to the
  6676. * other three rx return ring producer indexes.
  6677. */
  6678. switch (i) {
  6679. case 1:
  6680. prodptr = &sblk->idx[0].rx_producer;
  6681. break;
  6682. case 2:
  6683. prodptr = &sblk->rx_jumbo_consumer;
  6684. break;
  6685. case 3:
  6686. prodptr = &sblk->reserved;
  6687. break;
  6688. case 4:
  6689. prodptr = &sblk->rx_mini_consumer;
  6690. break;
  6691. }
  6692. tnapi->rx_rcb_prod_idx = prodptr;
  6693. } else {
  6694. tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
  6695. }
  6696. }
  6697. if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
  6698. goto err_out;
  6699. return 0;
  6700. err_out:
  6701. tg3_free_consistent(tp);
  6702. return -ENOMEM;
  6703. }
  6704. #define MAX_WAIT_CNT 1000
  6705. /* To stop a block, clear the enable bit and poll till it
  6706. * clears. tp->lock is held.
  6707. */
  6708. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  6709. {
  6710. unsigned int i;
  6711. u32 val;
  6712. if (tg3_flag(tp, 5705_PLUS)) {
  6713. switch (ofs) {
  6714. case RCVLSC_MODE:
  6715. case DMAC_MODE:
  6716. case MBFREE_MODE:
  6717. case BUFMGR_MODE:
  6718. case MEMARB_MODE:
  6719. /* We can't enable/disable these bits of the
  6720. * 5705/5750, just say success.
  6721. */
  6722. return 0;
  6723. default:
  6724. break;
  6725. }
  6726. }
  6727. val = tr32(ofs);
  6728. val &= ~enable_bit;
  6729. tw32_f(ofs, val);
  6730. for (i = 0; i < MAX_WAIT_CNT; i++) {
  6731. udelay(100);
  6732. val = tr32(ofs);
  6733. if ((val & enable_bit) == 0)
  6734. break;
  6735. }
  6736. if (i == MAX_WAIT_CNT && !silent) {
  6737. dev_err(&tp->pdev->dev,
  6738. "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
  6739. ofs, enable_bit);
  6740. return -ENODEV;
  6741. }
  6742. return 0;
  6743. }
  6744. /* tp->lock is held. */
  6745. static int tg3_abort_hw(struct tg3 *tp, int silent)
  6746. {
  6747. int i, err;
  6748. tg3_disable_ints(tp);
  6749. tp->rx_mode &= ~RX_MODE_ENABLE;
  6750. tw32_f(MAC_RX_MODE, tp->rx_mode);
  6751. udelay(10);
  6752. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  6753. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  6754. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  6755. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  6756. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  6757. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  6758. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  6759. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  6760. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  6761. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  6762. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  6763. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  6764. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  6765. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  6766. tw32_f(MAC_MODE, tp->mac_mode);
  6767. udelay(40);
  6768. tp->tx_mode &= ~TX_MODE_ENABLE;
  6769. tw32_f(MAC_TX_MODE, tp->tx_mode);
  6770. for (i = 0; i < MAX_WAIT_CNT; i++) {
  6771. udelay(100);
  6772. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  6773. break;
  6774. }
  6775. if (i >= MAX_WAIT_CNT) {
  6776. dev_err(&tp->pdev->dev,
  6777. "%s timed out, TX_MODE_ENABLE will not clear "
  6778. "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
  6779. err |= -ENODEV;
  6780. }
  6781. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  6782. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  6783. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  6784. tw32(FTQ_RESET, 0xffffffff);
  6785. tw32(FTQ_RESET, 0x00000000);
  6786. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  6787. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  6788. for (i = 0; i < tp->irq_cnt; i++) {
  6789. struct tg3_napi *tnapi = &tp->napi[i];
  6790. if (tnapi->hw_status)
  6791. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  6792. }
  6793. return err;
  6794. }
  6795. /* Save PCI command register before chip reset */
  6796. static void tg3_save_pci_state(struct tg3 *tp)
  6797. {
  6798. pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
  6799. }
  6800. /* Restore PCI state after chip reset */
  6801. static void tg3_restore_pci_state(struct tg3 *tp)
  6802. {
  6803. u32 val;
  6804. /* Re-enable indirect register accesses. */
  6805. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  6806. tp->misc_host_ctrl);
  6807. /* Set MAX PCI retry to zero. */
  6808. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  6809. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
  6810. tg3_flag(tp, PCIX_MODE))
  6811. val |= PCISTATE_RETRY_SAME_DMA;
  6812. /* Allow reads and writes to the APE register and memory space. */
  6813. if (tg3_flag(tp, ENABLE_APE))
  6814. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  6815. PCISTATE_ALLOW_APE_SHMEM_WR |
  6816. PCISTATE_ALLOW_APE_PSPACE_WR;
  6817. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  6818. pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
  6819. if (!tg3_flag(tp, PCI_EXPRESS)) {
  6820. pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  6821. tp->pci_cacheline_sz);
  6822. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  6823. tp->pci_lat_timer);
  6824. }
  6825. /* Make sure PCI-X relaxed ordering bit is clear. */
  6826. if (tg3_flag(tp, PCIX_MODE)) {
  6827. u16 pcix_cmd;
  6828. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6829. &pcix_cmd);
  6830. pcix_cmd &= ~PCI_X_CMD_ERO;
  6831. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  6832. pcix_cmd);
  6833. }
  6834. if (tg3_flag(tp, 5780_CLASS)) {
  6835. /* Chip reset on 5780 will reset MSI enable bit,
  6836. * so need to restore it.
  6837. */
  6838. if (tg3_flag(tp, USING_MSI)) {
  6839. u16 ctrl;
  6840. pci_read_config_word(tp->pdev,
  6841. tp->msi_cap + PCI_MSI_FLAGS,
  6842. &ctrl);
  6843. pci_write_config_word(tp->pdev,
  6844. tp->msi_cap + PCI_MSI_FLAGS,
  6845. ctrl | PCI_MSI_FLAGS_ENABLE);
  6846. val = tr32(MSGINT_MODE);
  6847. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  6848. }
  6849. }
  6850. }
  6851. /* tp->lock is held. */
  6852. static int tg3_chip_reset(struct tg3 *tp)
  6853. {
  6854. u32 val;
  6855. void (*write_op)(struct tg3 *, u32, u32);
  6856. int i, err;
  6857. tg3_nvram_lock(tp);
  6858. tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
  6859. /* No matching tg3_nvram_unlock() after this because
  6860. * chip reset below will undo the nvram lock.
  6861. */
  6862. tp->nvram_lock_cnt = 0;
  6863. /* GRC_MISC_CFG core clock reset will clear the memory
  6864. * enable bit in PCI register 4 and the MSI enable bit
  6865. * on some chips, so we save relevant registers here.
  6866. */
  6867. tg3_save_pci_state(tp);
  6868. if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
  6869. tg3_flag(tp, 5755_PLUS))
  6870. tw32(GRC_FASTBOOT_PC, 0);
  6871. /*
  6872. * We must avoid the readl() that normally takes place.
  6873. * It locks machines, causes machine checks, and other
  6874. * fun things. So, temporarily disable the 5701
  6875. * hardware workaround, while we do the reset.
  6876. */
  6877. write_op = tp->write32;
  6878. if (write_op == tg3_write_flush_reg32)
  6879. tp->write32 = tg3_write32;
  6880. /* Prevent the irq handler from reading or writing PCI registers
  6881. * during chip reset when the memory enable bit in the PCI command
  6882. * register may be cleared. The chip does not generate interrupt
  6883. * at this time, but the irq handler may still be called due to irq
  6884. * sharing or irqpoll.
  6885. */
  6886. tg3_flag_set(tp, CHIP_RESETTING);
  6887. for (i = 0; i < tp->irq_cnt; i++) {
  6888. struct tg3_napi *tnapi = &tp->napi[i];
  6889. if (tnapi->hw_status) {
  6890. tnapi->hw_status->status = 0;
  6891. tnapi->hw_status->status_tag = 0;
  6892. }
  6893. tnapi->last_tag = 0;
  6894. tnapi->last_irq_tag = 0;
  6895. }
  6896. smp_mb();
  6897. for (i = 0; i < tp->irq_cnt; i++)
  6898. synchronize_irq(tp->napi[i].irq_vec);
  6899. if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  6900. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  6901. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  6902. }
  6903. /* do the reset */
  6904. val = GRC_MISC_CFG_CORECLK_RESET;
  6905. if (tg3_flag(tp, PCI_EXPRESS)) {
  6906. /* Force PCIe 1.0a mode */
  6907. if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
  6908. !tg3_flag(tp, 57765_PLUS) &&
  6909. tr32(TG3_PCIE_PHY_TSTCTL) ==
  6910. (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
  6911. tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
  6912. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
  6913. tw32(GRC_MISC_CFG, (1 << 29));
  6914. val |= (1 << 29);
  6915. }
  6916. }
  6917. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  6918. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  6919. tw32(GRC_VCPU_EXT_CTRL,
  6920. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  6921. }
  6922. /* Manage gphy power for all CPMU absent PCIe devices. */
  6923. if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
  6924. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  6925. tw32(GRC_MISC_CFG, val);
  6926. /* restore 5701 hardware bug workaround write method */
  6927. tp->write32 = write_op;
  6928. /* Unfortunately, we have to delay before the PCI read back.
  6929. * Some 575X chips even will not respond to a PCI cfg access
  6930. * when the reset command is given to the chip.
  6931. *
  6932. * How do these hardware designers expect things to work
  6933. * properly if the PCI write is posted for a long period
  6934. * of time? It is always necessary to have some method by
  6935. * which a register read back can occur to push the write
  6936. * out which does the reset.
  6937. *
  6938. * For most tg3 variants the trick below was working.
  6939. * Ho hum...
  6940. */
  6941. udelay(120);
  6942. /* Flush PCI posted writes. The normal MMIO registers
  6943. * are inaccessible at this time so this is the only
  6944. * way to make this reliably (actually, this is no longer
  6945. * the case, see above). I tried to use indirect
  6946. * register read/write but this upset some 5701 variants.
  6947. */
  6948. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  6949. udelay(120);
  6950. if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
  6951. u16 val16;
  6952. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
  6953. int j;
  6954. u32 cfg_val;
  6955. /* Wait for link training to complete. */
  6956. for (j = 0; j < 5000; j++)
  6957. udelay(100);
  6958. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  6959. pci_write_config_dword(tp->pdev, 0xc4,
  6960. cfg_val | (1 << 15));
  6961. }
  6962. /* Clear the "no snoop" and "relaxed ordering" bits. */
  6963. val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
  6964. /*
  6965. * Older PCIe devices only support the 128 byte
  6966. * MPS setting. Enforce the restriction.
  6967. */
  6968. if (!tg3_flag(tp, CPMU_PRESENT))
  6969. val16 |= PCI_EXP_DEVCTL_PAYLOAD;
  6970. pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
  6971. /* Clear error status */
  6972. pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
  6973. PCI_EXP_DEVSTA_CED |
  6974. PCI_EXP_DEVSTA_NFED |
  6975. PCI_EXP_DEVSTA_FED |
  6976. PCI_EXP_DEVSTA_URD);
  6977. }
  6978. tg3_restore_pci_state(tp);
  6979. tg3_flag_clear(tp, CHIP_RESETTING);
  6980. tg3_flag_clear(tp, ERROR_PROCESSED);
  6981. val = 0;
  6982. if (tg3_flag(tp, 5780_CLASS))
  6983. val = tr32(MEMARB_MODE);
  6984. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  6985. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
  6986. tg3_stop_fw(tp);
  6987. tw32(0x5000, 0x400);
  6988. }
  6989. if (tg3_flag(tp, IS_SSB_CORE)) {
  6990. /*
  6991. * BCM4785: In order to avoid repercussions from using
  6992. * potentially defective internal ROM, stop the Rx RISC CPU,
  6993. * which is not required.
  6994. */
  6995. tg3_stop_fw(tp);
  6996. tg3_halt_cpu(tp, RX_CPU_BASE);
  6997. }
  6998. tw32(GRC_MODE, tp->grc_mode);
  6999. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
  7000. val = tr32(0xc4);
  7001. tw32(0xc4, val | (1 << 15));
  7002. }
  7003. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  7004. tg3_asic_rev(tp) == ASIC_REV_5705) {
  7005. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  7006. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
  7007. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  7008. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  7009. }
  7010. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  7011. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  7012. val = tp->mac_mode;
  7013. } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  7014. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  7015. val = tp->mac_mode;
  7016. } else
  7017. val = 0;
  7018. tw32_f(MAC_MODE, val);
  7019. udelay(40);
  7020. tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
  7021. err = tg3_poll_fw(tp);
  7022. if (err)
  7023. return err;
  7024. tg3_mdio_start(tp);
  7025. if (tg3_flag(tp, PCI_EXPRESS) &&
  7026. tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
  7027. tg3_asic_rev(tp) != ASIC_REV_5785 &&
  7028. !tg3_flag(tp, 57765_PLUS)) {
  7029. val = tr32(0x7c00);
  7030. tw32(0x7c00, val | (1 << 25));
  7031. }
  7032. if (tg3_asic_rev(tp) == ASIC_REV_5720) {
  7033. val = tr32(TG3_CPMU_CLCK_ORIDE);
  7034. tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
  7035. }
  7036. /* Reprobe ASF enable state. */
  7037. tg3_flag_clear(tp, ENABLE_ASF);
  7038. tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
  7039. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  7040. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  7041. u32 nic_cfg;
  7042. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  7043. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  7044. tg3_flag_set(tp, ENABLE_ASF);
  7045. tp->last_event_jiffies = jiffies;
  7046. if (tg3_flag(tp, 5750_PLUS))
  7047. tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
  7048. }
  7049. }
  7050. return 0;
  7051. }
  7052. static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
  7053. static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
  7054. /* tp->lock is held. */
  7055. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  7056. {
  7057. int err;
  7058. tg3_stop_fw(tp);
  7059. tg3_write_sig_pre_reset(tp, kind);
  7060. tg3_abort_hw(tp, silent);
  7061. err = tg3_chip_reset(tp);
  7062. __tg3_set_mac_addr(tp, 0);
  7063. tg3_write_sig_legacy(tp, kind);
  7064. tg3_write_sig_post_reset(tp, kind);
  7065. if (tp->hw_stats) {
  7066. /* Save the stats across chip resets... */
  7067. tg3_get_nstats(tp, &tp->net_stats_prev);
  7068. tg3_get_estats(tp, &tp->estats_prev);
  7069. /* And make sure the next sample is new data */
  7070. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  7071. }
  7072. if (err)
  7073. return err;
  7074. return 0;
  7075. }
  7076. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  7077. {
  7078. struct tg3 *tp = netdev_priv(dev);
  7079. struct sockaddr *addr = p;
  7080. int err = 0, skip_mac_1 = 0;
  7081. if (!is_valid_ether_addr(addr->sa_data))
  7082. return -EADDRNOTAVAIL;
  7083. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  7084. if (!netif_running(dev))
  7085. return 0;
  7086. if (tg3_flag(tp, ENABLE_ASF)) {
  7087. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  7088. addr0_high = tr32(MAC_ADDR_0_HIGH);
  7089. addr0_low = tr32(MAC_ADDR_0_LOW);
  7090. addr1_high = tr32(MAC_ADDR_1_HIGH);
  7091. addr1_low = tr32(MAC_ADDR_1_LOW);
  7092. /* Skip MAC addr 1 if ASF is using it. */
  7093. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  7094. !(addr1_high == 0 && addr1_low == 0))
  7095. skip_mac_1 = 1;
  7096. }
  7097. spin_lock_bh(&tp->lock);
  7098. __tg3_set_mac_addr(tp, skip_mac_1);
  7099. spin_unlock_bh(&tp->lock);
  7100. return err;
  7101. }
  7102. /* tp->lock is held. */
  7103. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  7104. dma_addr_t mapping, u32 maxlen_flags,
  7105. u32 nic_addr)
  7106. {
  7107. tg3_write_mem(tp,
  7108. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  7109. ((u64) mapping >> 32));
  7110. tg3_write_mem(tp,
  7111. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  7112. ((u64) mapping & 0xffffffff));
  7113. tg3_write_mem(tp,
  7114. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  7115. maxlen_flags);
  7116. if (!tg3_flag(tp, 5705_PLUS))
  7117. tg3_write_mem(tp,
  7118. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  7119. nic_addr);
  7120. }
  7121. static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
  7122. {
  7123. int i = 0;
  7124. if (!tg3_flag(tp, ENABLE_TSS)) {
  7125. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  7126. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  7127. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  7128. } else {
  7129. tw32(HOSTCC_TXCOL_TICKS, 0);
  7130. tw32(HOSTCC_TXMAX_FRAMES, 0);
  7131. tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
  7132. for (; i < tp->txq_cnt; i++) {
  7133. u32 reg;
  7134. reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
  7135. tw32(reg, ec->tx_coalesce_usecs);
  7136. reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
  7137. tw32(reg, ec->tx_max_coalesced_frames);
  7138. reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
  7139. tw32(reg, ec->tx_max_coalesced_frames_irq);
  7140. }
  7141. }
  7142. for (; i < tp->irq_max - 1; i++) {
  7143. tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
  7144. tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
  7145. tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  7146. }
  7147. }
  7148. static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
  7149. {
  7150. int i = 0;
  7151. u32 limit = tp->rxq_cnt;
  7152. if (!tg3_flag(tp, ENABLE_RSS)) {
  7153. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  7154. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  7155. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  7156. limit--;
  7157. } else {
  7158. tw32(HOSTCC_RXCOL_TICKS, 0);
  7159. tw32(HOSTCC_RXMAX_FRAMES, 0);
  7160. tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
  7161. }
  7162. for (; i < limit; i++) {
  7163. u32 reg;
  7164. reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
  7165. tw32(reg, ec->rx_coalesce_usecs);
  7166. reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
  7167. tw32(reg, ec->rx_max_coalesced_frames);
  7168. reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
  7169. tw32(reg, ec->rx_max_coalesced_frames_irq);
  7170. }
  7171. for (; i < tp->irq_max - 1; i++) {
  7172. tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
  7173. tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
  7174. tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
  7175. }
  7176. }
  7177. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  7178. {
  7179. tg3_coal_tx_init(tp, ec);
  7180. tg3_coal_rx_init(tp, ec);
  7181. if (!tg3_flag(tp, 5705_PLUS)) {
  7182. u32 val = ec->stats_block_coalesce_usecs;
  7183. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  7184. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  7185. if (!tp->link_up)
  7186. val = 0;
  7187. tw32(HOSTCC_STAT_COAL_TICKS, val);
  7188. }
  7189. }
  7190. /* tp->lock is held. */
  7191. static void tg3_rings_reset(struct tg3 *tp)
  7192. {
  7193. int i;
  7194. u32 stblk, txrcb, rxrcb, limit;
  7195. struct tg3_napi *tnapi = &tp->napi[0];
  7196. /* Disable all transmit rings but the first. */
  7197. if (!tg3_flag(tp, 5705_PLUS))
  7198. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
  7199. else if (tg3_flag(tp, 5717_PLUS))
  7200. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
  7201. else if (tg3_flag(tp, 57765_CLASS) ||
  7202. tg3_asic_rev(tp) == ASIC_REV_5762)
  7203. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
  7204. else
  7205. limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  7206. for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
  7207. txrcb < limit; txrcb += TG3_BDINFO_SIZE)
  7208. tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
  7209. BDINFO_FLAGS_DISABLED);
  7210. /* Disable all receive return rings but the first. */
  7211. if (tg3_flag(tp, 5717_PLUS))
  7212. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
  7213. else if (!tg3_flag(tp, 5705_PLUS))
  7214. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
  7215. else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  7216. tg3_asic_rev(tp) == ASIC_REV_5762 ||
  7217. tg3_flag(tp, 57765_CLASS))
  7218. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
  7219. else
  7220. limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  7221. for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
  7222. rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
  7223. tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
  7224. BDINFO_FLAGS_DISABLED);
  7225. /* Disable interrupts */
  7226. tw32_mailbox_f(tp->napi[0].int_mbox, 1);
  7227. tp->napi[0].chk_msi_cnt = 0;
  7228. tp->napi[0].last_rx_cons = 0;
  7229. tp->napi[0].last_tx_cons = 0;
  7230. /* Zero mailbox registers. */
  7231. if (tg3_flag(tp, SUPPORT_MSIX)) {
  7232. for (i = 1; i < tp->irq_max; i++) {
  7233. tp->napi[i].tx_prod = 0;
  7234. tp->napi[i].tx_cons = 0;
  7235. if (tg3_flag(tp, ENABLE_TSS))
  7236. tw32_mailbox(tp->napi[i].prodmbox, 0);
  7237. tw32_rx_mbox(tp->napi[i].consmbox, 0);
  7238. tw32_mailbox_f(tp->napi[i].int_mbox, 1);
  7239. tp->napi[i].chk_msi_cnt = 0;
  7240. tp->napi[i].last_rx_cons = 0;
  7241. tp->napi[i].last_tx_cons = 0;
  7242. }
  7243. if (!tg3_flag(tp, ENABLE_TSS))
  7244. tw32_mailbox(tp->napi[0].prodmbox, 0);
  7245. } else {
  7246. tp->napi[0].tx_prod = 0;
  7247. tp->napi[0].tx_cons = 0;
  7248. tw32_mailbox(tp->napi[0].prodmbox, 0);
  7249. tw32_rx_mbox(tp->napi[0].consmbox, 0);
  7250. }
  7251. /* Make sure the NIC-based send BD rings are disabled. */
  7252. if (!tg3_flag(tp, 5705_PLUS)) {
  7253. u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  7254. for (i = 0; i < 16; i++)
  7255. tw32_tx_mbox(mbox + i * 8, 0);
  7256. }
  7257. txrcb = NIC_SRAM_SEND_RCB;
  7258. rxrcb = NIC_SRAM_RCV_RET_RCB;
  7259. /* Clear status block in ram. */
  7260. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  7261. /* Set status block DMA address */
  7262. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7263. ((u64) tnapi->status_mapping >> 32));
  7264. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  7265. ((u64) tnapi->status_mapping & 0xffffffff));
  7266. if (tnapi->tx_ring) {
  7267. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  7268. (TG3_TX_RING_SIZE <<
  7269. BDINFO_FLAGS_MAXLEN_SHIFT),
  7270. NIC_SRAM_TX_BUFFER_DESC);
  7271. txrcb += TG3_BDINFO_SIZE;
  7272. }
  7273. if (tnapi->rx_rcb) {
  7274. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  7275. (tp->rx_ret_ring_mask + 1) <<
  7276. BDINFO_FLAGS_MAXLEN_SHIFT, 0);
  7277. rxrcb += TG3_BDINFO_SIZE;
  7278. }
  7279. stblk = HOSTCC_STATBLCK_RING1;
  7280. for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
  7281. u64 mapping = (u64)tnapi->status_mapping;
  7282. tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
  7283. tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
  7284. /* Clear status block in ram. */
  7285. memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
  7286. if (tnapi->tx_ring) {
  7287. tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
  7288. (TG3_TX_RING_SIZE <<
  7289. BDINFO_FLAGS_MAXLEN_SHIFT),
  7290. NIC_SRAM_TX_BUFFER_DESC);
  7291. txrcb += TG3_BDINFO_SIZE;
  7292. }
  7293. tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
  7294. ((tp->rx_ret_ring_mask + 1) <<
  7295. BDINFO_FLAGS_MAXLEN_SHIFT), 0);
  7296. stblk += 8;
  7297. rxrcb += TG3_BDINFO_SIZE;
  7298. }
  7299. }
  7300. static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
  7301. {
  7302. u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
  7303. if (!tg3_flag(tp, 5750_PLUS) ||
  7304. tg3_flag(tp, 5780_CLASS) ||
  7305. tg3_asic_rev(tp) == ASIC_REV_5750 ||
  7306. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  7307. tg3_flag(tp, 57765_PLUS))
  7308. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
  7309. else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  7310. tg3_asic_rev(tp) == ASIC_REV_5787)
  7311. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
  7312. else
  7313. bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
  7314. nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
  7315. host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
  7316. val = min(nic_rep_thresh, host_rep_thresh);
  7317. tw32(RCVBDI_STD_THRESH, val);
  7318. if (tg3_flag(tp, 57765_PLUS))
  7319. tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
  7320. if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
  7321. return;
  7322. bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
  7323. host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
  7324. val = min(bdcache_maxcnt / 2, host_rep_thresh);
  7325. tw32(RCVBDI_JUMBO_THRESH, val);
  7326. if (tg3_flag(tp, 57765_PLUS))
  7327. tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
  7328. }
  7329. static inline u32 calc_crc(unsigned char *buf, int len)
  7330. {
  7331. u32 reg;
  7332. u32 tmp;
  7333. int j, k;
  7334. reg = 0xffffffff;
  7335. for (j = 0; j < len; j++) {
  7336. reg ^= buf[j];
  7337. for (k = 0; k < 8; k++) {
  7338. tmp = reg & 0x01;
  7339. reg >>= 1;
  7340. if (tmp)
  7341. reg ^= 0xedb88320;
  7342. }
  7343. }
  7344. return ~reg;
  7345. }
  7346. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  7347. {
  7348. /* accept or reject all multicast frames */
  7349. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  7350. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  7351. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  7352. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  7353. }
  7354. static void __tg3_set_rx_mode(struct net_device *dev)
  7355. {
  7356. struct tg3 *tp = netdev_priv(dev);
  7357. u32 rx_mode;
  7358. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  7359. RX_MODE_KEEP_VLAN_TAG);
  7360. #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
  7361. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  7362. * flag clear.
  7363. */
  7364. if (!tg3_flag(tp, ENABLE_ASF))
  7365. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  7366. #endif
  7367. if (dev->flags & IFF_PROMISC) {
  7368. /* Promiscuous mode. */
  7369. rx_mode |= RX_MODE_PROMISC;
  7370. } else if (dev->flags & IFF_ALLMULTI) {
  7371. /* Accept all multicast. */
  7372. tg3_set_multi(tp, 1);
  7373. } else if (netdev_mc_empty(dev)) {
  7374. /* Reject all multicast. */
  7375. tg3_set_multi(tp, 0);
  7376. } else {
  7377. /* Accept one or more multicast(s). */
  7378. struct netdev_hw_addr *ha;
  7379. u32 mc_filter[4] = { 0, };
  7380. u32 regidx;
  7381. u32 bit;
  7382. u32 crc;
  7383. netdev_for_each_mc_addr(ha, dev) {
  7384. crc = calc_crc(ha->addr, ETH_ALEN);
  7385. bit = ~crc & 0x7f;
  7386. regidx = (bit & 0x60) >> 5;
  7387. bit &= 0x1f;
  7388. mc_filter[regidx] |= (1 << bit);
  7389. }
  7390. tw32(MAC_HASH_REG_0, mc_filter[0]);
  7391. tw32(MAC_HASH_REG_1, mc_filter[1]);
  7392. tw32(MAC_HASH_REG_2, mc_filter[2]);
  7393. tw32(MAC_HASH_REG_3, mc_filter[3]);
  7394. }
  7395. if (rx_mode != tp->rx_mode) {
  7396. tp->rx_mode = rx_mode;
  7397. tw32_f(MAC_RX_MODE, rx_mode);
  7398. udelay(10);
  7399. }
  7400. }
  7401. static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
  7402. {
  7403. int i;
  7404. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  7405. tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
  7406. }
  7407. static void tg3_rss_check_indir_tbl(struct tg3 *tp)
  7408. {
  7409. int i;
  7410. if (!tg3_flag(tp, SUPPORT_MSIX))
  7411. return;
  7412. if (tp->rxq_cnt == 1) {
  7413. memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
  7414. return;
  7415. }
  7416. /* Validate table against current IRQ count */
  7417. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
  7418. if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
  7419. break;
  7420. }
  7421. if (i != TG3_RSS_INDIR_TBL_SIZE)
  7422. tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
  7423. }
  7424. static void tg3_rss_write_indir_tbl(struct tg3 *tp)
  7425. {
  7426. int i = 0;
  7427. u32 reg = MAC_RSS_INDIR_TBL_0;
  7428. while (i < TG3_RSS_INDIR_TBL_SIZE) {
  7429. u32 val = tp->rss_ind_tbl[i];
  7430. i++;
  7431. for (; i % 8; i++) {
  7432. val <<= 4;
  7433. val |= tp->rss_ind_tbl[i];
  7434. }
  7435. tw32(reg, val);
  7436. reg += 4;
  7437. }
  7438. }
  7439. /* tp->lock is held. */
  7440. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  7441. {
  7442. u32 val, rdmac_mode;
  7443. int i, err, limit;
  7444. struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
  7445. tg3_disable_ints(tp);
  7446. tg3_stop_fw(tp);
  7447. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  7448. if (tg3_flag(tp, INIT_COMPLETE))
  7449. tg3_abort_hw(tp, 1);
  7450. /* Enable MAC control of LPI */
  7451. if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
  7452. val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
  7453. TG3_CPMU_EEE_LNKIDL_UART_IDL;
  7454. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
  7455. val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
  7456. tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
  7457. tw32_f(TG3_CPMU_EEE_CTRL,
  7458. TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
  7459. val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
  7460. TG3_CPMU_EEEMD_LPI_IN_TX |
  7461. TG3_CPMU_EEEMD_LPI_IN_RX |
  7462. TG3_CPMU_EEEMD_EEE_ENABLE;
  7463. if (tg3_asic_rev(tp) != ASIC_REV_5717)
  7464. val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
  7465. if (tg3_flag(tp, ENABLE_APE))
  7466. val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
  7467. tw32_f(TG3_CPMU_EEE_MODE, val);
  7468. tw32_f(TG3_CPMU_EEE_DBTMR1,
  7469. TG3_CPMU_DBTMR1_PCIEXIT_2047US |
  7470. TG3_CPMU_DBTMR1_LNKIDLE_2047US);
  7471. tw32_f(TG3_CPMU_EEE_DBTMR2,
  7472. TG3_CPMU_DBTMR2_APE_TX_2047US |
  7473. TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
  7474. }
  7475. if (reset_phy)
  7476. tg3_phy_reset(tp);
  7477. err = tg3_chip_reset(tp);
  7478. if (err)
  7479. return err;
  7480. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  7481. if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
  7482. val = tr32(TG3_CPMU_CTRL);
  7483. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  7484. tw32(TG3_CPMU_CTRL, val);
  7485. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  7486. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  7487. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  7488. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  7489. val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
  7490. val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
  7491. val |= CPMU_LNK_AWARE_MACCLK_6_25;
  7492. tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
  7493. val = tr32(TG3_CPMU_HST_ACC);
  7494. val &= ~CPMU_HST_ACC_MACCLK_MASK;
  7495. val |= CPMU_HST_ACC_MACCLK_6_25;
  7496. tw32(TG3_CPMU_HST_ACC, val);
  7497. }
  7498. if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  7499. val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
  7500. val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
  7501. PCIE_PWR_MGMT_L1_THRESH_4MS;
  7502. tw32(PCIE_PWR_MGMT_THRESH, val);
  7503. val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
  7504. tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
  7505. tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
  7506. val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
  7507. tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
  7508. }
  7509. if (tg3_flag(tp, L1PLLPD_EN)) {
  7510. u32 grc_mode = tr32(GRC_MODE);
  7511. /* Access the lower 1K of PL PCIE block registers. */
  7512. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  7513. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  7514. val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
  7515. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
  7516. val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
  7517. tw32(GRC_MODE, grc_mode);
  7518. }
  7519. if (tg3_flag(tp, 57765_CLASS)) {
  7520. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
  7521. u32 grc_mode = tr32(GRC_MODE);
  7522. /* Access the lower 1K of PL PCIE block registers. */
  7523. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  7524. tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
  7525. val = tr32(TG3_PCIE_TLDLPL_PORT +
  7526. TG3_PCIE_PL_LO_PHYCTL5);
  7527. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
  7528. val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
  7529. tw32(GRC_MODE, grc_mode);
  7530. }
  7531. if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
  7532. u32 grc_mode;
  7533. /* Fix transmit hangs */
  7534. val = tr32(TG3_CPMU_PADRNG_CTL);
  7535. val |= TG3_CPMU_PADRNG_CTL_RDIV2;
  7536. tw32(TG3_CPMU_PADRNG_CTL, val);
  7537. grc_mode = tr32(GRC_MODE);
  7538. /* Access the lower 1K of DL PCIE block registers. */
  7539. val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
  7540. tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
  7541. val = tr32(TG3_PCIE_TLDLPL_PORT +
  7542. TG3_PCIE_DL_LO_FTSMAX);
  7543. val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
  7544. tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
  7545. val | TG3_PCIE_DL_LO_FTSMAX_VAL);
  7546. tw32(GRC_MODE, grc_mode);
  7547. }
  7548. val = tr32(TG3_CPMU_LSPD_10MB_CLK);
  7549. val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
  7550. val |= CPMU_LSPD_10MB_MACCLK_6_25;
  7551. tw32(TG3_CPMU_LSPD_10MB_CLK, val);
  7552. }
  7553. /* This works around an issue with Athlon chipsets on
  7554. * B3 tigon3 silicon. This bit has no effect on any
  7555. * other revision. But do not set this on PCI Express
  7556. * chips and don't even touch the clocks if the CPMU is present.
  7557. */
  7558. if (!tg3_flag(tp, CPMU_PRESENT)) {
  7559. if (!tg3_flag(tp, PCI_EXPRESS))
  7560. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  7561. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  7562. }
  7563. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
  7564. tg3_flag(tp, PCIX_MODE)) {
  7565. val = tr32(TG3PCI_PCISTATE);
  7566. val |= PCISTATE_RETRY_SAME_DMA;
  7567. tw32(TG3PCI_PCISTATE, val);
  7568. }
  7569. if (tg3_flag(tp, ENABLE_APE)) {
  7570. /* Allow reads and writes to the
  7571. * APE register and memory space.
  7572. */
  7573. val = tr32(TG3PCI_PCISTATE);
  7574. val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  7575. PCISTATE_ALLOW_APE_SHMEM_WR |
  7576. PCISTATE_ALLOW_APE_PSPACE_WR;
  7577. tw32(TG3PCI_PCISTATE, val);
  7578. }
  7579. if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
  7580. /* Enable some hw fixes. */
  7581. val = tr32(TG3PCI_MSI_DATA);
  7582. val |= (1 << 26) | (1 << 28) | (1 << 29);
  7583. tw32(TG3PCI_MSI_DATA, val);
  7584. }
  7585. /* Descriptor ring init may make accesses to the
  7586. * NIC SRAM area to setup the TX descriptors, so we
  7587. * can only do this after the hardware has been
  7588. * successfully reset.
  7589. */
  7590. err = tg3_init_rings(tp);
  7591. if (err)
  7592. return err;
  7593. if (tg3_flag(tp, 57765_PLUS)) {
  7594. val = tr32(TG3PCI_DMA_RW_CTRL) &
  7595. ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  7596. if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
  7597. val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
  7598. if (!tg3_flag(tp, 57765_CLASS) &&
  7599. tg3_asic_rev(tp) != ASIC_REV_5717 &&
  7600. tg3_asic_rev(tp) != ASIC_REV_5762)
  7601. val |= DMA_RWCTRL_TAGGED_STAT_WA;
  7602. tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
  7603. } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
  7604. tg3_asic_rev(tp) != ASIC_REV_5761) {
  7605. /* This value is determined during the probe time DMA
  7606. * engine test, tg3_test_dma.
  7607. */
  7608. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  7609. }
  7610. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  7611. GRC_MODE_4X_NIC_SEND_RINGS |
  7612. GRC_MODE_NO_TX_PHDR_CSUM |
  7613. GRC_MODE_NO_RX_PHDR_CSUM);
  7614. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  7615. /* Pseudo-header checksum is done by hardware logic and not
  7616. * the offload processers, so make the chip do the pseudo-
  7617. * header checksums on receive. For transmit it is more
  7618. * convenient to do the pseudo-header checksum in software
  7619. * as Linux does that on transmit for us in all cases.
  7620. */
  7621. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  7622. val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
  7623. if (tp->rxptpctl)
  7624. tw32(TG3_RX_PTP_CTL,
  7625. tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
  7626. if (tg3_flag(tp, PTP_CAPABLE))
  7627. val |= GRC_MODE_TIME_SYNC_ENABLE;
  7628. tw32(GRC_MODE, tp->grc_mode | val);
  7629. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  7630. val = tr32(GRC_MISC_CFG);
  7631. val &= ~0xff;
  7632. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  7633. tw32(GRC_MISC_CFG, val);
  7634. /* Initialize MBUF/DESC pool. */
  7635. if (tg3_flag(tp, 5750_PLUS)) {
  7636. /* Do nothing. */
  7637. } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
  7638. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  7639. if (tg3_asic_rev(tp) == ASIC_REV_5704)
  7640. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  7641. else
  7642. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  7643. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  7644. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  7645. } else if (tg3_flag(tp, TSO_CAPABLE)) {
  7646. int fw_len;
  7647. fw_len = tp->fw_len;
  7648. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  7649. tw32(BUFMGR_MB_POOL_ADDR,
  7650. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  7651. tw32(BUFMGR_MB_POOL_SIZE,
  7652. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  7653. }
  7654. if (tp->dev->mtu <= ETH_DATA_LEN) {
  7655. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  7656. tp->bufmgr_config.mbuf_read_dma_low_water);
  7657. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  7658. tp->bufmgr_config.mbuf_mac_rx_low_water);
  7659. tw32(BUFMGR_MB_HIGH_WATER,
  7660. tp->bufmgr_config.mbuf_high_water);
  7661. } else {
  7662. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  7663. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  7664. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  7665. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  7666. tw32(BUFMGR_MB_HIGH_WATER,
  7667. tp->bufmgr_config.mbuf_high_water_jumbo);
  7668. }
  7669. tw32(BUFMGR_DMA_LOW_WATER,
  7670. tp->bufmgr_config.dma_low_water);
  7671. tw32(BUFMGR_DMA_HIGH_WATER,
  7672. tp->bufmgr_config.dma_high_water);
  7673. val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
  7674. if (tg3_asic_rev(tp) == ASIC_REV_5719)
  7675. val |= BUFMGR_MODE_NO_TX_UNDERRUN;
  7676. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  7677. tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  7678. tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
  7679. val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
  7680. tw32(BUFMGR_MODE, val);
  7681. for (i = 0; i < 2000; i++) {
  7682. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  7683. break;
  7684. udelay(10);
  7685. }
  7686. if (i >= 2000) {
  7687. netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
  7688. return -ENODEV;
  7689. }
  7690. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
  7691. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  7692. tg3_setup_rxbd_thresholds(tp);
  7693. /* Initialize TG3_BDINFO's at:
  7694. * RCVDBDI_STD_BD: standard eth size rx ring
  7695. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  7696. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  7697. *
  7698. * like so:
  7699. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  7700. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  7701. * ring attribute flags
  7702. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  7703. *
  7704. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  7705. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  7706. *
  7707. * The size of each ring is fixed in the firmware, but the location is
  7708. * configurable.
  7709. */
  7710. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7711. ((u64) tpr->rx_std_mapping >> 32));
  7712. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  7713. ((u64) tpr->rx_std_mapping & 0xffffffff));
  7714. if (!tg3_flag(tp, 5717_PLUS))
  7715. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  7716. NIC_SRAM_RX_BUFFER_DESC);
  7717. /* Disable the mini ring */
  7718. if (!tg3_flag(tp, 5705_PLUS))
  7719. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  7720. BDINFO_FLAGS_DISABLED);
  7721. /* Program the jumbo buffer descriptor ring control
  7722. * blocks on those devices that have them.
  7723. */
  7724. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  7725. (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
  7726. if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
  7727. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7728. ((u64) tpr->rx_jmb_mapping >> 32));
  7729. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  7730. ((u64) tpr->rx_jmb_mapping & 0xffffffff));
  7731. val = TG3_RX_JMB_RING_SIZE(tp) <<
  7732. BDINFO_FLAGS_MAXLEN_SHIFT;
  7733. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  7734. val | BDINFO_FLAGS_USE_EXT_RECV);
  7735. if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
  7736. tg3_flag(tp, 57765_CLASS) ||
  7737. tg3_asic_rev(tp) == ASIC_REV_5762)
  7738. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  7739. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  7740. } else {
  7741. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  7742. BDINFO_FLAGS_DISABLED);
  7743. }
  7744. if (tg3_flag(tp, 57765_PLUS)) {
  7745. val = TG3_RX_STD_RING_SIZE(tp);
  7746. val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
  7747. val |= (TG3_RX_STD_DMA_SZ << 2);
  7748. } else
  7749. val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
  7750. } else
  7751. val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
  7752. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
  7753. tpr->rx_std_prod_idx = tp->rx_pending;
  7754. tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
  7755. tpr->rx_jmb_prod_idx =
  7756. tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
  7757. tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
  7758. tg3_rings_reset(tp);
  7759. /* Initialize MAC address and backoff seed. */
  7760. __tg3_set_mac_addr(tp, 0);
  7761. /* MTU + ethernet header + FCS + optional VLAN tag */
  7762. tw32(MAC_RX_MTU_SIZE,
  7763. tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
  7764. /* The slot time is changed by tg3_setup_phy if we
  7765. * run at gigabit with half duplex.
  7766. */
  7767. val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  7768. (6 << TX_LENGTHS_IPG_SHIFT) |
  7769. (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
  7770. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  7771. tg3_asic_rev(tp) == ASIC_REV_5762)
  7772. val |= tr32(MAC_TX_LENGTHS) &
  7773. (TX_LENGTHS_JMB_FRM_LEN_MSK |
  7774. TX_LENGTHS_CNT_DWN_VAL_MSK);
  7775. tw32(MAC_TX_LENGTHS, val);
  7776. /* Receive rules. */
  7777. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  7778. tw32(RCVLPC_CONFIG, 0x0181);
  7779. /* Calculate RDMAC_MODE setting early, we need it to determine
  7780. * the RCVLPC_STATE_ENABLE mask.
  7781. */
  7782. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  7783. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  7784. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  7785. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  7786. RDMAC_MODE_LNGREAD_ENAB);
  7787. if (tg3_asic_rev(tp) == ASIC_REV_5717)
  7788. rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
  7789. if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
  7790. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  7791. tg3_asic_rev(tp) == ASIC_REV_57780)
  7792. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  7793. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  7794. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  7795. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  7796. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  7797. if (tg3_flag(tp, TSO_CAPABLE) &&
  7798. tg3_asic_rev(tp) == ASIC_REV_5705) {
  7799. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  7800. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  7801. !tg3_flag(tp, IS_5788)) {
  7802. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  7803. }
  7804. }
  7805. if (tg3_flag(tp, PCI_EXPRESS))
  7806. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  7807. if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  7808. tp->dma_limit = 0;
  7809. if (tp->dev->mtu <= ETH_DATA_LEN) {
  7810. rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
  7811. tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
  7812. }
  7813. }
  7814. if (tg3_flag(tp, HW_TSO_1) ||
  7815. tg3_flag(tp, HW_TSO_2) ||
  7816. tg3_flag(tp, HW_TSO_3))
  7817. rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
  7818. if (tg3_flag(tp, 57765_PLUS) ||
  7819. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  7820. tg3_asic_rev(tp) == ASIC_REV_57780)
  7821. rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
  7822. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  7823. tg3_asic_rev(tp) == ASIC_REV_5762)
  7824. rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
  7825. if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
  7826. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  7827. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  7828. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  7829. tg3_flag(tp, 57765_PLUS)) {
  7830. u32 tgtreg;
  7831. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  7832. tgtreg = TG3_RDMA_RSRVCTRL_REG2;
  7833. else
  7834. tgtreg = TG3_RDMA_RSRVCTRL_REG;
  7835. val = tr32(tgtreg);
  7836. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  7837. tg3_asic_rev(tp) == ASIC_REV_5762) {
  7838. val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
  7839. TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
  7840. TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
  7841. val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
  7842. TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
  7843. TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
  7844. }
  7845. tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
  7846. }
  7847. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  7848. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  7849. tg3_asic_rev(tp) == ASIC_REV_5762) {
  7850. u32 tgtreg;
  7851. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  7852. tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
  7853. else
  7854. tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
  7855. val = tr32(tgtreg);
  7856. tw32(tgtreg, val |
  7857. TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
  7858. TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
  7859. }
  7860. /* Receive/send statistics. */
  7861. if (tg3_flag(tp, 5750_PLUS)) {
  7862. val = tr32(RCVLPC_STATS_ENABLE);
  7863. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  7864. tw32(RCVLPC_STATS_ENABLE, val);
  7865. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  7866. tg3_flag(tp, TSO_CAPABLE)) {
  7867. val = tr32(RCVLPC_STATS_ENABLE);
  7868. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  7869. tw32(RCVLPC_STATS_ENABLE, val);
  7870. } else {
  7871. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  7872. }
  7873. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  7874. tw32(SNDDATAI_STATSENAB, 0xffffff);
  7875. tw32(SNDDATAI_STATSCTRL,
  7876. (SNDDATAI_SCTRL_ENABLE |
  7877. SNDDATAI_SCTRL_FASTUPD));
  7878. /* Setup host coalescing engine. */
  7879. tw32(HOSTCC_MODE, 0);
  7880. for (i = 0; i < 2000; i++) {
  7881. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  7882. break;
  7883. udelay(10);
  7884. }
  7885. __tg3_set_coalesce(tp, &tp->coal);
  7886. if (!tg3_flag(tp, 5705_PLUS)) {
  7887. /* Status/statistics block address. See tg3_timer,
  7888. * the tg3_periodic_fetch_stats call there, and
  7889. * tg3_get_stats to see how this works for 5705/5750 chips.
  7890. */
  7891. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  7892. ((u64) tp->stats_mapping >> 32));
  7893. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  7894. ((u64) tp->stats_mapping & 0xffffffff));
  7895. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  7896. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  7897. /* Clear statistics and status block memory areas */
  7898. for (i = NIC_SRAM_STATS_BLK;
  7899. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  7900. i += sizeof(u32)) {
  7901. tg3_write_mem(tp, i, 0);
  7902. udelay(40);
  7903. }
  7904. }
  7905. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  7906. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  7907. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  7908. if (!tg3_flag(tp, 5705_PLUS))
  7909. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  7910. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
  7911. tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
  7912. /* reset to prevent losing 1st rx packet intermittently */
  7913. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  7914. udelay(10);
  7915. }
  7916. tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  7917. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
  7918. MAC_MODE_FHDE_ENABLE;
  7919. if (tg3_flag(tp, ENABLE_APE))
  7920. tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  7921. if (!tg3_flag(tp, 5705_PLUS) &&
  7922. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  7923. tg3_asic_rev(tp) != ASIC_REV_5700)
  7924. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  7925. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  7926. udelay(40);
  7927. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  7928. * If TG3_FLAG_IS_NIC is zero, we should read the
  7929. * register to preserve the GPIO settings for LOMs. The GPIOs,
  7930. * whether used as inputs or outputs, are set by boot code after
  7931. * reset.
  7932. */
  7933. if (!tg3_flag(tp, IS_NIC)) {
  7934. u32 gpio_mask;
  7935. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  7936. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  7937. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  7938. if (tg3_asic_rev(tp) == ASIC_REV_5752)
  7939. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  7940. GRC_LCLCTRL_GPIO_OUTPUT3;
  7941. if (tg3_asic_rev(tp) == ASIC_REV_5755)
  7942. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  7943. tp->grc_local_ctrl &= ~gpio_mask;
  7944. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  7945. /* GPIO1 must be driven high for eeprom write protect */
  7946. if (tg3_flag(tp, EEPROM_WRITE_PROT))
  7947. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  7948. GRC_LCLCTRL_GPIO_OUTPUT1);
  7949. }
  7950. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  7951. udelay(100);
  7952. if (tg3_flag(tp, USING_MSIX)) {
  7953. val = tr32(MSGINT_MODE);
  7954. val |= MSGINT_MODE_ENABLE;
  7955. if (tp->irq_cnt > 1)
  7956. val |= MSGINT_MODE_MULTIVEC_EN;
  7957. if (!tg3_flag(tp, 1SHOT_MSI))
  7958. val |= MSGINT_MODE_ONE_SHOT_DISABLE;
  7959. tw32(MSGINT_MODE, val);
  7960. }
  7961. if (!tg3_flag(tp, 5705_PLUS)) {
  7962. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  7963. udelay(40);
  7964. }
  7965. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  7966. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  7967. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  7968. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  7969. WDMAC_MODE_LNGREAD_ENAB);
  7970. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  7971. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  7972. if (tg3_flag(tp, TSO_CAPABLE) &&
  7973. (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
  7974. tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
  7975. /* nothing */
  7976. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  7977. !tg3_flag(tp, IS_5788)) {
  7978. val |= WDMAC_MODE_RX_ACCEL;
  7979. }
  7980. }
  7981. /* Enable host coalescing bug fix */
  7982. if (tg3_flag(tp, 5755_PLUS))
  7983. val |= WDMAC_MODE_STATUS_TAG_FIX;
  7984. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  7985. val |= WDMAC_MODE_BURST_ALL_DATA;
  7986. tw32_f(WDMAC_MODE, val);
  7987. udelay(40);
  7988. if (tg3_flag(tp, PCIX_MODE)) {
  7989. u16 pcix_cmd;
  7990. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  7991. &pcix_cmd);
  7992. if (tg3_asic_rev(tp) == ASIC_REV_5703) {
  7993. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  7994. pcix_cmd |= PCI_X_CMD_READ_2K;
  7995. } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
  7996. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  7997. pcix_cmd |= PCI_X_CMD_READ_2K;
  7998. }
  7999. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  8000. pcix_cmd);
  8001. }
  8002. tw32_f(RDMAC_MODE, rdmac_mode);
  8003. udelay(40);
  8004. if (tg3_asic_rev(tp) == ASIC_REV_5719) {
  8005. for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
  8006. if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
  8007. break;
  8008. }
  8009. if (i < TG3_NUM_RDMA_CHANNELS) {
  8010. val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
  8011. val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
  8012. tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
  8013. tg3_flag_set(tp, 5719_RDMA_BUG);
  8014. }
  8015. }
  8016. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  8017. if (!tg3_flag(tp, 5705_PLUS))
  8018. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  8019. if (tg3_asic_rev(tp) == ASIC_REV_5761)
  8020. tw32(SNDDATAC_MODE,
  8021. SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
  8022. else
  8023. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  8024. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  8025. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  8026. val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
  8027. if (tg3_flag(tp, LRG_PROD_RING_CAP))
  8028. val |= RCVDBDI_MODE_LRG_RING_SZ;
  8029. tw32(RCVDBDI_MODE, val);
  8030. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  8031. if (tg3_flag(tp, HW_TSO_1) ||
  8032. tg3_flag(tp, HW_TSO_2) ||
  8033. tg3_flag(tp, HW_TSO_3))
  8034. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  8035. val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
  8036. if (tg3_flag(tp, ENABLE_TSS))
  8037. val |= SNDBDI_MODE_MULTI_TXQ_EN;
  8038. tw32(SNDBDI_MODE, val);
  8039. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  8040. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
  8041. err = tg3_load_5701_a0_firmware_fix(tp);
  8042. if (err)
  8043. return err;
  8044. }
  8045. if (tg3_flag(tp, TSO_CAPABLE)) {
  8046. err = tg3_load_tso_firmware(tp);
  8047. if (err)
  8048. return err;
  8049. }
  8050. tp->tx_mode = TX_MODE_ENABLE;
  8051. if (tg3_flag(tp, 5755_PLUS) ||
  8052. tg3_asic_rev(tp) == ASIC_REV_5906)
  8053. tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
  8054. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  8055. tg3_asic_rev(tp) == ASIC_REV_5762) {
  8056. val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
  8057. tp->tx_mode &= ~val;
  8058. tp->tx_mode |= tr32(MAC_TX_MODE) & val;
  8059. }
  8060. tw32_f(MAC_TX_MODE, tp->tx_mode);
  8061. udelay(100);
  8062. if (tg3_flag(tp, ENABLE_RSS)) {
  8063. tg3_rss_write_indir_tbl(tp);
  8064. /* Setup the "secret" hash key. */
  8065. tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
  8066. tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
  8067. tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
  8068. tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
  8069. tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
  8070. tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
  8071. tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
  8072. tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
  8073. tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
  8074. tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
  8075. }
  8076. tp->rx_mode = RX_MODE_ENABLE;
  8077. if (tg3_flag(tp, 5755_PLUS))
  8078. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  8079. if (tg3_flag(tp, ENABLE_RSS))
  8080. tp->rx_mode |= RX_MODE_RSS_ENABLE |
  8081. RX_MODE_RSS_ITBL_HASH_BITS_7 |
  8082. RX_MODE_RSS_IPV6_HASH_EN |
  8083. RX_MODE_RSS_TCP_IPV6_HASH_EN |
  8084. RX_MODE_RSS_IPV4_HASH_EN |
  8085. RX_MODE_RSS_TCP_IPV4_HASH_EN;
  8086. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8087. udelay(10);
  8088. tw32(MAC_LED_CTRL, tp->led_ctrl);
  8089. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  8090. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  8091. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  8092. udelay(10);
  8093. }
  8094. tw32_f(MAC_RX_MODE, tp->rx_mode);
  8095. udelay(10);
  8096. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  8097. if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
  8098. !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
  8099. /* Set drive transmission level to 1.2V */
  8100. /* only if the signal pre-emphasis bit is not set */
  8101. val = tr32(MAC_SERDES_CFG);
  8102. val &= 0xfffff000;
  8103. val |= 0x880;
  8104. tw32(MAC_SERDES_CFG, val);
  8105. }
  8106. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
  8107. tw32(MAC_SERDES_CFG, 0x616000);
  8108. }
  8109. /* Prevent chip from dropping frames when flow control
  8110. * is enabled.
  8111. */
  8112. if (tg3_flag(tp, 57765_CLASS))
  8113. val = 1;
  8114. else
  8115. val = 2;
  8116. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
  8117. if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
  8118. (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  8119. /* Use hardware link auto-negotiation */
  8120. tg3_flag_set(tp, HW_AUTONEG);
  8121. }
  8122. if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  8123. tg3_asic_rev(tp) == ASIC_REV_5714) {
  8124. u32 tmp;
  8125. tmp = tr32(SERDES_RX_CTRL);
  8126. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  8127. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  8128. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  8129. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  8130. }
  8131. if (!tg3_flag(tp, USE_PHYLIB)) {
  8132. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  8133. tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
  8134. err = tg3_setup_phy(tp, 0);
  8135. if (err)
  8136. return err;
  8137. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  8138. !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
  8139. u32 tmp;
  8140. /* Clear CRC stats. */
  8141. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  8142. tg3_writephy(tp, MII_TG3_TEST1,
  8143. tmp | MII_TG3_TEST1_CRC_EN);
  8144. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
  8145. }
  8146. }
  8147. }
  8148. __tg3_set_rx_mode(tp->dev);
  8149. /* Initialize receive rules. */
  8150. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  8151. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  8152. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  8153. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  8154. if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
  8155. limit = 8;
  8156. else
  8157. limit = 16;
  8158. if (tg3_flag(tp, ENABLE_ASF))
  8159. limit -= 4;
  8160. switch (limit) {
  8161. case 16:
  8162. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  8163. case 15:
  8164. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  8165. case 14:
  8166. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  8167. case 13:
  8168. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  8169. case 12:
  8170. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  8171. case 11:
  8172. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  8173. case 10:
  8174. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  8175. case 9:
  8176. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  8177. case 8:
  8178. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  8179. case 7:
  8180. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  8181. case 6:
  8182. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  8183. case 5:
  8184. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  8185. case 4:
  8186. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  8187. case 3:
  8188. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  8189. case 2:
  8190. case 1:
  8191. default:
  8192. break;
  8193. }
  8194. if (tg3_flag(tp, ENABLE_APE))
  8195. /* Write our heartbeat update interval to APE. */
  8196. tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
  8197. APE_HOST_HEARTBEAT_INT_DISABLE);
  8198. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  8199. return 0;
  8200. }
  8201. /* Called at device open time to get the chip ready for
  8202. * packet processing. Invoked with tp->lock held.
  8203. */
  8204. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  8205. {
  8206. tg3_switch_clocks(tp);
  8207. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  8208. return tg3_reset_hw(tp, reset_phy);
  8209. }
  8210. static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
  8211. {
  8212. int i;
  8213. for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
  8214. u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
  8215. tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
  8216. off += len;
  8217. if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
  8218. !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
  8219. memset(ocir, 0, TG3_OCIR_LEN);
  8220. }
  8221. }
  8222. /* sysfs attributes for hwmon */
  8223. static ssize_t tg3_show_temp(struct device *dev,
  8224. struct device_attribute *devattr, char *buf)
  8225. {
  8226. struct pci_dev *pdev = to_pci_dev(dev);
  8227. struct net_device *netdev = pci_get_drvdata(pdev);
  8228. struct tg3 *tp = netdev_priv(netdev);
  8229. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  8230. u32 temperature;
  8231. spin_lock_bh(&tp->lock);
  8232. tg3_ape_scratchpad_read(tp, &temperature, attr->index,
  8233. sizeof(temperature));
  8234. spin_unlock_bh(&tp->lock);
  8235. return sprintf(buf, "%u\n", temperature);
  8236. }
  8237. static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
  8238. TG3_TEMP_SENSOR_OFFSET);
  8239. static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
  8240. TG3_TEMP_CAUTION_OFFSET);
  8241. static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
  8242. TG3_TEMP_MAX_OFFSET);
  8243. static struct attribute *tg3_attributes[] = {
  8244. &sensor_dev_attr_temp1_input.dev_attr.attr,
  8245. &sensor_dev_attr_temp1_crit.dev_attr.attr,
  8246. &sensor_dev_attr_temp1_max.dev_attr.attr,
  8247. NULL
  8248. };
  8249. static const struct attribute_group tg3_group = {
  8250. .attrs = tg3_attributes,
  8251. };
  8252. static void tg3_hwmon_close(struct tg3 *tp)
  8253. {
  8254. if (tp->hwmon_dev) {
  8255. hwmon_device_unregister(tp->hwmon_dev);
  8256. tp->hwmon_dev = NULL;
  8257. sysfs_remove_group(&tp->pdev->dev.kobj, &tg3_group);
  8258. }
  8259. }
  8260. static void tg3_hwmon_open(struct tg3 *tp)
  8261. {
  8262. int i, err;
  8263. u32 size = 0;
  8264. struct pci_dev *pdev = tp->pdev;
  8265. struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
  8266. tg3_sd_scan_scratchpad(tp, ocirs);
  8267. for (i = 0; i < TG3_SD_NUM_RECS; i++) {
  8268. if (!ocirs[i].src_data_length)
  8269. continue;
  8270. size += ocirs[i].src_hdr_length;
  8271. size += ocirs[i].src_data_length;
  8272. }
  8273. if (!size)
  8274. return;
  8275. /* Register hwmon sysfs hooks */
  8276. err = sysfs_create_group(&pdev->dev.kobj, &tg3_group);
  8277. if (err) {
  8278. dev_err(&pdev->dev, "Cannot create sysfs group, aborting\n");
  8279. return;
  8280. }
  8281. tp->hwmon_dev = hwmon_device_register(&pdev->dev);
  8282. if (IS_ERR(tp->hwmon_dev)) {
  8283. tp->hwmon_dev = NULL;
  8284. dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
  8285. sysfs_remove_group(&pdev->dev.kobj, &tg3_group);
  8286. }
  8287. }
  8288. #define TG3_STAT_ADD32(PSTAT, REG) \
  8289. do { u32 __val = tr32(REG); \
  8290. (PSTAT)->low += __val; \
  8291. if ((PSTAT)->low < __val) \
  8292. (PSTAT)->high += 1; \
  8293. } while (0)
  8294. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  8295. {
  8296. struct tg3_hw_stats *sp = tp->hw_stats;
  8297. if (!tp->link_up)
  8298. return;
  8299. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  8300. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  8301. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  8302. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  8303. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  8304. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  8305. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  8306. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  8307. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  8308. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  8309. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  8310. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  8311. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  8312. if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
  8313. (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
  8314. sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
  8315. u32 val;
  8316. val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
  8317. val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
  8318. tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
  8319. tg3_flag_clear(tp, 5719_RDMA_BUG);
  8320. }
  8321. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  8322. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  8323. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  8324. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  8325. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  8326. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  8327. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  8328. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  8329. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  8330. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  8331. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  8332. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  8333. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  8334. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  8335. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  8336. if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
  8337. tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
  8338. tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
  8339. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  8340. } else {
  8341. u32 val = tr32(HOSTCC_FLOW_ATTN);
  8342. val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
  8343. if (val) {
  8344. tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
  8345. sp->rx_discards.low += val;
  8346. if (sp->rx_discards.low < val)
  8347. sp->rx_discards.high += 1;
  8348. }
  8349. sp->mbuf_lwm_thresh_hit = sp->rx_discards;
  8350. }
  8351. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  8352. }
  8353. static void tg3_chk_missed_msi(struct tg3 *tp)
  8354. {
  8355. u32 i;
  8356. for (i = 0; i < tp->irq_cnt; i++) {
  8357. struct tg3_napi *tnapi = &tp->napi[i];
  8358. if (tg3_has_work(tnapi)) {
  8359. if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
  8360. tnapi->last_tx_cons == tnapi->tx_cons) {
  8361. if (tnapi->chk_msi_cnt < 1) {
  8362. tnapi->chk_msi_cnt++;
  8363. return;
  8364. }
  8365. tg3_msi(0, tnapi);
  8366. }
  8367. }
  8368. tnapi->chk_msi_cnt = 0;
  8369. tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
  8370. tnapi->last_tx_cons = tnapi->tx_cons;
  8371. }
  8372. }
  8373. static void tg3_timer(unsigned long __opaque)
  8374. {
  8375. struct tg3 *tp = (struct tg3 *) __opaque;
  8376. if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
  8377. goto restart_timer;
  8378. spin_lock(&tp->lock);
  8379. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  8380. tg3_flag(tp, 57765_CLASS))
  8381. tg3_chk_missed_msi(tp);
  8382. if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
  8383. /* BCM4785: Flush posted writes from GbE to host memory. */
  8384. tr32(HOSTCC_MODE);
  8385. }
  8386. if (!tg3_flag(tp, TAGGED_STATUS)) {
  8387. /* All of this garbage is because when using non-tagged
  8388. * IRQ status the mailbox/status_block protocol the chip
  8389. * uses with the cpu is race prone.
  8390. */
  8391. if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
  8392. tw32(GRC_LOCAL_CTRL,
  8393. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  8394. } else {
  8395. tw32(HOSTCC_MODE, tp->coalesce_mode |
  8396. HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
  8397. }
  8398. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  8399. spin_unlock(&tp->lock);
  8400. tg3_reset_task_schedule(tp);
  8401. goto restart_timer;
  8402. }
  8403. }
  8404. /* This part only runs once per second. */
  8405. if (!--tp->timer_counter) {
  8406. if (tg3_flag(tp, 5705_PLUS))
  8407. tg3_periodic_fetch_stats(tp);
  8408. if (tp->setlpicnt && !--tp->setlpicnt)
  8409. tg3_phy_eee_enable(tp);
  8410. if (tg3_flag(tp, USE_LINKCHG_REG)) {
  8411. u32 mac_stat;
  8412. int phy_event;
  8413. mac_stat = tr32(MAC_STATUS);
  8414. phy_event = 0;
  8415. if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
  8416. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  8417. phy_event = 1;
  8418. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  8419. phy_event = 1;
  8420. if (phy_event)
  8421. tg3_setup_phy(tp, 0);
  8422. } else if (tg3_flag(tp, POLL_SERDES)) {
  8423. u32 mac_stat = tr32(MAC_STATUS);
  8424. int need_setup = 0;
  8425. if (tp->link_up &&
  8426. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  8427. need_setup = 1;
  8428. }
  8429. if (!tp->link_up &&
  8430. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  8431. MAC_STATUS_SIGNAL_DET))) {
  8432. need_setup = 1;
  8433. }
  8434. if (need_setup) {
  8435. if (!tp->serdes_counter) {
  8436. tw32_f(MAC_MODE,
  8437. (tp->mac_mode &
  8438. ~MAC_MODE_PORT_MODE_MASK));
  8439. udelay(40);
  8440. tw32_f(MAC_MODE, tp->mac_mode);
  8441. udelay(40);
  8442. }
  8443. tg3_setup_phy(tp, 0);
  8444. }
  8445. } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
  8446. tg3_flag(tp, 5780_CLASS)) {
  8447. tg3_serdes_parallel_detect(tp);
  8448. }
  8449. tp->timer_counter = tp->timer_multiplier;
  8450. }
  8451. /* Heartbeat is only sent once every 2 seconds.
  8452. *
  8453. * The heartbeat is to tell the ASF firmware that the host
  8454. * driver is still alive. In the event that the OS crashes,
  8455. * ASF needs to reset the hardware to free up the FIFO space
  8456. * that may be filled with rx packets destined for the host.
  8457. * If the FIFO is full, ASF will no longer function properly.
  8458. *
  8459. * Unintended resets have been reported on real time kernels
  8460. * where the timer doesn't run on time. Netpoll will also have
  8461. * same problem.
  8462. *
  8463. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  8464. * to check the ring condition when the heartbeat is expiring
  8465. * before doing the reset. This will prevent most unintended
  8466. * resets.
  8467. */
  8468. if (!--tp->asf_counter) {
  8469. if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
  8470. tg3_wait_for_event_ack(tp);
  8471. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  8472. FWCMD_NICDRV_ALIVE3);
  8473. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  8474. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
  8475. TG3_FW_UPDATE_TIMEOUT_SEC);
  8476. tg3_generate_fw_event(tp);
  8477. }
  8478. tp->asf_counter = tp->asf_multiplier;
  8479. }
  8480. spin_unlock(&tp->lock);
  8481. restart_timer:
  8482. tp->timer.expires = jiffies + tp->timer_offset;
  8483. add_timer(&tp->timer);
  8484. }
  8485. static void tg3_timer_init(struct tg3 *tp)
  8486. {
  8487. if (tg3_flag(tp, TAGGED_STATUS) &&
  8488. tg3_asic_rev(tp) != ASIC_REV_5717 &&
  8489. !tg3_flag(tp, 57765_CLASS))
  8490. tp->timer_offset = HZ;
  8491. else
  8492. tp->timer_offset = HZ / 10;
  8493. BUG_ON(tp->timer_offset > HZ);
  8494. tp->timer_multiplier = (HZ / tp->timer_offset);
  8495. tp->asf_multiplier = (HZ / tp->timer_offset) *
  8496. TG3_FW_UPDATE_FREQ_SEC;
  8497. init_timer(&tp->timer);
  8498. tp->timer.data = (unsigned long) tp;
  8499. tp->timer.function = tg3_timer;
  8500. }
  8501. static void tg3_timer_start(struct tg3 *tp)
  8502. {
  8503. tp->asf_counter = tp->asf_multiplier;
  8504. tp->timer_counter = tp->timer_multiplier;
  8505. tp->timer.expires = jiffies + tp->timer_offset;
  8506. add_timer(&tp->timer);
  8507. }
  8508. static void tg3_timer_stop(struct tg3 *tp)
  8509. {
  8510. del_timer_sync(&tp->timer);
  8511. }
  8512. /* Restart hardware after configuration changes, self-test, etc.
  8513. * Invoked with tp->lock held.
  8514. */
  8515. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  8516. __releases(tp->lock)
  8517. __acquires(tp->lock)
  8518. {
  8519. int err;
  8520. err = tg3_init_hw(tp, reset_phy);
  8521. if (err) {
  8522. netdev_err(tp->dev,
  8523. "Failed to re-initialize device, aborting\n");
  8524. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8525. tg3_full_unlock(tp);
  8526. tg3_timer_stop(tp);
  8527. tp->irq_sync = 0;
  8528. tg3_napi_enable(tp);
  8529. dev_close(tp->dev);
  8530. tg3_full_lock(tp, 0);
  8531. }
  8532. return err;
  8533. }
  8534. static void tg3_reset_task(struct work_struct *work)
  8535. {
  8536. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  8537. int err;
  8538. tg3_full_lock(tp, 0);
  8539. if (!netif_running(tp->dev)) {
  8540. tg3_flag_clear(tp, RESET_TASK_PENDING);
  8541. tg3_full_unlock(tp);
  8542. return;
  8543. }
  8544. tg3_full_unlock(tp);
  8545. tg3_phy_stop(tp);
  8546. tg3_netif_stop(tp);
  8547. tg3_full_lock(tp, 1);
  8548. if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
  8549. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  8550. tp->write32_rx_mbox = tg3_write_flush_reg32;
  8551. tg3_flag_set(tp, MBOX_WRITE_REORDER);
  8552. tg3_flag_clear(tp, TX_RECOVERY_PENDING);
  8553. }
  8554. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  8555. err = tg3_init_hw(tp, 1);
  8556. if (err)
  8557. goto out;
  8558. tg3_netif_start(tp);
  8559. out:
  8560. tg3_full_unlock(tp);
  8561. if (!err)
  8562. tg3_phy_start(tp);
  8563. tg3_flag_clear(tp, RESET_TASK_PENDING);
  8564. }
  8565. static int tg3_request_irq(struct tg3 *tp, int irq_num)
  8566. {
  8567. irq_handler_t fn;
  8568. unsigned long flags;
  8569. char *name;
  8570. struct tg3_napi *tnapi = &tp->napi[irq_num];
  8571. if (tp->irq_cnt == 1)
  8572. name = tp->dev->name;
  8573. else {
  8574. name = &tnapi->irq_lbl[0];
  8575. snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
  8576. name[IFNAMSIZ-1] = 0;
  8577. }
  8578. if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
  8579. fn = tg3_msi;
  8580. if (tg3_flag(tp, 1SHOT_MSI))
  8581. fn = tg3_msi_1shot;
  8582. flags = 0;
  8583. } else {
  8584. fn = tg3_interrupt;
  8585. if (tg3_flag(tp, TAGGED_STATUS))
  8586. fn = tg3_interrupt_tagged;
  8587. flags = IRQF_SHARED;
  8588. }
  8589. return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
  8590. }
  8591. static int tg3_test_interrupt(struct tg3 *tp)
  8592. {
  8593. struct tg3_napi *tnapi = &tp->napi[0];
  8594. struct net_device *dev = tp->dev;
  8595. int err, i, intr_ok = 0;
  8596. u32 val;
  8597. if (!netif_running(dev))
  8598. return -ENODEV;
  8599. tg3_disable_ints(tp);
  8600. free_irq(tnapi->irq_vec, tnapi);
  8601. /*
  8602. * Turn off MSI one shot mode. Otherwise this test has no
  8603. * observable way to know whether the interrupt was delivered.
  8604. */
  8605. if (tg3_flag(tp, 57765_PLUS)) {
  8606. val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
  8607. tw32(MSGINT_MODE, val);
  8608. }
  8609. err = request_irq(tnapi->irq_vec, tg3_test_isr,
  8610. IRQF_SHARED, dev->name, tnapi);
  8611. if (err)
  8612. return err;
  8613. tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
  8614. tg3_enable_ints(tp);
  8615. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  8616. tnapi->coal_now);
  8617. for (i = 0; i < 5; i++) {
  8618. u32 int_mbox, misc_host_ctrl;
  8619. int_mbox = tr32_mailbox(tnapi->int_mbox);
  8620. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  8621. if ((int_mbox != 0) ||
  8622. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  8623. intr_ok = 1;
  8624. break;
  8625. }
  8626. if (tg3_flag(tp, 57765_PLUS) &&
  8627. tnapi->hw_status->status_tag != tnapi->last_tag)
  8628. tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
  8629. msleep(10);
  8630. }
  8631. tg3_disable_ints(tp);
  8632. free_irq(tnapi->irq_vec, tnapi);
  8633. err = tg3_request_irq(tp, 0);
  8634. if (err)
  8635. return err;
  8636. if (intr_ok) {
  8637. /* Reenable MSI one shot mode. */
  8638. if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
  8639. val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
  8640. tw32(MSGINT_MODE, val);
  8641. }
  8642. return 0;
  8643. }
  8644. return -EIO;
  8645. }
  8646. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  8647. * successfully restored
  8648. */
  8649. static int tg3_test_msi(struct tg3 *tp)
  8650. {
  8651. int err;
  8652. u16 pci_cmd;
  8653. if (!tg3_flag(tp, USING_MSI))
  8654. return 0;
  8655. /* Turn off SERR reporting in case MSI terminates with Master
  8656. * Abort.
  8657. */
  8658. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  8659. pci_write_config_word(tp->pdev, PCI_COMMAND,
  8660. pci_cmd & ~PCI_COMMAND_SERR);
  8661. err = tg3_test_interrupt(tp);
  8662. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  8663. if (!err)
  8664. return 0;
  8665. /* other failures */
  8666. if (err != -EIO)
  8667. return err;
  8668. /* MSI test failed, go back to INTx mode */
  8669. netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
  8670. "to INTx mode. Please report this failure to the PCI "
  8671. "maintainer and include system chipset information\n");
  8672. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  8673. pci_disable_msi(tp->pdev);
  8674. tg3_flag_clear(tp, USING_MSI);
  8675. tp->napi[0].irq_vec = tp->pdev->irq;
  8676. err = tg3_request_irq(tp, 0);
  8677. if (err)
  8678. return err;
  8679. /* Need to reset the chip because the MSI cycle may have terminated
  8680. * with Master Abort.
  8681. */
  8682. tg3_full_lock(tp, 1);
  8683. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8684. err = tg3_init_hw(tp, 1);
  8685. tg3_full_unlock(tp);
  8686. if (err)
  8687. free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
  8688. return err;
  8689. }
  8690. static int tg3_request_firmware(struct tg3 *tp)
  8691. {
  8692. const __be32 *fw_data;
  8693. if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
  8694. netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
  8695. tp->fw_needed);
  8696. return -ENOENT;
  8697. }
  8698. fw_data = (void *)tp->fw->data;
  8699. /* Firmware blob starts with version numbers, followed by
  8700. * start address and _full_ length including BSS sections
  8701. * (which must be longer than the actual data, of course
  8702. */
  8703. tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
  8704. if (tp->fw_len < (tp->fw->size - 12)) {
  8705. netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
  8706. tp->fw_len, tp->fw_needed);
  8707. release_firmware(tp->fw);
  8708. tp->fw = NULL;
  8709. return -EINVAL;
  8710. }
  8711. /* We no longer need firmware; we have it. */
  8712. tp->fw_needed = NULL;
  8713. return 0;
  8714. }
  8715. static u32 tg3_irq_count(struct tg3 *tp)
  8716. {
  8717. u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
  8718. if (irq_cnt > 1) {
  8719. /* We want as many rx rings enabled as there are cpus.
  8720. * In multiqueue MSI-X mode, the first MSI-X vector
  8721. * only deals with link interrupts, etc, so we add
  8722. * one to the number of vectors we are requesting.
  8723. */
  8724. irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
  8725. }
  8726. return irq_cnt;
  8727. }
  8728. static bool tg3_enable_msix(struct tg3 *tp)
  8729. {
  8730. int i, rc;
  8731. struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
  8732. tp->txq_cnt = tp->txq_req;
  8733. tp->rxq_cnt = tp->rxq_req;
  8734. if (!tp->rxq_cnt)
  8735. tp->rxq_cnt = netif_get_num_default_rss_queues();
  8736. if (tp->rxq_cnt > tp->rxq_max)
  8737. tp->rxq_cnt = tp->rxq_max;
  8738. /* Disable multiple TX rings by default. Simple round-robin hardware
  8739. * scheduling of the TX rings can cause starvation of rings with
  8740. * small packets when other rings have TSO or jumbo packets.
  8741. */
  8742. if (!tp->txq_req)
  8743. tp->txq_cnt = 1;
  8744. tp->irq_cnt = tg3_irq_count(tp);
  8745. for (i = 0; i < tp->irq_max; i++) {
  8746. msix_ent[i].entry = i;
  8747. msix_ent[i].vector = 0;
  8748. }
  8749. rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
  8750. if (rc < 0) {
  8751. return false;
  8752. } else if (rc != 0) {
  8753. if (pci_enable_msix(tp->pdev, msix_ent, rc))
  8754. return false;
  8755. netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
  8756. tp->irq_cnt, rc);
  8757. tp->irq_cnt = rc;
  8758. tp->rxq_cnt = max(rc - 1, 1);
  8759. if (tp->txq_cnt)
  8760. tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
  8761. }
  8762. for (i = 0; i < tp->irq_max; i++)
  8763. tp->napi[i].irq_vec = msix_ent[i].vector;
  8764. if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
  8765. pci_disable_msix(tp->pdev);
  8766. return false;
  8767. }
  8768. if (tp->irq_cnt == 1)
  8769. return true;
  8770. tg3_flag_set(tp, ENABLE_RSS);
  8771. if (tp->txq_cnt > 1)
  8772. tg3_flag_set(tp, ENABLE_TSS);
  8773. netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
  8774. return true;
  8775. }
  8776. static void tg3_ints_init(struct tg3 *tp)
  8777. {
  8778. if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
  8779. !tg3_flag(tp, TAGGED_STATUS)) {
  8780. /* All MSI supporting chips should support tagged
  8781. * status. Assert that this is the case.
  8782. */
  8783. netdev_warn(tp->dev,
  8784. "MSI without TAGGED_STATUS? Not using MSI\n");
  8785. goto defcfg;
  8786. }
  8787. if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
  8788. tg3_flag_set(tp, USING_MSIX);
  8789. else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
  8790. tg3_flag_set(tp, USING_MSI);
  8791. if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
  8792. u32 msi_mode = tr32(MSGINT_MODE);
  8793. if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
  8794. msi_mode |= MSGINT_MODE_MULTIVEC_EN;
  8795. if (!tg3_flag(tp, 1SHOT_MSI))
  8796. msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
  8797. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  8798. }
  8799. defcfg:
  8800. if (!tg3_flag(tp, USING_MSIX)) {
  8801. tp->irq_cnt = 1;
  8802. tp->napi[0].irq_vec = tp->pdev->irq;
  8803. }
  8804. if (tp->irq_cnt == 1) {
  8805. tp->txq_cnt = 1;
  8806. tp->rxq_cnt = 1;
  8807. netif_set_real_num_tx_queues(tp->dev, 1);
  8808. netif_set_real_num_rx_queues(tp->dev, 1);
  8809. }
  8810. }
  8811. static void tg3_ints_fini(struct tg3 *tp)
  8812. {
  8813. if (tg3_flag(tp, USING_MSIX))
  8814. pci_disable_msix(tp->pdev);
  8815. else if (tg3_flag(tp, USING_MSI))
  8816. pci_disable_msi(tp->pdev);
  8817. tg3_flag_clear(tp, USING_MSI);
  8818. tg3_flag_clear(tp, USING_MSIX);
  8819. tg3_flag_clear(tp, ENABLE_RSS);
  8820. tg3_flag_clear(tp, ENABLE_TSS);
  8821. }
  8822. static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
  8823. bool init)
  8824. {
  8825. struct net_device *dev = tp->dev;
  8826. int i, err;
  8827. /*
  8828. * Setup interrupts first so we know how
  8829. * many NAPI resources to allocate
  8830. */
  8831. tg3_ints_init(tp);
  8832. tg3_rss_check_indir_tbl(tp);
  8833. /* The placement of this call is tied
  8834. * to the setup and use of Host TX descriptors.
  8835. */
  8836. err = tg3_alloc_consistent(tp);
  8837. if (err)
  8838. goto err_out1;
  8839. tg3_napi_init(tp);
  8840. tg3_napi_enable(tp);
  8841. for (i = 0; i < tp->irq_cnt; i++) {
  8842. struct tg3_napi *tnapi = &tp->napi[i];
  8843. err = tg3_request_irq(tp, i);
  8844. if (err) {
  8845. for (i--; i >= 0; i--) {
  8846. tnapi = &tp->napi[i];
  8847. free_irq(tnapi->irq_vec, tnapi);
  8848. }
  8849. goto err_out2;
  8850. }
  8851. }
  8852. tg3_full_lock(tp, 0);
  8853. err = tg3_init_hw(tp, reset_phy);
  8854. if (err) {
  8855. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8856. tg3_free_rings(tp);
  8857. }
  8858. tg3_full_unlock(tp);
  8859. if (err)
  8860. goto err_out3;
  8861. if (test_irq && tg3_flag(tp, USING_MSI)) {
  8862. err = tg3_test_msi(tp);
  8863. if (err) {
  8864. tg3_full_lock(tp, 0);
  8865. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8866. tg3_free_rings(tp);
  8867. tg3_full_unlock(tp);
  8868. goto err_out2;
  8869. }
  8870. if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
  8871. u32 val = tr32(PCIE_TRANSACTION_CFG);
  8872. tw32(PCIE_TRANSACTION_CFG,
  8873. val | PCIE_TRANS_CFG_1SHOT_MSI);
  8874. }
  8875. }
  8876. tg3_phy_start(tp);
  8877. tg3_hwmon_open(tp);
  8878. tg3_full_lock(tp, 0);
  8879. tg3_timer_start(tp);
  8880. tg3_flag_set(tp, INIT_COMPLETE);
  8881. tg3_enable_ints(tp);
  8882. if (init)
  8883. tg3_ptp_init(tp);
  8884. else
  8885. tg3_ptp_resume(tp);
  8886. tg3_full_unlock(tp);
  8887. netif_tx_start_all_queues(dev);
  8888. /*
  8889. * Reset loopback feature if it was turned on while the device was down
  8890. * make sure that it's installed properly now.
  8891. */
  8892. if (dev->features & NETIF_F_LOOPBACK)
  8893. tg3_set_loopback(dev, dev->features);
  8894. return 0;
  8895. err_out3:
  8896. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  8897. struct tg3_napi *tnapi = &tp->napi[i];
  8898. free_irq(tnapi->irq_vec, tnapi);
  8899. }
  8900. err_out2:
  8901. tg3_napi_disable(tp);
  8902. tg3_napi_fini(tp);
  8903. tg3_free_consistent(tp);
  8904. err_out1:
  8905. tg3_ints_fini(tp);
  8906. return err;
  8907. }
  8908. static void tg3_stop(struct tg3 *tp)
  8909. {
  8910. int i;
  8911. tg3_reset_task_cancel(tp);
  8912. tg3_netif_stop(tp);
  8913. tg3_timer_stop(tp);
  8914. tg3_hwmon_close(tp);
  8915. tg3_phy_stop(tp);
  8916. tg3_full_lock(tp, 1);
  8917. tg3_disable_ints(tp);
  8918. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  8919. tg3_free_rings(tp);
  8920. tg3_flag_clear(tp, INIT_COMPLETE);
  8921. tg3_full_unlock(tp);
  8922. for (i = tp->irq_cnt - 1; i >= 0; i--) {
  8923. struct tg3_napi *tnapi = &tp->napi[i];
  8924. free_irq(tnapi->irq_vec, tnapi);
  8925. }
  8926. tg3_ints_fini(tp);
  8927. tg3_napi_fini(tp);
  8928. tg3_free_consistent(tp);
  8929. }
  8930. static int tg3_open(struct net_device *dev)
  8931. {
  8932. struct tg3 *tp = netdev_priv(dev);
  8933. int err;
  8934. if (tp->fw_needed) {
  8935. err = tg3_request_firmware(tp);
  8936. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
  8937. if (err)
  8938. return err;
  8939. } else if (err) {
  8940. netdev_warn(tp->dev, "TSO capability disabled\n");
  8941. tg3_flag_clear(tp, TSO_CAPABLE);
  8942. } else if (!tg3_flag(tp, TSO_CAPABLE)) {
  8943. netdev_notice(tp->dev, "TSO capability restored\n");
  8944. tg3_flag_set(tp, TSO_CAPABLE);
  8945. }
  8946. }
  8947. tg3_carrier_off(tp);
  8948. err = tg3_power_up(tp);
  8949. if (err)
  8950. return err;
  8951. tg3_full_lock(tp, 0);
  8952. tg3_disable_ints(tp);
  8953. tg3_flag_clear(tp, INIT_COMPLETE);
  8954. tg3_full_unlock(tp);
  8955. err = tg3_start(tp, true, true, true);
  8956. if (err) {
  8957. tg3_frob_aux_power(tp, false);
  8958. pci_set_power_state(tp->pdev, PCI_D3hot);
  8959. }
  8960. if (tg3_flag(tp, PTP_CAPABLE)) {
  8961. tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
  8962. &tp->pdev->dev);
  8963. if (IS_ERR(tp->ptp_clock))
  8964. tp->ptp_clock = NULL;
  8965. }
  8966. return err;
  8967. }
  8968. static int tg3_close(struct net_device *dev)
  8969. {
  8970. struct tg3 *tp = netdev_priv(dev);
  8971. tg3_ptp_fini(tp);
  8972. tg3_stop(tp);
  8973. /* Clear stats across close / open calls */
  8974. memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
  8975. memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
  8976. tg3_power_down(tp);
  8977. tg3_carrier_off(tp);
  8978. return 0;
  8979. }
  8980. static inline u64 get_stat64(tg3_stat64_t *val)
  8981. {
  8982. return ((u64)val->high << 32) | ((u64)val->low);
  8983. }
  8984. static u64 tg3_calc_crc_errors(struct tg3 *tp)
  8985. {
  8986. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  8987. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  8988. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  8989. tg3_asic_rev(tp) == ASIC_REV_5701)) {
  8990. u32 val;
  8991. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  8992. tg3_writephy(tp, MII_TG3_TEST1,
  8993. val | MII_TG3_TEST1_CRC_EN);
  8994. tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
  8995. } else
  8996. val = 0;
  8997. tp->phy_crc_errors += val;
  8998. return tp->phy_crc_errors;
  8999. }
  9000. return get_stat64(&hw_stats->rx_fcs_errors);
  9001. }
  9002. #define ESTAT_ADD(member) \
  9003. estats->member = old_estats->member + \
  9004. get_stat64(&hw_stats->member)
  9005. static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
  9006. {
  9007. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  9008. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  9009. ESTAT_ADD(rx_octets);
  9010. ESTAT_ADD(rx_fragments);
  9011. ESTAT_ADD(rx_ucast_packets);
  9012. ESTAT_ADD(rx_mcast_packets);
  9013. ESTAT_ADD(rx_bcast_packets);
  9014. ESTAT_ADD(rx_fcs_errors);
  9015. ESTAT_ADD(rx_align_errors);
  9016. ESTAT_ADD(rx_xon_pause_rcvd);
  9017. ESTAT_ADD(rx_xoff_pause_rcvd);
  9018. ESTAT_ADD(rx_mac_ctrl_rcvd);
  9019. ESTAT_ADD(rx_xoff_entered);
  9020. ESTAT_ADD(rx_frame_too_long_errors);
  9021. ESTAT_ADD(rx_jabbers);
  9022. ESTAT_ADD(rx_undersize_packets);
  9023. ESTAT_ADD(rx_in_length_errors);
  9024. ESTAT_ADD(rx_out_length_errors);
  9025. ESTAT_ADD(rx_64_or_less_octet_packets);
  9026. ESTAT_ADD(rx_65_to_127_octet_packets);
  9027. ESTAT_ADD(rx_128_to_255_octet_packets);
  9028. ESTAT_ADD(rx_256_to_511_octet_packets);
  9029. ESTAT_ADD(rx_512_to_1023_octet_packets);
  9030. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  9031. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  9032. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  9033. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  9034. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  9035. ESTAT_ADD(tx_octets);
  9036. ESTAT_ADD(tx_collisions);
  9037. ESTAT_ADD(tx_xon_sent);
  9038. ESTAT_ADD(tx_xoff_sent);
  9039. ESTAT_ADD(tx_flow_control);
  9040. ESTAT_ADD(tx_mac_errors);
  9041. ESTAT_ADD(tx_single_collisions);
  9042. ESTAT_ADD(tx_mult_collisions);
  9043. ESTAT_ADD(tx_deferred);
  9044. ESTAT_ADD(tx_excessive_collisions);
  9045. ESTAT_ADD(tx_late_collisions);
  9046. ESTAT_ADD(tx_collide_2times);
  9047. ESTAT_ADD(tx_collide_3times);
  9048. ESTAT_ADD(tx_collide_4times);
  9049. ESTAT_ADD(tx_collide_5times);
  9050. ESTAT_ADD(tx_collide_6times);
  9051. ESTAT_ADD(tx_collide_7times);
  9052. ESTAT_ADD(tx_collide_8times);
  9053. ESTAT_ADD(tx_collide_9times);
  9054. ESTAT_ADD(tx_collide_10times);
  9055. ESTAT_ADD(tx_collide_11times);
  9056. ESTAT_ADD(tx_collide_12times);
  9057. ESTAT_ADD(tx_collide_13times);
  9058. ESTAT_ADD(tx_collide_14times);
  9059. ESTAT_ADD(tx_collide_15times);
  9060. ESTAT_ADD(tx_ucast_packets);
  9061. ESTAT_ADD(tx_mcast_packets);
  9062. ESTAT_ADD(tx_bcast_packets);
  9063. ESTAT_ADD(tx_carrier_sense_errors);
  9064. ESTAT_ADD(tx_discards);
  9065. ESTAT_ADD(tx_errors);
  9066. ESTAT_ADD(dma_writeq_full);
  9067. ESTAT_ADD(dma_write_prioq_full);
  9068. ESTAT_ADD(rxbds_empty);
  9069. ESTAT_ADD(rx_discards);
  9070. ESTAT_ADD(rx_errors);
  9071. ESTAT_ADD(rx_threshold_hit);
  9072. ESTAT_ADD(dma_readq_full);
  9073. ESTAT_ADD(dma_read_prioq_full);
  9074. ESTAT_ADD(tx_comp_queue_full);
  9075. ESTAT_ADD(ring_set_send_prod_index);
  9076. ESTAT_ADD(ring_status_update);
  9077. ESTAT_ADD(nic_irqs);
  9078. ESTAT_ADD(nic_avoided_irqs);
  9079. ESTAT_ADD(nic_tx_threshold_hit);
  9080. ESTAT_ADD(mbuf_lwm_thresh_hit);
  9081. }
  9082. static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
  9083. {
  9084. struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
  9085. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  9086. stats->rx_packets = old_stats->rx_packets +
  9087. get_stat64(&hw_stats->rx_ucast_packets) +
  9088. get_stat64(&hw_stats->rx_mcast_packets) +
  9089. get_stat64(&hw_stats->rx_bcast_packets);
  9090. stats->tx_packets = old_stats->tx_packets +
  9091. get_stat64(&hw_stats->tx_ucast_packets) +
  9092. get_stat64(&hw_stats->tx_mcast_packets) +
  9093. get_stat64(&hw_stats->tx_bcast_packets);
  9094. stats->rx_bytes = old_stats->rx_bytes +
  9095. get_stat64(&hw_stats->rx_octets);
  9096. stats->tx_bytes = old_stats->tx_bytes +
  9097. get_stat64(&hw_stats->tx_octets);
  9098. stats->rx_errors = old_stats->rx_errors +
  9099. get_stat64(&hw_stats->rx_errors);
  9100. stats->tx_errors = old_stats->tx_errors +
  9101. get_stat64(&hw_stats->tx_errors) +
  9102. get_stat64(&hw_stats->tx_mac_errors) +
  9103. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  9104. get_stat64(&hw_stats->tx_discards);
  9105. stats->multicast = old_stats->multicast +
  9106. get_stat64(&hw_stats->rx_mcast_packets);
  9107. stats->collisions = old_stats->collisions +
  9108. get_stat64(&hw_stats->tx_collisions);
  9109. stats->rx_length_errors = old_stats->rx_length_errors +
  9110. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  9111. get_stat64(&hw_stats->rx_undersize_packets);
  9112. stats->rx_over_errors = old_stats->rx_over_errors +
  9113. get_stat64(&hw_stats->rxbds_empty);
  9114. stats->rx_frame_errors = old_stats->rx_frame_errors +
  9115. get_stat64(&hw_stats->rx_align_errors);
  9116. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  9117. get_stat64(&hw_stats->tx_discards);
  9118. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  9119. get_stat64(&hw_stats->tx_carrier_sense_errors);
  9120. stats->rx_crc_errors = old_stats->rx_crc_errors +
  9121. tg3_calc_crc_errors(tp);
  9122. stats->rx_missed_errors = old_stats->rx_missed_errors +
  9123. get_stat64(&hw_stats->rx_discards);
  9124. stats->rx_dropped = tp->rx_dropped;
  9125. stats->tx_dropped = tp->tx_dropped;
  9126. }
  9127. static int tg3_get_regs_len(struct net_device *dev)
  9128. {
  9129. return TG3_REG_BLK_SIZE;
  9130. }
  9131. static void tg3_get_regs(struct net_device *dev,
  9132. struct ethtool_regs *regs, void *_p)
  9133. {
  9134. struct tg3 *tp = netdev_priv(dev);
  9135. regs->version = 0;
  9136. memset(_p, 0, TG3_REG_BLK_SIZE);
  9137. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9138. return;
  9139. tg3_full_lock(tp, 0);
  9140. tg3_dump_legacy_regs(tp, (u32 *)_p);
  9141. tg3_full_unlock(tp);
  9142. }
  9143. static int tg3_get_eeprom_len(struct net_device *dev)
  9144. {
  9145. struct tg3 *tp = netdev_priv(dev);
  9146. return tp->nvram_size;
  9147. }
  9148. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  9149. {
  9150. struct tg3 *tp = netdev_priv(dev);
  9151. int ret;
  9152. u8 *pd;
  9153. u32 i, offset, len, b_offset, b_count;
  9154. __be32 val;
  9155. if (tg3_flag(tp, NO_NVRAM))
  9156. return -EINVAL;
  9157. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9158. return -EAGAIN;
  9159. offset = eeprom->offset;
  9160. len = eeprom->len;
  9161. eeprom->len = 0;
  9162. eeprom->magic = TG3_EEPROM_MAGIC;
  9163. if (offset & 3) {
  9164. /* adjustments to start on required 4 byte boundary */
  9165. b_offset = offset & 3;
  9166. b_count = 4 - b_offset;
  9167. if (b_count > len) {
  9168. /* i.e. offset=1 len=2 */
  9169. b_count = len;
  9170. }
  9171. ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
  9172. if (ret)
  9173. return ret;
  9174. memcpy(data, ((char *)&val) + b_offset, b_count);
  9175. len -= b_count;
  9176. offset += b_count;
  9177. eeprom->len += b_count;
  9178. }
  9179. /* read bytes up to the last 4 byte boundary */
  9180. pd = &data[eeprom->len];
  9181. for (i = 0; i < (len - (len & 3)); i += 4) {
  9182. ret = tg3_nvram_read_be32(tp, offset + i, &val);
  9183. if (ret) {
  9184. eeprom->len += i;
  9185. return ret;
  9186. }
  9187. memcpy(pd + i, &val, 4);
  9188. }
  9189. eeprom->len += i;
  9190. if (len & 3) {
  9191. /* read last bytes not ending on 4 byte boundary */
  9192. pd = &data[eeprom->len];
  9193. b_count = len & 3;
  9194. b_offset = offset + len - b_count;
  9195. ret = tg3_nvram_read_be32(tp, b_offset, &val);
  9196. if (ret)
  9197. return ret;
  9198. memcpy(pd, &val, b_count);
  9199. eeprom->len += b_count;
  9200. }
  9201. return 0;
  9202. }
  9203. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  9204. {
  9205. struct tg3 *tp = netdev_priv(dev);
  9206. int ret;
  9207. u32 offset, len, b_offset, odd_len;
  9208. u8 *buf;
  9209. __be32 start, end;
  9210. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  9211. return -EAGAIN;
  9212. if (tg3_flag(tp, NO_NVRAM) ||
  9213. eeprom->magic != TG3_EEPROM_MAGIC)
  9214. return -EINVAL;
  9215. offset = eeprom->offset;
  9216. len = eeprom->len;
  9217. if ((b_offset = (offset & 3))) {
  9218. /* adjustments to start on required 4 byte boundary */
  9219. ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
  9220. if (ret)
  9221. return ret;
  9222. len += b_offset;
  9223. offset &= ~3;
  9224. if (len < 4)
  9225. len = 4;
  9226. }
  9227. odd_len = 0;
  9228. if (len & 3) {
  9229. /* adjustments to end on required 4 byte boundary */
  9230. odd_len = 1;
  9231. len = (len + 3) & ~3;
  9232. ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
  9233. if (ret)
  9234. return ret;
  9235. }
  9236. buf = data;
  9237. if (b_offset || odd_len) {
  9238. buf = kmalloc(len, GFP_KERNEL);
  9239. if (!buf)
  9240. return -ENOMEM;
  9241. if (b_offset)
  9242. memcpy(buf, &start, 4);
  9243. if (odd_len)
  9244. memcpy(buf+len-4, &end, 4);
  9245. memcpy(buf + b_offset, data, eeprom->len);
  9246. }
  9247. ret = tg3_nvram_write_block(tp, offset, len, buf);
  9248. if (buf != data)
  9249. kfree(buf);
  9250. return ret;
  9251. }
  9252. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  9253. {
  9254. struct tg3 *tp = netdev_priv(dev);
  9255. if (tg3_flag(tp, USE_PHYLIB)) {
  9256. struct phy_device *phydev;
  9257. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9258. return -EAGAIN;
  9259. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9260. return phy_ethtool_gset(phydev, cmd);
  9261. }
  9262. cmd->supported = (SUPPORTED_Autoneg);
  9263. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  9264. cmd->supported |= (SUPPORTED_1000baseT_Half |
  9265. SUPPORTED_1000baseT_Full);
  9266. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  9267. cmd->supported |= (SUPPORTED_100baseT_Half |
  9268. SUPPORTED_100baseT_Full |
  9269. SUPPORTED_10baseT_Half |
  9270. SUPPORTED_10baseT_Full |
  9271. SUPPORTED_TP);
  9272. cmd->port = PORT_TP;
  9273. } else {
  9274. cmd->supported |= SUPPORTED_FIBRE;
  9275. cmd->port = PORT_FIBRE;
  9276. }
  9277. cmd->advertising = tp->link_config.advertising;
  9278. if (tg3_flag(tp, PAUSE_AUTONEG)) {
  9279. if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
  9280. if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
  9281. cmd->advertising |= ADVERTISED_Pause;
  9282. } else {
  9283. cmd->advertising |= ADVERTISED_Pause |
  9284. ADVERTISED_Asym_Pause;
  9285. }
  9286. } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
  9287. cmd->advertising |= ADVERTISED_Asym_Pause;
  9288. }
  9289. }
  9290. if (netif_running(dev) && tp->link_up) {
  9291. ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
  9292. cmd->duplex = tp->link_config.active_duplex;
  9293. cmd->lp_advertising = tp->link_config.rmt_adv;
  9294. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
  9295. if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
  9296. cmd->eth_tp_mdix = ETH_TP_MDI_X;
  9297. else
  9298. cmd->eth_tp_mdix = ETH_TP_MDI;
  9299. }
  9300. } else {
  9301. ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
  9302. cmd->duplex = DUPLEX_UNKNOWN;
  9303. cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
  9304. }
  9305. cmd->phy_address = tp->phy_addr;
  9306. cmd->transceiver = XCVR_INTERNAL;
  9307. cmd->autoneg = tp->link_config.autoneg;
  9308. cmd->maxtxpkt = 0;
  9309. cmd->maxrxpkt = 0;
  9310. return 0;
  9311. }
  9312. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  9313. {
  9314. struct tg3 *tp = netdev_priv(dev);
  9315. u32 speed = ethtool_cmd_speed(cmd);
  9316. if (tg3_flag(tp, USE_PHYLIB)) {
  9317. struct phy_device *phydev;
  9318. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9319. return -EAGAIN;
  9320. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9321. return phy_ethtool_sset(phydev, cmd);
  9322. }
  9323. if (cmd->autoneg != AUTONEG_ENABLE &&
  9324. cmd->autoneg != AUTONEG_DISABLE)
  9325. return -EINVAL;
  9326. if (cmd->autoneg == AUTONEG_DISABLE &&
  9327. cmd->duplex != DUPLEX_FULL &&
  9328. cmd->duplex != DUPLEX_HALF)
  9329. return -EINVAL;
  9330. if (cmd->autoneg == AUTONEG_ENABLE) {
  9331. u32 mask = ADVERTISED_Autoneg |
  9332. ADVERTISED_Pause |
  9333. ADVERTISED_Asym_Pause;
  9334. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  9335. mask |= ADVERTISED_1000baseT_Half |
  9336. ADVERTISED_1000baseT_Full;
  9337. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  9338. mask |= ADVERTISED_100baseT_Half |
  9339. ADVERTISED_100baseT_Full |
  9340. ADVERTISED_10baseT_Half |
  9341. ADVERTISED_10baseT_Full |
  9342. ADVERTISED_TP;
  9343. else
  9344. mask |= ADVERTISED_FIBRE;
  9345. if (cmd->advertising & ~mask)
  9346. return -EINVAL;
  9347. mask &= (ADVERTISED_1000baseT_Half |
  9348. ADVERTISED_1000baseT_Full |
  9349. ADVERTISED_100baseT_Half |
  9350. ADVERTISED_100baseT_Full |
  9351. ADVERTISED_10baseT_Half |
  9352. ADVERTISED_10baseT_Full);
  9353. cmd->advertising &= mask;
  9354. } else {
  9355. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
  9356. if (speed != SPEED_1000)
  9357. return -EINVAL;
  9358. if (cmd->duplex != DUPLEX_FULL)
  9359. return -EINVAL;
  9360. } else {
  9361. if (speed != SPEED_100 &&
  9362. speed != SPEED_10)
  9363. return -EINVAL;
  9364. }
  9365. }
  9366. tg3_full_lock(tp, 0);
  9367. tp->link_config.autoneg = cmd->autoneg;
  9368. if (cmd->autoneg == AUTONEG_ENABLE) {
  9369. tp->link_config.advertising = (cmd->advertising |
  9370. ADVERTISED_Autoneg);
  9371. tp->link_config.speed = SPEED_UNKNOWN;
  9372. tp->link_config.duplex = DUPLEX_UNKNOWN;
  9373. } else {
  9374. tp->link_config.advertising = 0;
  9375. tp->link_config.speed = speed;
  9376. tp->link_config.duplex = cmd->duplex;
  9377. }
  9378. if (netif_running(dev))
  9379. tg3_setup_phy(tp, 1);
  9380. tg3_full_unlock(tp);
  9381. return 0;
  9382. }
  9383. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  9384. {
  9385. struct tg3 *tp = netdev_priv(dev);
  9386. strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
  9387. strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
  9388. strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
  9389. strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
  9390. }
  9391. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  9392. {
  9393. struct tg3 *tp = netdev_priv(dev);
  9394. if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
  9395. wol->supported = WAKE_MAGIC;
  9396. else
  9397. wol->supported = 0;
  9398. wol->wolopts = 0;
  9399. if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
  9400. wol->wolopts = WAKE_MAGIC;
  9401. memset(&wol->sopass, 0, sizeof(wol->sopass));
  9402. }
  9403. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  9404. {
  9405. struct tg3 *tp = netdev_priv(dev);
  9406. struct device *dp = &tp->pdev->dev;
  9407. if (wol->wolopts & ~WAKE_MAGIC)
  9408. return -EINVAL;
  9409. if ((wol->wolopts & WAKE_MAGIC) &&
  9410. !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
  9411. return -EINVAL;
  9412. device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
  9413. spin_lock_bh(&tp->lock);
  9414. if (device_may_wakeup(dp))
  9415. tg3_flag_set(tp, WOL_ENABLE);
  9416. else
  9417. tg3_flag_clear(tp, WOL_ENABLE);
  9418. spin_unlock_bh(&tp->lock);
  9419. return 0;
  9420. }
  9421. static u32 tg3_get_msglevel(struct net_device *dev)
  9422. {
  9423. struct tg3 *tp = netdev_priv(dev);
  9424. return tp->msg_enable;
  9425. }
  9426. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  9427. {
  9428. struct tg3 *tp = netdev_priv(dev);
  9429. tp->msg_enable = value;
  9430. }
  9431. static int tg3_nway_reset(struct net_device *dev)
  9432. {
  9433. struct tg3 *tp = netdev_priv(dev);
  9434. int r;
  9435. if (!netif_running(dev))
  9436. return -EAGAIN;
  9437. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  9438. return -EINVAL;
  9439. if (tg3_flag(tp, USE_PHYLIB)) {
  9440. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  9441. return -EAGAIN;
  9442. r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
  9443. } else {
  9444. u32 bmcr;
  9445. spin_lock_bh(&tp->lock);
  9446. r = -EINVAL;
  9447. tg3_readphy(tp, MII_BMCR, &bmcr);
  9448. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  9449. ((bmcr & BMCR_ANENABLE) ||
  9450. (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
  9451. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  9452. BMCR_ANENABLE);
  9453. r = 0;
  9454. }
  9455. spin_unlock_bh(&tp->lock);
  9456. }
  9457. return r;
  9458. }
  9459. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  9460. {
  9461. struct tg3 *tp = netdev_priv(dev);
  9462. ering->rx_max_pending = tp->rx_std_ring_mask;
  9463. if (tg3_flag(tp, JUMBO_RING_ENABLE))
  9464. ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
  9465. else
  9466. ering->rx_jumbo_max_pending = 0;
  9467. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  9468. ering->rx_pending = tp->rx_pending;
  9469. if (tg3_flag(tp, JUMBO_RING_ENABLE))
  9470. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  9471. else
  9472. ering->rx_jumbo_pending = 0;
  9473. ering->tx_pending = tp->napi[0].tx_pending;
  9474. }
  9475. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  9476. {
  9477. struct tg3 *tp = netdev_priv(dev);
  9478. int i, irq_sync = 0, err = 0;
  9479. if ((ering->rx_pending > tp->rx_std_ring_mask) ||
  9480. (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
  9481. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  9482. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  9483. (tg3_flag(tp, TSO_BUG) &&
  9484. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  9485. return -EINVAL;
  9486. if (netif_running(dev)) {
  9487. tg3_phy_stop(tp);
  9488. tg3_netif_stop(tp);
  9489. irq_sync = 1;
  9490. }
  9491. tg3_full_lock(tp, irq_sync);
  9492. tp->rx_pending = ering->rx_pending;
  9493. if (tg3_flag(tp, MAX_RXPEND_64) &&
  9494. tp->rx_pending > 63)
  9495. tp->rx_pending = 63;
  9496. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  9497. for (i = 0; i < tp->irq_max; i++)
  9498. tp->napi[i].tx_pending = ering->tx_pending;
  9499. if (netif_running(dev)) {
  9500. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9501. err = tg3_restart_hw(tp, 1);
  9502. if (!err)
  9503. tg3_netif_start(tp);
  9504. }
  9505. tg3_full_unlock(tp);
  9506. if (irq_sync && !err)
  9507. tg3_phy_start(tp);
  9508. return err;
  9509. }
  9510. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  9511. {
  9512. struct tg3 *tp = netdev_priv(dev);
  9513. epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
  9514. if (tp->link_config.flowctrl & FLOW_CTRL_RX)
  9515. epause->rx_pause = 1;
  9516. else
  9517. epause->rx_pause = 0;
  9518. if (tp->link_config.flowctrl & FLOW_CTRL_TX)
  9519. epause->tx_pause = 1;
  9520. else
  9521. epause->tx_pause = 0;
  9522. }
  9523. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  9524. {
  9525. struct tg3 *tp = netdev_priv(dev);
  9526. int err = 0;
  9527. if (tg3_flag(tp, USE_PHYLIB)) {
  9528. u32 newadv;
  9529. struct phy_device *phydev;
  9530. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  9531. if (!(phydev->supported & SUPPORTED_Pause) ||
  9532. (!(phydev->supported & SUPPORTED_Asym_Pause) &&
  9533. (epause->rx_pause != epause->tx_pause)))
  9534. return -EINVAL;
  9535. tp->link_config.flowctrl = 0;
  9536. if (epause->rx_pause) {
  9537. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  9538. if (epause->tx_pause) {
  9539. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  9540. newadv = ADVERTISED_Pause;
  9541. } else
  9542. newadv = ADVERTISED_Pause |
  9543. ADVERTISED_Asym_Pause;
  9544. } else if (epause->tx_pause) {
  9545. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  9546. newadv = ADVERTISED_Asym_Pause;
  9547. } else
  9548. newadv = 0;
  9549. if (epause->autoneg)
  9550. tg3_flag_set(tp, PAUSE_AUTONEG);
  9551. else
  9552. tg3_flag_clear(tp, PAUSE_AUTONEG);
  9553. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  9554. u32 oldadv = phydev->advertising &
  9555. (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
  9556. if (oldadv != newadv) {
  9557. phydev->advertising &=
  9558. ~(ADVERTISED_Pause |
  9559. ADVERTISED_Asym_Pause);
  9560. phydev->advertising |= newadv;
  9561. if (phydev->autoneg) {
  9562. /*
  9563. * Always renegotiate the link to
  9564. * inform our link partner of our
  9565. * flow control settings, even if the
  9566. * flow control is forced. Let
  9567. * tg3_adjust_link() do the final
  9568. * flow control setup.
  9569. */
  9570. return phy_start_aneg(phydev);
  9571. }
  9572. }
  9573. if (!epause->autoneg)
  9574. tg3_setup_flow_control(tp, 0, 0);
  9575. } else {
  9576. tp->link_config.advertising &=
  9577. ~(ADVERTISED_Pause |
  9578. ADVERTISED_Asym_Pause);
  9579. tp->link_config.advertising |= newadv;
  9580. }
  9581. } else {
  9582. int irq_sync = 0;
  9583. if (netif_running(dev)) {
  9584. tg3_netif_stop(tp);
  9585. irq_sync = 1;
  9586. }
  9587. tg3_full_lock(tp, irq_sync);
  9588. if (epause->autoneg)
  9589. tg3_flag_set(tp, PAUSE_AUTONEG);
  9590. else
  9591. tg3_flag_clear(tp, PAUSE_AUTONEG);
  9592. if (epause->rx_pause)
  9593. tp->link_config.flowctrl |= FLOW_CTRL_RX;
  9594. else
  9595. tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
  9596. if (epause->tx_pause)
  9597. tp->link_config.flowctrl |= FLOW_CTRL_TX;
  9598. else
  9599. tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
  9600. if (netif_running(dev)) {
  9601. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  9602. err = tg3_restart_hw(tp, 1);
  9603. if (!err)
  9604. tg3_netif_start(tp);
  9605. }
  9606. tg3_full_unlock(tp);
  9607. }
  9608. return err;
  9609. }
  9610. static int tg3_get_sset_count(struct net_device *dev, int sset)
  9611. {
  9612. switch (sset) {
  9613. case ETH_SS_TEST:
  9614. return TG3_NUM_TEST;
  9615. case ETH_SS_STATS:
  9616. return TG3_NUM_STATS;
  9617. default:
  9618. return -EOPNOTSUPP;
  9619. }
  9620. }
  9621. static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
  9622. u32 *rules __always_unused)
  9623. {
  9624. struct tg3 *tp = netdev_priv(dev);
  9625. if (!tg3_flag(tp, SUPPORT_MSIX))
  9626. return -EOPNOTSUPP;
  9627. switch (info->cmd) {
  9628. case ETHTOOL_GRXRINGS:
  9629. if (netif_running(tp->dev))
  9630. info->data = tp->rxq_cnt;
  9631. else {
  9632. info->data = num_online_cpus();
  9633. if (info->data > TG3_RSS_MAX_NUM_QS)
  9634. info->data = TG3_RSS_MAX_NUM_QS;
  9635. }
  9636. /* The first interrupt vector only
  9637. * handles link interrupts.
  9638. */
  9639. info->data -= 1;
  9640. return 0;
  9641. default:
  9642. return -EOPNOTSUPP;
  9643. }
  9644. }
  9645. static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
  9646. {
  9647. u32 size = 0;
  9648. struct tg3 *tp = netdev_priv(dev);
  9649. if (tg3_flag(tp, SUPPORT_MSIX))
  9650. size = TG3_RSS_INDIR_TBL_SIZE;
  9651. return size;
  9652. }
  9653. static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
  9654. {
  9655. struct tg3 *tp = netdev_priv(dev);
  9656. int i;
  9657. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  9658. indir[i] = tp->rss_ind_tbl[i];
  9659. return 0;
  9660. }
  9661. static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
  9662. {
  9663. struct tg3 *tp = netdev_priv(dev);
  9664. size_t i;
  9665. for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
  9666. tp->rss_ind_tbl[i] = indir[i];
  9667. if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
  9668. return 0;
  9669. /* It is legal to write the indirection
  9670. * table while the device is running.
  9671. */
  9672. tg3_full_lock(tp, 0);
  9673. tg3_rss_write_indir_tbl(tp);
  9674. tg3_full_unlock(tp);
  9675. return 0;
  9676. }
  9677. static void tg3_get_channels(struct net_device *dev,
  9678. struct ethtool_channels *channel)
  9679. {
  9680. struct tg3 *tp = netdev_priv(dev);
  9681. u32 deflt_qs = netif_get_num_default_rss_queues();
  9682. channel->max_rx = tp->rxq_max;
  9683. channel->max_tx = tp->txq_max;
  9684. if (netif_running(dev)) {
  9685. channel->rx_count = tp->rxq_cnt;
  9686. channel->tx_count = tp->txq_cnt;
  9687. } else {
  9688. if (tp->rxq_req)
  9689. channel->rx_count = tp->rxq_req;
  9690. else
  9691. channel->rx_count = min(deflt_qs, tp->rxq_max);
  9692. if (tp->txq_req)
  9693. channel->tx_count = tp->txq_req;
  9694. else
  9695. channel->tx_count = min(deflt_qs, tp->txq_max);
  9696. }
  9697. }
  9698. static int tg3_set_channels(struct net_device *dev,
  9699. struct ethtool_channels *channel)
  9700. {
  9701. struct tg3 *tp = netdev_priv(dev);
  9702. if (!tg3_flag(tp, SUPPORT_MSIX))
  9703. return -EOPNOTSUPP;
  9704. if (channel->rx_count > tp->rxq_max ||
  9705. channel->tx_count > tp->txq_max)
  9706. return -EINVAL;
  9707. tp->rxq_req = channel->rx_count;
  9708. tp->txq_req = channel->tx_count;
  9709. if (!netif_running(dev))
  9710. return 0;
  9711. tg3_stop(tp);
  9712. tg3_carrier_off(tp);
  9713. tg3_start(tp, true, false, false);
  9714. return 0;
  9715. }
  9716. static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
  9717. {
  9718. switch (stringset) {
  9719. case ETH_SS_STATS:
  9720. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  9721. break;
  9722. case ETH_SS_TEST:
  9723. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  9724. break;
  9725. default:
  9726. WARN_ON(1); /* we need a WARN() */
  9727. break;
  9728. }
  9729. }
  9730. static int tg3_set_phys_id(struct net_device *dev,
  9731. enum ethtool_phys_id_state state)
  9732. {
  9733. struct tg3 *tp = netdev_priv(dev);
  9734. if (!netif_running(tp->dev))
  9735. return -EAGAIN;
  9736. switch (state) {
  9737. case ETHTOOL_ID_ACTIVE:
  9738. return 1; /* cycle on/off once per second */
  9739. case ETHTOOL_ID_ON:
  9740. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  9741. LED_CTRL_1000MBPS_ON |
  9742. LED_CTRL_100MBPS_ON |
  9743. LED_CTRL_10MBPS_ON |
  9744. LED_CTRL_TRAFFIC_OVERRIDE |
  9745. LED_CTRL_TRAFFIC_BLINK |
  9746. LED_CTRL_TRAFFIC_LED);
  9747. break;
  9748. case ETHTOOL_ID_OFF:
  9749. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  9750. LED_CTRL_TRAFFIC_OVERRIDE);
  9751. break;
  9752. case ETHTOOL_ID_INACTIVE:
  9753. tw32(MAC_LED_CTRL, tp->led_ctrl);
  9754. break;
  9755. }
  9756. return 0;
  9757. }
  9758. static void tg3_get_ethtool_stats(struct net_device *dev,
  9759. struct ethtool_stats *estats, u64 *tmp_stats)
  9760. {
  9761. struct tg3 *tp = netdev_priv(dev);
  9762. if (tp->hw_stats)
  9763. tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
  9764. else
  9765. memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
  9766. }
  9767. static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
  9768. {
  9769. int i;
  9770. __be32 *buf;
  9771. u32 offset = 0, len = 0;
  9772. u32 magic, val;
  9773. if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
  9774. return NULL;
  9775. if (magic == TG3_EEPROM_MAGIC) {
  9776. for (offset = TG3_NVM_DIR_START;
  9777. offset < TG3_NVM_DIR_END;
  9778. offset += TG3_NVM_DIRENT_SIZE) {
  9779. if (tg3_nvram_read(tp, offset, &val))
  9780. return NULL;
  9781. if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
  9782. TG3_NVM_DIRTYPE_EXTVPD)
  9783. break;
  9784. }
  9785. if (offset != TG3_NVM_DIR_END) {
  9786. len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
  9787. if (tg3_nvram_read(tp, offset + 4, &offset))
  9788. return NULL;
  9789. offset = tg3_nvram_logical_addr(tp, offset);
  9790. }
  9791. }
  9792. if (!offset || !len) {
  9793. offset = TG3_NVM_VPD_OFF;
  9794. len = TG3_NVM_VPD_LEN;
  9795. }
  9796. buf = kmalloc(len, GFP_KERNEL);
  9797. if (buf == NULL)
  9798. return NULL;
  9799. if (magic == TG3_EEPROM_MAGIC) {
  9800. for (i = 0; i < len; i += 4) {
  9801. /* The data is in little-endian format in NVRAM.
  9802. * Use the big-endian read routines to preserve
  9803. * the byte order as it exists in NVRAM.
  9804. */
  9805. if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
  9806. goto error;
  9807. }
  9808. } else {
  9809. u8 *ptr;
  9810. ssize_t cnt;
  9811. unsigned int pos = 0;
  9812. ptr = (u8 *)&buf[0];
  9813. for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
  9814. cnt = pci_read_vpd(tp->pdev, pos,
  9815. len - pos, ptr);
  9816. if (cnt == -ETIMEDOUT || cnt == -EINTR)
  9817. cnt = 0;
  9818. else if (cnt < 0)
  9819. goto error;
  9820. }
  9821. if (pos != len)
  9822. goto error;
  9823. }
  9824. *vpdlen = len;
  9825. return buf;
  9826. error:
  9827. kfree(buf);
  9828. return NULL;
  9829. }
  9830. #define NVRAM_TEST_SIZE 0x100
  9831. #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
  9832. #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
  9833. #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
  9834. #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
  9835. #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
  9836. #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
  9837. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  9838. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  9839. static int tg3_test_nvram(struct tg3 *tp)
  9840. {
  9841. u32 csum, magic, len;
  9842. __be32 *buf;
  9843. int i, j, k, err = 0, size;
  9844. if (tg3_flag(tp, NO_NVRAM))
  9845. return 0;
  9846. if (tg3_nvram_read(tp, 0, &magic) != 0)
  9847. return -EIO;
  9848. if (magic == TG3_EEPROM_MAGIC)
  9849. size = NVRAM_TEST_SIZE;
  9850. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  9851. if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
  9852. TG3_EEPROM_SB_FORMAT_1) {
  9853. switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
  9854. case TG3_EEPROM_SB_REVISION_0:
  9855. size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
  9856. break;
  9857. case TG3_EEPROM_SB_REVISION_2:
  9858. size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
  9859. break;
  9860. case TG3_EEPROM_SB_REVISION_3:
  9861. size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
  9862. break;
  9863. case TG3_EEPROM_SB_REVISION_4:
  9864. size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
  9865. break;
  9866. case TG3_EEPROM_SB_REVISION_5:
  9867. size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
  9868. break;
  9869. case TG3_EEPROM_SB_REVISION_6:
  9870. size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
  9871. break;
  9872. default:
  9873. return -EIO;
  9874. }
  9875. } else
  9876. return 0;
  9877. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  9878. size = NVRAM_SELFBOOT_HW_SIZE;
  9879. else
  9880. return -EIO;
  9881. buf = kmalloc(size, GFP_KERNEL);
  9882. if (buf == NULL)
  9883. return -ENOMEM;
  9884. err = -EIO;
  9885. for (i = 0, j = 0; i < size; i += 4, j++) {
  9886. err = tg3_nvram_read_be32(tp, i, &buf[j]);
  9887. if (err)
  9888. break;
  9889. }
  9890. if (i < size)
  9891. goto out;
  9892. /* Selfboot format */
  9893. magic = be32_to_cpu(buf[0]);
  9894. if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
  9895. TG3_EEPROM_MAGIC_FW) {
  9896. u8 *buf8 = (u8 *) buf, csum8 = 0;
  9897. if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
  9898. TG3_EEPROM_SB_REVISION_2) {
  9899. /* For rev 2, the csum doesn't include the MBA. */
  9900. for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
  9901. csum8 += buf8[i];
  9902. for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
  9903. csum8 += buf8[i];
  9904. } else {
  9905. for (i = 0; i < size; i++)
  9906. csum8 += buf8[i];
  9907. }
  9908. if (csum8 == 0) {
  9909. err = 0;
  9910. goto out;
  9911. }
  9912. err = -EIO;
  9913. goto out;
  9914. }
  9915. if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
  9916. TG3_EEPROM_MAGIC_HW) {
  9917. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  9918. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  9919. u8 *buf8 = (u8 *) buf;
  9920. /* Separate the parity bits and the data bytes. */
  9921. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  9922. if ((i == 0) || (i == 8)) {
  9923. int l;
  9924. u8 msk;
  9925. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  9926. parity[k++] = buf8[i] & msk;
  9927. i++;
  9928. } else if (i == 16) {
  9929. int l;
  9930. u8 msk;
  9931. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  9932. parity[k++] = buf8[i] & msk;
  9933. i++;
  9934. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  9935. parity[k++] = buf8[i] & msk;
  9936. i++;
  9937. }
  9938. data[j++] = buf8[i];
  9939. }
  9940. err = -EIO;
  9941. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  9942. u8 hw8 = hweight8(data[i]);
  9943. if ((hw8 & 0x1) && parity[i])
  9944. goto out;
  9945. else if (!(hw8 & 0x1) && !parity[i])
  9946. goto out;
  9947. }
  9948. err = 0;
  9949. goto out;
  9950. }
  9951. err = -EIO;
  9952. /* Bootstrap checksum at offset 0x10 */
  9953. csum = calc_crc((unsigned char *) buf, 0x10);
  9954. if (csum != le32_to_cpu(buf[0x10/4]))
  9955. goto out;
  9956. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  9957. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  9958. if (csum != le32_to_cpu(buf[0xfc/4]))
  9959. goto out;
  9960. kfree(buf);
  9961. buf = tg3_vpd_readblock(tp, &len);
  9962. if (!buf)
  9963. return -ENOMEM;
  9964. i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
  9965. if (i > 0) {
  9966. j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
  9967. if (j < 0)
  9968. goto out;
  9969. if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
  9970. goto out;
  9971. i += PCI_VPD_LRDT_TAG_SIZE;
  9972. j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
  9973. PCI_VPD_RO_KEYWORD_CHKSUM);
  9974. if (j > 0) {
  9975. u8 csum8 = 0;
  9976. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  9977. for (i = 0; i <= j; i++)
  9978. csum8 += ((u8 *)buf)[i];
  9979. if (csum8)
  9980. goto out;
  9981. }
  9982. }
  9983. err = 0;
  9984. out:
  9985. kfree(buf);
  9986. return err;
  9987. }
  9988. #define TG3_SERDES_TIMEOUT_SEC 2
  9989. #define TG3_COPPER_TIMEOUT_SEC 6
  9990. static int tg3_test_link(struct tg3 *tp)
  9991. {
  9992. int i, max;
  9993. if (!netif_running(tp->dev))
  9994. return -ENODEV;
  9995. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  9996. max = TG3_SERDES_TIMEOUT_SEC;
  9997. else
  9998. max = TG3_COPPER_TIMEOUT_SEC;
  9999. for (i = 0; i < max; i++) {
  10000. if (tp->link_up)
  10001. return 0;
  10002. if (msleep_interruptible(1000))
  10003. break;
  10004. }
  10005. return -EIO;
  10006. }
  10007. /* Only test the commonly used registers */
  10008. static int tg3_test_registers(struct tg3 *tp)
  10009. {
  10010. int i, is_5705, is_5750;
  10011. u32 offset, read_mask, write_mask, val, save_val, read_val;
  10012. static struct {
  10013. u16 offset;
  10014. u16 flags;
  10015. #define TG3_FL_5705 0x1
  10016. #define TG3_FL_NOT_5705 0x2
  10017. #define TG3_FL_NOT_5788 0x4
  10018. #define TG3_FL_NOT_5750 0x8
  10019. u32 read_mask;
  10020. u32 write_mask;
  10021. } reg_tbl[] = {
  10022. /* MAC Control Registers */
  10023. { MAC_MODE, TG3_FL_NOT_5705,
  10024. 0x00000000, 0x00ef6f8c },
  10025. { MAC_MODE, TG3_FL_5705,
  10026. 0x00000000, 0x01ef6b8c },
  10027. { MAC_STATUS, TG3_FL_NOT_5705,
  10028. 0x03800107, 0x00000000 },
  10029. { MAC_STATUS, TG3_FL_5705,
  10030. 0x03800100, 0x00000000 },
  10031. { MAC_ADDR_0_HIGH, 0x0000,
  10032. 0x00000000, 0x0000ffff },
  10033. { MAC_ADDR_0_LOW, 0x0000,
  10034. 0x00000000, 0xffffffff },
  10035. { MAC_RX_MTU_SIZE, 0x0000,
  10036. 0x00000000, 0x0000ffff },
  10037. { MAC_TX_MODE, 0x0000,
  10038. 0x00000000, 0x00000070 },
  10039. { MAC_TX_LENGTHS, 0x0000,
  10040. 0x00000000, 0x00003fff },
  10041. { MAC_RX_MODE, TG3_FL_NOT_5705,
  10042. 0x00000000, 0x000007fc },
  10043. { MAC_RX_MODE, TG3_FL_5705,
  10044. 0x00000000, 0x000007dc },
  10045. { MAC_HASH_REG_0, 0x0000,
  10046. 0x00000000, 0xffffffff },
  10047. { MAC_HASH_REG_1, 0x0000,
  10048. 0x00000000, 0xffffffff },
  10049. { MAC_HASH_REG_2, 0x0000,
  10050. 0x00000000, 0xffffffff },
  10051. { MAC_HASH_REG_3, 0x0000,
  10052. 0x00000000, 0xffffffff },
  10053. /* Receive Data and Receive BD Initiator Control Registers. */
  10054. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  10055. 0x00000000, 0xffffffff },
  10056. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  10057. 0x00000000, 0xffffffff },
  10058. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  10059. 0x00000000, 0x00000003 },
  10060. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  10061. 0x00000000, 0xffffffff },
  10062. { RCVDBDI_STD_BD+0, 0x0000,
  10063. 0x00000000, 0xffffffff },
  10064. { RCVDBDI_STD_BD+4, 0x0000,
  10065. 0x00000000, 0xffffffff },
  10066. { RCVDBDI_STD_BD+8, 0x0000,
  10067. 0x00000000, 0xffff0002 },
  10068. { RCVDBDI_STD_BD+0xc, 0x0000,
  10069. 0x00000000, 0xffffffff },
  10070. /* Receive BD Initiator Control Registers. */
  10071. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  10072. 0x00000000, 0xffffffff },
  10073. { RCVBDI_STD_THRESH, TG3_FL_5705,
  10074. 0x00000000, 0x000003ff },
  10075. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  10076. 0x00000000, 0xffffffff },
  10077. /* Host Coalescing Control Registers. */
  10078. { HOSTCC_MODE, TG3_FL_NOT_5705,
  10079. 0x00000000, 0x00000004 },
  10080. { HOSTCC_MODE, TG3_FL_5705,
  10081. 0x00000000, 0x000000f6 },
  10082. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  10083. 0x00000000, 0xffffffff },
  10084. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  10085. 0x00000000, 0x000003ff },
  10086. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  10087. 0x00000000, 0xffffffff },
  10088. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  10089. 0x00000000, 0x000003ff },
  10090. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  10091. 0x00000000, 0xffffffff },
  10092. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  10093. 0x00000000, 0x000000ff },
  10094. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  10095. 0x00000000, 0xffffffff },
  10096. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  10097. 0x00000000, 0x000000ff },
  10098. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  10099. 0x00000000, 0xffffffff },
  10100. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  10101. 0x00000000, 0xffffffff },
  10102. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  10103. 0x00000000, 0xffffffff },
  10104. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  10105. 0x00000000, 0x000000ff },
  10106. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  10107. 0x00000000, 0xffffffff },
  10108. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  10109. 0x00000000, 0x000000ff },
  10110. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  10111. 0x00000000, 0xffffffff },
  10112. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  10113. 0x00000000, 0xffffffff },
  10114. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  10115. 0x00000000, 0xffffffff },
  10116. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  10117. 0x00000000, 0xffffffff },
  10118. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  10119. 0x00000000, 0xffffffff },
  10120. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  10121. 0xffffffff, 0x00000000 },
  10122. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  10123. 0xffffffff, 0x00000000 },
  10124. /* Buffer Manager Control Registers. */
  10125. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  10126. 0x00000000, 0x007fff80 },
  10127. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  10128. 0x00000000, 0x007fffff },
  10129. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  10130. 0x00000000, 0x0000003f },
  10131. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  10132. 0x00000000, 0x000001ff },
  10133. { BUFMGR_MB_HIGH_WATER, 0x0000,
  10134. 0x00000000, 0x000001ff },
  10135. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  10136. 0xffffffff, 0x00000000 },
  10137. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  10138. 0xffffffff, 0x00000000 },
  10139. /* Mailbox Registers */
  10140. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  10141. 0x00000000, 0x000001ff },
  10142. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  10143. 0x00000000, 0x000001ff },
  10144. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  10145. 0x00000000, 0x000007ff },
  10146. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  10147. 0x00000000, 0x000001ff },
  10148. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  10149. };
  10150. is_5705 = is_5750 = 0;
  10151. if (tg3_flag(tp, 5705_PLUS)) {
  10152. is_5705 = 1;
  10153. if (tg3_flag(tp, 5750_PLUS))
  10154. is_5750 = 1;
  10155. }
  10156. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  10157. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  10158. continue;
  10159. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  10160. continue;
  10161. if (tg3_flag(tp, IS_5788) &&
  10162. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  10163. continue;
  10164. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  10165. continue;
  10166. offset = (u32) reg_tbl[i].offset;
  10167. read_mask = reg_tbl[i].read_mask;
  10168. write_mask = reg_tbl[i].write_mask;
  10169. /* Save the original register content */
  10170. save_val = tr32(offset);
  10171. /* Determine the read-only value. */
  10172. read_val = save_val & read_mask;
  10173. /* Write zero to the register, then make sure the read-only bits
  10174. * are not changed and the read/write bits are all zeros.
  10175. */
  10176. tw32(offset, 0);
  10177. val = tr32(offset);
  10178. /* Test the read-only and read/write bits. */
  10179. if (((val & read_mask) != read_val) || (val & write_mask))
  10180. goto out;
  10181. /* Write ones to all the bits defined by RdMask and WrMask, then
  10182. * make sure the read-only bits are not changed and the
  10183. * read/write bits are all ones.
  10184. */
  10185. tw32(offset, read_mask | write_mask);
  10186. val = tr32(offset);
  10187. /* Test the read-only bits. */
  10188. if ((val & read_mask) != read_val)
  10189. goto out;
  10190. /* Test the read/write bits. */
  10191. if ((val & write_mask) != write_mask)
  10192. goto out;
  10193. tw32(offset, save_val);
  10194. }
  10195. return 0;
  10196. out:
  10197. if (netif_msg_hw(tp))
  10198. netdev_err(tp->dev,
  10199. "Register test failed at offset %x\n", offset);
  10200. tw32(offset, save_val);
  10201. return -EIO;
  10202. }
  10203. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  10204. {
  10205. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  10206. int i;
  10207. u32 j;
  10208. for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
  10209. for (j = 0; j < len; j += 4) {
  10210. u32 val;
  10211. tg3_write_mem(tp, offset + j, test_pattern[i]);
  10212. tg3_read_mem(tp, offset + j, &val);
  10213. if (val != test_pattern[i])
  10214. return -EIO;
  10215. }
  10216. }
  10217. return 0;
  10218. }
  10219. static int tg3_test_memory(struct tg3 *tp)
  10220. {
  10221. static struct mem_entry {
  10222. u32 offset;
  10223. u32 len;
  10224. } mem_tbl_570x[] = {
  10225. { 0x00000000, 0x00b50},
  10226. { 0x00002000, 0x1c000},
  10227. { 0xffffffff, 0x00000}
  10228. }, mem_tbl_5705[] = {
  10229. { 0x00000100, 0x0000c},
  10230. { 0x00000200, 0x00008},
  10231. { 0x00004000, 0x00800},
  10232. { 0x00006000, 0x01000},
  10233. { 0x00008000, 0x02000},
  10234. { 0x00010000, 0x0e000},
  10235. { 0xffffffff, 0x00000}
  10236. }, mem_tbl_5755[] = {
  10237. { 0x00000200, 0x00008},
  10238. { 0x00004000, 0x00800},
  10239. { 0x00006000, 0x00800},
  10240. { 0x00008000, 0x02000},
  10241. { 0x00010000, 0x0c000},
  10242. { 0xffffffff, 0x00000}
  10243. }, mem_tbl_5906[] = {
  10244. { 0x00000200, 0x00008},
  10245. { 0x00004000, 0x00400},
  10246. { 0x00006000, 0x00400},
  10247. { 0x00008000, 0x01000},
  10248. { 0x00010000, 0x01000},
  10249. { 0xffffffff, 0x00000}
  10250. }, mem_tbl_5717[] = {
  10251. { 0x00000200, 0x00008},
  10252. { 0x00010000, 0x0a000},
  10253. { 0x00020000, 0x13c00},
  10254. { 0xffffffff, 0x00000}
  10255. }, mem_tbl_57765[] = {
  10256. { 0x00000200, 0x00008},
  10257. { 0x00004000, 0x00800},
  10258. { 0x00006000, 0x09800},
  10259. { 0x00010000, 0x0a000},
  10260. { 0xffffffff, 0x00000}
  10261. };
  10262. struct mem_entry *mem_tbl;
  10263. int err = 0;
  10264. int i;
  10265. if (tg3_flag(tp, 5717_PLUS))
  10266. mem_tbl = mem_tbl_5717;
  10267. else if (tg3_flag(tp, 57765_CLASS) ||
  10268. tg3_asic_rev(tp) == ASIC_REV_5762)
  10269. mem_tbl = mem_tbl_57765;
  10270. else if (tg3_flag(tp, 5755_PLUS))
  10271. mem_tbl = mem_tbl_5755;
  10272. else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  10273. mem_tbl = mem_tbl_5906;
  10274. else if (tg3_flag(tp, 5705_PLUS))
  10275. mem_tbl = mem_tbl_5705;
  10276. else
  10277. mem_tbl = mem_tbl_570x;
  10278. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  10279. err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
  10280. if (err)
  10281. break;
  10282. }
  10283. return err;
  10284. }
  10285. #define TG3_TSO_MSS 500
  10286. #define TG3_TSO_IP_HDR_LEN 20
  10287. #define TG3_TSO_TCP_HDR_LEN 20
  10288. #define TG3_TSO_TCP_OPT_LEN 12
  10289. static const u8 tg3_tso_header[] = {
  10290. 0x08, 0x00,
  10291. 0x45, 0x00, 0x00, 0x00,
  10292. 0x00, 0x00, 0x40, 0x00,
  10293. 0x40, 0x06, 0x00, 0x00,
  10294. 0x0a, 0x00, 0x00, 0x01,
  10295. 0x0a, 0x00, 0x00, 0x02,
  10296. 0x0d, 0x00, 0xe0, 0x00,
  10297. 0x00, 0x00, 0x01, 0x00,
  10298. 0x00, 0x00, 0x02, 0x00,
  10299. 0x80, 0x10, 0x10, 0x00,
  10300. 0x14, 0x09, 0x00, 0x00,
  10301. 0x01, 0x01, 0x08, 0x0a,
  10302. 0x11, 0x11, 0x11, 0x11,
  10303. 0x11, 0x11, 0x11, 0x11,
  10304. };
  10305. static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
  10306. {
  10307. u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
  10308. u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
  10309. u32 budget;
  10310. struct sk_buff *skb;
  10311. u8 *tx_data, *rx_data;
  10312. dma_addr_t map;
  10313. int num_pkts, tx_len, rx_len, i, err;
  10314. struct tg3_rx_buffer_desc *desc;
  10315. struct tg3_napi *tnapi, *rnapi;
  10316. struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
  10317. tnapi = &tp->napi[0];
  10318. rnapi = &tp->napi[0];
  10319. if (tp->irq_cnt > 1) {
  10320. if (tg3_flag(tp, ENABLE_RSS))
  10321. rnapi = &tp->napi[1];
  10322. if (tg3_flag(tp, ENABLE_TSS))
  10323. tnapi = &tp->napi[1];
  10324. }
  10325. coal_now = tnapi->coal_now | rnapi->coal_now;
  10326. err = -EIO;
  10327. tx_len = pktsz;
  10328. skb = netdev_alloc_skb(tp->dev, tx_len);
  10329. if (!skb)
  10330. return -ENOMEM;
  10331. tx_data = skb_put(skb, tx_len);
  10332. memcpy(tx_data, tp->dev->dev_addr, 6);
  10333. memset(tx_data + 6, 0x0, 8);
  10334. tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
  10335. if (tso_loopback) {
  10336. struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
  10337. u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
  10338. TG3_TSO_TCP_OPT_LEN;
  10339. memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
  10340. sizeof(tg3_tso_header));
  10341. mss = TG3_TSO_MSS;
  10342. val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
  10343. num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
  10344. /* Set the total length field in the IP header */
  10345. iph->tot_len = htons((u16)(mss + hdr_len));
  10346. base_flags = (TXD_FLAG_CPU_PRE_DMA |
  10347. TXD_FLAG_CPU_POST_DMA);
  10348. if (tg3_flag(tp, HW_TSO_1) ||
  10349. tg3_flag(tp, HW_TSO_2) ||
  10350. tg3_flag(tp, HW_TSO_3)) {
  10351. struct tcphdr *th;
  10352. val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
  10353. th = (struct tcphdr *)&tx_data[val];
  10354. th->check = 0;
  10355. } else
  10356. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  10357. if (tg3_flag(tp, HW_TSO_3)) {
  10358. mss |= (hdr_len & 0xc) << 12;
  10359. if (hdr_len & 0x10)
  10360. base_flags |= 0x00000010;
  10361. base_flags |= (hdr_len & 0x3e0) << 5;
  10362. } else if (tg3_flag(tp, HW_TSO_2))
  10363. mss |= hdr_len << 9;
  10364. else if (tg3_flag(tp, HW_TSO_1) ||
  10365. tg3_asic_rev(tp) == ASIC_REV_5705) {
  10366. mss |= (TG3_TSO_TCP_OPT_LEN << 9);
  10367. } else {
  10368. base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
  10369. }
  10370. data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
  10371. } else {
  10372. num_pkts = 1;
  10373. data_off = ETH_HLEN;
  10374. if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
  10375. tx_len > VLAN_ETH_FRAME_LEN)
  10376. base_flags |= TXD_FLAG_JMB_PKT;
  10377. }
  10378. for (i = data_off; i < tx_len; i++)
  10379. tx_data[i] = (u8) (i & 0xff);
  10380. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  10381. if (pci_dma_mapping_error(tp->pdev, map)) {
  10382. dev_kfree_skb(skb);
  10383. return -EIO;
  10384. }
  10385. val = tnapi->tx_prod;
  10386. tnapi->tx_buffers[val].skb = skb;
  10387. dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
  10388. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  10389. rnapi->coal_now);
  10390. udelay(10);
  10391. rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
  10392. budget = tg3_tx_avail(tnapi);
  10393. if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
  10394. base_flags | TXD_FLAG_END, mss, 0)) {
  10395. tnapi->tx_buffers[val].skb = NULL;
  10396. dev_kfree_skb(skb);
  10397. return -EIO;
  10398. }
  10399. tnapi->tx_prod++;
  10400. /* Sync BD data before updating mailbox */
  10401. wmb();
  10402. tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
  10403. tr32_mailbox(tnapi->prodmbox);
  10404. udelay(10);
  10405. /* 350 usec to allow enough time on some 10/100 Mbps devices. */
  10406. for (i = 0; i < 35; i++) {
  10407. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  10408. coal_now);
  10409. udelay(10);
  10410. tx_idx = tnapi->hw_status->idx[0].tx_consumer;
  10411. rx_idx = rnapi->hw_status->idx[0].rx_producer;
  10412. if ((tx_idx == tnapi->tx_prod) &&
  10413. (rx_idx == (rx_start_idx + num_pkts)))
  10414. break;
  10415. }
  10416. tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
  10417. dev_kfree_skb(skb);
  10418. if (tx_idx != tnapi->tx_prod)
  10419. goto out;
  10420. if (rx_idx != rx_start_idx + num_pkts)
  10421. goto out;
  10422. val = data_off;
  10423. while (rx_idx != rx_start_idx) {
  10424. desc = &rnapi->rx_rcb[rx_start_idx++];
  10425. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  10426. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  10427. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  10428. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  10429. goto out;
  10430. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
  10431. - ETH_FCS_LEN;
  10432. if (!tso_loopback) {
  10433. if (rx_len != tx_len)
  10434. goto out;
  10435. if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
  10436. if (opaque_key != RXD_OPAQUE_RING_STD)
  10437. goto out;
  10438. } else {
  10439. if (opaque_key != RXD_OPAQUE_RING_JUMBO)
  10440. goto out;
  10441. }
  10442. } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  10443. (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  10444. >> RXD_TCPCSUM_SHIFT != 0xffff) {
  10445. goto out;
  10446. }
  10447. if (opaque_key == RXD_OPAQUE_RING_STD) {
  10448. rx_data = tpr->rx_std_buffers[desc_idx].data;
  10449. map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
  10450. mapping);
  10451. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  10452. rx_data = tpr->rx_jmb_buffers[desc_idx].data;
  10453. map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
  10454. mapping);
  10455. } else
  10456. goto out;
  10457. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
  10458. PCI_DMA_FROMDEVICE);
  10459. rx_data += TG3_RX_OFFSET(tp);
  10460. for (i = data_off; i < rx_len; i++, val++) {
  10461. if (*(rx_data + i) != (u8) (val & 0xff))
  10462. goto out;
  10463. }
  10464. }
  10465. err = 0;
  10466. /* tg3_free_rings will unmap and free the rx_data */
  10467. out:
  10468. return err;
  10469. }
  10470. #define TG3_STD_LOOPBACK_FAILED 1
  10471. #define TG3_JMB_LOOPBACK_FAILED 2
  10472. #define TG3_TSO_LOOPBACK_FAILED 4
  10473. #define TG3_LOOPBACK_FAILED \
  10474. (TG3_STD_LOOPBACK_FAILED | \
  10475. TG3_JMB_LOOPBACK_FAILED | \
  10476. TG3_TSO_LOOPBACK_FAILED)
  10477. static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
  10478. {
  10479. int err = -EIO;
  10480. u32 eee_cap;
  10481. u32 jmb_pkt_sz = 9000;
  10482. if (tp->dma_limit)
  10483. jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
  10484. eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
  10485. tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
  10486. if (!netif_running(tp->dev)) {
  10487. data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10488. data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10489. if (do_extlpbk)
  10490. data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10491. goto done;
  10492. }
  10493. err = tg3_reset_hw(tp, 1);
  10494. if (err) {
  10495. data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10496. data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10497. if (do_extlpbk)
  10498. data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
  10499. goto done;
  10500. }
  10501. if (tg3_flag(tp, ENABLE_RSS)) {
  10502. int i;
  10503. /* Reroute all rx packets to the 1st queue */
  10504. for (i = MAC_RSS_INDIR_TBL_0;
  10505. i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
  10506. tw32(i, 0x0);
  10507. }
  10508. /* HW errata - mac loopback fails in some cases on 5780.
  10509. * Normal traffic and PHY loopback are not affected by
  10510. * errata. Also, the MAC loopback test is deprecated for
  10511. * all newer ASIC revisions.
  10512. */
  10513. if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
  10514. !tg3_flag(tp, CPMU_PRESENT)) {
  10515. tg3_mac_loopback(tp, true);
  10516. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  10517. data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
  10518. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  10519. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  10520. data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
  10521. tg3_mac_loopback(tp, false);
  10522. }
  10523. if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
  10524. !tg3_flag(tp, USE_PHYLIB)) {
  10525. int i;
  10526. tg3_phy_lpbk_set(tp, 0, false);
  10527. /* Wait for link */
  10528. for (i = 0; i < 100; i++) {
  10529. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  10530. break;
  10531. mdelay(1);
  10532. }
  10533. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  10534. data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
  10535. if (tg3_flag(tp, TSO_CAPABLE) &&
  10536. tg3_run_loopback(tp, ETH_FRAME_LEN, true))
  10537. data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
  10538. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  10539. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  10540. data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
  10541. if (do_extlpbk) {
  10542. tg3_phy_lpbk_set(tp, 0, true);
  10543. /* All link indications report up, but the hardware
  10544. * isn't really ready for about 20 msec. Double it
  10545. * to be sure.
  10546. */
  10547. mdelay(40);
  10548. if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
  10549. data[TG3_EXT_LOOPB_TEST] |=
  10550. TG3_STD_LOOPBACK_FAILED;
  10551. if (tg3_flag(tp, TSO_CAPABLE) &&
  10552. tg3_run_loopback(tp, ETH_FRAME_LEN, true))
  10553. data[TG3_EXT_LOOPB_TEST] |=
  10554. TG3_TSO_LOOPBACK_FAILED;
  10555. if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
  10556. tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
  10557. data[TG3_EXT_LOOPB_TEST] |=
  10558. TG3_JMB_LOOPBACK_FAILED;
  10559. }
  10560. /* Re-enable gphy autopowerdown. */
  10561. if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
  10562. tg3_phy_toggle_apd(tp, true);
  10563. }
  10564. err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
  10565. data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
  10566. done:
  10567. tp->phy_flags |= eee_cap;
  10568. return err;
  10569. }
  10570. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  10571. u64 *data)
  10572. {
  10573. struct tg3 *tp = netdev_priv(dev);
  10574. bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
  10575. if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
  10576. tg3_power_up(tp)) {
  10577. etest->flags |= ETH_TEST_FL_FAILED;
  10578. memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
  10579. return;
  10580. }
  10581. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  10582. if (tg3_test_nvram(tp) != 0) {
  10583. etest->flags |= ETH_TEST_FL_FAILED;
  10584. data[TG3_NVRAM_TEST] = 1;
  10585. }
  10586. if (!doextlpbk && tg3_test_link(tp)) {
  10587. etest->flags |= ETH_TEST_FL_FAILED;
  10588. data[TG3_LINK_TEST] = 1;
  10589. }
  10590. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  10591. int err, err2 = 0, irq_sync = 0;
  10592. if (netif_running(dev)) {
  10593. tg3_phy_stop(tp);
  10594. tg3_netif_stop(tp);
  10595. irq_sync = 1;
  10596. }
  10597. tg3_full_lock(tp, irq_sync);
  10598. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  10599. err = tg3_nvram_lock(tp);
  10600. tg3_halt_cpu(tp, RX_CPU_BASE);
  10601. if (!tg3_flag(tp, 5705_PLUS))
  10602. tg3_halt_cpu(tp, TX_CPU_BASE);
  10603. if (!err)
  10604. tg3_nvram_unlock(tp);
  10605. if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
  10606. tg3_phy_reset(tp);
  10607. if (tg3_test_registers(tp) != 0) {
  10608. etest->flags |= ETH_TEST_FL_FAILED;
  10609. data[TG3_REGISTER_TEST] = 1;
  10610. }
  10611. if (tg3_test_memory(tp) != 0) {
  10612. etest->flags |= ETH_TEST_FL_FAILED;
  10613. data[TG3_MEMORY_TEST] = 1;
  10614. }
  10615. if (doextlpbk)
  10616. etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
  10617. if (tg3_test_loopback(tp, data, doextlpbk))
  10618. etest->flags |= ETH_TEST_FL_FAILED;
  10619. tg3_full_unlock(tp);
  10620. if (tg3_test_interrupt(tp) != 0) {
  10621. etest->flags |= ETH_TEST_FL_FAILED;
  10622. data[TG3_INTERRUPT_TEST] = 1;
  10623. }
  10624. tg3_full_lock(tp, 0);
  10625. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10626. if (netif_running(dev)) {
  10627. tg3_flag_set(tp, INIT_COMPLETE);
  10628. err2 = tg3_restart_hw(tp, 1);
  10629. if (!err2)
  10630. tg3_netif_start(tp);
  10631. }
  10632. tg3_full_unlock(tp);
  10633. if (irq_sync && !err2)
  10634. tg3_phy_start(tp);
  10635. }
  10636. if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
  10637. tg3_power_down(tp);
  10638. }
  10639. static int tg3_hwtstamp_ioctl(struct net_device *dev,
  10640. struct ifreq *ifr, int cmd)
  10641. {
  10642. struct tg3 *tp = netdev_priv(dev);
  10643. struct hwtstamp_config stmpconf;
  10644. if (!tg3_flag(tp, PTP_CAPABLE))
  10645. return -EINVAL;
  10646. if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
  10647. return -EFAULT;
  10648. if (stmpconf.flags)
  10649. return -EINVAL;
  10650. switch (stmpconf.tx_type) {
  10651. case HWTSTAMP_TX_ON:
  10652. tg3_flag_set(tp, TX_TSTAMP_EN);
  10653. break;
  10654. case HWTSTAMP_TX_OFF:
  10655. tg3_flag_clear(tp, TX_TSTAMP_EN);
  10656. break;
  10657. default:
  10658. return -ERANGE;
  10659. }
  10660. switch (stmpconf.rx_filter) {
  10661. case HWTSTAMP_FILTER_NONE:
  10662. tp->rxptpctl = 0;
  10663. break;
  10664. case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
  10665. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  10666. TG3_RX_PTP_CTL_ALL_V1_EVENTS;
  10667. break;
  10668. case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
  10669. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  10670. TG3_RX_PTP_CTL_SYNC_EVNT;
  10671. break;
  10672. case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
  10673. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
  10674. TG3_RX_PTP_CTL_DELAY_REQ;
  10675. break;
  10676. case HWTSTAMP_FILTER_PTP_V2_EVENT:
  10677. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  10678. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  10679. break;
  10680. case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
  10681. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  10682. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  10683. break;
  10684. case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
  10685. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  10686. TG3_RX_PTP_CTL_ALL_V2_EVENTS;
  10687. break;
  10688. case HWTSTAMP_FILTER_PTP_V2_SYNC:
  10689. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  10690. TG3_RX_PTP_CTL_SYNC_EVNT;
  10691. break;
  10692. case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
  10693. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  10694. TG3_RX_PTP_CTL_SYNC_EVNT;
  10695. break;
  10696. case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
  10697. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  10698. TG3_RX_PTP_CTL_SYNC_EVNT;
  10699. break;
  10700. case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
  10701. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
  10702. TG3_RX_PTP_CTL_DELAY_REQ;
  10703. break;
  10704. case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
  10705. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
  10706. TG3_RX_PTP_CTL_DELAY_REQ;
  10707. break;
  10708. case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
  10709. tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
  10710. TG3_RX_PTP_CTL_DELAY_REQ;
  10711. break;
  10712. default:
  10713. return -ERANGE;
  10714. }
  10715. if (netif_running(dev) && tp->rxptpctl)
  10716. tw32(TG3_RX_PTP_CTL,
  10717. tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
  10718. return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
  10719. -EFAULT : 0;
  10720. }
  10721. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  10722. {
  10723. struct mii_ioctl_data *data = if_mii(ifr);
  10724. struct tg3 *tp = netdev_priv(dev);
  10725. int err;
  10726. if (tg3_flag(tp, USE_PHYLIB)) {
  10727. struct phy_device *phydev;
  10728. if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
  10729. return -EAGAIN;
  10730. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  10731. return phy_mii_ioctl(phydev, ifr, cmd);
  10732. }
  10733. switch (cmd) {
  10734. case SIOCGMIIPHY:
  10735. data->phy_id = tp->phy_addr;
  10736. /* fallthru */
  10737. case SIOCGMIIREG: {
  10738. u32 mii_regval;
  10739. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  10740. break; /* We have no PHY */
  10741. if (!netif_running(dev))
  10742. return -EAGAIN;
  10743. spin_lock_bh(&tp->lock);
  10744. err = __tg3_readphy(tp, data->phy_id & 0x1f,
  10745. data->reg_num & 0x1f, &mii_regval);
  10746. spin_unlock_bh(&tp->lock);
  10747. data->val_out = mii_regval;
  10748. return err;
  10749. }
  10750. case SIOCSMIIREG:
  10751. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  10752. break; /* We have no PHY */
  10753. if (!netif_running(dev))
  10754. return -EAGAIN;
  10755. spin_lock_bh(&tp->lock);
  10756. err = __tg3_writephy(tp, data->phy_id & 0x1f,
  10757. data->reg_num & 0x1f, data->val_in);
  10758. spin_unlock_bh(&tp->lock);
  10759. return err;
  10760. case SIOCSHWTSTAMP:
  10761. return tg3_hwtstamp_ioctl(dev, ifr, cmd);
  10762. default:
  10763. /* do nothing */
  10764. break;
  10765. }
  10766. return -EOPNOTSUPP;
  10767. }
  10768. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  10769. {
  10770. struct tg3 *tp = netdev_priv(dev);
  10771. memcpy(ec, &tp->coal, sizeof(*ec));
  10772. return 0;
  10773. }
  10774. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  10775. {
  10776. struct tg3 *tp = netdev_priv(dev);
  10777. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  10778. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  10779. if (!tg3_flag(tp, 5705_PLUS)) {
  10780. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  10781. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  10782. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  10783. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  10784. }
  10785. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  10786. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  10787. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  10788. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  10789. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  10790. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  10791. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  10792. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  10793. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  10794. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  10795. return -EINVAL;
  10796. /* No rx interrupts will be generated if both are zero */
  10797. if ((ec->rx_coalesce_usecs == 0) &&
  10798. (ec->rx_max_coalesced_frames == 0))
  10799. return -EINVAL;
  10800. /* No tx interrupts will be generated if both are zero */
  10801. if ((ec->tx_coalesce_usecs == 0) &&
  10802. (ec->tx_max_coalesced_frames == 0))
  10803. return -EINVAL;
  10804. /* Only copy relevant parameters, ignore all others. */
  10805. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  10806. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  10807. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  10808. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  10809. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  10810. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  10811. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  10812. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  10813. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  10814. if (netif_running(dev)) {
  10815. tg3_full_lock(tp, 0);
  10816. __tg3_set_coalesce(tp, &tp->coal);
  10817. tg3_full_unlock(tp);
  10818. }
  10819. return 0;
  10820. }
  10821. static const struct ethtool_ops tg3_ethtool_ops = {
  10822. .get_settings = tg3_get_settings,
  10823. .set_settings = tg3_set_settings,
  10824. .get_drvinfo = tg3_get_drvinfo,
  10825. .get_regs_len = tg3_get_regs_len,
  10826. .get_regs = tg3_get_regs,
  10827. .get_wol = tg3_get_wol,
  10828. .set_wol = tg3_set_wol,
  10829. .get_msglevel = tg3_get_msglevel,
  10830. .set_msglevel = tg3_set_msglevel,
  10831. .nway_reset = tg3_nway_reset,
  10832. .get_link = ethtool_op_get_link,
  10833. .get_eeprom_len = tg3_get_eeprom_len,
  10834. .get_eeprom = tg3_get_eeprom,
  10835. .set_eeprom = tg3_set_eeprom,
  10836. .get_ringparam = tg3_get_ringparam,
  10837. .set_ringparam = tg3_set_ringparam,
  10838. .get_pauseparam = tg3_get_pauseparam,
  10839. .set_pauseparam = tg3_set_pauseparam,
  10840. .self_test = tg3_self_test,
  10841. .get_strings = tg3_get_strings,
  10842. .set_phys_id = tg3_set_phys_id,
  10843. .get_ethtool_stats = tg3_get_ethtool_stats,
  10844. .get_coalesce = tg3_get_coalesce,
  10845. .set_coalesce = tg3_set_coalesce,
  10846. .get_sset_count = tg3_get_sset_count,
  10847. .get_rxnfc = tg3_get_rxnfc,
  10848. .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
  10849. .get_rxfh_indir = tg3_get_rxfh_indir,
  10850. .set_rxfh_indir = tg3_set_rxfh_indir,
  10851. .get_channels = tg3_get_channels,
  10852. .set_channels = tg3_set_channels,
  10853. .get_ts_info = tg3_get_ts_info,
  10854. };
  10855. static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
  10856. struct rtnl_link_stats64 *stats)
  10857. {
  10858. struct tg3 *tp = netdev_priv(dev);
  10859. spin_lock_bh(&tp->lock);
  10860. if (!tp->hw_stats) {
  10861. spin_unlock_bh(&tp->lock);
  10862. return &tp->net_stats_prev;
  10863. }
  10864. tg3_get_nstats(tp, stats);
  10865. spin_unlock_bh(&tp->lock);
  10866. return stats;
  10867. }
  10868. static void tg3_set_rx_mode(struct net_device *dev)
  10869. {
  10870. struct tg3 *tp = netdev_priv(dev);
  10871. if (!netif_running(dev))
  10872. return;
  10873. tg3_full_lock(tp, 0);
  10874. __tg3_set_rx_mode(dev);
  10875. tg3_full_unlock(tp);
  10876. }
  10877. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  10878. int new_mtu)
  10879. {
  10880. dev->mtu = new_mtu;
  10881. if (new_mtu > ETH_DATA_LEN) {
  10882. if (tg3_flag(tp, 5780_CLASS)) {
  10883. netdev_update_features(dev);
  10884. tg3_flag_clear(tp, TSO_CAPABLE);
  10885. } else {
  10886. tg3_flag_set(tp, JUMBO_RING_ENABLE);
  10887. }
  10888. } else {
  10889. if (tg3_flag(tp, 5780_CLASS)) {
  10890. tg3_flag_set(tp, TSO_CAPABLE);
  10891. netdev_update_features(dev);
  10892. }
  10893. tg3_flag_clear(tp, JUMBO_RING_ENABLE);
  10894. }
  10895. }
  10896. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  10897. {
  10898. struct tg3 *tp = netdev_priv(dev);
  10899. int err, reset_phy = 0;
  10900. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  10901. return -EINVAL;
  10902. if (!netif_running(dev)) {
  10903. /* We'll just catch it later when the
  10904. * device is up'd.
  10905. */
  10906. tg3_set_mtu(dev, tp, new_mtu);
  10907. return 0;
  10908. }
  10909. tg3_phy_stop(tp);
  10910. tg3_netif_stop(tp);
  10911. tg3_full_lock(tp, 1);
  10912. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10913. tg3_set_mtu(dev, tp, new_mtu);
  10914. /* Reset PHY, otherwise the read DMA engine will be in a mode that
  10915. * breaks all requests to 256 bytes.
  10916. */
  10917. if (tg3_asic_rev(tp) == ASIC_REV_57766)
  10918. reset_phy = 1;
  10919. err = tg3_restart_hw(tp, reset_phy);
  10920. if (!err)
  10921. tg3_netif_start(tp);
  10922. tg3_full_unlock(tp);
  10923. if (!err)
  10924. tg3_phy_start(tp);
  10925. return err;
  10926. }
  10927. static const struct net_device_ops tg3_netdev_ops = {
  10928. .ndo_open = tg3_open,
  10929. .ndo_stop = tg3_close,
  10930. .ndo_start_xmit = tg3_start_xmit,
  10931. .ndo_get_stats64 = tg3_get_stats64,
  10932. .ndo_validate_addr = eth_validate_addr,
  10933. .ndo_set_rx_mode = tg3_set_rx_mode,
  10934. .ndo_set_mac_address = tg3_set_mac_addr,
  10935. .ndo_do_ioctl = tg3_ioctl,
  10936. .ndo_tx_timeout = tg3_tx_timeout,
  10937. .ndo_change_mtu = tg3_change_mtu,
  10938. .ndo_fix_features = tg3_fix_features,
  10939. .ndo_set_features = tg3_set_features,
  10940. #ifdef CONFIG_NET_POLL_CONTROLLER
  10941. .ndo_poll_controller = tg3_poll_controller,
  10942. #endif
  10943. };
  10944. static void tg3_get_eeprom_size(struct tg3 *tp)
  10945. {
  10946. u32 cursize, val, magic;
  10947. tp->nvram_size = EEPROM_CHIP_SIZE;
  10948. if (tg3_nvram_read(tp, 0, &magic) != 0)
  10949. return;
  10950. if ((magic != TG3_EEPROM_MAGIC) &&
  10951. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  10952. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  10953. return;
  10954. /*
  10955. * Size the chip by reading offsets at increasing powers of two.
  10956. * When we encounter our validation signature, we know the addressing
  10957. * has wrapped around, and thus have our chip size.
  10958. */
  10959. cursize = 0x10;
  10960. while (cursize < tp->nvram_size) {
  10961. if (tg3_nvram_read(tp, cursize, &val) != 0)
  10962. return;
  10963. if (val == magic)
  10964. break;
  10965. cursize <<= 1;
  10966. }
  10967. tp->nvram_size = cursize;
  10968. }
  10969. static void tg3_get_nvram_size(struct tg3 *tp)
  10970. {
  10971. u32 val;
  10972. if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
  10973. return;
  10974. /* Selfboot format */
  10975. if (val != TG3_EEPROM_MAGIC) {
  10976. tg3_get_eeprom_size(tp);
  10977. return;
  10978. }
  10979. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  10980. if (val != 0) {
  10981. /* This is confusing. We want to operate on the
  10982. * 16-bit value at offset 0xf2. The tg3_nvram_read()
  10983. * call will read from NVRAM and byteswap the data
  10984. * according to the byteswapping settings for all
  10985. * other register accesses. This ensures the data we
  10986. * want will always reside in the lower 16-bits.
  10987. * However, the data in NVRAM is in LE format, which
  10988. * means the data from the NVRAM read will always be
  10989. * opposite the endianness of the CPU. The 16-bit
  10990. * byteswap then brings the data to CPU endianness.
  10991. */
  10992. tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
  10993. return;
  10994. }
  10995. }
  10996. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  10997. }
  10998. static void tg3_get_nvram_info(struct tg3 *tp)
  10999. {
  11000. u32 nvcfg1;
  11001. nvcfg1 = tr32(NVRAM_CFG1);
  11002. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  11003. tg3_flag_set(tp, FLASH);
  11004. } else {
  11005. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11006. tw32(NVRAM_CFG1, nvcfg1);
  11007. }
  11008. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  11009. tg3_flag(tp, 5780_CLASS)) {
  11010. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  11011. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  11012. tp->nvram_jedecnum = JEDEC_ATMEL;
  11013. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  11014. tg3_flag_set(tp, NVRAM_BUFFERED);
  11015. break;
  11016. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  11017. tp->nvram_jedecnum = JEDEC_ATMEL;
  11018. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  11019. break;
  11020. case FLASH_VENDOR_ATMEL_EEPROM:
  11021. tp->nvram_jedecnum = JEDEC_ATMEL;
  11022. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11023. tg3_flag_set(tp, NVRAM_BUFFERED);
  11024. break;
  11025. case FLASH_VENDOR_ST:
  11026. tp->nvram_jedecnum = JEDEC_ST;
  11027. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  11028. tg3_flag_set(tp, NVRAM_BUFFERED);
  11029. break;
  11030. case FLASH_VENDOR_SAIFUN:
  11031. tp->nvram_jedecnum = JEDEC_SAIFUN;
  11032. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  11033. break;
  11034. case FLASH_VENDOR_SST_SMALL:
  11035. case FLASH_VENDOR_SST_LARGE:
  11036. tp->nvram_jedecnum = JEDEC_SST;
  11037. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  11038. break;
  11039. }
  11040. } else {
  11041. tp->nvram_jedecnum = JEDEC_ATMEL;
  11042. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  11043. tg3_flag_set(tp, NVRAM_BUFFERED);
  11044. }
  11045. }
  11046. static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
  11047. {
  11048. switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  11049. case FLASH_5752PAGE_SIZE_256:
  11050. tp->nvram_pagesize = 256;
  11051. break;
  11052. case FLASH_5752PAGE_SIZE_512:
  11053. tp->nvram_pagesize = 512;
  11054. break;
  11055. case FLASH_5752PAGE_SIZE_1K:
  11056. tp->nvram_pagesize = 1024;
  11057. break;
  11058. case FLASH_5752PAGE_SIZE_2K:
  11059. tp->nvram_pagesize = 2048;
  11060. break;
  11061. case FLASH_5752PAGE_SIZE_4K:
  11062. tp->nvram_pagesize = 4096;
  11063. break;
  11064. case FLASH_5752PAGE_SIZE_264:
  11065. tp->nvram_pagesize = 264;
  11066. break;
  11067. case FLASH_5752PAGE_SIZE_528:
  11068. tp->nvram_pagesize = 528;
  11069. break;
  11070. }
  11071. }
  11072. static void tg3_get_5752_nvram_info(struct tg3 *tp)
  11073. {
  11074. u32 nvcfg1;
  11075. nvcfg1 = tr32(NVRAM_CFG1);
  11076. /* NVRAM protection for TPM */
  11077. if (nvcfg1 & (1 << 27))
  11078. tg3_flag_set(tp, PROTECTED_NVRAM);
  11079. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11080. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  11081. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  11082. tp->nvram_jedecnum = JEDEC_ATMEL;
  11083. tg3_flag_set(tp, NVRAM_BUFFERED);
  11084. break;
  11085. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11086. tp->nvram_jedecnum = JEDEC_ATMEL;
  11087. tg3_flag_set(tp, NVRAM_BUFFERED);
  11088. tg3_flag_set(tp, FLASH);
  11089. break;
  11090. case FLASH_5752VENDOR_ST_M45PE10:
  11091. case FLASH_5752VENDOR_ST_M45PE20:
  11092. case FLASH_5752VENDOR_ST_M45PE40:
  11093. tp->nvram_jedecnum = JEDEC_ST;
  11094. tg3_flag_set(tp, NVRAM_BUFFERED);
  11095. tg3_flag_set(tp, FLASH);
  11096. break;
  11097. }
  11098. if (tg3_flag(tp, FLASH)) {
  11099. tg3_nvram_get_pagesize(tp, nvcfg1);
  11100. } else {
  11101. /* For eeprom, set pagesize to maximum eeprom size */
  11102. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11103. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11104. tw32(NVRAM_CFG1, nvcfg1);
  11105. }
  11106. }
  11107. static void tg3_get_5755_nvram_info(struct tg3 *tp)
  11108. {
  11109. u32 nvcfg1, protect = 0;
  11110. nvcfg1 = tr32(NVRAM_CFG1);
  11111. /* NVRAM protection for TPM */
  11112. if (nvcfg1 & (1 << 27)) {
  11113. tg3_flag_set(tp, PROTECTED_NVRAM);
  11114. protect = 1;
  11115. }
  11116. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  11117. switch (nvcfg1) {
  11118. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  11119. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  11120. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  11121. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  11122. tp->nvram_jedecnum = JEDEC_ATMEL;
  11123. tg3_flag_set(tp, NVRAM_BUFFERED);
  11124. tg3_flag_set(tp, FLASH);
  11125. tp->nvram_pagesize = 264;
  11126. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  11127. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  11128. tp->nvram_size = (protect ? 0x3e200 :
  11129. TG3_NVRAM_SIZE_512KB);
  11130. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  11131. tp->nvram_size = (protect ? 0x1f200 :
  11132. TG3_NVRAM_SIZE_256KB);
  11133. else
  11134. tp->nvram_size = (protect ? 0x1f200 :
  11135. TG3_NVRAM_SIZE_128KB);
  11136. break;
  11137. case FLASH_5752VENDOR_ST_M45PE10:
  11138. case FLASH_5752VENDOR_ST_M45PE20:
  11139. case FLASH_5752VENDOR_ST_M45PE40:
  11140. tp->nvram_jedecnum = JEDEC_ST;
  11141. tg3_flag_set(tp, NVRAM_BUFFERED);
  11142. tg3_flag_set(tp, FLASH);
  11143. tp->nvram_pagesize = 256;
  11144. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  11145. tp->nvram_size = (protect ?
  11146. TG3_NVRAM_SIZE_64KB :
  11147. TG3_NVRAM_SIZE_128KB);
  11148. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  11149. tp->nvram_size = (protect ?
  11150. TG3_NVRAM_SIZE_64KB :
  11151. TG3_NVRAM_SIZE_256KB);
  11152. else
  11153. tp->nvram_size = (protect ?
  11154. TG3_NVRAM_SIZE_128KB :
  11155. TG3_NVRAM_SIZE_512KB);
  11156. break;
  11157. }
  11158. }
  11159. static void tg3_get_5787_nvram_info(struct tg3 *tp)
  11160. {
  11161. u32 nvcfg1;
  11162. nvcfg1 = tr32(NVRAM_CFG1);
  11163. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11164. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  11165. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  11166. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  11167. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  11168. tp->nvram_jedecnum = JEDEC_ATMEL;
  11169. tg3_flag_set(tp, NVRAM_BUFFERED);
  11170. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11171. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11172. tw32(NVRAM_CFG1, nvcfg1);
  11173. break;
  11174. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11175. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  11176. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  11177. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  11178. tp->nvram_jedecnum = JEDEC_ATMEL;
  11179. tg3_flag_set(tp, NVRAM_BUFFERED);
  11180. tg3_flag_set(tp, FLASH);
  11181. tp->nvram_pagesize = 264;
  11182. break;
  11183. case FLASH_5752VENDOR_ST_M45PE10:
  11184. case FLASH_5752VENDOR_ST_M45PE20:
  11185. case FLASH_5752VENDOR_ST_M45PE40:
  11186. tp->nvram_jedecnum = JEDEC_ST;
  11187. tg3_flag_set(tp, NVRAM_BUFFERED);
  11188. tg3_flag_set(tp, FLASH);
  11189. tp->nvram_pagesize = 256;
  11190. break;
  11191. }
  11192. }
  11193. static void tg3_get_5761_nvram_info(struct tg3 *tp)
  11194. {
  11195. u32 nvcfg1, protect = 0;
  11196. nvcfg1 = tr32(NVRAM_CFG1);
  11197. /* NVRAM protection for TPM */
  11198. if (nvcfg1 & (1 << 27)) {
  11199. tg3_flag_set(tp, PROTECTED_NVRAM);
  11200. protect = 1;
  11201. }
  11202. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  11203. switch (nvcfg1) {
  11204. case FLASH_5761VENDOR_ATMEL_ADB021D:
  11205. case FLASH_5761VENDOR_ATMEL_ADB041D:
  11206. case FLASH_5761VENDOR_ATMEL_ADB081D:
  11207. case FLASH_5761VENDOR_ATMEL_ADB161D:
  11208. case FLASH_5761VENDOR_ATMEL_MDB021D:
  11209. case FLASH_5761VENDOR_ATMEL_MDB041D:
  11210. case FLASH_5761VENDOR_ATMEL_MDB081D:
  11211. case FLASH_5761VENDOR_ATMEL_MDB161D:
  11212. tp->nvram_jedecnum = JEDEC_ATMEL;
  11213. tg3_flag_set(tp, NVRAM_BUFFERED);
  11214. tg3_flag_set(tp, FLASH);
  11215. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11216. tp->nvram_pagesize = 256;
  11217. break;
  11218. case FLASH_5761VENDOR_ST_A_M45PE20:
  11219. case FLASH_5761VENDOR_ST_A_M45PE40:
  11220. case FLASH_5761VENDOR_ST_A_M45PE80:
  11221. case FLASH_5761VENDOR_ST_A_M45PE16:
  11222. case FLASH_5761VENDOR_ST_M_M45PE20:
  11223. case FLASH_5761VENDOR_ST_M_M45PE40:
  11224. case FLASH_5761VENDOR_ST_M_M45PE80:
  11225. case FLASH_5761VENDOR_ST_M_M45PE16:
  11226. tp->nvram_jedecnum = JEDEC_ST;
  11227. tg3_flag_set(tp, NVRAM_BUFFERED);
  11228. tg3_flag_set(tp, FLASH);
  11229. tp->nvram_pagesize = 256;
  11230. break;
  11231. }
  11232. if (protect) {
  11233. tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
  11234. } else {
  11235. switch (nvcfg1) {
  11236. case FLASH_5761VENDOR_ATMEL_ADB161D:
  11237. case FLASH_5761VENDOR_ATMEL_MDB161D:
  11238. case FLASH_5761VENDOR_ST_A_M45PE16:
  11239. case FLASH_5761VENDOR_ST_M_M45PE16:
  11240. tp->nvram_size = TG3_NVRAM_SIZE_2MB;
  11241. break;
  11242. case FLASH_5761VENDOR_ATMEL_ADB081D:
  11243. case FLASH_5761VENDOR_ATMEL_MDB081D:
  11244. case FLASH_5761VENDOR_ST_A_M45PE80:
  11245. case FLASH_5761VENDOR_ST_M_M45PE80:
  11246. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  11247. break;
  11248. case FLASH_5761VENDOR_ATMEL_ADB041D:
  11249. case FLASH_5761VENDOR_ATMEL_MDB041D:
  11250. case FLASH_5761VENDOR_ST_A_M45PE40:
  11251. case FLASH_5761VENDOR_ST_M_M45PE40:
  11252. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11253. break;
  11254. case FLASH_5761VENDOR_ATMEL_ADB021D:
  11255. case FLASH_5761VENDOR_ATMEL_MDB021D:
  11256. case FLASH_5761VENDOR_ST_A_M45PE20:
  11257. case FLASH_5761VENDOR_ST_M_M45PE20:
  11258. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11259. break;
  11260. }
  11261. }
  11262. }
  11263. static void tg3_get_5906_nvram_info(struct tg3 *tp)
  11264. {
  11265. tp->nvram_jedecnum = JEDEC_ATMEL;
  11266. tg3_flag_set(tp, NVRAM_BUFFERED);
  11267. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11268. }
  11269. static void tg3_get_57780_nvram_info(struct tg3 *tp)
  11270. {
  11271. u32 nvcfg1;
  11272. nvcfg1 = tr32(NVRAM_CFG1);
  11273. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11274. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  11275. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  11276. tp->nvram_jedecnum = JEDEC_ATMEL;
  11277. tg3_flag_set(tp, NVRAM_BUFFERED);
  11278. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11279. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11280. tw32(NVRAM_CFG1, nvcfg1);
  11281. return;
  11282. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11283. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  11284. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  11285. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  11286. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  11287. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  11288. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  11289. tp->nvram_jedecnum = JEDEC_ATMEL;
  11290. tg3_flag_set(tp, NVRAM_BUFFERED);
  11291. tg3_flag_set(tp, FLASH);
  11292. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11293. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  11294. case FLASH_57780VENDOR_ATMEL_AT45DB011D:
  11295. case FLASH_57780VENDOR_ATMEL_AT45DB011B:
  11296. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11297. break;
  11298. case FLASH_57780VENDOR_ATMEL_AT45DB021D:
  11299. case FLASH_57780VENDOR_ATMEL_AT45DB021B:
  11300. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11301. break;
  11302. case FLASH_57780VENDOR_ATMEL_AT45DB041D:
  11303. case FLASH_57780VENDOR_ATMEL_AT45DB041B:
  11304. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11305. break;
  11306. }
  11307. break;
  11308. case FLASH_5752VENDOR_ST_M45PE10:
  11309. case FLASH_5752VENDOR_ST_M45PE20:
  11310. case FLASH_5752VENDOR_ST_M45PE40:
  11311. tp->nvram_jedecnum = JEDEC_ST;
  11312. tg3_flag_set(tp, NVRAM_BUFFERED);
  11313. tg3_flag_set(tp, FLASH);
  11314. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11315. case FLASH_5752VENDOR_ST_M45PE10:
  11316. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11317. break;
  11318. case FLASH_5752VENDOR_ST_M45PE20:
  11319. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11320. break;
  11321. case FLASH_5752VENDOR_ST_M45PE40:
  11322. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11323. break;
  11324. }
  11325. break;
  11326. default:
  11327. tg3_flag_set(tp, NO_NVRAM);
  11328. return;
  11329. }
  11330. tg3_nvram_get_pagesize(tp, nvcfg1);
  11331. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  11332. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11333. }
  11334. static void tg3_get_5717_nvram_info(struct tg3 *tp)
  11335. {
  11336. u32 nvcfg1;
  11337. nvcfg1 = tr32(NVRAM_CFG1);
  11338. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11339. case FLASH_5717VENDOR_ATMEL_EEPROM:
  11340. case FLASH_5717VENDOR_MICRO_EEPROM:
  11341. tp->nvram_jedecnum = JEDEC_ATMEL;
  11342. tg3_flag_set(tp, NVRAM_BUFFERED);
  11343. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11344. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11345. tw32(NVRAM_CFG1, nvcfg1);
  11346. return;
  11347. case FLASH_5717VENDOR_ATMEL_MDB011D:
  11348. case FLASH_5717VENDOR_ATMEL_ADB011B:
  11349. case FLASH_5717VENDOR_ATMEL_ADB011D:
  11350. case FLASH_5717VENDOR_ATMEL_MDB021D:
  11351. case FLASH_5717VENDOR_ATMEL_ADB021B:
  11352. case FLASH_5717VENDOR_ATMEL_ADB021D:
  11353. case FLASH_5717VENDOR_ATMEL_45USPT:
  11354. tp->nvram_jedecnum = JEDEC_ATMEL;
  11355. tg3_flag_set(tp, NVRAM_BUFFERED);
  11356. tg3_flag_set(tp, FLASH);
  11357. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11358. case FLASH_5717VENDOR_ATMEL_MDB021D:
  11359. /* Detect size with tg3_nvram_get_size() */
  11360. break;
  11361. case FLASH_5717VENDOR_ATMEL_ADB021B:
  11362. case FLASH_5717VENDOR_ATMEL_ADB021D:
  11363. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11364. break;
  11365. default:
  11366. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11367. break;
  11368. }
  11369. break;
  11370. case FLASH_5717VENDOR_ST_M_M25PE10:
  11371. case FLASH_5717VENDOR_ST_A_M25PE10:
  11372. case FLASH_5717VENDOR_ST_M_M45PE10:
  11373. case FLASH_5717VENDOR_ST_A_M45PE10:
  11374. case FLASH_5717VENDOR_ST_M_M25PE20:
  11375. case FLASH_5717VENDOR_ST_A_M25PE20:
  11376. case FLASH_5717VENDOR_ST_M_M45PE20:
  11377. case FLASH_5717VENDOR_ST_A_M45PE20:
  11378. case FLASH_5717VENDOR_ST_25USPT:
  11379. case FLASH_5717VENDOR_ST_45USPT:
  11380. tp->nvram_jedecnum = JEDEC_ST;
  11381. tg3_flag_set(tp, NVRAM_BUFFERED);
  11382. tg3_flag_set(tp, FLASH);
  11383. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  11384. case FLASH_5717VENDOR_ST_M_M25PE20:
  11385. case FLASH_5717VENDOR_ST_M_M45PE20:
  11386. /* Detect size with tg3_nvram_get_size() */
  11387. break;
  11388. case FLASH_5717VENDOR_ST_A_M25PE20:
  11389. case FLASH_5717VENDOR_ST_A_M45PE20:
  11390. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11391. break;
  11392. default:
  11393. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11394. break;
  11395. }
  11396. break;
  11397. default:
  11398. tg3_flag_set(tp, NO_NVRAM);
  11399. return;
  11400. }
  11401. tg3_nvram_get_pagesize(tp, nvcfg1);
  11402. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  11403. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11404. }
  11405. static void tg3_get_5720_nvram_info(struct tg3 *tp)
  11406. {
  11407. u32 nvcfg1, nvmpinstrp;
  11408. nvcfg1 = tr32(NVRAM_CFG1);
  11409. nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
  11410. if (tg3_asic_rev(tp) == ASIC_REV_5762) {
  11411. if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
  11412. tg3_flag_set(tp, NO_NVRAM);
  11413. return;
  11414. }
  11415. switch (nvmpinstrp) {
  11416. case FLASH_5762_EEPROM_HD:
  11417. nvmpinstrp = FLASH_5720_EEPROM_HD;
  11418. break;
  11419. case FLASH_5762_EEPROM_LD:
  11420. nvmpinstrp = FLASH_5720_EEPROM_LD;
  11421. break;
  11422. }
  11423. }
  11424. switch (nvmpinstrp) {
  11425. case FLASH_5720_EEPROM_HD:
  11426. case FLASH_5720_EEPROM_LD:
  11427. tp->nvram_jedecnum = JEDEC_ATMEL;
  11428. tg3_flag_set(tp, NVRAM_BUFFERED);
  11429. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  11430. tw32(NVRAM_CFG1, nvcfg1);
  11431. if (nvmpinstrp == FLASH_5720_EEPROM_HD)
  11432. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  11433. else
  11434. tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
  11435. return;
  11436. case FLASH_5720VENDOR_M_ATMEL_DB011D:
  11437. case FLASH_5720VENDOR_A_ATMEL_DB011B:
  11438. case FLASH_5720VENDOR_A_ATMEL_DB011D:
  11439. case FLASH_5720VENDOR_M_ATMEL_DB021D:
  11440. case FLASH_5720VENDOR_A_ATMEL_DB021B:
  11441. case FLASH_5720VENDOR_A_ATMEL_DB021D:
  11442. case FLASH_5720VENDOR_M_ATMEL_DB041D:
  11443. case FLASH_5720VENDOR_A_ATMEL_DB041B:
  11444. case FLASH_5720VENDOR_A_ATMEL_DB041D:
  11445. case FLASH_5720VENDOR_M_ATMEL_DB081D:
  11446. case FLASH_5720VENDOR_A_ATMEL_DB081D:
  11447. case FLASH_5720VENDOR_ATMEL_45USPT:
  11448. tp->nvram_jedecnum = JEDEC_ATMEL;
  11449. tg3_flag_set(tp, NVRAM_BUFFERED);
  11450. tg3_flag_set(tp, FLASH);
  11451. switch (nvmpinstrp) {
  11452. case FLASH_5720VENDOR_M_ATMEL_DB021D:
  11453. case FLASH_5720VENDOR_A_ATMEL_DB021B:
  11454. case FLASH_5720VENDOR_A_ATMEL_DB021D:
  11455. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11456. break;
  11457. case FLASH_5720VENDOR_M_ATMEL_DB041D:
  11458. case FLASH_5720VENDOR_A_ATMEL_DB041B:
  11459. case FLASH_5720VENDOR_A_ATMEL_DB041D:
  11460. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11461. break;
  11462. case FLASH_5720VENDOR_M_ATMEL_DB081D:
  11463. case FLASH_5720VENDOR_A_ATMEL_DB081D:
  11464. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  11465. break;
  11466. default:
  11467. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  11468. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11469. break;
  11470. }
  11471. break;
  11472. case FLASH_5720VENDOR_M_ST_M25PE10:
  11473. case FLASH_5720VENDOR_M_ST_M45PE10:
  11474. case FLASH_5720VENDOR_A_ST_M25PE10:
  11475. case FLASH_5720VENDOR_A_ST_M45PE10:
  11476. case FLASH_5720VENDOR_M_ST_M25PE20:
  11477. case FLASH_5720VENDOR_M_ST_M45PE20:
  11478. case FLASH_5720VENDOR_A_ST_M25PE20:
  11479. case FLASH_5720VENDOR_A_ST_M45PE20:
  11480. case FLASH_5720VENDOR_M_ST_M25PE40:
  11481. case FLASH_5720VENDOR_M_ST_M45PE40:
  11482. case FLASH_5720VENDOR_A_ST_M25PE40:
  11483. case FLASH_5720VENDOR_A_ST_M45PE40:
  11484. case FLASH_5720VENDOR_M_ST_M25PE80:
  11485. case FLASH_5720VENDOR_M_ST_M45PE80:
  11486. case FLASH_5720VENDOR_A_ST_M25PE80:
  11487. case FLASH_5720VENDOR_A_ST_M45PE80:
  11488. case FLASH_5720VENDOR_ST_25USPT:
  11489. case FLASH_5720VENDOR_ST_45USPT:
  11490. tp->nvram_jedecnum = JEDEC_ST;
  11491. tg3_flag_set(tp, NVRAM_BUFFERED);
  11492. tg3_flag_set(tp, FLASH);
  11493. switch (nvmpinstrp) {
  11494. case FLASH_5720VENDOR_M_ST_M25PE20:
  11495. case FLASH_5720VENDOR_M_ST_M45PE20:
  11496. case FLASH_5720VENDOR_A_ST_M25PE20:
  11497. case FLASH_5720VENDOR_A_ST_M45PE20:
  11498. tp->nvram_size = TG3_NVRAM_SIZE_256KB;
  11499. break;
  11500. case FLASH_5720VENDOR_M_ST_M25PE40:
  11501. case FLASH_5720VENDOR_M_ST_M45PE40:
  11502. case FLASH_5720VENDOR_A_ST_M25PE40:
  11503. case FLASH_5720VENDOR_A_ST_M45PE40:
  11504. tp->nvram_size = TG3_NVRAM_SIZE_512KB;
  11505. break;
  11506. case FLASH_5720VENDOR_M_ST_M25PE80:
  11507. case FLASH_5720VENDOR_M_ST_M45PE80:
  11508. case FLASH_5720VENDOR_A_ST_M25PE80:
  11509. case FLASH_5720VENDOR_A_ST_M45PE80:
  11510. tp->nvram_size = TG3_NVRAM_SIZE_1MB;
  11511. break;
  11512. default:
  11513. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  11514. tp->nvram_size = TG3_NVRAM_SIZE_128KB;
  11515. break;
  11516. }
  11517. break;
  11518. default:
  11519. tg3_flag_set(tp, NO_NVRAM);
  11520. return;
  11521. }
  11522. tg3_nvram_get_pagesize(tp, nvcfg1);
  11523. if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
  11524. tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
  11525. if (tg3_asic_rev(tp) == ASIC_REV_5762) {
  11526. u32 val;
  11527. if (tg3_nvram_read(tp, 0, &val))
  11528. return;
  11529. if (val != TG3_EEPROM_MAGIC &&
  11530. (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
  11531. tg3_flag_set(tp, NO_NVRAM);
  11532. }
  11533. }
  11534. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  11535. static void tg3_nvram_init(struct tg3 *tp)
  11536. {
  11537. if (tg3_flag(tp, IS_SSB_CORE)) {
  11538. /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
  11539. tg3_flag_clear(tp, NVRAM);
  11540. tg3_flag_clear(tp, NVRAM_BUFFERED);
  11541. tg3_flag_set(tp, NO_NVRAM);
  11542. return;
  11543. }
  11544. tw32_f(GRC_EEPROM_ADDR,
  11545. (EEPROM_ADDR_FSM_RESET |
  11546. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  11547. EEPROM_ADDR_CLKPERD_SHIFT)));
  11548. msleep(1);
  11549. /* Enable seeprom accesses. */
  11550. tw32_f(GRC_LOCAL_CTRL,
  11551. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  11552. udelay(100);
  11553. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  11554. tg3_asic_rev(tp) != ASIC_REV_5701) {
  11555. tg3_flag_set(tp, NVRAM);
  11556. if (tg3_nvram_lock(tp)) {
  11557. netdev_warn(tp->dev,
  11558. "Cannot get nvram lock, %s failed\n",
  11559. __func__);
  11560. return;
  11561. }
  11562. tg3_enable_nvram_access(tp);
  11563. tp->nvram_size = 0;
  11564. if (tg3_asic_rev(tp) == ASIC_REV_5752)
  11565. tg3_get_5752_nvram_info(tp);
  11566. else if (tg3_asic_rev(tp) == ASIC_REV_5755)
  11567. tg3_get_5755_nvram_info(tp);
  11568. else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
  11569. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  11570. tg3_asic_rev(tp) == ASIC_REV_5785)
  11571. tg3_get_5787_nvram_info(tp);
  11572. else if (tg3_asic_rev(tp) == ASIC_REV_5761)
  11573. tg3_get_5761_nvram_info(tp);
  11574. else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  11575. tg3_get_5906_nvram_info(tp);
  11576. else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
  11577. tg3_flag(tp, 57765_CLASS))
  11578. tg3_get_57780_nvram_info(tp);
  11579. else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  11580. tg3_asic_rev(tp) == ASIC_REV_5719)
  11581. tg3_get_5717_nvram_info(tp);
  11582. else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  11583. tg3_asic_rev(tp) == ASIC_REV_5762)
  11584. tg3_get_5720_nvram_info(tp);
  11585. else
  11586. tg3_get_nvram_info(tp);
  11587. if (tp->nvram_size == 0)
  11588. tg3_get_nvram_size(tp);
  11589. tg3_disable_nvram_access(tp);
  11590. tg3_nvram_unlock(tp);
  11591. } else {
  11592. tg3_flag_clear(tp, NVRAM);
  11593. tg3_flag_clear(tp, NVRAM_BUFFERED);
  11594. tg3_get_eeprom_size(tp);
  11595. }
  11596. }
  11597. struct subsys_tbl_ent {
  11598. u16 subsys_vendor, subsys_devid;
  11599. u32 phy_id;
  11600. };
  11601. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  11602. /* Broadcom boards. */
  11603. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11604. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
  11605. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11606. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
  11607. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11608. TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
  11609. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11610. TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
  11611. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11612. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
  11613. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11614. TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
  11615. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11616. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
  11617. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11618. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
  11619. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11620. TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
  11621. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11622. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
  11623. { TG3PCI_SUBVENDOR_ID_BROADCOM,
  11624. TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
  11625. /* 3com boards. */
  11626. { TG3PCI_SUBVENDOR_ID_3COM,
  11627. TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
  11628. { TG3PCI_SUBVENDOR_ID_3COM,
  11629. TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
  11630. { TG3PCI_SUBVENDOR_ID_3COM,
  11631. TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
  11632. { TG3PCI_SUBVENDOR_ID_3COM,
  11633. TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
  11634. { TG3PCI_SUBVENDOR_ID_3COM,
  11635. TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
  11636. /* DELL boards. */
  11637. { TG3PCI_SUBVENDOR_ID_DELL,
  11638. TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
  11639. { TG3PCI_SUBVENDOR_ID_DELL,
  11640. TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
  11641. { TG3PCI_SUBVENDOR_ID_DELL,
  11642. TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
  11643. { TG3PCI_SUBVENDOR_ID_DELL,
  11644. TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
  11645. /* Compaq boards. */
  11646. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  11647. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
  11648. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  11649. TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
  11650. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  11651. TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
  11652. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  11653. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
  11654. { TG3PCI_SUBVENDOR_ID_COMPAQ,
  11655. TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
  11656. /* IBM boards. */
  11657. { TG3PCI_SUBVENDOR_ID_IBM,
  11658. TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
  11659. };
  11660. static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
  11661. {
  11662. int i;
  11663. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  11664. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  11665. tp->pdev->subsystem_vendor) &&
  11666. (subsys_id_to_phy_id[i].subsys_devid ==
  11667. tp->pdev->subsystem_device))
  11668. return &subsys_id_to_phy_id[i];
  11669. }
  11670. return NULL;
  11671. }
  11672. static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  11673. {
  11674. u32 val;
  11675. tp->phy_id = TG3_PHY_ID_INVALID;
  11676. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  11677. /* Assume an onboard device and WOL capable by default. */
  11678. tg3_flag_set(tp, EEPROM_WRITE_PROT);
  11679. tg3_flag_set(tp, WOL_CAP);
  11680. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  11681. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  11682. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  11683. tg3_flag_set(tp, IS_NIC);
  11684. }
  11685. val = tr32(VCPU_CFGSHDW);
  11686. if (val & VCPU_CFGSHDW_ASPM_DBNC)
  11687. tg3_flag_set(tp, ASPM_WORKAROUND);
  11688. if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
  11689. (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
  11690. tg3_flag_set(tp, WOL_ENABLE);
  11691. device_set_wakeup_enable(&tp->pdev->dev, true);
  11692. }
  11693. goto done;
  11694. }
  11695. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  11696. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  11697. u32 nic_cfg, led_cfg;
  11698. u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
  11699. int eeprom_phy_serdes = 0;
  11700. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  11701. tp->nic_sram_data_cfg = nic_cfg;
  11702. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  11703. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  11704. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  11705. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  11706. tg3_asic_rev(tp) != ASIC_REV_5703 &&
  11707. (ver > 0) && (ver < 0x100))
  11708. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  11709. if (tg3_asic_rev(tp) == ASIC_REV_5785)
  11710. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
  11711. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  11712. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  11713. eeprom_phy_serdes = 1;
  11714. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  11715. if (nic_phy_id != 0) {
  11716. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  11717. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  11718. eeprom_phy_id = (id1 >> 16) << 10;
  11719. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  11720. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  11721. } else
  11722. eeprom_phy_id = 0;
  11723. tp->phy_id = eeprom_phy_id;
  11724. if (eeprom_phy_serdes) {
  11725. if (!tg3_flag(tp, 5705_PLUS))
  11726. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  11727. else
  11728. tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
  11729. }
  11730. if (tg3_flag(tp, 5750_PLUS))
  11731. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  11732. SHASTA_EXT_LED_MODE_MASK);
  11733. else
  11734. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  11735. switch (led_cfg) {
  11736. default:
  11737. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  11738. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  11739. break;
  11740. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  11741. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  11742. break;
  11743. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  11744. tp->led_ctrl = LED_CTRL_MODE_MAC;
  11745. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  11746. * read on some older 5700/5701 bootcode.
  11747. */
  11748. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  11749. tg3_asic_rev(tp) == ASIC_REV_5701)
  11750. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  11751. break;
  11752. case SHASTA_EXT_LED_SHARED:
  11753. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  11754. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
  11755. tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
  11756. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  11757. LED_CTRL_MODE_PHY_2);
  11758. break;
  11759. case SHASTA_EXT_LED_MAC:
  11760. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  11761. break;
  11762. case SHASTA_EXT_LED_COMBO:
  11763. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  11764. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
  11765. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  11766. LED_CTRL_MODE_PHY_2);
  11767. break;
  11768. }
  11769. if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
  11770. tg3_asic_rev(tp) == ASIC_REV_5701) &&
  11771. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  11772. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  11773. if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
  11774. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  11775. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  11776. tg3_flag_set(tp, EEPROM_WRITE_PROT);
  11777. if ((tp->pdev->subsystem_vendor ==
  11778. PCI_VENDOR_ID_ARIMA) &&
  11779. (tp->pdev->subsystem_device == 0x205a ||
  11780. tp->pdev->subsystem_device == 0x2063))
  11781. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  11782. } else {
  11783. tg3_flag_clear(tp, EEPROM_WRITE_PROT);
  11784. tg3_flag_set(tp, IS_NIC);
  11785. }
  11786. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  11787. tg3_flag_set(tp, ENABLE_ASF);
  11788. if (tg3_flag(tp, 5750_PLUS))
  11789. tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
  11790. }
  11791. if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
  11792. tg3_flag(tp, 5750_PLUS))
  11793. tg3_flag_set(tp, ENABLE_APE);
  11794. if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
  11795. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  11796. tg3_flag_clear(tp, WOL_CAP);
  11797. if (tg3_flag(tp, WOL_CAP) &&
  11798. (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
  11799. tg3_flag_set(tp, WOL_ENABLE);
  11800. device_set_wakeup_enable(&tp->pdev->dev, true);
  11801. }
  11802. if (cfg2 & (1 << 17))
  11803. tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
  11804. /* serdes signal pre-emphasis in register 0x590 set by */
  11805. /* bootcode if bit 18 is set */
  11806. if (cfg2 & (1 << 18))
  11807. tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
  11808. if ((tg3_flag(tp, 57765_PLUS) ||
  11809. (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  11810. tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
  11811. (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
  11812. tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
  11813. if (tg3_flag(tp, PCI_EXPRESS) &&
  11814. tg3_asic_rev(tp) != ASIC_REV_5785 &&
  11815. !tg3_flag(tp, 57765_PLUS)) {
  11816. u32 cfg3;
  11817. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  11818. if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
  11819. tg3_flag_set(tp, ASPM_WORKAROUND);
  11820. }
  11821. if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
  11822. tg3_flag_set(tp, RGMII_INBAND_DISABLE);
  11823. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
  11824. tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
  11825. if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
  11826. tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
  11827. }
  11828. done:
  11829. if (tg3_flag(tp, WOL_CAP))
  11830. device_set_wakeup_enable(&tp->pdev->dev,
  11831. tg3_flag(tp, WOL_ENABLE));
  11832. else
  11833. device_set_wakeup_capable(&tp->pdev->dev, false);
  11834. }
  11835. static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
  11836. {
  11837. int i, err;
  11838. u32 val2, off = offset * 8;
  11839. err = tg3_nvram_lock(tp);
  11840. if (err)
  11841. return err;
  11842. tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
  11843. tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
  11844. APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
  11845. tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
  11846. udelay(10);
  11847. for (i = 0; i < 100; i++) {
  11848. val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
  11849. if (val2 & APE_OTP_STATUS_CMD_DONE) {
  11850. *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
  11851. break;
  11852. }
  11853. udelay(10);
  11854. }
  11855. tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
  11856. tg3_nvram_unlock(tp);
  11857. if (val2 & APE_OTP_STATUS_CMD_DONE)
  11858. return 0;
  11859. return -EBUSY;
  11860. }
  11861. static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  11862. {
  11863. int i;
  11864. u32 val;
  11865. tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  11866. tw32(OTP_CTRL, cmd);
  11867. /* Wait for up to 1 ms for command to execute. */
  11868. for (i = 0; i < 100; i++) {
  11869. val = tr32(OTP_STATUS);
  11870. if (val & OTP_STATUS_CMD_DONE)
  11871. break;
  11872. udelay(10);
  11873. }
  11874. return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  11875. }
  11876. /* Read the gphy configuration from the OTP region of the chip. The gphy
  11877. * configuration is a 32-bit value that straddles the alignment boundary.
  11878. * We do two 32-bit reads and then shift and merge the results.
  11879. */
  11880. static u32 tg3_read_otp_phycfg(struct tg3 *tp)
  11881. {
  11882. u32 bhalf_otp, thalf_otp;
  11883. tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  11884. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  11885. return 0;
  11886. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  11887. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  11888. return 0;
  11889. thalf_otp = tr32(OTP_READ_DATA);
  11890. tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  11891. if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  11892. return 0;
  11893. bhalf_otp = tr32(OTP_READ_DATA);
  11894. return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  11895. }
  11896. static void tg3_phy_init_link_config(struct tg3 *tp)
  11897. {
  11898. u32 adv = ADVERTISED_Autoneg;
  11899. if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
  11900. adv |= ADVERTISED_1000baseT_Half |
  11901. ADVERTISED_1000baseT_Full;
  11902. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  11903. adv |= ADVERTISED_100baseT_Half |
  11904. ADVERTISED_100baseT_Full |
  11905. ADVERTISED_10baseT_Half |
  11906. ADVERTISED_10baseT_Full |
  11907. ADVERTISED_TP;
  11908. else
  11909. adv |= ADVERTISED_FIBRE;
  11910. tp->link_config.advertising = adv;
  11911. tp->link_config.speed = SPEED_UNKNOWN;
  11912. tp->link_config.duplex = DUPLEX_UNKNOWN;
  11913. tp->link_config.autoneg = AUTONEG_ENABLE;
  11914. tp->link_config.active_speed = SPEED_UNKNOWN;
  11915. tp->link_config.active_duplex = DUPLEX_UNKNOWN;
  11916. tp->old_link = -1;
  11917. }
  11918. static int tg3_phy_probe(struct tg3 *tp)
  11919. {
  11920. u32 hw_phy_id_1, hw_phy_id_2;
  11921. u32 hw_phy_id, hw_phy_id_masked;
  11922. int err;
  11923. /* flow control autonegotiation is default behavior */
  11924. tg3_flag_set(tp, PAUSE_AUTONEG);
  11925. tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  11926. if (tg3_flag(tp, ENABLE_APE)) {
  11927. switch (tp->pci_fn) {
  11928. case 0:
  11929. tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
  11930. break;
  11931. case 1:
  11932. tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
  11933. break;
  11934. case 2:
  11935. tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
  11936. break;
  11937. case 3:
  11938. tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
  11939. break;
  11940. }
  11941. }
  11942. if (tg3_flag(tp, USE_PHYLIB))
  11943. return tg3_phy_init(tp);
  11944. /* Reading the PHY ID register can conflict with ASF
  11945. * firmware access to the PHY hardware.
  11946. */
  11947. err = 0;
  11948. if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
  11949. hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
  11950. } else {
  11951. /* Now read the physical PHY_ID from the chip and verify
  11952. * that it is sane. If it doesn't look good, we fall back
  11953. * to either the hard-coded table based PHY_ID and failing
  11954. * that the value found in the eeprom area.
  11955. */
  11956. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  11957. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  11958. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  11959. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  11960. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  11961. hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
  11962. }
  11963. if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
  11964. tp->phy_id = hw_phy_id;
  11965. if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
  11966. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  11967. else
  11968. tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
  11969. } else {
  11970. if (tp->phy_id != TG3_PHY_ID_INVALID) {
  11971. /* Do nothing, phy ID already set up in
  11972. * tg3_get_eeprom_hw_cfg().
  11973. */
  11974. } else {
  11975. struct subsys_tbl_ent *p;
  11976. /* No eeprom signature? Try the hardcoded
  11977. * subsys device table.
  11978. */
  11979. p = tg3_lookup_by_subsys(tp);
  11980. if (p) {
  11981. tp->phy_id = p->phy_id;
  11982. } else if (!tg3_flag(tp, IS_SSB_CORE)) {
  11983. /* For now we saw the IDs 0xbc050cd0,
  11984. * 0xbc050f80 and 0xbc050c30 on devices
  11985. * connected to an BCM4785 and there are
  11986. * probably more. Just assume that the phy is
  11987. * supported when it is connected to a SSB core
  11988. * for now.
  11989. */
  11990. return -ENODEV;
  11991. }
  11992. if (!tp->phy_id ||
  11993. tp->phy_id == TG3_PHY_ID_BCM8002)
  11994. tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
  11995. }
  11996. }
  11997. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  11998. (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  11999. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  12000. tg3_asic_rev(tp) == ASIC_REV_5762 ||
  12001. (tg3_asic_rev(tp) == ASIC_REV_5717 &&
  12002. tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
  12003. (tg3_asic_rev(tp) == ASIC_REV_57765 &&
  12004. tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0)))
  12005. tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
  12006. tg3_phy_init_link_config(tp);
  12007. if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
  12008. !tg3_flag(tp, ENABLE_APE) &&
  12009. !tg3_flag(tp, ENABLE_ASF)) {
  12010. u32 bmsr, dummy;
  12011. tg3_readphy(tp, MII_BMSR, &bmsr);
  12012. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  12013. (bmsr & BMSR_LSTATUS))
  12014. goto skip_phy_reset;
  12015. err = tg3_phy_reset(tp);
  12016. if (err)
  12017. return err;
  12018. tg3_phy_set_wirespeed(tp);
  12019. if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
  12020. tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
  12021. tp->link_config.flowctrl);
  12022. tg3_writephy(tp, MII_BMCR,
  12023. BMCR_ANENABLE | BMCR_ANRESTART);
  12024. }
  12025. }
  12026. skip_phy_reset:
  12027. if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
  12028. err = tg3_init_5401phy_dsp(tp);
  12029. if (err)
  12030. return err;
  12031. err = tg3_init_5401phy_dsp(tp);
  12032. }
  12033. return err;
  12034. }
  12035. static void tg3_read_vpd(struct tg3 *tp)
  12036. {
  12037. u8 *vpd_data;
  12038. unsigned int block_end, rosize, len;
  12039. u32 vpdlen;
  12040. int j, i = 0;
  12041. vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
  12042. if (!vpd_data)
  12043. goto out_no_vpd;
  12044. i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
  12045. if (i < 0)
  12046. goto out_not_found;
  12047. rosize = pci_vpd_lrdt_size(&vpd_data[i]);
  12048. block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
  12049. i += PCI_VPD_LRDT_TAG_SIZE;
  12050. if (block_end > vpdlen)
  12051. goto out_not_found;
  12052. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12053. PCI_VPD_RO_KEYWORD_MFR_ID);
  12054. if (j > 0) {
  12055. len = pci_vpd_info_field_size(&vpd_data[j]);
  12056. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  12057. if (j + len > block_end || len != 4 ||
  12058. memcmp(&vpd_data[j], "1028", 4))
  12059. goto partno;
  12060. j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12061. PCI_VPD_RO_KEYWORD_VENDOR0);
  12062. if (j < 0)
  12063. goto partno;
  12064. len = pci_vpd_info_field_size(&vpd_data[j]);
  12065. j += PCI_VPD_INFO_FLD_HDR_SIZE;
  12066. if (j + len > block_end)
  12067. goto partno;
  12068. memcpy(tp->fw_ver, &vpd_data[j], len);
  12069. strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
  12070. }
  12071. partno:
  12072. i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
  12073. PCI_VPD_RO_KEYWORD_PARTNO);
  12074. if (i < 0)
  12075. goto out_not_found;
  12076. len = pci_vpd_info_field_size(&vpd_data[i]);
  12077. i += PCI_VPD_INFO_FLD_HDR_SIZE;
  12078. if (len > TG3_BPN_SIZE ||
  12079. (len + i) > vpdlen)
  12080. goto out_not_found;
  12081. memcpy(tp->board_part_number, &vpd_data[i], len);
  12082. out_not_found:
  12083. kfree(vpd_data);
  12084. if (tp->board_part_number[0])
  12085. return;
  12086. out_no_vpd:
  12087. if (tg3_asic_rev(tp) == ASIC_REV_5717) {
  12088. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  12089. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
  12090. strcpy(tp->board_part_number, "BCM5717");
  12091. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
  12092. strcpy(tp->board_part_number, "BCM5718");
  12093. else
  12094. goto nomatch;
  12095. } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
  12096. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
  12097. strcpy(tp->board_part_number, "BCM57780");
  12098. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
  12099. strcpy(tp->board_part_number, "BCM57760");
  12100. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
  12101. strcpy(tp->board_part_number, "BCM57790");
  12102. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
  12103. strcpy(tp->board_part_number, "BCM57788");
  12104. else
  12105. goto nomatch;
  12106. } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
  12107. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
  12108. strcpy(tp->board_part_number, "BCM57761");
  12109. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
  12110. strcpy(tp->board_part_number, "BCM57765");
  12111. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
  12112. strcpy(tp->board_part_number, "BCM57781");
  12113. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
  12114. strcpy(tp->board_part_number, "BCM57785");
  12115. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
  12116. strcpy(tp->board_part_number, "BCM57791");
  12117. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
  12118. strcpy(tp->board_part_number, "BCM57795");
  12119. else
  12120. goto nomatch;
  12121. } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
  12122. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
  12123. strcpy(tp->board_part_number, "BCM57762");
  12124. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
  12125. strcpy(tp->board_part_number, "BCM57766");
  12126. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
  12127. strcpy(tp->board_part_number, "BCM57782");
  12128. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
  12129. strcpy(tp->board_part_number, "BCM57786");
  12130. else
  12131. goto nomatch;
  12132. } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  12133. strcpy(tp->board_part_number, "BCM95906");
  12134. } else {
  12135. nomatch:
  12136. strcpy(tp->board_part_number, "none");
  12137. }
  12138. }
  12139. static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
  12140. {
  12141. u32 val;
  12142. if (tg3_nvram_read(tp, offset, &val) ||
  12143. (val & 0xfc000000) != 0x0c000000 ||
  12144. tg3_nvram_read(tp, offset + 4, &val) ||
  12145. val != 0)
  12146. return 0;
  12147. return 1;
  12148. }
  12149. static void tg3_read_bc_ver(struct tg3 *tp)
  12150. {
  12151. u32 val, offset, start, ver_offset;
  12152. int i, dst_off;
  12153. bool newver = false;
  12154. if (tg3_nvram_read(tp, 0xc, &offset) ||
  12155. tg3_nvram_read(tp, 0x4, &start))
  12156. return;
  12157. offset = tg3_nvram_logical_addr(tp, offset);
  12158. if (tg3_nvram_read(tp, offset, &val))
  12159. return;
  12160. if ((val & 0xfc000000) == 0x0c000000) {
  12161. if (tg3_nvram_read(tp, offset + 4, &val))
  12162. return;
  12163. if (val == 0)
  12164. newver = true;
  12165. }
  12166. dst_off = strlen(tp->fw_ver);
  12167. if (newver) {
  12168. if (TG3_VER_SIZE - dst_off < 16 ||
  12169. tg3_nvram_read(tp, offset + 8, &ver_offset))
  12170. return;
  12171. offset = offset + ver_offset - start;
  12172. for (i = 0; i < 16; i += 4) {
  12173. __be32 v;
  12174. if (tg3_nvram_read_be32(tp, offset + i, &v))
  12175. return;
  12176. memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
  12177. }
  12178. } else {
  12179. u32 major, minor;
  12180. if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
  12181. return;
  12182. major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
  12183. TG3_NVM_BCVER_MAJSFT;
  12184. minor = ver_offset & TG3_NVM_BCVER_MINMSK;
  12185. snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
  12186. "v%d.%02d", major, minor);
  12187. }
  12188. }
  12189. static void tg3_read_hwsb_ver(struct tg3 *tp)
  12190. {
  12191. u32 val, major, minor;
  12192. /* Use native endian representation */
  12193. if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
  12194. return;
  12195. major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
  12196. TG3_NVM_HWSB_CFG1_MAJSFT;
  12197. minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
  12198. TG3_NVM_HWSB_CFG1_MINSFT;
  12199. snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
  12200. }
  12201. static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
  12202. {
  12203. u32 offset, major, minor, build;
  12204. strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
  12205. if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
  12206. return;
  12207. switch (val & TG3_EEPROM_SB_REVISION_MASK) {
  12208. case TG3_EEPROM_SB_REVISION_0:
  12209. offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
  12210. break;
  12211. case TG3_EEPROM_SB_REVISION_2:
  12212. offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
  12213. break;
  12214. case TG3_EEPROM_SB_REVISION_3:
  12215. offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
  12216. break;
  12217. case TG3_EEPROM_SB_REVISION_4:
  12218. offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
  12219. break;
  12220. case TG3_EEPROM_SB_REVISION_5:
  12221. offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
  12222. break;
  12223. case TG3_EEPROM_SB_REVISION_6:
  12224. offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
  12225. break;
  12226. default:
  12227. return;
  12228. }
  12229. if (tg3_nvram_read(tp, offset, &val))
  12230. return;
  12231. build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
  12232. TG3_EEPROM_SB_EDH_BLD_SHFT;
  12233. major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
  12234. TG3_EEPROM_SB_EDH_MAJ_SHFT;
  12235. minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
  12236. if (minor > 99 || build > 26)
  12237. return;
  12238. offset = strlen(tp->fw_ver);
  12239. snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
  12240. " v%d.%02d", major, minor);
  12241. if (build > 0) {
  12242. offset = strlen(tp->fw_ver);
  12243. if (offset < TG3_VER_SIZE - 1)
  12244. tp->fw_ver[offset] = 'a' + build - 1;
  12245. }
  12246. }
  12247. static void tg3_read_mgmtfw_ver(struct tg3 *tp)
  12248. {
  12249. u32 val, offset, start;
  12250. int i, vlen;
  12251. for (offset = TG3_NVM_DIR_START;
  12252. offset < TG3_NVM_DIR_END;
  12253. offset += TG3_NVM_DIRENT_SIZE) {
  12254. if (tg3_nvram_read(tp, offset, &val))
  12255. return;
  12256. if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
  12257. break;
  12258. }
  12259. if (offset == TG3_NVM_DIR_END)
  12260. return;
  12261. if (!tg3_flag(tp, 5705_PLUS))
  12262. start = 0x08000000;
  12263. else if (tg3_nvram_read(tp, offset - 4, &start))
  12264. return;
  12265. if (tg3_nvram_read(tp, offset + 4, &offset) ||
  12266. !tg3_fw_img_is_valid(tp, offset) ||
  12267. tg3_nvram_read(tp, offset + 8, &val))
  12268. return;
  12269. offset += val - start;
  12270. vlen = strlen(tp->fw_ver);
  12271. tp->fw_ver[vlen++] = ',';
  12272. tp->fw_ver[vlen++] = ' ';
  12273. for (i = 0; i < 4; i++) {
  12274. __be32 v;
  12275. if (tg3_nvram_read_be32(tp, offset, &v))
  12276. return;
  12277. offset += sizeof(v);
  12278. if (vlen > TG3_VER_SIZE - sizeof(v)) {
  12279. memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
  12280. break;
  12281. }
  12282. memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
  12283. vlen += sizeof(v);
  12284. }
  12285. }
  12286. static void tg3_probe_ncsi(struct tg3 *tp)
  12287. {
  12288. u32 apedata;
  12289. apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
  12290. if (apedata != APE_SEG_SIG_MAGIC)
  12291. return;
  12292. apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
  12293. if (!(apedata & APE_FW_STATUS_READY))
  12294. return;
  12295. if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
  12296. tg3_flag_set(tp, APE_HAS_NCSI);
  12297. }
  12298. static void tg3_read_dash_ver(struct tg3 *tp)
  12299. {
  12300. int vlen;
  12301. u32 apedata;
  12302. char *fwtype;
  12303. apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
  12304. if (tg3_flag(tp, APE_HAS_NCSI))
  12305. fwtype = "NCSI";
  12306. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
  12307. fwtype = "SMASH";
  12308. else
  12309. fwtype = "DASH";
  12310. vlen = strlen(tp->fw_ver);
  12311. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
  12312. fwtype,
  12313. (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
  12314. (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
  12315. (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
  12316. (apedata & APE_FW_VERSION_BLDMSK));
  12317. }
  12318. static void tg3_read_otp_ver(struct tg3 *tp)
  12319. {
  12320. u32 val, val2;
  12321. if (tg3_asic_rev(tp) != ASIC_REV_5762)
  12322. return;
  12323. if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
  12324. !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
  12325. TG3_OTP_MAGIC0_VALID(val)) {
  12326. u64 val64 = (u64) val << 32 | val2;
  12327. u32 ver = 0;
  12328. int i, vlen;
  12329. for (i = 0; i < 7; i++) {
  12330. if ((val64 & 0xff) == 0)
  12331. break;
  12332. ver = val64 & 0xff;
  12333. val64 >>= 8;
  12334. }
  12335. vlen = strlen(tp->fw_ver);
  12336. snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
  12337. }
  12338. }
  12339. static void tg3_read_fw_ver(struct tg3 *tp)
  12340. {
  12341. u32 val;
  12342. bool vpd_vers = false;
  12343. if (tp->fw_ver[0] != 0)
  12344. vpd_vers = true;
  12345. if (tg3_flag(tp, NO_NVRAM)) {
  12346. strcat(tp->fw_ver, "sb");
  12347. tg3_read_otp_ver(tp);
  12348. return;
  12349. }
  12350. if (tg3_nvram_read(tp, 0, &val))
  12351. return;
  12352. if (val == TG3_EEPROM_MAGIC)
  12353. tg3_read_bc_ver(tp);
  12354. else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
  12355. tg3_read_sb_ver(tp, val);
  12356. else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  12357. tg3_read_hwsb_ver(tp);
  12358. if (tg3_flag(tp, ENABLE_ASF)) {
  12359. if (tg3_flag(tp, ENABLE_APE)) {
  12360. tg3_probe_ncsi(tp);
  12361. if (!vpd_vers)
  12362. tg3_read_dash_ver(tp);
  12363. } else if (!vpd_vers) {
  12364. tg3_read_mgmtfw_ver(tp);
  12365. }
  12366. }
  12367. tp->fw_ver[TG3_VER_SIZE - 1] = 0;
  12368. }
  12369. static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
  12370. {
  12371. if (tg3_flag(tp, LRG_PROD_RING_CAP))
  12372. return TG3_RX_RET_MAX_SIZE_5717;
  12373. else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
  12374. return TG3_RX_RET_MAX_SIZE_5700;
  12375. else
  12376. return TG3_RX_RET_MAX_SIZE_5705;
  12377. }
  12378. static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
  12379. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  12380. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  12381. { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
  12382. { },
  12383. };
  12384. static struct pci_dev *tg3_find_peer(struct tg3 *tp)
  12385. {
  12386. struct pci_dev *peer;
  12387. unsigned int func, devnr = tp->pdev->devfn & ~7;
  12388. for (func = 0; func < 8; func++) {
  12389. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  12390. if (peer && peer != tp->pdev)
  12391. break;
  12392. pci_dev_put(peer);
  12393. }
  12394. /* 5704 can be configured in single-port mode, set peer to
  12395. * tp->pdev in that case.
  12396. */
  12397. if (!peer) {
  12398. peer = tp->pdev;
  12399. return peer;
  12400. }
  12401. /*
  12402. * We don't need to keep the refcount elevated; there's no way
  12403. * to remove one half of this device without removing the other
  12404. */
  12405. pci_dev_put(peer);
  12406. return peer;
  12407. }
  12408. static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
  12409. {
  12410. tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
  12411. if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
  12412. u32 reg;
  12413. /* All devices that use the alternate
  12414. * ASIC REV location have a CPMU.
  12415. */
  12416. tg3_flag_set(tp, CPMU_PRESENT);
  12417. if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  12418. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
  12419. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  12420. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
  12421. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
  12422. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
  12423. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
  12424. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727)
  12425. reg = TG3PCI_GEN2_PRODID_ASICREV;
  12426. else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
  12427. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
  12428. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
  12429. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
  12430. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
  12431. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
  12432. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
  12433. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
  12434. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
  12435. tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
  12436. reg = TG3PCI_GEN15_PRODID_ASICREV;
  12437. else
  12438. reg = TG3PCI_PRODID_ASICREV;
  12439. pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
  12440. }
  12441. /* Wrong chip ID in 5752 A0. This code can be removed later
  12442. * as A0 is not in production.
  12443. */
  12444. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
  12445. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  12446. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
  12447. tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
  12448. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  12449. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  12450. tg3_asic_rev(tp) == ASIC_REV_5720)
  12451. tg3_flag_set(tp, 5717_PLUS);
  12452. if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
  12453. tg3_asic_rev(tp) == ASIC_REV_57766)
  12454. tg3_flag_set(tp, 57765_CLASS);
  12455. if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
  12456. tg3_asic_rev(tp) == ASIC_REV_5762)
  12457. tg3_flag_set(tp, 57765_PLUS);
  12458. /* Intentionally exclude ASIC_REV_5906 */
  12459. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  12460. tg3_asic_rev(tp) == ASIC_REV_5787 ||
  12461. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  12462. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  12463. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  12464. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  12465. tg3_flag(tp, 57765_PLUS))
  12466. tg3_flag_set(tp, 5755_PLUS);
  12467. if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
  12468. tg3_asic_rev(tp) == ASIC_REV_5714)
  12469. tg3_flag_set(tp, 5780_CLASS);
  12470. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  12471. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  12472. tg3_asic_rev(tp) == ASIC_REV_5906 ||
  12473. tg3_flag(tp, 5755_PLUS) ||
  12474. tg3_flag(tp, 5780_CLASS))
  12475. tg3_flag_set(tp, 5750_PLUS);
  12476. if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
  12477. tg3_flag(tp, 5750_PLUS))
  12478. tg3_flag_set(tp, 5705_PLUS);
  12479. }
  12480. static bool tg3_10_100_only_device(struct tg3 *tp,
  12481. const struct pci_device_id *ent)
  12482. {
  12483. u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
  12484. if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
  12485. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  12486. (tp->phy_flags & TG3_PHYFLG_IS_FET))
  12487. return true;
  12488. if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
  12489. if (tg3_asic_rev(tp) == ASIC_REV_5705) {
  12490. if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
  12491. return true;
  12492. } else {
  12493. return true;
  12494. }
  12495. }
  12496. return false;
  12497. }
  12498. static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
  12499. {
  12500. u32 misc_ctrl_reg;
  12501. u32 pci_state_reg, grc_misc_cfg;
  12502. u32 val;
  12503. u16 pci_cmd;
  12504. int err;
  12505. /* Force memory write invalidate off. If we leave it on,
  12506. * then on 5700_BX chips we have to enable a workaround.
  12507. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  12508. * to match the cacheline size. The Broadcom driver have this
  12509. * workaround but turns MWI off all the times so never uses
  12510. * it. This seems to suggest that the workaround is insufficient.
  12511. */
  12512. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  12513. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  12514. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  12515. /* Important! -- Make sure register accesses are byteswapped
  12516. * correctly. Also, for those chips that require it, make
  12517. * sure that indirect register accesses are enabled before
  12518. * the first operation.
  12519. */
  12520. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  12521. &misc_ctrl_reg);
  12522. tp->misc_host_ctrl |= (misc_ctrl_reg &
  12523. MISC_HOST_CTRL_CHIPREV);
  12524. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  12525. tp->misc_host_ctrl);
  12526. tg3_detect_asic_rev(tp, misc_ctrl_reg);
  12527. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  12528. * we need to disable memory and use config. cycles
  12529. * only to access all registers. The 5702/03 chips
  12530. * can mistakenly decode the special cycles from the
  12531. * ICH chipsets as memory write cycles, causing corruption
  12532. * of register and memory space. Only certain ICH bridges
  12533. * will drive special cycles with non-zero data during the
  12534. * address phase which can fall within the 5703's address
  12535. * range. This is not an ICH bug as the PCI spec allows
  12536. * non-zero address during special cycles. However, only
  12537. * these ICH bridges are known to drive non-zero addresses
  12538. * during special cycles.
  12539. *
  12540. * Since special cycles do not cross PCI bridges, we only
  12541. * enable this workaround if the 5703 is on the secondary
  12542. * bus of these ICH bridges.
  12543. */
  12544. if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
  12545. (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
  12546. static struct tg3_dev_id {
  12547. u32 vendor;
  12548. u32 device;
  12549. u32 rev;
  12550. } ich_chipsets[] = {
  12551. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  12552. PCI_ANY_ID },
  12553. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  12554. PCI_ANY_ID },
  12555. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  12556. 0xa },
  12557. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  12558. PCI_ANY_ID },
  12559. { },
  12560. };
  12561. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  12562. struct pci_dev *bridge = NULL;
  12563. while (pci_id->vendor != 0) {
  12564. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  12565. bridge);
  12566. if (!bridge) {
  12567. pci_id++;
  12568. continue;
  12569. }
  12570. if (pci_id->rev != PCI_ANY_ID) {
  12571. if (bridge->revision > pci_id->rev)
  12572. continue;
  12573. }
  12574. if (bridge->subordinate &&
  12575. (bridge->subordinate->number ==
  12576. tp->pdev->bus->number)) {
  12577. tg3_flag_set(tp, ICH_WORKAROUND);
  12578. pci_dev_put(bridge);
  12579. break;
  12580. }
  12581. }
  12582. }
  12583. if (tg3_asic_rev(tp) == ASIC_REV_5701) {
  12584. static struct tg3_dev_id {
  12585. u32 vendor;
  12586. u32 device;
  12587. } bridge_chipsets[] = {
  12588. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
  12589. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
  12590. { },
  12591. };
  12592. struct tg3_dev_id *pci_id = &bridge_chipsets[0];
  12593. struct pci_dev *bridge = NULL;
  12594. while (pci_id->vendor != 0) {
  12595. bridge = pci_get_device(pci_id->vendor,
  12596. pci_id->device,
  12597. bridge);
  12598. if (!bridge) {
  12599. pci_id++;
  12600. continue;
  12601. }
  12602. if (bridge->subordinate &&
  12603. (bridge->subordinate->number <=
  12604. tp->pdev->bus->number) &&
  12605. (bridge->subordinate->busn_res.end >=
  12606. tp->pdev->bus->number)) {
  12607. tg3_flag_set(tp, 5701_DMA_BUG);
  12608. pci_dev_put(bridge);
  12609. break;
  12610. }
  12611. }
  12612. }
  12613. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  12614. * DMA addresses > 40-bit. This bridge may have other additional
  12615. * 57xx devices behind it in some 4-port NIC designs for example.
  12616. * Any tg3 device found behind the bridge will also need the 40-bit
  12617. * DMA workaround.
  12618. */
  12619. if (tg3_flag(tp, 5780_CLASS)) {
  12620. tg3_flag_set(tp, 40BIT_DMA_BUG);
  12621. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  12622. } else {
  12623. struct pci_dev *bridge = NULL;
  12624. do {
  12625. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  12626. PCI_DEVICE_ID_SERVERWORKS_EPB,
  12627. bridge);
  12628. if (bridge && bridge->subordinate &&
  12629. (bridge->subordinate->number <=
  12630. tp->pdev->bus->number) &&
  12631. (bridge->subordinate->busn_res.end >=
  12632. tp->pdev->bus->number)) {
  12633. tg3_flag_set(tp, 40BIT_DMA_BUG);
  12634. pci_dev_put(bridge);
  12635. break;
  12636. }
  12637. } while (bridge);
  12638. }
  12639. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  12640. tg3_asic_rev(tp) == ASIC_REV_5714)
  12641. tp->pdev_peer = tg3_find_peer(tp);
  12642. /* Determine TSO capabilities */
  12643. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
  12644. ; /* Do nothing. HW bug. */
  12645. else if (tg3_flag(tp, 57765_PLUS))
  12646. tg3_flag_set(tp, HW_TSO_3);
  12647. else if (tg3_flag(tp, 5755_PLUS) ||
  12648. tg3_asic_rev(tp) == ASIC_REV_5906)
  12649. tg3_flag_set(tp, HW_TSO_2);
  12650. else if (tg3_flag(tp, 5750_PLUS)) {
  12651. tg3_flag_set(tp, HW_TSO_1);
  12652. tg3_flag_set(tp, TSO_BUG);
  12653. if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
  12654. tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
  12655. tg3_flag_clear(tp, TSO_BUG);
  12656. } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  12657. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  12658. tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
  12659. tg3_flag_set(tp, TSO_BUG);
  12660. if (tg3_asic_rev(tp) == ASIC_REV_5705)
  12661. tp->fw_needed = FIRMWARE_TG3TSO5;
  12662. else
  12663. tp->fw_needed = FIRMWARE_TG3TSO;
  12664. }
  12665. /* Selectively allow TSO based on operating conditions */
  12666. if (tg3_flag(tp, HW_TSO_1) ||
  12667. tg3_flag(tp, HW_TSO_2) ||
  12668. tg3_flag(tp, HW_TSO_3) ||
  12669. tp->fw_needed) {
  12670. /* For firmware TSO, assume ASF is disabled.
  12671. * We'll disable TSO later if we discover ASF
  12672. * is enabled in tg3_get_eeprom_hw_cfg().
  12673. */
  12674. tg3_flag_set(tp, TSO_CAPABLE);
  12675. } else {
  12676. tg3_flag_clear(tp, TSO_CAPABLE);
  12677. tg3_flag_clear(tp, TSO_BUG);
  12678. tp->fw_needed = NULL;
  12679. }
  12680. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
  12681. tp->fw_needed = FIRMWARE_TG3;
  12682. tp->irq_max = 1;
  12683. if (tg3_flag(tp, 5750_PLUS)) {
  12684. tg3_flag_set(tp, SUPPORT_MSI);
  12685. if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
  12686. tg3_chip_rev(tp) == CHIPREV_5750_BX ||
  12687. (tg3_asic_rev(tp) == ASIC_REV_5714 &&
  12688. tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
  12689. tp->pdev_peer == tp->pdev))
  12690. tg3_flag_clear(tp, SUPPORT_MSI);
  12691. if (tg3_flag(tp, 5755_PLUS) ||
  12692. tg3_asic_rev(tp) == ASIC_REV_5906) {
  12693. tg3_flag_set(tp, 1SHOT_MSI);
  12694. }
  12695. if (tg3_flag(tp, 57765_PLUS)) {
  12696. tg3_flag_set(tp, SUPPORT_MSIX);
  12697. tp->irq_max = TG3_IRQ_MAX_VECS;
  12698. }
  12699. }
  12700. tp->txq_max = 1;
  12701. tp->rxq_max = 1;
  12702. if (tp->irq_max > 1) {
  12703. tp->rxq_max = TG3_RSS_MAX_NUM_QS;
  12704. tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
  12705. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  12706. tg3_asic_rev(tp) == ASIC_REV_5720)
  12707. tp->txq_max = tp->irq_max - 1;
  12708. }
  12709. if (tg3_flag(tp, 5755_PLUS) ||
  12710. tg3_asic_rev(tp) == ASIC_REV_5906)
  12711. tg3_flag_set(tp, SHORT_DMA_BUG);
  12712. if (tg3_asic_rev(tp) == ASIC_REV_5719)
  12713. tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
  12714. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  12715. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  12716. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  12717. tg3_asic_rev(tp) == ASIC_REV_5762)
  12718. tg3_flag_set(tp, LRG_PROD_RING_CAP);
  12719. if (tg3_flag(tp, 57765_PLUS) &&
  12720. tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
  12721. tg3_flag_set(tp, USE_JUMBO_BDFLAG);
  12722. if (!tg3_flag(tp, 5705_PLUS) ||
  12723. tg3_flag(tp, 5780_CLASS) ||
  12724. tg3_flag(tp, USE_JUMBO_BDFLAG))
  12725. tg3_flag_set(tp, JUMBO_CAPABLE);
  12726. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  12727. &pci_state_reg);
  12728. if (pci_is_pcie(tp->pdev)) {
  12729. u16 lnkctl;
  12730. tg3_flag_set(tp, PCI_EXPRESS);
  12731. pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
  12732. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
  12733. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  12734. tg3_flag_clear(tp, HW_TSO_2);
  12735. tg3_flag_clear(tp, TSO_CAPABLE);
  12736. }
  12737. if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
  12738. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  12739. tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
  12740. tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
  12741. tg3_flag_set(tp, CLKREQ_BUG);
  12742. } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
  12743. tg3_flag_set(tp, L1PLLPD_EN);
  12744. }
  12745. } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
  12746. /* BCM5785 devices are effectively PCIe devices, and should
  12747. * follow PCIe codepaths, but do not have a PCIe capabilities
  12748. * section.
  12749. */
  12750. tg3_flag_set(tp, PCI_EXPRESS);
  12751. } else if (!tg3_flag(tp, 5705_PLUS) ||
  12752. tg3_flag(tp, 5780_CLASS)) {
  12753. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  12754. if (!tp->pcix_cap) {
  12755. dev_err(&tp->pdev->dev,
  12756. "Cannot find PCI-X capability, aborting\n");
  12757. return -EIO;
  12758. }
  12759. if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
  12760. tg3_flag_set(tp, PCIX_MODE);
  12761. }
  12762. /* If we have an AMD 762 or VIA K8T800 chipset, write
  12763. * reordering to the mailbox registers done by the host
  12764. * controller can cause major troubles. We read back from
  12765. * every mailbox register write to force the writes to be
  12766. * posted to the chip in order.
  12767. */
  12768. if (pci_dev_present(tg3_write_reorder_chipsets) &&
  12769. !tg3_flag(tp, PCI_EXPRESS))
  12770. tg3_flag_set(tp, MBOX_WRITE_REORDER);
  12771. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
  12772. &tp->pci_cacheline_sz);
  12773. pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  12774. &tp->pci_lat_timer);
  12775. if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
  12776. tp->pci_lat_timer < 64) {
  12777. tp->pci_lat_timer = 64;
  12778. pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
  12779. tp->pci_lat_timer);
  12780. }
  12781. /* Important! -- It is critical that the PCI-X hw workaround
  12782. * situation is decided before the first MMIO register access.
  12783. */
  12784. if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
  12785. /* 5700 BX chips need to have their TX producer index
  12786. * mailboxes written twice to workaround a bug.
  12787. */
  12788. tg3_flag_set(tp, TXD_MBOX_HWBUG);
  12789. /* If we are in PCI-X mode, enable register write workaround.
  12790. *
  12791. * The workaround is to use indirect register accesses
  12792. * for all chip writes not to mailbox registers.
  12793. */
  12794. if (tg3_flag(tp, PCIX_MODE)) {
  12795. u32 pm_reg;
  12796. tg3_flag_set(tp, PCIX_TARGET_HWBUG);
  12797. /* The chip can have it's power management PCI config
  12798. * space registers clobbered due to this bug.
  12799. * So explicitly force the chip into D0 here.
  12800. */
  12801. pci_read_config_dword(tp->pdev,
  12802. tp->pm_cap + PCI_PM_CTRL,
  12803. &pm_reg);
  12804. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  12805. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  12806. pci_write_config_dword(tp->pdev,
  12807. tp->pm_cap + PCI_PM_CTRL,
  12808. pm_reg);
  12809. /* Also, force SERR#/PERR# in PCI command. */
  12810. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  12811. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  12812. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  12813. }
  12814. }
  12815. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  12816. tg3_flag_set(tp, PCI_HIGH_SPEED);
  12817. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  12818. tg3_flag_set(tp, PCI_32BIT);
  12819. /* Chip-specific fixup from Broadcom driver */
  12820. if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
  12821. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  12822. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  12823. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  12824. }
  12825. /* Default fast path register access methods */
  12826. tp->read32 = tg3_read32;
  12827. tp->write32 = tg3_write32;
  12828. tp->read32_mbox = tg3_read32;
  12829. tp->write32_mbox = tg3_write32;
  12830. tp->write32_tx_mbox = tg3_write32;
  12831. tp->write32_rx_mbox = tg3_write32;
  12832. /* Various workaround register access methods */
  12833. if (tg3_flag(tp, PCIX_TARGET_HWBUG))
  12834. tp->write32 = tg3_write_indirect_reg32;
  12835. else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
  12836. (tg3_flag(tp, PCI_EXPRESS) &&
  12837. tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
  12838. /*
  12839. * Back to back register writes can cause problems on these
  12840. * chips, the workaround is to read back all reg writes
  12841. * except those to mailbox regs.
  12842. *
  12843. * See tg3_write_indirect_reg32().
  12844. */
  12845. tp->write32 = tg3_write_flush_reg32;
  12846. }
  12847. if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
  12848. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  12849. if (tg3_flag(tp, MBOX_WRITE_REORDER))
  12850. tp->write32_rx_mbox = tg3_write_flush_reg32;
  12851. }
  12852. if (tg3_flag(tp, ICH_WORKAROUND)) {
  12853. tp->read32 = tg3_read_indirect_reg32;
  12854. tp->write32 = tg3_write_indirect_reg32;
  12855. tp->read32_mbox = tg3_read_indirect_mbox;
  12856. tp->write32_mbox = tg3_write_indirect_mbox;
  12857. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  12858. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  12859. iounmap(tp->regs);
  12860. tp->regs = NULL;
  12861. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  12862. pci_cmd &= ~PCI_COMMAND_MEMORY;
  12863. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  12864. }
  12865. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  12866. tp->read32_mbox = tg3_read32_mbox_5906;
  12867. tp->write32_mbox = tg3_write32_mbox_5906;
  12868. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  12869. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  12870. }
  12871. if (tp->write32 == tg3_write_indirect_reg32 ||
  12872. (tg3_flag(tp, PCIX_MODE) &&
  12873. (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  12874. tg3_asic_rev(tp) == ASIC_REV_5701)))
  12875. tg3_flag_set(tp, SRAM_USE_CONFIG);
  12876. /* The memory arbiter has to be enabled in order for SRAM accesses
  12877. * to succeed. Normally on powerup the tg3 chip firmware will make
  12878. * sure it is enabled, but other entities such as system netboot
  12879. * code might disable it.
  12880. */
  12881. val = tr32(MEMARB_MODE);
  12882. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  12883. tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
  12884. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  12885. tg3_flag(tp, 5780_CLASS)) {
  12886. if (tg3_flag(tp, PCIX_MODE)) {
  12887. pci_read_config_dword(tp->pdev,
  12888. tp->pcix_cap + PCI_X_STATUS,
  12889. &val);
  12890. tp->pci_fn = val & 0x7;
  12891. }
  12892. } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  12893. tg3_asic_rev(tp) == ASIC_REV_5719 ||
  12894. tg3_asic_rev(tp) == ASIC_REV_5720) {
  12895. tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
  12896. if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
  12897. val = tr32(TG3_CPMU_STATUS);
  12898. if (tg3_asic_rev(tp) == ASIC_REV_5717)
  12899. tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
  12900. else
  12901. tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
  12902. TG3_CPMU_STATUS_FSHFT_5719;
  12903. }
  12904. if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
  12905. tp->write32_tx_mbox = tg3_write_flush_reg32;
  12906. tp->write32_rx_mbox = tg3_write_flush_reg32;
  12907. }
  12908. /* Get eeprom hw config before calling tg3_set_power_state().
  12909. * In particular, the TG3_FLAG_IS_NIC flag must be
  12910. * determined before calling tg3_set_power_state() so that
  12911. * we know whether or not to switch out of Vaux power.
  12912. * When the flag is set, it means that GPIO1 is used for eeprom
  12913. * write protect and also implies that it is a LOM where GPIOs
  12914. * are not used to switch power.
  12915. */
  12916. tg3_get_eeprom_hw_cfg(tp);
  12917. if (tp->fw_needed && tg3_flag(tp, ENABLE_ASF)) {
  12918. tg3_flag_clear(tp, TSO_CAPABLE);
  12919. tg3_flag_clear(tp, TSO_BUG);
  12920. tp->fw_needed = NULL;
  12921. }
  12922. if (tg3_flag(tp, ENABLE_APE)) {
  12923. /* Allow reads and writes to the
  12924. * APE register and memory space.
  12925. */
  12926. pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
  12927. PCISTATE_ALLOW_APE_SHMEM_WR |
  12928. PCISTATE_ALLOW_APE_PSPACE_WR;
  12929. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
  12930. pci_state_reg);
  12931. tg3_ape_lock_init(tp);
  12932. }
  12933. /* Set up tp->grc_local_ctrl before calling
  12934. * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
  12935. * will bring 5700's external PHY out of reset.
  12936. * It is also used as eeprom write protect on LOMs.
  12937. */
  12938. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  12939. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  12940. tg3_flag(tp, EEPROM_WRITE_PROT))
  12941. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  12942. GRC_LCLCTRL_GPIO_OUTPUT1);
  12943. /* Unused GPIO3 must be driven as output on 5752 because there
  12944. * are no pull-up resistors on unused GPIO pins.
  12945. */
  12946. else if (tg3_asic_rev(tp) == ASIC_REV_5752)
  12947. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  12948. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  12949. tg3_asic_rev(tp) == ASIC_REV_57780 ||
  12950. tg3_flag(tp, 57765_CLASS))
  12951. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  12952. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  12953. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
  12954. /* Turn off the debug UART. */
  12955. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  12956. if (tg3_flag(tp, IS_NIC))
  12957. /* Keep VMain power. */
  12958. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  12959. GRC_LCLCTRL_GPIO_OUTPUT0;
  12960. }
  12961. if (tg3_asic_rev(tp) == ASIC_REV_5762)
  12962. tp->grc_local_ctrl |=
  12963. tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
  12964. /* Switch out of Vaux if it is a NIC */
  12965. tg3_pwrsrc_switch_to_vmain(tp);
  12966. /* Derive initial jumbo mode from MTU assigned in
  12967. * ether_setup() via the alloc_etherdev() call
  12968. */
  12969. if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
  12970. tg3_flag_set(tp, JUMBO_RING_ENABLE);
  12971. /* Determine WakeOnLan speed to use. */
  12972. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  12973. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  12974. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
  12975. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
  12976. tg3_flag_clear(tp, WOL_SPEED_100MB);
  12977. } else {
  12978. tg3_flag_set(tp, WOL_SPEED_100MB);
  12979. }
  12980. if (tg3_asic_rev(tp) == ASIC_REV_5906)
  12981. tp->phy_flags |= TG3_PHYFLG_IS_FET;
  12982. /* A few boards don't want Ethernet@WireSpeed phy feature */
  12983. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  12984. (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  12985. (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
  12986. (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
  12987. (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
  12988. (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
  12989. tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
  12990. if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
  12991. tg3_chip_rev(tp) == CHIPREV_5704_AX)
  12992. tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
  12993. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
  12994. tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
  12995. if (tg3_flag(tp, 5705_PLUS) &&
  12996. !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
  12997. tg3_asic_rev(tp) != ASIC_REV_5785 &&
  12998. tg3_asic_rev(tp) != ASIC_REV_57780 &&
  12999. !tg3_flag(tp, 57765_PLUS)) {
  13000. if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
  13001. tg3_asic_rev(tp) == ASIC_REV_5787 ||
  13002. tg3_asic_rev(tp) == ASIC_REV_5784 ||
  13003. tg3_asic_rev(tp) == ASIC_REV_5761) {
  13004. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  13005. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  13006. tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
  13007. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  13008. tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
  13009. } else
  13010. tp->phy_flags |= TG3_PHYFLG_BER_BUG;
  13011. }
  13012. if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  13013. tg3_chip_rev(tp) != CHIPREV_5784_AX) {
  13014. tp->phy_otp = tg3_read_otp_phycfg(tp);
  13015. if (tp->phy_otp == 0)
  13016. tp->phy_otp = TG3_OTP_DEFAULT;
  13017. }
  13018. if (tg3_flag(tp, CPMU_PRESENT))
  13019. tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
  13020. else
  13021. tp->mi_mode = MAC_MI_MODE_BASE;
  13022. tp->coalesce_mode = 0;
  13023. if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
  13024. tg3_chip_rev(tp) != CHIPREV_5700_BX)
  13025. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  13026. /* Set these bits to enable statistics workaround. */
  13027. if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
  13028. tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
  13029. tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
  13030. tp->coalesce_mode |= HOSTCC_MODE_ATTN;
  13031. tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
  13032. }
  13033. if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
  13034. tg3_asic_rev(tp) == ASIC_REV_57780)
  13035. tg3_flag_set(tp, USE_PHYLIB);
  13036. err = tg3_mdio_init(tp);
  13037. if (err)
  13038. return err;
  13039. /* Initialize data/descriptor byte/word swapping. */
  13040. val = tr32(GRC_MODE);
  13041. if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
  13042. tg3_asic_rev(tp) == ASIC_REV_5762)
  13043. val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
  13044. GRC_MODE_WORD_SWAP_B2HRX_DATA |
  13045. GRC_MODE_B2HRX_ENABLE |
  13046. GRC_MODE_HTX2B_ENABLE |
  13047. GRC_MODE_HOST_STACKUP);
  13048. else
  13049. val &= GRC_MODE_HOST_STACKUP;
  13050. tw32(GRC_MODE, val | tp->grc_mode);
  13051. tg3_switch_clocks(tp);
  13052. /* Clear this out for sanity. */
  13053. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  13054. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  13055. &pci_state_reg);
  13056. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  13057. !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
  13058. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
  13059. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
  13060. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
  13061. tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
  13062. void __iomem *sram_base;
  13063. /* Write some dummy words into the SRAM status block
  13064. * area, see if it reads back correctly. If the return
  13065. * value is bad, force enable the PCIX workaround.
  13066. */
  13067. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  13068. writel(0x00000000, sram_base);
  13069. writel(0x00000000, sram_base + 4);
  13070. writel(0xffffffff, sram_base + 4);
  13071. if (readl(sram_base) != 0x00000000)
  13072. tg3_flag_set(tp, PCIX_TARGET_HWBUG);
  13073. }
  13074. }
  13075. udelay(50);
  13076. tg3_nvram_init(tp);
  13077. grc_misc_cfg = tr32(GRC_MISC_CFG);
  13078. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  13079. if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
  13080. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  13081. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  13082. tg3_flag_set(tp, IS_5788);
  13083. if (!tg3_flag(tp, IS_5788) &&
  13084. tg3_asic_rev(tp) != ASIC_REV_5700)
  13085. tg3_flag_set(tp, TAGGED_STATUS);
  13086. if (tg3_flag(tp, TAGGED_STATUS)) {
  13087. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  13088. HOSTCC_MODE_CLRTICK_TXBD);
  13089. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  13090. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  13091. tp->misc_host_ctrl);
  13092. }
  13093. /* Preserve the APE MAC_MODE bits */
  13094. if (tg3_flag(tp, ENABLE_APE))
  13095. tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
  13096. else
  13097. tp->mac_mode = 0;
  13098. if (tg3_10_100_only_device(tp, ent))
  13099. tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
  13100. err = tg3_phy_probe(tp);
  13101. if (err) {
  13102. dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
  13103. /* ... but do not return immediately ... */
  13104. tg3_mdio_fini(tp);
  13105. }
  13106. tg3_read_vpd(tp);
  13107. tg3_read_fw_ver(tp);
  13108. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
  13109. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  13110. } else {
  13111. if (tg3_asic_rev(tp) == ASIC_REV_5700)
  13112. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  13113. else
  13114. tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
  13115. }
  13116. /* 5700 {AX,BX} chips have a broken status block link
  13117. * change bit implementation, so we must use the
  13118. * status register in those cases.
  13119. */
  13120. if (tg3_asic_rev(tp) == ASIC_REV_5700)
  13121. tg3_flag_set(tp, USE_LINKCHG_REG);
  13122. else
  13123. tg3_flag_clear(tp, USE_LINKCHG_REG);
  13124. /* The led_ctrl is set during tg3_phy_probe, here we might
  13125. * have to force the link status polling mechanism based
  13126. * upon subsystem IDs.
  13127. */
  13128. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  13129. tg3_asic_rev(tp) == ASIC_REV_5701 &&
  13130. !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
  13131. tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
  13132. tg3_flag_set(tp, USE_LINKCHG_REG);
  13133. }
  13134. /* For all SERDES we poll the MAC status register. */
  13135. if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
  13136. tg3_flag_set(tp, POLL_SERDES);
  13137. else
  13138. tg3_flag_clear(tp, POLL_SERDES);
  13139. tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
  13140. tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
  13141. if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
  13142. tg3_flag(tp, PCIX_MODE)) {
  13143. tp->rx_offset = NET_SKB_PAD;
  13144. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  13145. tp->rx_copy_thresh = ~(u16)0;
  13146. #endif
  13147. }
  13148. tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
  13149. tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
  13150. tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
  13151. tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
  13152. /* Increment the rx prod index on the rx std ring by at most
  13153. * 8 for these chips to workaround hw errata.
  13154. */
  13155. if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
  13156. tg3_asic_rev(tp) == ASIC_REV_5752 ||
  13157. tg3_asic_rev(tp) == ASIC_REV_5755)
  13158. tp->rx_std_max_post = 8;
  13159. if (tg3_flag(tp, ASPM_WORKAROUND))
  13160. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  13161. PCIE_PWR_MGMT_L1_THRESH_MSK;
  13162. return err;
  13163. }
  13164. #ifdef CONFIG_SPARC
  13165. static int tg3_get_macaddr_sparc(struct tg3 *tp)
  13166. {
  13167. struct net_device *dev = tp->dev;
  13168. struct pci_dev *pdev = tp->pdev;
  13169. struct device_node *dp = pci_device_to_OF_node(pdev);
  13170. const unsigned char *addr;
  13171. int len;
  13172. addr = of_get_property(dp, "local-mac-address", &len);
  13173. if (addr && len == 6) {
  13174. memcpy(dev->dev_addr, addr, 6);
  13175. return 0;
  13176. }
  13177. return -ENODEV;
  13178. }
  13179. static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
  13180. {
  13181. struct net_device *dev = tp->dev;
  13182. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  13183. return 0;
  13184. }
  13185. #endif
  13186. static int tg3_get_device_address(struct tg3 *tp)
  13187. {
  13188. struct net_device *dev = tp->dev;
  13189. u32 hi, lo, mac_offset;
  13190. int addr_ok = 0;
  13191. int err;
  13192. #ifdef CONFIG_SPARC
  13193. if (!tg3_get_macaddr_sparc(tp))
  13194. return 0;
  13195. #endif
  13196. if (tg3_flag(tp, IS_SSB_CORE)) {
  13197. err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
  13198. if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
  13199. return 0;
  13200. }
  13201. mac_offset = 0x7c;
  13202. if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
  13203. tg3_flag(tp, 5780_CLASS)) {
  13204. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  13205. mac_offset = 0xcc;
  13206. if (tg3_nvram_lock(tp))
  13207. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  13208. else
  13209. tg3_nvram_unlock(tp);
  13210. } else if (tg3_flag(tp, 5717_PLUS)) {
  13211. if (tp->pci_fn & 1)
  13212. mac_offset = 0xcc;
  13213. if (tp->pci_fn > 1)
  13214. mac_offset += 0x18c;
  13215. } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
  13216. mac_offset = 0x10;
  13217. /* First try to get it from MAC address mailbox. */
  13218. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  13219. if ((hi >> 16) == 0x484b) {
  13220. dev->dev_addr[0] = (hi >> 8) & 0xff;
  13221. dev->dev_addr[1] = (hi >> 0) & 0xff;
  13222. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  13223. dev->dev_addr[2] = (lo >> 24) & 0xff;
  13224. dev->dev_addr[3] = (lo >> 16) & 0xff;
  13225. dev->dev_addr[4] = (lo >> 8) & 0xff;
  13226. dev->dev_addr[5] = (lo >> 0) & 0xff;
  13227. /* Some old bootcode may report a 0 MAC address in SRAM */
  13228. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  13229. }
  13230. if (!addr_ok) {
  13231. /* Next, try NVRAM. */
  13232. if (!tg3_flag(tp, NO_NVRAM) &&
  13233. !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
  13234. !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
  13235. memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
  13236. memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
  13237. }
  13238. /* Finally just fetch it out of the MAC control regs. */
  13239. else {
  13240. hi = tr32(MAC_ADDR_0_HIGH);
  13241. lo = tr32(MAC_ADDR_0_LOW);
  13242. dev->dev_addr[5] = lo & 0xff;
  13243. dev->dev_addr[4] = (lo >> 8) & 0xff;
  13244. dev->dev_addr[3] = (lo >> 16) & 0xff;
  13245. dev->dev_addr[2] = (lo >> 24) & 0xff;
  13246. dev->dev_addr[1] = hi & 0xff;
  13247. dev->dev_addr[0] = (hi >> 8) & 0xff;
  13248. }
  13249. }
  13250. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  13251. #ifdef CONFIG_SPARC
  13252. if (!tg3_get_default_macaddr_sparc(tp))
  13253. return 0;
  13254. #endif
  13255. return -EINVAL;
  13256. }
  13257. return 0;
  13258. }
  13259. #define BOUNDARY_SINGLE_CACHELINE 1
  13260. #define BOUNDARY_MULTI_CACHELINE 2
  13261. static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  13262. {
  13263. int cacheline_size;
  13264. u8 byte;
  13265. int goal;
  13266. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  13267. if (byte == 0)
  13268. cacheline_size = 1024;
  13269. else
  13270. cacheline_size = (int) byte * 4;
  13271. /* On 5703 and later chips, the boundary bits have no
  13272. * effect.
  13273. */
  13274. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  13275. tg3_asic_rev(tp) != ASIC_REV_5701 &&
  13276. !tg3_flag(tp, PCI_EXPRESS))
  13277. goto out;
  13278. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  13279. goal = BOUNDARY_MULTI_CACHELINE;
  13280. #else
  13281. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  13282. goal = BOUNDARY_SINGLE_CACHELINE;
  13283. #else
  13284. goal = 0;
  13285. #endif
  13286. #endif
  13287. if (tg3_flag(tp, 57765_PLUS)) {
  13288. val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
  13289. goto out;
  13290. }
  13291. if (!goal)
  13292. goto out;
  13293. /* PCI controllers on most RISC systems tend to disconnect
  13294. * when a device tries to burst across a cache-line boundary.
  13295. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  13296. *
  13297. * Unfortunately, for PCI-E there are only limited
  13298. * write-side controls for this, and thus for reads
  13299. * we will still get the disconnects. We'll also waste
  13300. * these PCI cycles for both read and write for chips
  13301. * other than 5700 and 5701 which do not implement the
  13302. * boundary bits.
  13303. */
  13304. if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
  13305. switch (cacheline_size) {
  13306. case 16:
  13307. case 32:
  13308. case 64:
  13309. case 128:
  13310. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13311. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  13312. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  13313. } else {
  13314. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  13315. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  13316. }
  13317. break;
  13318. case 256:
  13319. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  13320. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  13321. break;
  13322. default:
  13323. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  13324. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  13325. break;
  13326. }
  13327. } else if (tg3_flag(tp, PCI_EXPRESS)) {
  13328. switch (cacheline_size) {
  13329. case 16:
  13330. case 32:
  13331. case 64:
  13332. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13333. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  13334. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  13335. break;
  13336. }
  13337. /* fallthrough */
  13338. case 128:
  13339. default:
  13340. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  13341. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  13342. break;
  13343. }
  13344. } else {
  13345. switch (cacheline_size) {
  13346. case 16:
  13347. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13348. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  13349. DMA_RWCTRL_WRITE_BNDRY_16);
  13350. break;
  13351. }
  13352. /* fallthrough */
  13353. case 32:
  13354. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13355. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  13356. DMA_RWCTRL_WRITE_BNDRY_32);
  13357. break;
  13358. }
  13359. /* fallthrough */
  13360. case 64:
  13361. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13362. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  13363. DMA_RWCTRL_WRITE_BNDRY_64);
  13364. break;
  13365. }
  13366. /* fallthrough */
  13367. case 128:
  13368. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  13369. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  13370. DMA_RWCTRL_WRITE_BNDRY_128);
  13371. break;
  13372. }
  13373. /* fallthrough */
  13374. case 256:
  13375. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  13376. DMA_RWCTRL_WRITE_BNDRY_256);
  13377. break;
  13378. case 512:
  13379. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  13380. DMA_RWCTRL_WRITE_BNDRY_512);
  13381. break;
  13382. case 1024:
  13383. default:
  13384. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  13385. DMA_RWCTRL_WRITE_BNDRY_1024);
  13386. break;
  13387. }
  13388. }
  13389. out:
  13390. return val;
  13391. }
  13392. static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
  13393. int size, int to_device)
  13394. {
  13395. struct tg3_internal_buffer_desc test_desc;
  13396. u32 sram_dma_descs;
  13397. int i, ret;
  13398. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  13399. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  13400. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  13401. tw32(RDMAC_STATUS, 0);
  13402. tw32(WDMAC_STATUS, 0);
  13403. tw32(BUFMGR_MODE, 0);
  13404. tw32(FTQ_RESET, 0);
  13405. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  13406. test_desc.addr_lo = buf_dma & 0xffffffff;
  13407. test_desc.nic_mbuf = 0x00002100;
  13408. test_desc.len = size;
  13409. /*
  13410. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  13411. * the *second* time the tg3 driver was getting loaded after an
  13412. * initial scan.
  13413. *
  13414. * Broadcom tells me:
  13415. * ...the DMA engine is connected to the GRC block and a DMA
  13416. * reset may affect the GRC block in some unpredictable way...
  13417. * The behavior of resets to individual blocks has not been tested.
  13418. *
  13419. * Broadcom noted the GRC reset will also reset all sub-components.
  13420. */
  13421. if (to_device) {
  13422. test_desc.cqid_sqid = (13 << 8) | 2;
  13423. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  13424. udelay(40);
  13425. } else {
  13426. test_desc.cqid_sqid = (16 << 8) | 7;
  13427. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  13428. udelay(40);
  13429. }
  13430. test_desc.flags = 0x00000005;
  13431. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  13432. u32 val;
  13433. val = *(((u32 *)&test_desc) + i);
  13434. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  13435. sram_dma_descs + (i * sizeof(u32)));
  13436. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  13437. }
  13438. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  13439. if (to_device)
  13440. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  13441. else
  13442. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  13443. ret = -ENODEV;
  13444. for (i = 0; i < 40; i++) {
  13445. u32 val;
  13446. if (to_device)
  13447. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  13448. else
  13449. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  13450. if ((val & 0xffff) == sram_dma_descs) {
  13451. ret = 0;
  13452. break;
  13453. }
  13454. udelay(100);
  13455. }
  13456. return ret;
  13457. }
  13458. #define TEST_BUFFER_SIZE 0x2000
  13459. static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
  13460. { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  13461. { },
  13462. };
  13463. static int tg3_test_dma(struct tg3 *tp)
  13464. {
  13465. dma_addr_t buf_dma;
  13466. u32 *buf, saved_dma_rwctrl;
  13467. int ret = 0;
  13468. buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
  13469. &buf_dma, GFP_KERNEL);
  13470. if (!buf) {
  13471. ret = -ENOMEM;
  13472. goto out_nofree;
  13473. }
  13474. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  13475. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  13476. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  13477. if (tg3_flag(tp, 57765_PLUS))
  13478. goto out;
  13479. if (tg3_flag(tp, PCI_EXPRESS)) {
  13480. /* DMA read watermark not used on PCIE */
  13481. tp->dma_rwctrl |= 0x00180000;
  13482. } else if (!tg3_flag(tp, PCIX_MODE)) {
  13483. if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
  13484. tg3_asic_rev(tp) == ASIC_REV_5750)
  13485. tp->dma_rwctrl |= 0x003f0000;
  13486. else
  13487. tp->dma_rwctrl |= 0x003f000f;
  13488. } else {
  13489. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  13490. tg3_asic_rev(tp) == ASIC_REV_5704) {
  13491. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  13492. u32 read_water = 0x7;
  13493. /* If the 5704 is behind the EPB bridge, we can
  13494. * do the less restrictive ONE_DMA workaround for
  13495. * better performance.
  13496. */
  13497. if (tg3_flag(tp, 40BIT_DMA_BUG) &&
  13498. tg3_asic_rev(tp) == ASIC_REV_5704)
  13499. tp->dma_rwctrl |= 0x8000;
  13500. else if (ccval == 0x6 || ccval == 0x7)
  13501. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  13502. if (tg3_asic_rev(tp) == ASIC_REV_5703)
  13503. read_water = 4;
  13504. /* Set bit 23 to enable PCIX hw bug fix */
  13505. tp->dma_rwctrl |=
  13506. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  13507. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  13508. (1 << 23);
  13509. } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
  13510. /* 5780 always in PCIX mode */
  13511. tp->dma_rwctrl |= 0x00144000;
  13512. } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
  13513. /* 5714 always in PCIX mode */
  13514. tp->dma_rwctrl |= 0x00148000;
  13515. } else {
  13516. tp->dma_rwctrl |= 0x001b000f;
  13517. }
  13518. }
  13519. if (tg3_flag(tp, ONE_DMA_AT_ONCE))
  13520. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  13521. if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
  13522. tg3_asic_rev(tp) == ASIC_REV_5704)
  13523. tp->dma_rwctrl &= 0xfffffff0;
  13524. if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
  13525. tg3_asic_rev(tp) == ASIC_REV_5701) {
  13526. /* Remove this if it causes problems for some boards. */
  13527. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  13528. /* On 5700/5701 chips, we need to set this bit.
  13529. * Otherwise the chip will issue cacheline transactions
  13530. * to streamable DMA memory with not all the byte
  13531. * enables turned on. This is an error on several
  13532. * RISC PCI controllers, in particular sparc64.
  13533. *
  13534. * On 5703/5704 chips, this bit has been reassigned
  13535. * a different meaning. In particular, it is used
  13536. * on those chips to enable a PCI-X workaround.
  13537. */
  13538. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  13539. }
  13540. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  13541. #if 0
  13542. /* Unneeded, already done by tg3_get_invariants. */
  13543. tg3_switch_clocks(tp);
  13544. #endif
  13545. if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
  13546. tg3_asic_rev(tp) != ASIC_REV_5701)
  13547. goto out;
  13548. /* It is best to perform DMA test with maximum write burst size
  13549. * to expose the 5700/5701 write DMA bug.
  13550. */
  13551. saved_dma_rwctrl = tp->dma_rwctrl;
  13552. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  13553. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  13554. while (1) {
  13555. u32 *p = buf, i;
  13556. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  13557. p[i] = i;
  13558. /* Send the buffer to the chip. */
  13559. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  13560. if (ret) {
  13561. dev_err(&tp->pdev->dev,
  13562. "%s: Buffer write failed. err = %d\n",
  13563. __func__, ret);
  13564. break;
  13565. }
  13566. #if 0
  13567. /* validate data reached card RAM correctly. */
  13568. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  13569. u32 val;
  13570. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  13571. if (le32_to_cpu(val) != p[i]) {
  13572. dev_err(&tp->pdev->dev,
  13573. "%s: Buffer corrupted on device! "
  13574. "(%d != %d)\n", __func__, val, i);
  13575. /* ret = -ENODEV here? */
  13576. }
  13577. p[i] = 0;
  13578. }
  13579. #endif
  13580. /* Now read it back. */
  13581. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  13582. if (ret) {
  13583. dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
  13584. "err = %d\n", __func__, ret);
  13585. break;
  13586. }
  13587. /* Verify it. */
  13588. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  13589. if (p[i] == i)
  13590. continue;
  13591. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  13592. DMA_RWCTRL_WRITE_BNDRY_16) {
  13593. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  13594. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  13595. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  13596. break;
  13597. } else {
  13598. dev_err(&tp->pdev->dev,
  13599. "%s: Buffer corrupted on read back! "
  13600. "(%d != %d)\n", __func__, p[i], i);
  13601. ret = -ENODEV;
  13602. goto out;
  13603. }
  13604. }
  13605. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  13606. /* Success. */
  13607. ret = 0;
  13608. break;
  13609. }
  13610. }
  13611. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  13612. DMA_RWCTRL_WRITE_BNDRY_16) {
  13613. /* DMA test passed without adjusting DMA boundary,
  13614. * now look for chipsets that are known to expose the
  13615. * DMA bug without failing the test.
  13616. */
  13617. if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
  13618. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  13619. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  13620. } else {
  13621. /* Safe to use the calculated DMA boundary. */
  13622. tp->dma_rwctrl = saved_dma_rwctrl;
  13623. }
  13624. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  13625. }
  13626. out:
  13627. dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
  13628. out_nofree:
  13629. return ret;
  13630. }
  13631. static void tg3_init_bufmgr_config(struct tg3 *tp)
  13632. {
  13633. if (tg3_flag(tp, 57765_PLUS)) {
  13634. tp->bufmgr_config.mbuf_read_dma_low_water =
  13635. DEFAULT_MB_RDMA_LOW_WATER_5705;
  13636. tp->bufmgr_config.mbuf_mac_rx_low_water =
  13637. DEFAULT_MB_MACRX_LOW_WATER_57765;
  13638. tp->bufmgr_config.mbuf_high_water =
  13639. DEFAULT_MB_HIGH_WATER_57765;
  13640. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  13641. DEFAULT_MB_RDMA_LOW_WATER_5705;
  13642. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  13643. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
  13644. tp->bufmgr_config.mbuf_high_water_jumbo =
  13645. DEFAULT_MB_HIGH_WATER_JUMBO_57765;
  13646. } else if (tg3_flag(tp, 5705_PLUS)) {
  13647. tp->bufmgr_config.mbuf_read_dma_low_water =
  13648. DEFAULT_MB_RDMA_LOW_WATER_5705;
  13649. tp->bufmgr_config.mbuf_mac_rx_low_water =
  13650. DEFAULT_MB_MACRX_LOW_WATER_5705;
  13651. tp->bufmgr_config.mbuf_high_water =
  13652. DEFAULT_MB_HIGH_WATER_5705;
  13653. if (tg3_asic_rev(tp) == ASIC_REV_5906) {
  13654. tp->bufmgr_config.mbuf_mac_rx_low_water =
  13655. DEFAULT_MB_MACRX_LOW_WATER_5906;
  13656. tp->bufmgr_config.mbuf_high_water =
  13657. DEFAULT_MB_HIGH_WATER_5906;
  13658. }
  13659. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  13660. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  13661. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  13662. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  13663. tp->bufmgr_config.mbuf_high_water_jumbo =
  13664. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  13665. } else {
  13666. tp->bufmgr_config.mbuf_read_dma_low_water =
  13667. DEFAULT_MB_RDMA_LOW_WATER;
  13668. tp->bufmgr_config.mbuf_mac_rx_low_water =
  13669. DEFAULT_MB_MACRX_LOW_WATER;
  13670. tp->bufmgr_config.mbuf_high_water =
  13671. DEFAULT_MB_HIGH_WATER;
  13672. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  13673. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  13674. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  13675. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  13676. tp->bufmgr_config.mbuf_high_water_jumbo =
  13677. DEFAULT_MB_HIGH_WATER_JUMBO;
  13678. }
  13679. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  13680. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  13681. }
  13682. static char *tg3_phy_string(struct tg3 *tp)
  13683. {
  13684. switch (tp->phy_id & TG3_PHY_ID_MASK) {
  13685. case TG3_PHY_ID_BCM5400: return "5400";
  13686. case TG3_PHY_ID_BCM5401: return "5401";
  13687. case TG3_PHY_ID_BCM5411: return "5411";
  13688. case TG3_PHY_ID_BCM5701: return "5701";
  13689. case TG3_PHY_ID_BCM5703: return "5703";
  13690. case TG3_PHY_ID_BCM5704: return "5704";
  13691. case TG3_PHY_ID_BCM5705: return "5705";
  13692. case TG3_PHY_ID_BCM5750: return "5750";
  13693. case TG3_PHY_ID_BCM5752: return "5752";
  13694. case TG3_PHY_ID_BCM5714: return "5714";
  13695. case TG3_PHY_ID_BCM5780: return "5780";
  13696. case TG3_PHY_ID_BCM5755: return "5755";
  13697. case TG3_PHY_ID_BCM5787: return "5787";
  13698. case TG3_PHY_ID_BCM5784: return "5784";
  13699. case TG3_PHY_ID_BCM5756: return "5722/5756";
  13700. case TG3_PHY_ID_BCM5906: return "5906";
  13701. case TG3_PHY_ID_BCM5761: return "5761";
  13702. case TG3_PHY_ID_BCM5718C: return "5718C";
  13703. case TG3_PHY_ID_BCM5718S: return "5718S";
  13704. case TG3_PHY_ID_BCM57765: return "57765";
  13705. case TG3_PHY_ID_BCM5719C: return "5719C";
  13706. case TG3_PHY_ID_BCM5720C: return "5720C";
  13707. case TG3_PHY_ID_BCM5762: return "5762C";
  13708. case TG3_PHY_ID_BCM8002: return "8002/serdes";
  13709. case 0: return "serdes";
  13710. default: return "unknown";
  13711. }
  13712. }
  13713. static char *tg3_bus_string(struct tg3 *tp, char *str)
  13714. {
  13715. if (tg3_flag(tp, PCI_EXPRESS)) {
  13716. strcpy(str, "PCI Express");
  13717. return str;
  13718. } else if (tg3_flag(tp, PCIX_MODE)) {
  13719. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  13720. strcpy(str, "PCIX:");
  13721. if ((clock_ctrl == 7) ||
  13722. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  13723. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  13724. strcat(str, "133MHz");
  13725. else if (clock_ctrl == 0)
  13726. strcat(str, "33MHz");
  13727. else if (clock_ctrl == 2)
  13728. strcat(str, "50MHz");
  13729. else if (clock_ctrl == 4)
  13730. strcat(str, "66MHz");
  13731. else if (clock_ctrl == 6)
  13732. strcat(str, "100MHz");
  13733. } else {
  13734. strcpy(str, "PCI:");
  13735. if (tg3_flag(tp, PCI_HIGH_SPEED))
  13736. strcat(str, "66MHz");
  13737. else
  13738. strcat(str, "33MHz");
  13739. }
  13740. if (tg3_flag(tp, PCI_32BIT))
  13741. strcat(str, ":32-bit");
  13742. else
  13743. strcat(str, ":64-bit");
  13744. return str;
  13745. }
  13746. static void tg3_init_coal(struct tg3 *tp)
  13747. {
  13748. struct ethtool_coalesce *ec = &tp->coal;
  13749. memset(ec, 0, sizeof(*ec));
  13750. ec->cmd = ETHTOOL_GCOALESCE;
  13751. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  13752. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  13753. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  13754. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  13755. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  13756. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  13757. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  13758. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  13759. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  13760. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  13761. HOSTCC_MODE_CLRTICK_TXBD)) {
  13762. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  13763. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  13764. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  13765. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  13766. }
  13767. if (tg3_flag(tp, 5705_PLUS)) {
  13768. ec->rx_coalesce_usecs_irq = 0;
  13769. ec->tx_coalesce_usecs_irq = 0;
  13770. ec->stats_block_coalesce_usecs = 0;
  13771. }
  13772. }
  13773. static int tg3_init_one(struct pci_dev *pdev,
  13774. const struct pci_device_id *ent)
  13775. {
  13776. struct net_device *dev;
  13777. struct tg3 *tp;
  13778. int i, err, pm_cap;
  13779. u32 sndmbx, rcvmbx, intmbx;
  13780. char str[40];
  13781. u64 dma_mask, persist_dma_mask;
  13782. netdev_features_t features = 0;
  13783. printk_once(KERN_INFO "%s\n", version);
  13784. err = pci_enable_device(pdev);
  13785. if (err) {
  13786. dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
  13787. return err;
  13788. }
  13789. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  13790. if (err) {
  13791. dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
  13792. goto err_out_disable_pdev;
  13793. }
  13794. pci_set_master(pdev);
  13795. /* Find power-management capability. */
  13796. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  13797. if (pm_cap == 0) {
  13798. dev_err(&pdev->dev,
  13799. "Cannot find Power Management capability, aborting\n");
  13800. err = -EIO;
  13801. goto err_out_free_res;
  13802. }
  13803. err = pci_set_power_state(pdev, PCI_D0);
  13804. if (err) {
  13805. dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
  13806. goto err_out_free_res;
  13807. }
  13808. dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
  13809. if (!dev) {
  13810. err = -ENOMEM;
  13811. goto err_out_power_down;
  13812. }
  13813. SET_NETDEV_DEV(dev, &pdev->dev);
  13814. tp = netdev_priv(dev);
  13815. tp->pdev = pdev;
  13816. tp->dev = dev;
  13817. tp->pm_cap = pm_cap;
  13818. tp->rx_mode = TG3_DEF_RX_MODE;
  13819. tp->tx_mode = TG3_DEF_TX_MODE;
  13820. tp->irq_sync = 1;
  13821. if (tg3_debug > 0)
  13822. tp->msg_enable = tg3_debug;
  13823. else
  13824. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  13825. if (pdev_is_ssb_gige_core(pdev)) {
  13826. tg3_flag_set(tp, IS_SSB_CORE);
  13827. if (ssb_gige_must_flush_posted_writes(pdev))
  13828. tg3_flag_set(tp, FLUSH_POSTED_WRITES);
  13829. if (ssb_gige_one_dma_at_once(pdev))
  13830. tg3_flag_set(tp, ONE_DMA_AT_ONCE);
  13831. if (ssb_gige_have_roboswitch(pdev))
  13832. tg3_flag_set(tp, ROBOSWITCH);
  13833. if (ssb_gige_is_rgmii(pdev))
  13834. tg3_flag_set(tp, RGMII_MODE);
  13835. }
  13836. /* The word/byte swap controls here control register access byte
  13837. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  13838. * setting below.
  13839. */
  13840. tp->misc_host_ctrl =
  13841. MISC_HOST_CTRL_MASK_PCI_INT |
  13842. MISC_HOST_CTRL_WORD_SWAP |
  13843. MISC_HOST_CTRL_INDIR_ACCESS |
  13844. MISC_HOST_CTRL_PCISTATE_RW;
  13845. /* The NONFRM (non-frame) byte/word swap controls take effect
  13846. * on descriptor entries, anything which isn't packet data.
  13847. *
  13848. * The StrongARM chips on the board (one for tx, one for rx)
  13849. * are running in big-endian mode.
  13850. */
  13851. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  13852. GRC_MODE_WSWAP_NONFRM_DATA);
  13853. #ifdef __BIG_ENDIAN
  13854. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  13855. #endif
  13856. spin_lock_init(&tp->lock);
  13857. spin_lock_init(&tp->indirect_lock);
  13858. INIT_WORK(&tp->reset_task, tg3_reset_task);
  13859. tp->regs = pci_ioremap_bar(pdev, BAR_0);
  13860. if (!tp->regs) {
  13861. dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
  13862. err = -ENOMEM;
  13863. goto err_out_free_dev;
  13864. }
  13865. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
  13866. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
  13867. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
  13868. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
  13869. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
  13870. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
  13871. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
  13872. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
  13873. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
  13874. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
  13875. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
  13876. tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727) {
  13877. tg3_flag_set(tp, ENABLE_APE);
  13878. tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
  13879. if (!tp->aperegs) {
  13880. dev_err(&pdev->dev,
  13881. "Cannot map APE registers, aborting\n");
  13882. err = -ENOMEM;
  13883. goto err_out_iounmap;
  13884. }
  13885. }
  13886. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  13887. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  13888. dev->ethtool_ops = &tg3_ethtool_ops;
  13889. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  13890. dev->netdev_ops = &tg3_netdev_ops;
  13891. dev->irq = pdev->irq;
  13892. err = tg3_get_invariants(tp, ent);
  13893. if (err) {
  13894. dev_err(&pdev->dev,
  13895. "Problem fetching invariants of chip, aborting\n");
  13896. goto err_out_apeunmap;
  13897. }
  13898. /* The EPB bridge inside 5714, 5715, and 5780 and any
  13899. * device behind the EPB cannot support DMA addresses > 40-bit.
  13900. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  13901. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  13902. * do DMA address check in tg3_start_xmit().
  13903. */
  13904. if (tg3_flag(tp, IS_5788))
  13905. persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
  13906. else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
  13907. persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
  13908. #ifdef CONFIG_HIGHMEM
  13909. dma_mask = DMA_BIT_MASK(64);
  13910. #endif
  13911. } else
  13912. persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
  13913. /* Configure DMA attributes. */
  13914. if (dma_mask > DMA_BIT_MASK(32)) {
  13915. err = pci_set_dma_mask(pdev, dma_mask);
  13916. if (!err) {
  13917. features |= NETIF_F_HIGHDMA;
  13918. err = pci_set_consistent_dma_mask(pdev,
  13919. persist_dma_mask);
  13920. if (err < 0) {
  13921. dev_err(&pdev->dev, "Unable to obtain 64 bit "
  13922. "DMA for consistent allocations\n");
  13923. goto err_out_apeunmap;
  13924. }
  13925. }
  13926. }
  13927. if (err || dma_mask == DMA_BIT_MASK(32)) {
  13928. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  13929. if (err) {
  13930. dev_err(&pdev->dev,
  13931. "No usable DMA configuration, aborting\n");
  13932. goto err_out_apeunmap;
  13933. }
  13934. }
  13935. tg3_init_bufmgr_config(tp);
  13936. features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  13937. /* 5700 B0 chips do not support checksumming correctly due
  13938. * to hardware bugs.
  13939. */
  13940. if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
  13941. features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
  13942. if (tg3_flag(tp, 5755_PLUS))
  13943. features |= NETIF_F_IPV6_CSUM;
  13944. }
  13945. /* TSO is on by default on chips that support hardware TSO.
  13946. * Firmware TSO on older chips gives lower performance, so it
  13947. * is off by default, but can be enabled using ethtool.
  13948. */
  13949. if ((tg3_flag(tp, HW_TSO_1) ||
  13950. tg3_flag(tp, HW_TSO_2) ||
  13951. tg3_flag(tp, HW_TSO_3)) &&
  13952. (features & NETIF_F_IP_CSUM))
  13953. features |= NETIF_F_TSO;
  13954. if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
  13955. if (features & NETIF_F_IPV6_CSUM)
  13956. features |= NETIF_F_TSO6;
  13957. if (tg3_flag(tp, HW_TSO_3) ||
  13958. tg3_asic_rev(tp) == ASIC_REV_5761 ||
  13959. (tg3_asic_rev(tp) == ASIC_REV_5784 &&
  13960. tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
  13961. tg3_asic_rev(tp) == ASIC_REV_5785 ||
  13962. tg3_asic_rev(tp) == ASIC_REV_57780)
  13963. features |= NETIF_F_TSO_ECN;
  13964. }
  13965. dev->features |= features;
  13966. dev->vlan_features |= features;
  13967. /*
  13968. * Add loopback capability only for a subset of devices that support
  13969. * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
  13970. * loopback for the remaining devices.
  13971. */
  13972. if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
  13973. !tg3_flag(tp, CPMU_PRESENT))
  13974. /* Add the loopback capability */
  13975. features |= NETIF_F_LOOPBACK;
  13976. dev->hw_features |= features;
  13977. if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
  13978. !tg3_flag(tp, TSO_CAPABLE) &&
  13979. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  13980. tg3_flag_set(tp, MAX_RXPEND_64);
  13981. tp->rx_pending = 63;
  13982. }
  13983. err = tg3_get_device_address(tp);
  13984. if (err) {
  13985. dev_err(&pdev->dev,
  13986. "Could not obtain valid ethernet address, aborting\n");
  13987. goto err_out_apeunmap;
  13988. }
  13989. /*
  13990. * Reset chip in case UNDI or EFI driver did not shutdown
  13991. * DMA self test will enable WDMAC and we'll see (spurious)
  13992. * pending DMA on the PCI bus at that point.
  13993. */
  13994. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  13995. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  13996. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  13997. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  13998. }
  13999. err = tg3_test_dma(tp);
  14000. if (err) {
  14001. dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
  14002. goto err_out_apeunmap;
  14003. }
  14004. intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
  14005. rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
  14006. sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
  14007. for (i = 0; i < tp->irq_max; i++) {
  14008. struct tg3_napi *tnapi = &tp->napi[i];
  14009. tnapi->tp = tp;
  14010. tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
  14011. tnapi->int_mbox = intmbx;
  14012. if (i <= 4)
  14013. intmbx += 0x8;
  14014. else
  14015. intmbx += 0x4;
  14016. tnapi->consmbox = rcvmbx;
  14017. tnapi->prodmbox = sndmbx;
  14018. if (i)
  14019. tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
  14020. else
  14021. tnapi->coal_now = HOSTCC_MODE_NOW;
  14022. if (!tg3_flag(tp, SUPPORT_MSIX))
  14023. break;
  14024. /*
  14025. * If we support MSIX, we'll be using RSS. If we're using
  14026. * RSS, the first vector only handles link interrupts and the
  14027. * remaining vectors handle rx and tx interrupts. Reuse the
  14028. * mailbox values for the next iteration. The values we setup
  14029. * above are still useful for the single vectored mode.
  14030. */
  14031. if (!i)
  14032. continue;
  14033. rcvmbx += 0x8;
  14034. if (sndmbx & 0x4)
  14035. sndmbx -= 0x4;
  14036. else
  14037. sndmbx += 0xc;
  14038. }
  14039. tg3_init_coal(tp);
  14040. pci_set_drvdata(pdev, dev);
  14041. if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
  14042. tg3_asic_rev(tp) == ASIC_REV_5720 ||
  14043. tg3_asic_rev(tp) == ASIC_REV_5762)
  14044. tg3_flag_set(tp, PTP_CAPABLE);
  14045. if (tg3_flag(tp, 5717_PLUS)) {
  14046. /* Resume a low-power mode */
  14047. tg3_frob_aux_power(tp, false);
  14048. }
  14049. tg3_timer_init(tp);
  14050. tg3_carrier_off(tp);
  14051. err = register_netdev(dev);
  14052. if (err) {
  14053. dev_err(&pdev->dev, "Cannot register net device, aborting\n");
  14054. goto err_out_apeunmap;
  14055. }
  14056. netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
  14057. tp->board_part_number,
  14058. tg3_chip_rev_id(tp),
  14059. tg3_bus_string(tp, str),
  14060. dev->dev_addr);
  14061. if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
  14062. struct phy_device *phydev;
  14063. phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
  14064. netdev_info(dev,
  14065. "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
  14066. phydev->drv->name, dev_name(&phydev->dev));
  14067. } else {
  14068. char *ethtype;
  14069. if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
  14070. ethtype = "10/100Base-TX";
  14071. else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
  14072. ethtype = "1000Base-SX";
  14073. else
  14074. ethtype = "10/100/1000Base-T";
  14075. netdev_info(dev, "attached PHY is %s (%s Ethernet) "
  14076. "(WireSpeed[%d], EEE[%d])\n",
  14077. tg3_phy_string(tp), ethtype,
  14078. (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
  14079. (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
  14080. }
  14081. netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
  14082. (dev->features & NETIF_F_RXCSUM) != 0,
  14083. tg3_flag(tp, USE_LINKCHG_REG) != 0,
  14084. (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
  14085. tg3_flag(tp, ENABLE_ASF) != 0,
  14086. tg3_flag(tp, TSO_CAPABLE) != 0);
  14087. netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  14088. tp->dma_rwctrl,
  14089. pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
  14090. ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
  14091. pci_save_state(pdev);
  14092. return 0;
  14093. err_out_apeunmap:
  14094. if (tp->aperegs) {
  14095. iounmap(tp->aperegs);
  14096. tp->aperegs = NULL;
  14097. }
  14098. err_out_iounmap:
  14099. if (tp->regs) {
  14100. iounmap(tp->regs);
  14101. tp->regs = NULL;
  14102. }
  14103. err_out_free_dev:
  14104. free_netdev(dev);
  14105. err_out_power_down:
  14106. pci_set_power_state(pdev, PCI_D3hot);
  14107. err_out_free_res:
  14108. pci_release_regions(pdev);
  14109. err_out_disable_pdev:
  14110. pci_disable_device(pdev);
  14111. pci_set_drvdata(pdev, NULL);
  14112. return err;
  14113. }
  14114. static void tg3_remove_one(struct pci_dev *pdev)
  14115. {
  14116. struct net_device *dev = pci_get_drvdata(pdev);
  14117. if (dev) {
  14118. struct tg3 *tp = netdev_priv(dev);
  14119. release_firmware(tp->fw);
  14120. tg3_reset_task_cancel(tp);
  14121. if (tg3_flag(tp, USE_PHYLIB)) {
  14122. tg3_phy_fini(tp);
  14123. tg3_mdio_fini(tp);
  14124. }
  14125. unregister_netdev(dev);
  14126. if (tp->aperegs) {
  14127. iounmap(tp->aperegs);
  14128. tp->aperegs = NULL;
  14129. }
  14130. if (tp->regs) {
  14131. iounmap(tp->regs);
  14132. tp->regs = NULL;
  14133. }
  14134. free_netdev(dev);
  14135. pci_release_regions(pdev);
  14136. pci_disable_device(pdev);
  14137. pci_set_drvdata(pdev, NULL);
  14138. }
  14139. }
  14140. #ifdef CONFIG_PM_SLEEP
  14141. static int tg3_suspend(struct device *device)
  14142. {
  14143. struct pci_dev *pdev = to_pci_dev(device);
  14144. struct net_device *dev = pci_get_drvdata(pdev);
  14145. struct tg3 *tp = netdev_priv(dev);
  14146. int err;
  14147. if (!netif_running(dev))
  14148. return 0;
  14149. tg3_reset_task_cancel(tp);
  14150. tg3_phy_stop(tp);
  14151. tg3_netif_stop(tp);
  14152. tg3_timer_stop(tp);
  14153. tg3_full_lock(tp, 1);
  14154. tg3_disable_ints(tp);
  14155. tg3_full_unlock(tp);
  14156. netif_device_detach(dev);
  14157. tg3_full_lock(tp, 0);
  14158. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  14159. tg3_flag_clear(tp, INIT_COMPLETE);
  14160. tg3_full_unlock(tp);
  14161. err = tg3_power_down_prepare(tp);
  14162. if (err) {
  14163. int err2;
  14164. tg3_full_lock(tp, 0);
  14165. tg3_flag_set(tp, INIT_COMPLETE);
  14166. err2 = tg3_restart_hw(tp, 1);
  14167. if (err2)
  14168. goto out;
  14169. tg3_timer_start(tp);
  14170. netif_device_attach(dev);
  14171. tg3_netif_start(tp);
  14172. out:
  14173. tg3_full_unlock(tp);
  14174. if (!err2)
  14175. tg3_phy_start(tp);
  14176. }
  14177. return err;
  14178. }
  14179. static int tg3_resume(struct device *device)
  14180. {
  14181. struct pci_dev *pdev = to_pci_dev(device);
  14182. struct net_device *dev = pci_get_drvdata(pdev);
  14183. struct tg3 *tp = netdev_priv(dev);
  14184. int err;
  14185. if (!netif_running(dev))
  14186. return 0;
  14187. netif_device_attach(dev);
  14188. tg3_full_lock(tp, 0);
  14189. tg3_flag_set(tp, INIT_COMPLETE);
  14190. err = tg3_restart_hw(tp, 1);
  14191. if (err)
  14192. goto out;
  14193. tg3_timer_start(tp);
  14194. tg3_netif_start(tp);
  14195. out:
  14196. tg3_full_unlock(tp);
  14197. if (!err)
  14198. tg3_phy_start(tp);
  14199. return err;
  14200. }
  14201. static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
  14202. #define TG3_PM_OPS (&tg3_pm_ops)
  14203. #else
  14204. #define TG3_PM_OPS NULL
  14205. #endif /* CONFIG_PM_SLEEP */
  14206. /**
  14207. * tg3_io_error_detected - called when PCI error is detected
  14208. * @pdev: Pointer to PCI device
  14209. * @state: The current pci connection state
  14210. *
  14211. * This function is called after a PCI bus error affecting
  14212. * this device has been detected.
  14213. */
  14214. static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
  14215. pci_channel_state_t state)
  14216. {
  14217. struct net_device *netdev = pci_get_drvdata(pdev);
  14218. struct tg3 *tp = netdev_priv(netdev);
  14219. pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
  14220. netdev_info(netdev, "PCI I/O error detected\n");
  14221. rtnl_lock();
  14222. if (!netif_running(netdev))
  14223. goto done;
  14224. tg3_phy_stop(tp);
  14225. tg3_netif_stop(tp);
  14226. tg3_timer_stop(tp);
  14227. /* Want to make sure that the reset task doesn't run */
  14228. tg3_reset_task_cancel(tp);
  14229. netif_device_detach(netdev);
  14230. /* Clean up software state, even if MMIO is blocked */
  14231. tg3_full_lock(tp, 0);
  14232. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  14233. tg3_full_unlock(tp);
  14234. done:
  14235. if (state == pci_channel_io_perm_failure)
  14236. err = PCI_ERS_RESULT_DISCONNECT;
  14237. else
  14238. pci_disable_device(pdev);
  14239. rtnl_unlock();
  14240. return err;
  14241. }
  14242. /**
  14243. * tg3_io_slot_reset - called after the pci bus has been reset.
  14244. * @pdev: Pointer to PCI device
  14245. *
  14246. * Restart the card from scratch, as if from a cold-boot.
  14247. * At this point, the card has exprienced a hard reset,
  14248. * followed by fixups by BIOS, and has its config space
  14249. * set up identically to what it was at cold boot.
  14250. */
  14251. static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
  14252. {
  14253. struct net_device *netdev = pci_get_drvdata(pdev);
  14254. struct tg3 *tp = netdev_priv(netdev);
  14255. pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
  14256. int err;
  14257. rtnl_lock();
  14258. if (pci_enable_device(pdev)) {
  14259. netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
  14260. goto done;
  14261. }
  14262. pci_set_master(pdev);
  14263. pci_restore_state(pdev);
  14264. pci_save_state(pdev);
  14265. if (!netif_running(netdev)) {
  14266. rc = PCI_ERS_RESULT_RECOVERED;
  14267. goto done;
  14268. }
  14269. err = tg3_power_up(tp);
  14270. if (err)
  14271. goto done;
  14272. rc = PCI_ERS_RESULT_RECOVERED;
  14273. done:
  14274. rtnl_unlock();
  14275. return rc;
  14276. }
  14277. /**
  14278. * tg3_io_resume - called when traffic can start flowing again.
  14279. * @pdev: Pointer to PCI device
  14280. *
  14281. * This callback is called when the error recovery driver tells
  14282. * us that its OK to resume normal operation.
  14283. */
  14284. static void tg3_io_resume(struct pci_dev *pdev)
  14285. {
  14286. struct net_device *netdev = pci_get_drvdata(pdev);
  14287. struct tg3 *tp = netdev_priv(netdev);
  14288. int err;
  14289. rtnl_lock();
  14290. if (!netif_running(netdev))
  14291. goto done;
  14292. tg3_full_lock(tp, 0);
  14293. tg3_flag_set(tp, INIT_COMPLETE);
  14294. err = tg3_restart_hw(tp, 1);
  14295. if (err) {
  14296. tg3_full_unlock(tp);
  14297. netdev_err(netdev, "Cannot restart hardware after reset.\n");
  14298. goto done;
  14299. }
  14300. netif_device_attach(netdev);
  14301. tg3_timer_start(tp);
  14302. tg3_netif_start(tp);
  14303. tg3_full_unlock(tp);
  14304. tg3_phy_start(tp);
  14305. done:
  14306. rtnl_unlock();
  14307. }
  14308. static const struct pci_error_handlers tg3_err_handler = {
  14309. .error_detected = tg3_io_error_detected,
  14310. .slot_reset = tg3_io_slot_reset,
  14311. .resume = tg3_io_resume
  14312. };
  14313. static struct pci_driver tg3_driver = {
  14314. .name = DRV_MODULE_NAME,
  14315. .id_table = tg3_pci_tbl,
  14316. .probe = tg3_init_one,
  14317. .remove = tg3_remove_one,
  14318. .err_handler = &tg3_err_handler,
  14319. .driver.pm = TG3_PM_OPS,
  14320. };
  14321. static int __init tg3_init(void)
  14322. {
  14323. return pci_register_driver(&tg3_driver);
  14324. }
  14325. static void __exit tg3_cleanup(void)
  14326. {
  14327. pci_unregister_driver(&tg3_driver);
  14328. }
  14329. module_init(tg3_init);
  14330. module_exit(tg3_cleanup);