intel_dp.c 82 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <linux/export.h>
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/drm_edid.h>
  34. #include "intel_drv.h"
  35. #include <drm/i915_drm.h>
  36. #include "i915_drv.h"
  37. #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  38. /**
  39. * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  40. * @intel_dp: DP struct
  41. *
  42. * If a CPU or PCH DP output is attached to an eDP panel, this function
  43. * will return true, and false otherwise.
  44. */
  45. static bool is_edp(struct intel_dp *intel_dp)
  46. {
  47. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  48. return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  49. }
  50. /**
  51. * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  52. * @intel_dp: DP struct
  53. *
  54. * Returns true if the given DP struct corresponds to a PCH DP port attached
  55. * to an eDP panel, false otherwise. Helpful for determining whether we
  56. * may need FDI resources for a given DP output or not.
  57. */
  58. static bool is_pch_edp(struct intel_dp *intel_dp)
  59. {
  60. return intel_dp->is_pch_edp;
  61. }
  62. /**
  63. * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  64. * @intel_dp: DP struct
  65. *
  66. * Returns true if the given DP struct corresponds to a CPU eDP port.
  67. */
  68. static bool is_cpu_edp(struct intel_dp *intel_dp)
  69. {
  70. return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  71. }
  72. static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  73. {
  74. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  75. return intel_dig_port->base.base.dev;
  76. }
  77. static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  78. {
  79. return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  80. }
  81. /**
  82. * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  83. * @encoder: DRM encoder
  84. *
  85. * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
  86. * by intel_display.c.
  87. */
  88. bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  89. {
  90. struct intel_dp *intel_dp;
  91. if (!encoder)
  92. return false;
  93. intel_dp = enc_to_intel_dp(encoder);
  94. return is_pch_edp(intel_dp);
  95. }
  96. static void intel_dp_link_down(struct intel_dp *intel_dp);
  97. void
  98. intel_edp_link_config(struct intel_encoder *intel_encoder,
  99. int *lane_num, int *link_bw)
  100. {
  101. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  102. *lane_num = intel_dp->lane_count;
  103. *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
  104. }
  105. int
  106. intel_edp_target_clock(struct intel_encoder *intel_encoder,
  107. struct drm_display_mode *mode)
  108. {
  109. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  110. struct intel_connector *intel_connector = intel_dp->attached_connector;
  111. if (intel_connector->panel.fixed_mode)
  112. return intel_connector->panel.fixed_mode->clock;
  113. else
  114. return mode->clock;
  115. }
  116. static int
  117. intel_dp_max_link_bw(struct intel_dp *intel_dp)
  118. {
  119. int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  120. switch (max_link_bw) {
  121. case DP_LINK_BW_1_62:
  122. case DP_LINK_BW_2_7:
  123. break;
  124. default:
  125. max_link_bw = DP_LINK_BW_1_62;
  126. break;
  127. }
  128. return max_link_bw;
  129. }
  130. /*
  131. * The units on the numbers in the next two are... bizarre. Examples will
  132. * make it clearer; this one parallels an example in the eDP spec.
  133. *
  134. * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  135. *
  136. * 270000 * 1 * 8 / 10 == 216000
  137. *
  138. * The actual data capacity of that configuration is 2.16Gbit/s, so the
  139. * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
  140. * or equivalently, kilopixels per second - so for 1680x1050R it'd be
  141. * 119000. At 18bpp that's 2142000 kilobits per second.
  142. *
  143. * Thus the strange-looking division by 10 in intel_dp_link_required, to
  144. * get the result in decakilobits instead of kilobits.
  145. */
  146. static int
  147. intel_dp_link_required(int pixel_clock, int bpp)
  148. {
  149. return (pixel_clock * bpp + 9) / 10;
  150. }
  151. static int
  152. intel_dp_max_data_rate(int max_link_clock, int max_lanes)
  153. {
  154. return (max_link_clock * max_lanes * 8) / 10;
  155. }
  156. static bool
  157. intel_dp_adjust_dithering(struct intel_dp *intel_dp,
  158. struct drm_display_mode *mode,
  159. bool adjust_mode)
  160. {
  161. int max_link_clock =
  162. drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
  163. int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
  164. int max_rate, mode_rate;
  165. mode_rate = intel_dp_link_required(mode->clock, 24);
  166. max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
  167. if (mode_rate > max_rate) {
  168. mode_rate = intel_dp_link_required(mode->clock, 18);
  169. if (mode_rate > max_rate)
  170. return false;
  171. if (adjust_mode)
  172. mode->private_flags
  173. |= INTEL_MODE_DP_FORCE_6BPC;
  174. return true;
  175. }
  176. return true;
  177. }
  178. static int
  179. intel_dp_mode_valid(struct drm_connector *connector,
  180. struct drm_display_mode *mode)
  181. {
  182. struct intel_dp *intel_dp = intel_attached_dp(connector);
  183. struct intel_connector *intel_connector = to_intel_connector(connector);
  184. struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  185. if (is_edp(intel_dp) && fixed_mode) {
  186. if (mode->hdisplay > fixed_mode->hdisplay)
  187. return MODE_PANEL;
  188. if (mode->vdisplay > fixed_mode->vdisplay)
  189. return MODE_PANEL;
  190. }
  191. if (!intel_dp_adjust_dithering(intel_dp, mode, false))
  192. return MODE_CLOCK_HIGH;
  193. if (mode->clock < 10000)
  194. return MODE_CLOCK_LOW;
  195. if (mode->flags & DRM_MODE_FLAG_DBLCLK)
  196. return MODE_H_ILLEGAL;
  197. return MODE_OK;
  198. }
  199. static uint32_t
  200. pack_aux(uint8_t *src, int src_bytes)
  201. {
  202. int i;
  203. uint32_t v = 0;
  204. if (src_bytes > 4)
  205. src_bytes = 4;
  206. for (i = 0; i < src_bytes; i++)
  207. v |= ((uint32_t) src[i]) << ((3-i) * 8);
  208. return v;
  209. }
  210. static void
  211. unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
  212. {
  213. int i;
  214. if (dst_bytes > 4)
  215. dst_bytes = 4;
  216. for (i = 0; i < dst_bytes; i++)
  217. dst[i] = src >> ((3-i) * 8);
  218. }
  219. /* hrawclock is 1/4 the FSB frequency */
  220. static int
  221. intel_hrawclk(struct drm_device *dev)
  222. {
  223. struct drm_i915_private *dev_priv = dev->dev_private;
  224. uint32_t clkcfg;
  225. /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
  226. if (IS_VALLEYVIEW(dev))
  227. return 200;
  228. clkcfg = I915_READ(CLKCFG);
  229. switch (clkcfg & CLKCFG_FSB_MASK) {
  230. case CLKCFG_FSB_400:
  231. return 100;
  232. case CLKCFG_FSB_533:
  233. return 133;
  234. case CLKCFG_FSB_667:
  235. return 166;
  236. case CLKCFG_FSB_800:
  237. return 200;
  238. case CLKCFG_FSB_1067:
  239. return 266;
  240. case CLKCFG_FSB_1333:
  241. return 333;
  242. /* these two are just a guess; one of them might be right */
  243. case CLKCFG_FSB_1600:
  244. case CLKCFG_FSB_1600_ALT:
  245. return 400;
  246. default:
  247. return 133;
  248. }
  249. }
  250. static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
  251. {
  252. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  253. struct drm_i915_private *dev_priv = dev->dev_private;
  254. return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
  255. }
  256. static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
  257. {
  258. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  259. struct drm_i915_private *dev_priv = dev->dev_private;
  260. return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
  261. }
  262. static void
  263. intel_dp_check_edp(struct intel_dp *intel_dp)
  264. {
  265. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  266. struct drm_i915_private *dev_priv = dev->dev_private;
  267. if (!is_edp(intel_dp))
  268. return;
  269. if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
  270. WARN(1, "eDP powered off while attempting aux channel communication.\n");
  271. DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
  272. I915_READ(PCH_PP_STATUS),
  273. I915_READ(PCH_PP_CONTROL));
  274. }
  275. }
  276. static uint32_t
  277. intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
  278. {
  279. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  280. struct drm_device *dev = intel_dig_port->base.base.dev;
  281. struct drm_i915_private *dev_priv = dev->dev_private;
  282. uint32_t ch_ctl = intel_dp->output_reg + 0x10;
  283. uint32_t status;
  284. bool done;
  285. if (IS_HASWELL(dev)) {
  286. switch (intel_dig_port->port) {
  287. case PORT_A:
  288. ch_ctl = DPA_AUX_CH_CTL;
  289. break;
  290. case PORT_B:
  291. ch_ctl = PCH_DPB_AUX_CH_CTL;
  292. break;
  293. case PORT_C:
  294. ch_ctl = PCH_DPC_AUX_CH_CTL;
  295. break;
  296. case PORT_D:
  297. ch_ctl = PCH_DPD_AUX_CH_CTL;
  298. break;
  299. default:
  300. BUG();
  301. }
  302. }
  303. #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  304. if (has_aux_irq)
  305. done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
  306. msecs_to_jiffies(10));
  307. else
  308. done = wait_for_atomic(C, 10) == 0;
  309. if (!done)
  310. DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
  311. has_aux_irq);
  312. #undef C
  313. return status;
  314. }
  315. static int
  316. intel_dp_aux_ch(struct intel_dp *intel_dp,
  317. uint8_t *send, int send_bytes,
  318. uint8_t *recv, int recv_size)
  319. {
  320. uint32_t output_reg = intel_dp->output_reg;
  321. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  322. struct drm_device *dev = intel_dig_port->base.base.dev;
  323. struct drm_i915_private *dev_priv = dev->dev_private;
  324. uint32_t ch_ctl = output_reg + 0x10;
  325. uint32_t ch_data = ch_ctl + 4;
  326. int i, ret, recv_bytes;
  327. uint32_t status;
  328. uint32_t aux_clock_divider;
  329. int try, precharge;
  330. bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
  331. /* dp aux is extremely sensitive to irq latency, hence request the
  332. * lowest possible wakeup latency and so prevent the cpu from going into
  333. * deep sleep states.
  334. */
  335. pm_qos_update_request(&dev_priv->pm_qos, 0);
  336. if (IS_HASWELL(dev)) {
  337. switch (intel_dig_port->port) {
  338. case PORT_A:
  339. ch_ctl = DPA_AUX_CH_CTL;
  340. ch_data = DPA_AUX_CH_DATA1;
  341. break;
  342. case PORT_B:
  343. ch_ctl = PCH_DPB_AUX_CH_CTL;
  344. ch_data = PCH_DPB_AUX_CH_DATA1;
  345. break;
  346. case PORT_C:
  347. ch_ctl = PCH_DPC_AUX_CH_CTL;
  348. ch_data = PCH_DPC_AUX_CH_DATA1;
  349. break;
  350. case PORT_D:
  351. ch_ctl = PCH_DPD_AUX_CH_CTL;
  352. ch_data = PCH_DPD_AUX_CH_DATA1;
  353. break;
  354. default:
  355. BUG();
  356. }
  357. }
  358. intel_dp_check_edp(intel_dp);
  359. /* The clock divider is based off the hrawclk,
  360. * and would like to run at 2MHz. So, take the
  361. * hrawclk value and divide by 2 and use that
  362. *
  363. * Note that PCH attached eDP panels should use a 125MHz input
  364. * clock divider.
  365. */
  366. if (is_cpu_edp(intel_dp)) {
  367. if (HAS_DDI(dev))
  368. aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
  369. else if (IS_VALLEYVIEW(dev))
  370. aux_clock_divider = 100;
  371. else if (IS_GEN6(dev) || IS_GEN7(dev))
  372. aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
  373. else
  374. aux_clock_divider = 225; /* eDP input clock at 450Mhz */
  375. } else if (HAS_PCH_SPLIT(dev))
  376. aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
  377. else
  378. aux_clock_divider = intel_hrawclk(dev) / 2;
  379. if (IS_GEN6(dev))
  380. precharge = 3;
  381. else
  382. precharge = 5;
  383. /* Try to wait for any previous AUX channel activity */
  384. for (try = 0; try < 3; try++) {
  385. status = I915_READ_NOTRACE(ch_ctl);
  386. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  387. break;
  388. msleep(1);
  389. }
  390. if (try == 3) {
  391. WARN(1, "dp_aux_ch not started status 0x%08x\n",
  392. I915_READ(ch_ctl));
  393. ret = -EBUSY;
  394. goto out;
  395. }
  396. /* Must try at least 3 times according to DP spec */
  397. for (try = 0; try < 5; try++) {
  398. /* Load the send data into the aux channel data registers */
  399. for (i = 0; i < send_bytes; i += 4)
  400. I915_WRITE(ch_data + i,
  401. pack_aux(send + i, send_bytes - i));
  402. /* Send the command and wait for it to complete */
  403. I915_WRITE(ch_ctl,
  404. DP_AUX_CH_CTL_SEND_BUSY |
  405. (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
  406. DP_AUX_CH_CTL_TIME_OUT_400us |
  407. (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  408. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  409. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
  410. DP_AUX_CH_CTL_DONE |
  411. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  412. DP_AUX_CH_CTL_RECEIVE_ERROR);
  413. status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
  414. /* Clear done status and any errors */
  415. I915_WRITE(ch_ctl,
  416. status |
  417. DP_AUX_CH_CTL_DONE |
  418. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  419. DP_AUX_CH_CTL_RECEIVE_ERROR);
  420. if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
  421. DP_AUX_CH_CTL_RECEIVE_ERROR))
  422. continue;
  423. if (status & DP_AUX_CH_CTL_DONE)
  424. break;
  425. }
  426. if ((status & DP_AUX_CH_CTL_DONE) == 0) {
  427. DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
  428. ret = -EBUSY;
  429. goto out;
  430. }
  431. /* Check for timeout or receive error.
  432. * Timeouts occur when the sink is not connected
  433. */
  434. if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
  435. DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
  436. ret = -EIO;
  437. goto out;
  438. }
  439. /* Timeouts occur when the device isn't connected, so they're
  440. * "normal" -- don't fill the kernel log with these */
  441. if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
  442. DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
  443. ret = -ETIMEDOUT;
  444. goto out;
  445. }
  446. /* Unload any bytes sent back from the other side */
  447. recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
  448. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
  449. if (recv_bytes > recv_size)
  450. recv_bytes = recv_size;
  451. for (i = 0; i < recv_bytes; i += 4)
  452. unpack_aux(I915_READ(ch_data + i),
  453. recv + i, recv_bytes - i);
  454. ret = recv_bytes;
  455. out:
  456. pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
  457. return ret;
  458. }
  459. /* Write data to the aux channel in native mode */
  460. static int
  461. intel_dp_aux_native_write(struct intel_dp *intel_dp,
  462. uint16_t address, uint8_t *send, int send_bytes)
  463. {
  464. int ret;
  465. uint8_t msg[20];
  466. int msg_bytes;
  467. uint8_t ack;
  468. intel_dp_check_edp(intel_dp);
  469. if (send_bytes > 16)
  470. return -1;
  471. msg[0] = AUX_NATIVE_WRITE << 4;
  472. msg[1] = address >> 8;
  473. msg[2] = address & 0xff;
  474. msg[3] = send_bytes - 1;
  475. memcpy(&msg[4], send, send_bytes);
  476. msg_bytes = send_bytes + 4;
  477. for (;;) {
  478. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
  479. if (ret < 0)
  480. return ret;
  481. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  482. break;
  483. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  484. udelay(100);
  485. else
  486. return -EIO;
  487. }
  488. return send_bytes;
  489. }
  490. /* Write a single byte to the aux channel in native mode */
  491. static int
  492. intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
  493. uint16_t address, uint8_t byte)
  494. {
  495. return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
  496. }
  497. /* read bytes from a native aux channel */
  498. static int
  499. intel_dp_aux_native_read(struct intel_dp *intel_dp,
  500. uint16_t address, uint8_t *recv, int recv_bytes)
  501. {
  502. uint8_t msg[4];
  503. int msg_bytes;
  504. uint8_t reply[20];
  505. int reply_bytes;
  506. uint8_t ack;
  507. int ret;
  508. intel_dp_check_edp(intel_dp);
  509. msg[0] = AUX_NATIVE_READ << 4;
  510. msg[1] = address >> 8;
  511. msg[2] = address & 0xff;
  512. msg[3] = recv_bytes - 1;
  513. msg_bytes = 4;
  514. reply_bytes = recv_bytes + 1;
  515. for (;;) {
  516. ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
  517. reply, reply_bytes);
  518. if (ret == 0)
  519. return -EPROTO;
  520. if (ret < 0)
  521. return ret;
  522. ack = reply[0];
  523. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
  524. memcpy(recv, reply + 1, ret - 1);
  525. return ret - 1;
  526. }
  527. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  528. udelay(100);
  529. else
  530. return -EIO;
  531. }
  532. }
  533. static int
  534. intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  535. uint8_t write_byte, uint8_t *read_byte)
  536. {
  537. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  538. struct intel_dp *intel_dp = container_of(adapter,
  539. struct intel_dp,
  540. adapter);
  541. uint16_t address = algo_data->address;
  542. uint8_t msg[5];
  543. uint8_t reply[2];
  544. unsigned retry;
  545. int msg_bytes;
  546. int reply_bytes;
  547. int ret;
  548. intel_dp_check_edp(intel_dp);
  549. /* Set up the command byte */
  550. if (mode & MODE_I2C_READ)
  551. msg[0] = AUX_I2C_READ << 4;
  552. else
  553. msg[0] = AUX_I2C_WRITE << 4;
  554. if (!(mode & MODE_I2C_STOP))
  555. msg[0] |= AUX_I2C_MOT << 4;
  556. msg[1] = address >> 8;
  557. msg[2] = address;
  558. switch (mode) {
  559. case MODE_I2C_WRITE:
  560. msg[3] = 0;
  561. msg[4] = write_byte;
  562. msg_bytes = 5;
  563. reply_bytes = 1;
  564. break;
  565. case MODE_I2C_READ:
  566. msg[3] = 0;
  567. msg_bytes = 4;
  568. reply_bytes = 2;
  569. break;
  570. default:
  571. msg_bytes = 3;
  572. reply_bytes = 1;
  573. break;
  574. }
  575. for (retry = 0; retry < 5; retry++) {
  576. ret = intel_dp_aux_ch(intel_dp,
  577. msg, msg_bytes,
  578. reply, reply_bytes);
  579. if (ret < 0) {
  580. DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
  581. return ret;
  582. }
  583. switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
  584. case AUX_NATIVE_REPLY_ACK:
  585. /* I2C-over-AUX Reply field is only valid
  586. * when paired with AUX ACK.
  587. */
  588. break;
  589. case AUX_NATIVE_REPLY_NACK:
  590. DRM_DEBUG_KMS("aux_ch native nack\n");
  591. return -EREMOTEIO;
  592. case AUX_NATIVE_REPLY_DEFER:
  593. udelay(100);
  594. continue;
  595. default:
  596. DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
  597. reply[0]);
  598. return -EREMOTEIO;
  599. }
  600. switch (reply[0] & AUX_I2C_REPLY_MASK) {
  601. case AUX_I2C_REPLY_ACK:
  602. if (mode == MODE_I2C_READ) {
  603. *read_byte = reply[1];
  604. }
  605. return reply_bytes - 1;
  606. case AUX_I2C_REPLY_NACK:
  607. DRM_DEBUG_KMS("aux_i2c nack\n");
  608. return -EREMOTEIO;
  609. case AUX_I2C_REPLY_DEFER:
  610. DRM_DEBUG_KMS("aux_i2c defer\n");
  611. udelay(100);
  612. break;
  613. default:
  614. DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
  615. return -EREMOTEIO;
  616. }
  617. }
  618. DRM_ERROR("too many retries, giving up\n");
  619. return -EREMOTEIO;
  620. }
  621. static int
  622. intel_dp_i2c_init(struct intel_dp *intel_dp,
  623. struct intel_connector *intel_connector, const char *name)
  624. {
  625. int ret;
  626. DRM_DEBUG_KMS("i2c_init %s\n", name);
  627. intel_dp->algo.running = false;
  628. intel_dp->algo.address = 0;
  629. intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
  630. memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
  631. intel_dp->adapter.owner = THIS_MODULE;
  632. intel_dp->adapter.class = I2C_CLASS_DDC;
  633. strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
  634. intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
  635. intel_dp->adapter.algo_data = &intel_dp->algo;
  636. intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
  637. ironlake_edp_panel_vdd_on(intel_dp);
  638. ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
  639. ironlake_edp_panel_vdd_off(intel_dp, false);
  640. return ret;
  641. }
  642. bool
  643. intel_dp_mode_fixup(struct drm_encoder *encoder,
  644. const struct drm_display_mode *mode,
  645. struct drm_display_mode *adjusted_mode)
  646. {
  647. struct drm_device *dev = encoder->dev;
  648. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  649. struct intel_connector *intel_connector = intel_dp->attached_connector;
  650. int lane_count, clock;
  651. int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
  652. int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
  653. int bpp, mode_rate;
  654. static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
  655. if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
  656. intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
  657. adjusted_mode);
  658. intel_pch_panel_fitting(dev,
  659. intel_connector->panel.fitting_mode,
  660. mode, adjusted_mode);
  661. }
  662. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  663. return false;
  664. DRM_DEBUG_KMS("DP link computation with max lane count %i "
  665. "max bw %02x pixel clock %iKHz\n",
  666. max_lane_count, bws[max_clock], adjusted_mode->clock);
  667. if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
  668. return false;
  669. bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
  670. if (intel_dp->color_range_auto) {
  671. /*
  672. * See:
  673. * CEA-861-E - 5.1 Default Encoding Parameters
  674. * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
  675. */
  676. if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
  677. intel_dp->color_range = DP_COLOR_RANGE_16_235;
  678. else
  679. intel_dp->color_range = 0;
  680. }
  681. if (intel_dp->color_range)
  682. adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
  683. mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
  684. for (clock = 0; clock <= max_clock; clock++) {
  685. for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
  686. int link_bw_clock =
  687. drm_dp_bw_code_to_link_rate(bws[clock]);
  688. int link_avail = intel_dp_max_data_rate(link_bw_clock,
  689. lane_count);
  690. if (mode_rate <= link_avail) {
  691. intel_dp->link_bw = bws[clock];
  692. intel_dp->lane_count = lane_count;
  693. adjusted_mode->clock = link_bw_clock;
  694. DRM_DEBUG_KMS("DP link bw %02x lane "
  695. "count %d clock %d bpp %d\n",
  696. intel_dp->link_bw, intel_dp->lane_count,
  697. adjusted_mode->clock, bpp);
  698. DRM_DEBUG_KMS("DP link bw required %i available %i\n",
  699. mode_rate, link_avail);
  700. return true;
  701. }
  702. }
  703. }
  704. return false;
  705. }
  706. void
  707. intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
  708. struct drm_display_mode *adjusted_mode)
  709. {
  710. struct drm_device *dev = crtc->dev;
  711. struct intel_encoder *intel_encoder;
  712. struct intel_dp *intel_dp;
  713. struct drm_i915_private *dev_priv = dev->dev_private;
  714. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  715. int lane_count = 4;
  716. struct intel_link_m_n m_n;
  717. int pipe = intel_crtc->pipe;
  718. enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
  719. /*
  720. * Find the lane count in the intel_encoder private
  721. */
  722. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  723. intel_dp = enc_to_intel_dp(&intel_encoder->base);
  724. if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
  725. intel_encoder->type == INTEL_OUTPUT_EDP)
  726. {
  727. lane_count = intel_dp->lane_count;
  728. break;
  729. }
  730. }
  731. /*
  732. * Compute the GMCH and Link ratios. The '3' here is
  733. * the number of bytes_per_pixel post-LUT, which we always
  734. * set up for 8-bits of R/G/B, or 3 bytes total.
  735. */
  736. intel_link_compute_m_n(intel_crtc->bpp, lane_count,
  737. mode->clock, adjusted_mode->clock, &m_n);
  738. if (IS_HASWELL(dev)) {
  739. I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
  740. TU_SIZE(m_n.tu) | m_n.gmch_m);
  741. I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
  742. I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
  743. I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
  744. } else if (HAS_PCH_SPLIT(dev)) {
  745. I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
  746. I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
  747. I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
  748. I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
  749. } else if (IS_VALLEYVIEW(dev)) {
  750. I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
  751. I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
  752. I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
  753. I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
  754. } else {
  755. I915_WRITE(PIPE_GMCH_DATA_M(pipe),
  756. TU_SIZE(m_n.tu) | m_n.gmch_m);
  757. I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
  758. I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
  759. I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
  760. }
  761. }
  762. void intel_dp_init_link_config(struct intel_dp *intel_dp)
  763. {
  764. memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
  765. intel_dp->link_configuration[0] = intel_dp->link_bw;
  766. intel_dp->link_configuration[1] = intel_dp->lane_count;
  767. intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
  768. /*
  769. * Check for DPCD version > 1.1 and enhanced framing support
  770. */
  771. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  772. (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
  773. intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  774. }
  775. }
  776. static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
  777. {
  778. struct drm_device *dev = crtc->dev;
  779. struct drm_i915_private *dev_priv = dev->dev_private;
  780. u32 dpa_ctl;
  781. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  782. dpa_ctl = I915_READ(DP_A);
  783. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  784. if (clock < 200000) {
  785. /* For a long time we've carried around a ILK-DevA w/a for the
  786. * 160MHz clock. If we're really unlucky, it's still required.
  787. */
  788. DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
  789. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  790. } else {
  791. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  792. }
  793. I915_WRITE(DP_A, dpa_ctl);
  794. POSTING_READ(DP_A);
  795. udelay(500);
  796. }
  797. static void
  798. intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
  799. struct drm_display_mode *adjusted_mode)
  800. {
  801. struct drm_device *dev = encoder->dev;
  802. struct drm_i915_private *dev_priv = dev->dev_private;
  803. struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
  804. struct drm_crtc *crtc = encoder->crtc;
  805. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  806. /*
  807. * There are four kinds of DP registers:
  808. *
  809. * IBX PCH
  810. * SNB CPU
  811. * IVB CPU
  812. * CPT PCH
  813. *
  814. * IBX PCH and CPU are the same for almost everything,
  815. * except that the CPU DP PLL is configured in this
  816. * register
  817. *
  818. * CPT PCH is quite different, having many bits moved
  819. * to the TRANS_DP_CTL register instead. That
  820. * configuration happens (oddly) in ironlake_pch_enable
  821. */
  822. /* Preserve the BIOS-computed detected bit. This is
  823. * supposed to be read-only.
  824. */
  825. intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
  826. /* Handle DP bits in common between all three register formats */
  827. intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
  828. switch (intel_dp->lane_count) {
  829. case 1:
  830. intel_dp->DP |= DP_PORT_WIDTH_1;
  831. break;
  832. case 2:
  833. intel_dp->DP |= DP_PORT_WIDTH_2;
  834. break;
  835. case 4:
  836. intel_dp->DP |= DP_PORT_WIDTH_4;
  837. break;
  838. }
  839. if (intel_dp->has_audio) {
  840. DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
  841. pipe_name(intel_crtc->pipe));
  842. intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
  843. intel_write_eld(encoder, adjusted_mode);
  844. }
  845. intel_dp_init_link_config(intel_dp);
  846. /* Split out the IBX/CPU vs CPT settings */
  847. if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
  848. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  849. intel_dp->DP |= DP_SYNC_HS_HIGH;
  850. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  851. intel_dp->DP |= DP_SYNC_VS_HIGH;
  852. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  853. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  854. intel_dp->DP |= DP_ENHANCED_FRAMING;
  855. intel_dp->DP |= intel_crtc->pipe << 29;
  856. /* don't miss out required setting for eDP */
  857. if (adjusted_mode->clock < 200000)
  858. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  859. else
  860. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  861. } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
  862. if (!HAS_PCH_SPLIT(dev))
  863. intel_dp->DP |= intel_dp->color_range;
  864. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  865. intel_dp->DP |= DP_SYNC_HS_HIGH;
  866. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  867. intel_dp->DP |= DP_SYNC_VS_HIGH;
  868. intel_dp->DP |= DP_LINK_TRAIN_OFF;
  869. if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
  870. intel_dp->DP |= DP_ENHANCED_FRAMING;
  871. if (intel_crtc->pipe == 1)
  872. intel_dp->DP |= DP_PIPEB_SELECT;
  873. if (is_cpu_edp(intel_dp)) {
  874. /* don't miss out required setting for eDP */
  875. if (adjusted_mode->clock < 200000)
  876. intel_dp->DP |= DP_PLL_FREQ_160MHZ;
  877. else
  878. intel_dp->DP |= DP_PLL_FREQ_270MHZ;
  879. }
  880. } else {
  881. intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
  882. }
  883. if (is_cpu_edp(intel_dp))
  884. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  885. }
  886. #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  887. #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
  888. #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
  889. #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  890. #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
  891. #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
  892. static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
  893. u32 mask,
  894. u32 value)
  895. {
  896. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  897. struct drm_i915_private *dev_priv = dev->dev_private;
  898. DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
  899. mask, value,
  900. I915_READ(PCH_PP_STATUS),
  901. I915_READ(PCH_PP_CONTROL));
  902. if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
  903. DRM_ERROR("Panel status timeout: status %08x control %08x\n",
  904. I915_READ(PCH_PP_STATUS),
  905. I915_READ(PCH_PP_CONTROL));
  906. }
  907. }
  908. static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
  909. {
  910. DRM_DEBUG_KMS("Wait for panel power on\n");
  911. ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
  912. }
  913. static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
  914. {
  915. DRM_DEBUG_KMS("Wait for panel power off time\n");
  916. ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
  917. }
  918. static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
  919. {
  920. DRM_DEBUG_KMS("Wait for panel power cycle\n");
  921. ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
  922. }
  923. /* Read the current pp_control value, unlocking the register if it
  924. * is locked
  925. */
  926. static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
  927. {
  928. u32 control = I915_READ(PCH_PP_CONTROL);
  929. control &= ~PANEL_UNLOCK_MASK;
  930. control |= PANEL_UNLOCK_REGS;
  931. return control;
  932. }
  933. void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
  934. {
  935. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  936. struct drm_i915_private *dev_priv = dev->dev_private;
  937. u32 pp;
  938. if (!is_edp(intel_dp))
  939. return;
  940. DRM_DEBUG_KMS("Turn eDP VDD on\n");
  941. WARN(intel_dp->want_panel_vdd,
  942. "eDP VDD already requested on\n");
  943. intel_dp->want_panel_vdd = true;
  944. if (ironlake_edp_have_panel_vdd(intel_dp)) {
  945. DRM_DEBUG_KMS("eDP VDD already on\n");
  946. return;
  947. }
  948. if (!ironlake_edp_have_panel_power(intel_dp))
  949. ironlake_wait_panel_power_cycle(intel_dp);
  950. pp = ironlake_get_pp_control(dev_priv);
  951. pp |= EDP_FORCE_VDD;
  952. I915_WRITE(PCH_PP_CONTROL, pp);
  953. POSTING_READ(PCH_PP_CONTROL);
  954. DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
  955. I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
  956. /*
  957. * If the panel wasn't on, delay before accessing aux channel
  958. */
  959. if (!ironlake_edp_have_panel_power(intel_dp)) {
  960. DRM_DEBUG_KMS("eDP was not running\n");
  961. msleep(intel_dp->panel_power_up_delay);
  962. }
  963. }
  964. static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
  965. {
  966. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  967. struct drm_i915_private *dev_priv = dev->dev_private;
  968. u32 pp;
  969. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
  970. if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
  971. pp = ironlake_get_pp_control(dev_priv);
  972. pp &= ~EDP_FORCE_VDD;
  973. I915_WRITE(PCH_PP_CONTROL, pp);
  974. POSTING_READ(PCH_PP_CONTROL);
  975. /* Make sure sequencer is idle before allowing subsequent activity */
  976. DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
  977. I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
  978. msleep(intel_dp->panel_power_down_delay);
  979. }
  980. }
  981. static void ironlake_panel_vdd_work(struct work_struct *__work)
  982. {
  983. struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
  984. struct intel_dp, panel_vdd_work);
  985. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  986. mutex_lock(&dev->mode_config.mutex);
  987. ironlake_panel_vdd_off_sync(intel_dp);
  988. mutex_unlock(&dev->mode_config.mutex);
  989. }
  990. void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
  991. {
  992. if (!is_edp(intel_dp))
  993. return;
  994. DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
  995. WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
  996. intel_dp->want_panel_vdd = false;
  997. if (sync) {
  998. ironlake_panel_vdd_off_sync(intel_dp);
  999. } else {
  1000. /*
  1001. * Queue the timer to fire a long
  1002. * time from now (relative to the power down delay)
  1003. * to keep the panel power up across a sequence of operations
  1004. */
  1005. schedule_delayed_work(&intel_dp->panel_vdd_work,
  1006. msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
  1007. }
  1008. }
  1009. void ironlake_edp_panel_on(struct intel_dp *intel_dp)
  1010. {
  1011. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1012. struct drm_i915_private *dev_priv = dev->dev_private;
  1013. u32 pp;
  1014. if (!is_edp(intel_dp))
  1015. return;
  1016. DRM_DEBUG_KMS("Turn eDP power on\n");
  1017. if (ironlake_edp_have_panel_power(intel_dp)) {
  1018. DRM_DEBUG_KMS("eDP power already on\n");
  1019. return;
  1020. }
  1021. ironlake_wait_panel_power_cycle(intel_dp);
  1022. pp = ironlake_get_pp_control(dev_priv);
  1023. if (IS_GEN5(dev)) {
  1024. /* ILK workaround: disable reset around power sequence */
  1025. pp &= ~PANEL_POWER_RESET;
  1026. I915_WRITE(PCH_PP_CONTROL, pp);
  1027. POSTING_READ(PCH_PP_CONTROL);
  1028. }
  1029. pp |= POWER_TARGET_ON;
  1030. if (!IS_GEN5(dev))
  1031. pp |= PANEL_POWER_RESET;
  1032. I915_WRITE(PCH_PP_CONTROL, pp);
  1033. POSTING_READ(PCH_PP_CONTROL);
  1034. ironlake_wait_panel_on(intel_dp);
  1035. if (IS_GEN5(dev)) {
  1036. pp |= PANEL_POWER_RESET; /* restore panel reset bit */
  1037. I915_WRITE(PCH_PP_CONTROL, pp);
  1038. POSTING_READ(PCH_PP_CONTROL);
  1039. }
  1040. }
  1041. void ironlake_edp_panel_off(struct intel_dp *intel_dp)
  1042. {
  1043. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1044. struct drm_i915_private *dev_priv = dev->dev_private;
  1045. u32 pp;
  1046. if (!is_edp(intel_dp))
  1047. return;
  1048. DRM_DEBUG_KMS("Turn eDP power off\n");
  1049. WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
  1050. pp = ironlake_get_pp_control(dev_priv);
  1051. /* We need to switch off panel power _and_ force vdd, for otherwise some
  1052. * panels get very unhappy and cease to work. */
  1053. pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
  1054. I915_WRITE(PCH_PP_CONTROL, pp);
  1055. POSTING_READ(PCH_PP_CONTROL);
  1056. intel_dp->want_panel_vdd = false;
  1057. ironlake_wait_panel_off(intel_dp);
  1058. }
  1059. void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
  1060. {
  1061. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1062. struct drm_device *dev = intel_dig_port->base.base.dev;
  1063. struct drm_i915_private *dev_priv = dev->dev_private;
  1064. int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
  1065. u32 pp;
  1066. if (!is_edp(intel_dp))
  1067. return;
  1068. DRM_DEBUG_KMS("\n");
  1069. /*
  1070. * If we enable the backlight right away following a panel power
  1071. * on, we may see slight flicker as the panel syncs with the eDP
  1072. * link. So delay a bit to make sure the image is solid before
  1073. * allowing it to appear.
  1074. */
  1075. msleep(intel_dp->backlight_on_delay);
  1076. pp = ironlake_get_pp_control(dev_priv);
  1077. pp |= EDP_BLC_ENABLE;
  1078. I915_WRITE(PCH_PP_CONTROL, pp);
  1079. POSTING_READ(PCH_PP_CONTROL);
  1080. intel_panel_enable_backlight(dev, pipe);
  1081. }
  1082. void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
  1083. {
  1084. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1085. struct drm_i915_private *dev_priv = dev->dev_private;
  1086. u32 pp;
  1087. if (!is_edp(intel_dp))
  1088. return;
  1089. intel_panel_disable_backlight(dev);
  1090. DRM_DEBUG_KMS("\n");
  1091. pp = ironlake_get_pp_control(dev_priv);
  1092. pp &= ~EDP_BLC_ENABLE;
  1093. I915_WRITE(PCH_PP_CONTROL, pp);
  1094. POSTING_READ(PCH_PP_CONTROL);
  1095. msleep(intel_dp->backlight_off_delay);
  1096. }
  1097. static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
  1098. {
  1099. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1100. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1101. struct drm_device *dev = crtc->dev;
  1102. struct drm_i915_private *dev_priv = dev->dev_private;
  1103. u32 dpa_ctl;
  1104. assert_pipe_disabled(dev_priv,
  1105. to_intel_crtc(crtc)->pipe);
  1106. DRM_DEBUG_KMS("\n");
  1107. dpa_ctl = I915_READ(DP_A);
  1108. WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
  1109. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1110. /* We don't adjust intel_dp->DP while tearing down the link, to
  1111. * facilitate link retraining (e.g. after hotplug). Hence clear all
  1112. * enable bits here to ensure that we don't enable too much. */
  1113. intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
  1114. intel_dp->DP |= DP_PLL_ENABLE;
  1115. I915_WRITE(DP_A, intel_dp->DP);
  1116. POSTING_READ(DP_A);
  1117. udelay(200);
  1118. }
  1119. static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
  1120. {
  1121. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1122. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1123. struct drm_device *dev = crtc->dev;
  1124. struct drm_i915_private *dev_priv = dev->dev_private;
  1125. u32 dpa_ctl;
  1126. assert_pipe_disabled(dev_priv,
  1127. to_intel_crtc(crtc)->pipe);
  1128. dpa_ctl = I915_READ(DP_A);
  1129. WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
  1130. "dp pll off, should be on\n");
  1131. WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
  1132. /* We can't rely on the value tracked for the DP register in
  1133. * intel_dp->DP because link_down must not change that (otherwise link
  1134. * re-training will fail. */
  1135. dpa_ctl &= ~DP_PLL_ENABLE;
  1136. I915_WRITE(DP_A, dpa_ctl);
  1137. POSTING_READ(DP_A);
  1138. udelay(200);
  1139. }
  1140. /* If the sink supports it, try to set the power state appropriately */
  1141. void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
  1142. {
  1143. int ret, i;
  1144. /* Should have a valid DPCD by this point */
  1145. if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
  1146. return;
  1147. if (mode != DRM_MODE_DPMS_ON) {
  1148. ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
  1149. DP_SET_POWER_D3);
  1150. if (ret != 1)
  1151. DRM_DEBUG_DRIVER("failed to write sink power state\n");
  1152. } else {
  1153. /*
  1154. * When turning on, we need to retry for 1ms to give the sink
  1155. * time to wake up.
  1156. */
  1157. for (i = 0; i < 3; i++) {
  1158. ret = intel_dp_aux_native_write_1(intel_dp,
  1159. DP_SET_POWER,
  1160. DP_SET_POWER_D0);
  1161. if (ret == 1)
  1162. break;
  1163. msleep(1);
  1164. }
  1165. }
  1166. }
  1167. static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
  1168. enum pipe *pipe)
  1169. {
  1170. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1171. struct drm_device *dev = encoder->base.dev;
  1172. struct drm_i915_private *dev_priv = dev->dev_private;
  1173. u32 tmp = I915_READ(intel_dp->output_reg);
  1174. if (!(tmp & DP_PORT_EN))
  1175. return false;
  1176. if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
  1177. *pipe = PORT_TO_PIPE_CPT(tmp);
  1178. } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
  1179. *pipe = PORT_TO_PIPE(tmp);
  1180. } else {
  1181. u32 trans_sel;
  1182. u32 trans_dp;
  1183. int i;
  1184. switch (intel_dp->output_reg) {
  1185. case PCH_DP_B:
  1186. trans_sel = TRANS_DP_PORT_SEL_B;
  1187. break;
  1188. case PCH_DP_C:
  1189. trans_sel = TRANS_DP_PORT_SEL_C;
  1190. break;
  1191. case PCH_DP_D:
  1192. trans_sel = TRANS_DP_PORT_SEL_D;
  1193. break;
  1194. default:
  1195. return true;
  1196. }
  1197. for_each_pipe(i) {
  1198. trans_dp = I915_READ(TRANS_DP_CTL(i));
  1199. if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
  1200. *pipe = i;
  1201. return true;
  1202. }
  1203. }
  1204. DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
  1205. intel_dp->output_reg);
  1206. }
  1207. return true;
  1208. }
  1209. static void intel_disable_dp(struct intel_encoder *encoder)
  1210. {
  1211. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1212. /* Make sure the panel is off before trying to change the mode. But also
  1213. * ensure that we have vdd while we switch off the panel. */
  1214. ironlake_edp_panel_vdd_on(intel_dp);
  1215. ironlake_edp_backlight_off(intel_dp);
  1216. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1217. ironlake_edp_panel_off(intel_dp);
  1218. /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
  1219. if (!is_cpu_edp(intel_dp))
  1220. intel_dp_link_down(intel_dp);
  1221. }
  1222. static void intel_post_disable_dp(struct intel_encoder *encoder)
  1223. {
  1224. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1225. if (is_cpu_edp(intel_dp)) {
  1226. intel_dp_link_down(intel_dp);
  1227. ironlake_edp_pll_off(intel_dp);
  1228. }
  1229. }
  1230. static void intel_enable_dp(struct intel_encoder *encoder)
  1231. {
  1232. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1233. struct drm_device *dev = encoder->base.dev;
  1234. struct drm_i915_private *dev_priv = dev->dev_private;
  1235. uint32_t dp_reg = I915_READ(intel_dp->output_reg);
  1236. if (WARN_ON(dp_reg & DP_PORT_EN))
  1237. return;
  1238. ironlake_edp_panel_vdd_on(intel_dp);
  1239. intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
  1240. intel_dp_start_link_train(intel_dp);
  1241. ironlake_edp_panel_on(intel_dp);
  1242. ironlake_edp_panel_vdd_off(intel_dp, true);
  1243. intel_dp_complete_link_train(intel_dp);
  1244. ironlake_edp_backlight_on(intel_dp);
  1245. }
  1246. static void intel_pre_enable_dp(struct intel_encoder *encoder)
  1247. {
  1248. struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1249. if (is_cpu_edp(intel_dp))
  1250. ironlake_edp_pll_on(intel_dp);
  1251. }
  1252. /*
  1253. * Native read with retry for link status and receiver capability reads for
  1254. * cases where the sink may still be asleep.
  1255. */
  1256. static bool
  1257. intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
  1258. uint8_t *recv, int recv_bytes)
  1259. {
  1260. int ret, i;
  1261. /*
  1262. * Sinks are *supposed* to come up within 1ms from an off state,
  1263. * but we're also supposed to retry 3 times per the spec.
  1264. */
  1265. for (i = 0; i < 3; i++) {
  1266. ret = intel_dp_aux_native_read(intel_dp, address, recv,
  1267. recv_bytes);
  1268. if (ret == recv_bytes)
  1269. return true;
  1270. msleep(1);
  1271. }
  1272. return false;
  1273. }
  1274. /*
  1275. * Fetch AUX CH registers 0x202 - 0x207 which contain
  1276. * link status information
  1277. */
  1278. static bool
  1279. intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1280. {
  1281. return intel_dp_aux_native_read_retry(intel_dp,
  1282. DP_LANE0_1_STATUS,
  1283. link_status,
  1284. DP_LINK_STATUS_SIZE);
  1285. }
  1286. #if 0
  1287. static char *voltage_names[] = {
  1288. "0.4V", "0.6V", "0.8V", "1.2V"
  1289. };
  1290. static char *pre_emph_names[] = {
  1291. "0dB", "3.5dB", "6dB", "9.5dB"
  1292. };
  1293. static char *link_train_names[] = {
  1294. "pattern 1", "pattern 2", "idle", "off"
  1295. };
  1296. #endif
  1297. /*
  1298. * These are source-specific values; current Intel hardware supports
  1299. * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  1300. */
  1301. static uint8_t
  1302. intel_dp_voltage_max(struct intel_dp *intel_dp)
  1303. {
  1304. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1305. if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
  1306. return DP_TRAIN_VOLTAGE_SWING_800;
  1307. else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
  1308. return DP_TRAIN_VOLTAGE_SWING_1200;
  1309. else
  1310. return DP_TRAIN_VOLTAGE_SWING_800;
  1311. }
  1312. static uint8_t
  1313. intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
  1314. {
  1315. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1316. if (IS_HASWELL(dev)) {
  1317. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1318. case DP_TRAIN_VOLTAGE_SWING_400:
  1319. return DP_TRAIN_PRE_EMPHASIS_9_5;
  1320. case DP_TRAIN_VOLTAGE_SWING_600:
  1321. return DP_TRAIN_PRE_EMPHASIS_6;
  1322. case DP_TRAIN_VOLTAGE_SWING_800:
  1323. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1324. case DP_TRAIN_VOLTAGE_SWING_1200:
  1325. default:
  1326. return DP_TRAIN_PRE_EMPHASIS_0;
  1327. }
  1328. } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
  1329. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1330. case DP_TRAIN_VOLTAGE_SWING_400:
  1331. return DP_TRAIN_PRE_EMPHASIS_6;
  1332. case DP_TRAIN_VOLTAGE_SWING_600:
  1333. case DP_TRAIN_VOLTAGE_SWING_800:
  1334. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1335. default:
  1336. return DP_TRAIN_PRE_EMPHASIS_0;
  1337. }
  1338. } else {
  1339. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1340. case DP_TRAIN_VOLTAGE_SWING_400:
  1341. return DP_TRAIN_PRE_EMPHASIS_6;
  1342. case DP_TRAIN_VOLTAGE_SWING_600:
  1343. return DP_TRAIN_PRE_EMPHASIS_6;
  1344. case DP_TRAIN_VOLTAGE_SWING_800:
  1345. return DP_TRAIN_PRE_EMPHASIS_3_5;
  1346. case DP_TRAIN_VOLTAGE_SWING_1200:
  1347. default:
  1348. return DP_TRAIN_PRE_EMPHASIS_0;
  1349. }
  1350. }
  1351. }
  1352. static void
  1353. intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
  1354. {
  1355. uint8_t v = 0;
  1356. uint8_t p = 0;
  1357. int lane;
  1358. uint8_t voltage_max;
  1359. uint8_t preemph_max;
  1360. for (lane = 0; lane < intel_dp->lane_count; lane++) {
  1361. uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  1362. uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  1363. if (this_v > v)
  1364. v = this_v;
  1365. if (this_p > p)
  1366. p = this_p;
  1367. }
  1368. voltage_max = intel_dp_voltage_max(intel_dp);
  1369. if (v >= voltage_max)
  1370. v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
  1371. preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
  1372. if (p >= preemph_max)
  1373. p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  1374. for (lane = 0; lane < 4; lane++)
  1375. intel_dp->train_set[lane] = v | p;
  1376. }
  1377. static uint32_t
  1378. intel_gen4_signal_levels(uint8_t train_set)
  1379. {
  1380. uint32_t signal_levels = 0;
  1381. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  1382. case DP_TRAIN_VOLTAGE_SWING_400:
  1383. default:
  1384. signal_levels |= DP_VOLTAGE_0_4;
  1385. break;
  1386. case DP_TRAIN_VOLTAGE_SWING_600:
  1387. signal_levels |= DP_VOLTAGE_0_6;
  1388. break;
  1389. case DP_TRAIN_VOLTAGE_SWING_800:
  1390. signal_levels |= DP_VOLTAGE_0_8;
  1391. break;
  1392. case DP_TRAIN_VOLTAGE_SWING_1200:
  1393. signal_levels |= DP_VOLTAGE_1_2;
  1394. break;
  1395. }
  1396. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  1397. case DP_TRAIN_PRE_EMPHASIS_0:
  1398. default:
  1399. signal_levels |= DP_PRE_EMPHASIS_0;
  1400. break;
  1401. case DP_TRAIN_PRE_EMPHASIS_3_5:
  1402. signal_levels |= DP_PRE_EMPHASIS_3_5;
  1403. break;
  1404. case DP_TRAIN_PRE_EMPHASIS_6:
  1405. signal_levels |= DP_PRE_EMPHASIS_6;
  1406. break;
  1407. case DP_TRAIN_PRE_EMPHASIS_9_5:
  1408. signal_levels |= DP_PRE_EMPHASIS_9_5;
  1409. break;
  1410. }
  1411. return signal_levels;
  1412. }
  1413. /* Gen6's DP voltage swing and pre-emphasis control */
  1414. static uint32_t
  1415. intel_gen6_edp_signal_levels(uint8_t train_set)
  1416. {
  1417. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1418. DP_TRAIN_PRE_EMPHASIS_MASK);
  1419. switch (signal_levels) {
  1420. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1421. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1422. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1423. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1424. return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
  1425. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1426. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1427. return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
  1428. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1429. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1430. return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
  1431. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1432. case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
  1433. return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
  1434. default:
  1435. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1436. "0x%x\n", signal_levels);
  1437. return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
  1438. }
  1439. }
  1440. /* Gen7's DP voltage swing and pre-emphasis control */
  1441. static uint32_t
  1442. intel_gen7_edp_signal_levels(uint8_t train_set)
  1443. {
  1444. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1445. DP_TRAIN_PRE_EMPHASIS_MASK);
  1446. switch (signal_levels) {
  1447. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1448. return EDP_LINK_TRAIN_400MV_0DB_IVB;
  1449. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1450. return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
  1451. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1452. return EDP_LINK_TRAIN_400MV_6DB_IVB;
  1453. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1454. return EDP_LINK_TRAIN_600MV_0DB_IVB;
  1455. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1456. return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
  1457. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1458. return EDP_LINK_TRAIN_800MV_0DB_IVB;
  1459. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1460. return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
  1461. default:
  1462. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1463. "0x%x\n", signal_levels);
  1464. return EDP_LINK_TRAIN_500MV_0DB_IVB;
  1465. }
  1466. }
  1467. /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
  1468. static uint32_t
  1469. intel_hsw_signal_levels(uint8_t train_set)
  1470. {
  1471. int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
  1472. DP_TRAIN_PRE_EMPHASIS_MASK);
  1473. switch (signal_levels) {
  1474. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  1475. return DDI_BUF_EMP_400MV_0DB_HSW;
  1476. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1477. return DDI_BUF_EMP_400MV_3_5DB_HSW;
  1478. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  1479. return DDI_BUF_EMP_400MV_6DB_HSW;
  1480. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
  1481. return DDI_BUF_EMP_400MV_9_5DB_HSW;
  1482. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
  1483. return DDI_BUF_EMP_600MV_0DB_HSW;
  1484. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1485. return DDI_BUF_EMP_600MV_3_5DB_HSW;
  1486. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
  1487. return DDI_BUF_EMP_600MV_6DB_HSW;
  1488. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  1489. return DDI_BUF_EMP_800MV_0DB_HSW;
  1490. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
  1491. return DDI_BUF_EMP_800MV_3_5DB_HSW;
  1492. default:
  1493. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
  1494. "0x%x\n", signal_levels);
  1495. return DDI_BUF_EMP_400MV_0DB_HSW;
  1496. }
  1497. }
  1498. /* Properly updates "DP" with the correct signal levels. */
  1499. static void
  1500. intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
  1501. {
  1502. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1503. struct drm_device *dev = intel_dig_port->base.base.dev;
  1504. uint32_t signal_levels, mask;
  1505. uint8_t train_set = intel_dp->train_set[0];
  1506. if (IS_HASWELL(dev)) {
  1507. signal_levels = intel_hsw_signal_levels(train_set);
  1508. mask = DDI_BUF_EMP_MASK;
  1509. } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
  1510. signal_levels = intel_gen7_edp_signal_levels(train_set);
  1511. mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
  1512. } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
  1513. signal_levels = intel_gen6_edp_signal_levels(train_set);
  1514. mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
  1515. } else {
  1516. signal_levels = intel_gen4_signal_levels(train_set);
  1517. mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
  1518. }
  1519. DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
  1520. *DP = (*DP & ~mask) | signal_levels;
  1521. }
  1522. static bool
  1523. intel_dp_set_link_train(struct intel_dp *intel_dp,
  1524. uint32_t dp_reg_value,
  1525. uint8_t dp_train_pat)
  1526. {
  1527. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1528. struct drm_device *dev = intel_dig_port->base.base.dev;
  1529. struct drm_i915_private *dev_priv = dev->dev_private;
  1530. enum port port = intel_dig_port->port;
  1531. int ret;
  1532. uint32_t temp;
  1533. if (IS_HASWELL(dev)) {
  1534. temp = I915_READ(DP_TP_CTL(port));
  1535. if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
  1536. temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
  1537. else
  1538. temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
  1539. temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
  1540. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1541. case DP_TRAINING_PATTERN_DISABLE:
  1542. if (port != PORT_A) {
  1543. temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
  1544. I915_WRITE(DP_TP_CTL(port), temp);
  1545. if (wait_for((I915_READ(DP_TP_STATUS(port)) &
  1546. DP_TP_STATUS_IDLE_DONE), 1))
  1547. DRM_ERROR("Timed out waiting for DP idle patterns\n");
  1548. temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
  1549. }
  1550. temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
  1551. break;
  1552. case DP_TRAINING_PATTERN_1:
  1553. temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
  1554. break;
  1555. case DP_TRAINING_PATTERN_2:
  1556. temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
  1557. break;
  1558. case DP_TRAINING_PATTERN_3:
  1559. temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
  1560. break;
  1561. }
  1562. I915_WRITE(DP_TP_CTL(port), temp);
  1563. } else if (HAS_PCH_CPT(dev) &&
  1564. (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
  1565. dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
  1566. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1567. case DP_TRAINING_PATTERN_DISABLE:
  1568. dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
  1569. break;
  1570. case DP_TRAINING_PATTERN_1:
  1571. dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
  1572. break;
  1573. case DP_TRAINING_PATTERN_2:
  1574. dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
  1575. break;
  1576. case DP_TRAINING_PATTERN_3:
  1577. DRM_ERROR("DP training pattern 3 not supported\n");
  1578. dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
  1579. break;
  1580. }
  1581. } else {
  1582. dp_reg_value &= ~DP_LINK_TRAIN_MASK;
  1583. switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
  1584. case DP_TRAINING_PATTERN_DISABLE:
  1585. dp_reg_value |= DP_LINK_TRAIN_OFF;
  1586. break;
  1587. case DP_TRAINING_PATTERN_1:
  1588. dp_reg_value |= DP_LINK_TRAIN_PAT_1;
  1589. break;
  1590. case DP_TRAINING_PATTERN_2:
  1591. dp_reg_value |= DP_LINK_TRAIN_PAT_2;
  1592. break;
  1593. case DP_TRAINING_PATTERN_3:
  1594. DRM_ERROR("DP training pattern 3 not supported\n");
  1595. dp_reg_value |= DP_LINK_TRAIN_PAT_2;
  1596. break;
  1597. }
  1598. }
  1599. I915_WRITE(intel_dp->output_reg, dp_reg_value);
  1600. POSTING_READ(intel_dp->output_reg);
  1601. intel_dp_aux_native_write_1(intel_dp,
  1602. DP_TRAINING_PATTERN_SET,
  1603. dp_train_pat);
  1604. if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
  1605. DP_TRAINING_PATTERN_DISABLE) {
  1606. ret = intel_dp_aux_native_write(intel_dp,
  1607. DP_TRAINING_LANE0_SET,
  1608. intel_dp->train_set,
  1609. intel_dp->lane_count);
  1610. if (ret != intel_dp->lane_count)
  1611. return false;
  1612. }
  1613. return true;
  1614. }
  1615. /* Enable corresponding port and start training pattern 1 */
  1616. void
  1617. intel_dp_start_link_train(struct intel_dp *intel_dp)
  1618. {
  1619. struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
  1620. struct drm_device *dev = encoder->dev;
  1621. int i;
  1622. uint8_t voltage;
  1623. bool clock_recovery = false;
  1624. int voltage_tries, loop_tries;
  1625. uint32_t DP = intel_dp->DP;
  1626. if (HAS_DDI(dev))
  1627. intel_ddi_prepare_link_retrain(encoder);
  1628. /* Write the link configuration data */
  1629. intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
  1630. intel_dp->link_configuration,
  1631. DP_LINK_CONFIGURATION_SIZE);
  1632. DP |= DP_PORT_EN;
  1633. memset(intel_dp->train_set, 0, 4);
  1634. voltage = 0xff;
  1635. voltage_tries = 0;
  1636. loop_tries = 0;
  1637. clock_recovery = false;
  1638. for (;;) {
  1639. /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
  1640. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1641. intel_dp_set_signal_levels(intel_dp, &DP);
  1642. /* Set training pattern 1 */
  1643. if (!intel_dp_set_link_train(intel_dp, DP,
  1644. DP_TRAINING_PATTERN_1 |
  1645. DP_LINK_SCRAMBLING_DISABLE))
  1646. break;
  1647. drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
  1648. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  1649. DRM_ERROR("failed to get link status\n");
  1650. break;
  1651. }
  1652. if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  1653. DRM_DEBUG_KMS("clock recovery OK\n");
  1654. clock_recovery = true;
  1655. break;
  1656. }
  1657. /* Check to see if we've tried the max voltage */
  1658. for (i = 0; i < intel_dp->lane_count; i++)
  1659. if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  1660. break;
  1661. if (i == intel_dp->lane_count && voltage_tries == 5) {
  1662. ++loop_tries;
  1663. if (loop_tries == 5) {
  1664. DRM_DEBUG_KMS("too many full retries, give up\n");
  1665. break;
  1666. }
  1667. memset(intel_dp->train_set, 0, 4);
  1668. voltage_tries = 0;
  1669. continue;
  1670. }
  1671. /* Check to see if we've tried the same voltage 5 times */
  1672. if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  1673. ++voltage_tries;
  1674. if (voltage_tries == 5) {
  1675. DRM_DEBUG_KMS("too many voltage retries, give up\n");
  1676. break;
  1677. }
  1678. } else
  1679. voltage_tries = 0;
  1680. voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  1681. /* Compute new intel_dp->train_set as requested by target */
  1682. intel_get_adjust_train(intel_dp, link_status);
  1683. }
  1684. intel_dp->DP = DP;
  1685. }
  1686. void
  1687. intel_dp_complete_link_train(struct intel_dp *intel_dp)
  1688. {
  1689. bool channel_eq = false;
  1690. int tries, cr_tries;
  1691. uint32_t DP = intel_dp->DP;
  1692. /* channel equalization */
  1693. tries = 0;
  1694. cr_tries = 0;
  1695. channel_eq = false;
  1696. for (;;) {
  1697. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1698. if (cr_tries > 5) {
  1699. DRM_ERROR("failed to train DP, aborting\n");
  1700. intel_dp_link_down(intel_dp);
  1701. break;
  1702. }
  1703. intel_dp_set_signal_levels(intel_dp, &DP);
  1704. /* channel eq pattern */
  1705. if (!intel_dp_set_link_train(intel_dp, DP,
  1706. DP_TRAINING_PATTERN_2 |
  1707. DP_LINK_SCRAMBLING_DISABLE))
  1708. break;
  1709. drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
  1710. if (!intel_dp_get_link_status(intel_dp, link_status))
  1711. break;
  1712. /* Make sure clock is still ok */
  1713. if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
  1714. intel_dp_start_link_train(intel_dp);
  1715. cr_tries++;
  1716. continue;
  1717. }
  1718. if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
  1719. channel_eq = true;
  1720. break;
  1721. }
  1722. /* Try 5 times, then try clock recovery if that fails */
  1723. if (tries > 5) {
  1724. intel_dp_link_down(intel_dp);
  1725. intel_dp_start_link_train(intel_dp);
  1726. tries = 0;
  1727. cr_tries++;
  1728. continue;
  1729. }
  1730. /* Compute new intel_dp->train_set as requested by target */
  1731. intel_get_adjust_train(intel_dp, link_status);
  1732. ++tries;
  1733. }
  1734. if (channel_eq)
  1735. DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
  1736. intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
  1737. }
  1738. static void
  1739. intel_dp_link_down(struct intel_dp *intel_dp)
  1740. {
  1741. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1742. struct drm_device *dev = intel_dig_port->base.base.dev;
  1743. struct drm_i915_private *dev_priv = dev->dev_private;
  1744. struct intel_crtc *intel_crtc =
  1745. to_intel_crtc(intel_dig_port->base.base.crtc);
  1746. uint32_t DP = intel_dp->DP;
  1747. /*
  1748. * DDI code has a strict mode set sequence and we should try to respect
  1749. * it, otherwise we might hang the machine in many different ways. So we
  1750. * really should be disabling the port only on a complete crtc_disable
  1751. * sequence. This function is just called under two conditions on DDI
  1752. * code:
  1753. * - Link train failed while doing crtc_enable, and on this case we
  1754. * really should respect the mode set sequence and wait for a
  1755. * crtc_disable.
  1756. * - Someone turned the monitor off and intel_dp_check_link_status
  1757. * called us. We don't need to disable the whole port on this case, so
  1758. * when someone turns the monitor on again,
  1759. * intel_ddi_prepare_link_retrain will take care of redoing the link
  1760. * train.
  1761. */
  1762. if (HAS_DDI(dev))
  1763. return;
  1764. if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
  1765. return;
  1766. DRM_DEBUG_KMS("\n");
  1767. if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
  1768. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  1769. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
  1770. } else {
  1771. DP &= ~DP_LINK_TRAIN_MASK;
  1772. I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
  1773. }
  1774. POSTING_READ(intel_dp->output_reg);
  1775. /* We don't really know why we're doing this */
  1776. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1777. if (HAS_PCH_IBX(dev) &&
  1778. I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
  1779. struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
  1780. /* Hardware workaround: leaving our transcoder select
  1781. * set to transcoder B while it's off will prevent the
  1782. * corresponding HDMI output on transcoder A.
  1783. *
  1784. * Combine this with another hardware workaround:
  1785. * transcoder select bit can only be cleared while the
  1786. * port is enabled.
  1787. */
  1788. DP &= ~DP_PIPEB_SELECT;
  1789. I915_WRITE(intel_dp->output_reg, DP);
  1790. /* Changes to enable or select take place the vblank
  1791. * after being written.
  1792. */
  1793. if (WARN_ON(crtc == NULL)) {
  1794. /* We should never try to disable a port without a crtc
  1795. * attached. For paranoia keep the code around for a
  1796. * bit. */
  1797. POSTING_READ(intel_dp->output_reg);
  1798. msleep(50);
  1799. } else
  1800. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1801. }
  1802. DP &= ~DP_AUDIO_OUTPUT_ENABLE;
  1803. I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
  1804. POSTING_READ(intel_dp->output_reg);
  1805. msleep(intel_dp->panel_power_down_delay);
  1806. }
  1807. static bool
  1808. intel_dp_get_dpcd(struct intel_dp *intel_dp)
  1809. {
  1810. char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
  1811. if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
  1812. sizeof(intel_dp->dpcd)) == 0)
  1813. return false; /* aux transfer failed */
  1814. hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
  1815. 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
  1816. DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
  1817. if (intel_dp->dpcd[DP_DPCD_REV] == 0)
  1818. return false; /* DPCD not present */
  1819. if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
  1820. DP_DWN_STRM_PORT_PRESENT))
  1821. return true; /* native DP sink */
  1822. if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
  1823. return true; /* no per-port downstream info */
  1824. if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
  1825. intel_dp->downstream_ports,
  1826. DP_MAX_DOWNSTREAM_PORTS) == 0)
  1827. return false; /* downstream port status fetch failed */
  1828. return true;
  1829. }
  1830. static void
  1831. intel_dp_probe_oui(struct intel_dp *intel_dp)
  1832. {
  1833. u8 buf[3];
  1834. if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  1835. return;
  1836. ironlake_edp_panel_vdd_on(intel_dp);
  1837. if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
  1838. DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
  1839. buf[0], buf[1], buf[2]);
  1840. if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
  1841. DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
  1842. buf[0], buf[1], buf[2]);
  1843. ironlake_edp_panel_vdd_off(intel_dp, false);
  1844. }
  1845. static bool
  1846. intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
  1847. {
  1848. int ret;
  1849. ret = intel_dp_aux_native_read_retry(intel_dp,
  1850. DP_DEVICE_SERVICE_IRQ_VECTOR,
  1851. sink_irq_vector, 1);
  1852. if (!ret)
  1853. return false;
  1854. return true;
  1855. }
  1856. static void
  1857. intel_dp_handle_test_request(struct intel_dp *intel_dp)
  1858. {
  1859. /* NAK by default */
  1860. intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
  1861. }
  1862. /*
  1863. * According to DP spec
  1864. * 5.1.2:
  1865. * 1. Read DPCD
  1866. * 2. Configure link according to Receiver Capabilities
  1867. * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
  1868. * 4. Check link status on receipt of hot-plug interrupt
  1869. */
  1870. void
  1871. intel_dp_check_link_status(struct intel_dp *intel_dp)
  1872. {
  1873. struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
  1874. u8 sink_irq_vector;
  1875. u8 link_status[DP_LINK_STATUS_SIZE];
  1876. if (!intel_encoder->connectors_active)
  1877. return;
  1878. if (WARN_ON(!intel_encoder->base.crtc))
  1879. return;
  1880. /* Try to read receiver status if the link appears to be up */
  1881. if (!intel_dp_get_link_status(intel_dp, link_status)) {
  1882. intel_dp_link_down(intel_dp);
  1883. return;
  1884. }
  1885. /* Now read the DPCD to see if it's actually running */
  1886. if (!intel_dp_get_dpcd(intel_dp)) {
  1887. intel_dp_link_down(intel_dp);
  1888. return;
  1889. }
  1890. /* Try to read the source of the interrupt */
  1891. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
  1892. intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
  1893. /* Clear interrupt source */
  1894. intel_dp_aux_native_write_1(intel_dp,
  1895. DP_DEVICE_SERVICE_IRQ_VECTOR,
  1896. sink_irq_vector);
  1897. if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
  1898. intel_dp_handle_test_request(intel_dp);
  1899. if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
  1900. DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
  1901. }
  1902. if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
  1903. DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
  1904. drm_get_encoder_name(&intel_encoder->base));
  1905. intel_dp_start_link_train(intel_dp);
  1906. intel_dp_complete_link_train(intel_dp);
  1907. }
  1908. }
  1909. /* XXX this is probably wrong for multiple downstream ports */
  1910. static enum drm_connector_status
  1911. intel_dp_detect_dpcd(struct intel_dp *intel_dp)
  1912. {
  1913. uint8_t *dpcd = intel_dp->dpcd;
  1914. bool hpd;
  1915. uint8_t type;
  1916. if (!intel_dp_get_dpcd(intel_dp))
  1917. return connector_status_disconnected;
  1918. /* if there's no downstream port, we're done */
  1919. if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
  1920. return connector_status_connected;
  1921. /* If we're HPD-aware, SINK_COUNT changes dynamically */
  1922. hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
  1923. if (hpd) {
  1924. uint8_t reg;
  1925. if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
  1926. &reg, 1))
  1927. return connector_status_unknown;
  1928. return DP_GET_SINK_COUNT(reg) ? connector_status_connected
  1929. : connector_status_disconnected;
  1930. }
  1931. /* If no HPD, poke DDC gently */
  1932. if (drm_probe_ddc(&intel_dp->adapter))
  1933. return connector_status_connected;
  1934. /* Well we tried, say unknown for unreliable port types */
  1935. type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
  1936. if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
  1937. return connector_status_unknown;
  1938. /* Anything else is out of spec, warn and ignore */
  1939. DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
  1940. return connector_status_disconnected;
  1941. }
  1942. static enum drm_connector_status
  1943. ironlake_dp_detect(struct intel_dp *intel_dp)
  1944. {
  1945. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1946. struct drm_i915_private *dev_priv = dev->dev_private;
  1947. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1948. enum drm_connector_status status;
  1949. /* Can't disconnect eDP, but you can close the lid... */
  1950. if (is_edp(intel_dp)) {
  1951. status = intel_panel_detect(dev);
  1952. if (status == connector_status_unknown)
  1953. status = connector_status_connected;
  1954. return status;
  1955. }
  1956. if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
  1957. return connector_status_disconnected;
  1958. return intel_dp_detect_dpcd(intel_dp);
  1959. }
  1960. static enum drm_connector_status
  1961. g4x_dp_detect(struct intel_dp *intel_dp)
  1962. {
  1963. struct drm_device *dev = intel_dp_to_dev(intel_dp);
  1964. struct drm_i915_private *dev_priv = dev->dev_private;
  1965. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  1966. uint32_t bit;
  1967. switch (intel_dig_port->port) {
  1968. case PORT_B:
  1969. bit = PORTB_HOTPLUG_LIVE_STATUS;
  1970. break;
  1971. case PORT_C:
  1972. bit = PORTC_HOTPLUG_LIVE_STATUS;
  1973. break;
  1974. case PORT_D:
  1975. bit = PORTD_HOTPLUG_LIVE_STATUS;
  1976. break;
  1977. default:
  1978. return connector_status_unknown;
  1979. }
  1980. if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
  1981. return connector_status_disconnected;
  1982. return intel_dp_detect_dpcd(intel_dp);
  1983. }
  1984. static struct edid *
  1985. intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
  1986. {
  1987. struct intel_connector *intel_connector = to_intel_connector(connector);
  1988. /* use cached edid if we have one */
  1989. if (intel_connector->edid) {
  1990. struct edid *edid;
  1991. int size;
  1992. /* invalid edid */
  1993. if (IS_ERR(intel_connector->edid))
  1994. return NULL;
  1995. size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
  1996. edid = kmalloc(size, GFP_KERNEL);
  1997. if (!edid)
  1998. return NULL;
  1999. memcpy(edid, intel_connector->edid, size);
  2000. return edid;
  2001. }
  2002. return drm_get_edid(connector, adapter);
  2003. }
  2004. static int
  2005. intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
  2006. {
  2007. struct intel_connector *intel_connector = to_intel_connector(connector);
  2008. /* use cached edid if we have one */
  2009. if (intel_connector->edid) {
  2010. /* invalid edid */
  2011. if (IS_ERR(intel_connector->edid))
  2012. return 0;
  2013. return intel_connector_update_modes(connector,
  2014. intel_connector->edid);
  2015. }
  2016. return intel_ddc_get_modes(connector, adapter);
  2017. }
  2018. static enum drm_connector_status
  2019. intel_dp_detect(struct drm_connector *connector, bool force)
  2020. {
  2021. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2022. struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  2023. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  2024. struct drm_device *dev = connector->dev;
  2025. enum drm_connector_status status;
  2026. struct edid *edid = NULL;
  2027. intel_dp->has_audio = false;
  2028. if (HAS_PCH_SPLIT(dev))
  2029. status = ironlake_dp_detect(intel_dp);
  2030. else
  2031. status = g4x_dp_detect(intel_dp);
  2032. if (status != connector_status_connected)
  2033. return status;
  2034. intel_dp_probe_oui(intel_dp);
  2035. if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
  2036. intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
  2037. } else {
  2038. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  2039. if (edid) {
  2040. intel_dp->has_audio = drm_detect_monitor_audio(edid);
  2041. kfree(edid);
  2042. }
  2043. }
  2044. if (intel_encoder->type != INTEL_OUTPUT_EDP)
  2045. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  2046. return connector_status_connected;
  2047. }
  2048. static int intel_dp_get_modes(struct drm_connector *connector)
  2049. {
  2050. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2051. struct intel_connector *intel_connector = to_intel_connector(connector);
  2052. struct drm_device *dev = connector->dev;
  2053. int ret;
  2054. /* We should parse the EDID data and find out if it has an audio sink
  2055. */
  2056. ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
  2057. if (ret)
  2058. return ret;
  2059. /* if eDP has no EDID, fall back to fixed mode */
  2060. if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
  2061. struct drm_display_mode *mode;
  2062. mode = drm_mode_duplicate(dev,
  2063. intel_connector->panel.fixed_mode);
  2064. if (mode) {
  2065. drm_mode_probed_add(connector, mode);
  2066. return 1;
  2067. }
  2068. }
  2069. return 0;
  2070. }
  2071. static bool
  2072. intel_dp_detect_audio(struct drm_connector *connector)
  2073. {
  2074. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2075. struct edid *edid;
  2076. bool has_audio = false;
  2077. edid = intel_dp_get_edid(connector, &intel_dp->adapter);
  2078. if (edid) {
  2079. has_audio = drm_detect_monitor_audio(edid);
  2080. kfree(edid);
  2081. }
  2082. return has_audio;
  2083. }
  2084. static int
  2085. intel_dp_set_property(struct drm_connector *connector,
  2086. struct drm_property *property,
  2087. uint64_t val)
  2088. {
  2089. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  2090. struct intel_connector *intel_connector = to_intel_connector(connector);
  2091. struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
  2092. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2093. int ret;
  2094. ret = drm_object_property_set_value(&connector->base, property, val);
  2095. if (ret)
  2096. return ret;
  2097. if (property == dev_priv->force_audio_property) {
  2098. int i = val;
  2099. bool has_audio;
  2100. if (i == intel_dp->force_audio)
  2101. return 0;
  2102. intel_dp->force_audio = i;
  2103. if (i == HDMI_AUDIO_AUTO)
  2104. has_audio = intel_dp_detect_audio(connector);
  2105. else
  2106. has_audio = (i == HDMI_AUDIO_ON);
  2107. if (has_audio == intel_dp->has_audio)
  2108. return 0;
  2109. intel_dp->has_audio = has_audio;
  2110. goto done;
  2111. }
  2112. if (property == dev_priv->broadcast_rgb_property) {
  2113. switch (val) {
  2114. case INTEL_BROADCAST_RGB_AUTO:
  2115. intel_dp->color_range_auto = true;
  2116. break;
  2117. case INTEL_BROADCAST_RGB_FULL:
  2118. intel_dp->color_range_auto = false;
  2119. intel_dp->color_range = 0;
  2120. break;
  2121. case INTEL_BROADCAST_RGB_LIMITED:
  2122. intel_dp->color_range_auto = false;
  2123. intel_dp->color_range = DP_COLOR_RANGE_16_235;
  2124. break;
  2125. default:
  2126. return -EINVAL;
  2127. }
  2128. goto done;
  2129. }
  2130. if (is_edp(intel_dp) &&
  2131. property == connector->dev->mode_config.scaling_mode_property) {
  2132. if (val == DRM_MODE_SCALE_NONE) {
  2133. DRM_DEBUG_KMS("no scaling not supported\n");
  2134. return -EINVAL;
  2135. }
  2136. if (intel_connector->panel.fitting_mode == val) {
  2137. /* the eDP scaling property is not changed */
  2138. return 0;
  2139. }
  2140. intel_connector->panel.fitting_mode = val;
  2141. goto done;
  2142. }
  2143. return -EINVAL;
  2144. done:
  2145. if (intel_encoder->base.crtc)
  2146. intel_crtc_restore_mode(intel_encoder->base.crtc);
  2147. return 0;
  2148. }
  2149. static void
  2150. intel_dp_destroy(struct drm_connector *connector)
  2151. {
  2152. struct drm_device *dev = connector->dev;
  2153. struct intel_dp *intel_dp = intel_attached_dp(connector);
  2154. struct intel_connector *intel_connector = to_intel_connector(connector);
  2155. if (!IS_ERR_OR_NULL(intel_connector->edid))
  2156. kfree(intel_connector->edid);
  2157. if (is_edp(intel_dp)) {
  2158. intel_panel_destroy_backlight(dev);
  2159. intel_panel_fini(&intel_connector->panel);
  2160. }
  2161. drm_sysfs_connector_remove(connector);
  2162. drm_connector_cleanup(connector);
  2163. kfree(connector);
  2164. }
  2165. void intel_dp_encoder_destroy(struct drm_encoder *encoder)
  2166. {
  2167. struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  2168. struct intel_dp *intel_dp = &intel_dig_port->dp;
  2169. i2c_del_adapter(&intel_dp->adapter);
  2170. drm_encoder_cleanup(encoder);
  2171. if (is_edp(intel_dp)) {
  2172. cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
  2173. ironlake_panel_vdd_off_sync(intel_dp);
  2174. }
  2175. kfree(intel_dig_port);
  2176. }
  2177. static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
  2178. .mode_fixup = intel_dp_mode_fixup,
  2179. .mode_set = intel_dp_mode_set,
  2180. };
  2181. static const struct drm_connector_funcs intel_dp_connector_funcs = {
  2182. .dpms = intel_connector_dpms,
  2183. .detect = intel_dp_detect,
  2184. .fill_modes = drm_helper_probe_single_connector_modes,
  2185. .set_property = intel_dp_set_property,
  2186. .destroy = intel_dp_destroy,
  2187. };
  2188. static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
  2189. .get_modes = intel_dp_get_modes,
  2190. .mode_valid = intel_dp_mode_valid,
  2191. .best_encoder = intel_best_encoder,
  2192. };
  2193. static const struct drm_encoder_funcs intel_dp_enc_funcs = {
  2194. .destroy = intel_dp_encoder_destroy,
  2195. };
  2196. static void
  2197. intel_dp_hot_plug(struct intel_encoder *intel_encoder)
  2198. {
  2199. struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2200. intel_dp_check_link_status(intel_dp);
  2201. }
  2202. /* Return which DP Port should be selected for Transcoder DP control */
  2203. int
  2204. intel_trans_dp_port_sel(struct drm_crtc *crtc)
  2205. {
  2206. struct drm_device *dev = crtc->dev;
  2207. struct intel_encoder *intel_encoder;
  2208. struct intel_dp *intel_dp;
  2209. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  2210. intel_dp = enc_to_intel_dp(&intel_encoder->base);
  2211. if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
  2212. intel_encoder->type == INTEL_OUTPUT_EDP)
  2213. return intel_dp->output_reg;
  2214. }
  2215. return -1;
  2216. }
  2217. /* check the VBT to see whether the eDP is on DP-D port */
  2218. bool intel_dpd_is_edp(struct drm_device *dev)
  2219. {
  2220. struct drm_i915_private *dev_priv = dev->dev_private;
  2221. struct child_device_config *p_child;
  2222. int i;
  2223. if (!dev_priv->child_dev_num)
  2224. return false;
  2225. for (i = 0; i < dev_priv->child_dev_num; i++) {
  2226. p_child = dev_priv->child_dev + i;
  2227. if (p_child->dvo_port == PORT_IDPD &&
  2228. p_child->device_type == DEVICE_TYPE_eDP)
  2229. return true;
  2230. }
  2231. return false;
  2232. }
  2233. static void
  2234. intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
  2235. {
  2236. struct intel_connector *intel_connector = to_intel_connector(connector);
  2237. intel_attach_force_audio_property(connector);
  2238. intel_attach_broadcast_rgb_property(connector);
  2239. intel_dp->color_range_auto = true;
  2240. if (is_edp(intel_dp)) {
  2241. drm_mode_create_scaling_mode_property(connector->dev);
  2242. drm_object_attach_property(
  2243. &connector->base,
  2244. connector->dev->mode_config.scaling_mode_property,
  2245. DRM_MODE_SCALE_ASPECT);
  2246. intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
  2247. }
  2248. }
  2249. static void
  2250. intel_dp_init_panel_power_sequencer(struct drm_device *dev,
  2251. struct intel_dp *intel_dp,
  2252. struct edp_power_seq *out)
  2253. {
  2254. struct drm_i915_private *dev_priv = dev->dev_private;
  2255. struct edp_power_seq cur, vbt, spec, final;
  2256. u32 pp_on, pp_off, pp_div, pp;
  2257. /* Workaround: Need to write PP_CONTROL with the unlock key as
  2258. * the very first thing. */
  2259. pp = ironlake_get_pp_control(dev_priv);
  2260. I915_WRITE(PCH_PP_CONTROL, pp);
  2261. pp_on = I915_READ(PCH_PP_ON_DELAYS);
  2262. pp_off = I915_READ(PCH_PP_OFF_DELAYS);
  2263. pp_div = I915_READ(PCH_PP_DIVISOR);
  2264. /* Pull timing values out of registers */
  2265. cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
  2266. PANEL_POWER_UP_DELAY_SHIFT;
  2267. cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
  2268. PANEL_LIGHT_ON_DELAY_SHIFT;
  2269. cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
  2270. PANEL_LIGHT_OFF_DELAY_SHIFT;
  2271. cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
  2272. PANEL_POWER_DOWN_DELAY_SHIFT;
  2273. cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
  2274. PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
  2275. DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2276. cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
  2277. vbt = dev_priv->edp.pps;
  2278. /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
  2279. * our hw here, which are all in 100usec. */
  2280. spec.t1_t3 = 210 * 10;
  2281. spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
  2282. spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
  2283. spec.t10 = 500 * 10;
  2284. /* This one is special and actually in units of 100ms, but zero
  2285. * based in the hw (so we need to add 100 ms). But the sw vbt
  2286. * table multiplies it with 1000 to make it in units of 100usec,
  2287. * too. */
  2288. spec.t11_t12 = (510 + 100) * 10;
  2289. DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
  2290. vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
  2291. /* Use the max of the register settings and vbt. If both are
  2292. * unset, fall back to the spec limits. */
  2293. #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
  2294. spec.field : \
  2295. max(cur.field, vbt.field))
  2296. assign_final(t1_t3);
  2297. assign_final(t8);
  2298. assign_final(t9);
  2299. assign_final(t10);
  2300. assign_final(t11_t12);
  2301. #undef assign_final
  2302. #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
  2303. intel_dp->panel_power_up_delay = get_delay(t1_t3);
  2304. intel_dp->backlight_on_delay = get_delay(t8);
  2305. intel_dp->backlight_off_delay = get_delay(t9);
  2306. intel_dp->panel_power_down_delay = get_delay(t10);
  2307. intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
  2308. #undef get_delay
  2309. DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
  2310. intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
  2311. intel_dp->panel_power_cycle_delay);
  2312. DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
  2313. intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
  2314. if (out)
  2315. *out = final;
  2316. }
  2317. static void
  2318. intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
  2319. struct intel_dp *intel_dp,
  2320. struct edp_power_seq *seq)
  2321. {
  2322. struct drm_i915_private *dev_priv = dev->dev_private;
  2323. u32 pp_on, pp_off, pp_div;
  2324. /* And finally store the new values in the power sequencer. */
  2325. pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
  2326. (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
  2327. pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
  2328. (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
  2329. /* Compute the divisor for the pp clock, simply match the Bspec
  2330. * formula. */
  2331. pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
  2332. << PP_REFERENCE_DIVIDER_SHIFT;
  2333. pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
  2334. << PANEL_POWER_CYCLE_DELAY_SHIFT);
  2335. /* Haswell doesn't have any port selection bits for the panel
  2336. * power sequencer any more. */
  2337. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
  2338. if (is_cpu_edp(intel_dp))
  2339. pp_on |= PANEL_POWER_PORT_DP_A;
  2340. else
  2341. pp_on |= PANEL_POWER_PORT_DP_D;
  2342. }
  2343. I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
  2344. I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
  2345. I915_WRITE(PCH_PP_DIVISOR, pp_div);
  2346. DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
  2347. I915_READ(PCH_PP_ON_DELAYS),
  2348. I915_READ(PCH_PP_OFF_DELAYS),
  2349. I915_READ(PCH_PP_DIVISOR));
  2350. }
  2351. void
  2352. intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
  2353. struct intel_connector *intel_connector)
  2354. {
  2355. struct drm_connector *connector = &intel_connector->base;
  2356. struct intel_dp *intel_dp = &intel_dig_port->dp;
  2357. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  2358. struct drm_device *dev = intel_encoder->base.dev;
  2359. struct drm_i915_private *dev_priv = dev->dev_private;
  2360. struct drm_display_mode *fixed_mode = NULL;
  2361. struct edp_power_seq power_seq = { 0 };
  2362. enum port port = intel_dig_port->port;
  2363. const char *name = NULL;
  2364. int type;
  2365. /* Preserve the current hw state. */
  2366. intel_dp->DP = I915_READ(intel_dp->output_reg);
  2367. intel_dp->attached_connector = intel_connector;
  2368. if (HAS_PCH_SPLIT(dev) && port == PORT_D)
  2369. if (intel_dpd_is_edp(dev))
  2370. intel_dp->is_pch_edp = true;
  2371. /*
  2372. * FIXME : We need to initialize built-in panels before external panels.
  2373. * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
  2374. */
  2375. if (IS_VALLEYVIEW(dev) && port == PORT_C) {
  2376. type = DRM_MODE_CONNECTOR_eDP;
  2377. intel_encoder->type = INTEL_OUTPUT_EDP;
  2378. } else if (port == PORT_A || is_pch_edp(intel_dp)) {
  2379. type = DRM_MODE_CONNECTOR_eDP;
  2380. intel_encoder->type = INTEL_OUTPUT_EDP;
  2381. } else {
  2382. /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
  2383. * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
  2384. * rewrite it.
  2385. */
  2386. type = DRM_MODE_CONNECTOR_DisplayPort;
  2387. }
  2388. drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
  2389. drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
  2390. connector->polled = DRM_CONNECTOR_POLL_HPD;
  2391. connector->interlace_allowed = true;
  2392. connector->doublescan_allowed = 0;
  2393. INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
  2394. ironlake_panel_vdd_work);
  2395. intel_connector_attach_encoder(intel_connector, intel_encoder);
  2396. drm_sysfs_connector_add(connector);
  2397. if (HAS_DDI(dev))
  2398. intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
  2399. else
  2400. intel_connector->get_hw_state = intel_connector_get_hw_state;
  2401. /* Set up the DDC bus. */
  2402. switch (port) {
  2403. case PORT_A:
  2404. name = "DPDDC-A";
  2405. break;
  2406. case PORT_B:
  2407. dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
  2408. name = "DPDDC-B";
  2409. break;
  2410. case PORT_C:
  2411. dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
  2412. name = "DPDDC-C";
  2413. break;
  2414. case PORT_D:
  2415. dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
  2416. name = "DPDDC-D";
  2417. break;
  2418. default:
  2419. WARN(1, "Invalid port %c\n", port_name(port));
  2420. break;
  2421. }
  2422. if (is_edp(intel_dp))
  2423. intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
  2424. intel_dp_i2c_init(intel_dp, intel_connector, name);
  2425. /* Cache DPCD and EDID for edp. */
  2426. if (is_edp(intel_dp)) {
  2427. bool ret;
  2428. struct drm_display_mode *scan;
  2429. struct edid *edid;
  2430. ironlake_edp_panel_vdd_on(intel_dp);
  2431. ret = intel_dp_get_dpcd(intel_dp);
  2432. ironlake_edp_panel_vdd_off(intel_dp, false);
  2433. if (ret) {
  2434. if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
  2435. dev_priv->no_aux_handshake =
  2436. intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
  2437. DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
  2438. } else {
  2439. /* if this fails, presume the device is a ghost */
  2440. DRM_INFO("failed to retrieve link info, disabling eDP\n");
  2441. intel_dp_encoder_destroy(&intel_encoder->base);
  2442. intel_dp_destroy(connector);
  2443. return;
  2444. }
  2445. /* We now know it's not a ghost, init power sequence regs. */
  2446. intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
  2447. &power_seq);
  2448. ironlake_edp_panel_vdd_on(intel_dp);
  2449. edid = drm_get_edid(connector, &intel_dp->adapter);
  2450. if (edid) {
  2451. if (drm_add_edid_modes(connector, edid)) {
  2452. drm_mode_connector_update_edid_property(connector, edid);
  2453. drm_edid_to_eld(connector, edid);
  2454. } else {
  2455. kfree(edid);
  2456. edid = ERR_PTR(-EINVAL);
  2457. }
  2458. } else {
  2459. edid = ERR_PTR(-ENOENT);
  2460. }
  2461. intel_connector->edid = edid;
  2462. /* prefer fixed mode from EDID if available */
  2463. list_for_each_entry(scan, &connector->probed_modes, head) {
  2464. if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
  2465. fixed_mode = drm_mode_duplicate(dev, scan);
  2466. break;
  2467. }
  2468. }
  2469. /* fallback to VBT if available for eDP */
  2470. if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
  2471. fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
  2472. if (fixed_mode)
  2473. fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  2474. }
  2475. ironlake_edp_panel_vdd_off(intel_dp, false);
  2476. }
  2477. if (is_edp(intel_dp)) {
  2478. intel_panel_init(&intel_connector->panel, fixed_mode);
  2479. intel_panel_setup_backlight(connector);
  2480. }
  2481. intel_dp_add_properties(intel_dp, connector);
  2482. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  2483. * 0xd. Failure to do so will result in spurious interrupts being
  2484. * generated on the port when a cable is not attached.
  2485. */
  2486. if (IS_G4X(dev) && !IS_GM45(dev)) {
  2487. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  2488. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  2489. }
  2490. }
  2491. void
  2492. intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
  2493. {
  2494. struct intel_digital_port *intel_dig_port;
  2495. struct intel_encoder *intel_encoder;
  2496. struct drm_encoder *encoder;
  2497. struct intel_connector *intel_connector;
  2498. intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
  2499. if (!intel_dig_port)
  2500. return;
  2501. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  2502. if (!intel_connector) {
  2503. kfree(intel_dig_port);
  2504. return;
  2505. }
  2506. intel_encoder = &intel_dig_port->base;
  2507. encoder = &intel_encoder->base;
  2508. drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
  2509. DRM_MODE_ENCODER_TMDS);
  2510. drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
  2511. intel_encoder->enable = intel_enable_dp;
  2512. intel_encoder->pre_enable = intel_pre_enable_dp;
  2513. intel_encoder->disable = intel_disable_dp;
  2514. intel_encoder->post_disable = intel_post_disable_dp;
  2515. intel_encoder->get_hw_state = intel_dp_get_hw_state;
  2516. intel_dig_port->port = port;
  2517. intel_dig_port->dp.output_reg = output_reg;
  2518. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  2519. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2520. intel_encoder->cloneable = false;
  2521. intel_encoder->hot_plug = intel_dp_hot_plug;
  2522. intel_dp_init_connector(intel_dig_port, intel_connector);
  2523. }