i915_drv.h 59 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903
  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #ifndef _I915_DRV_H_
  30. #define _I915_DRV_H_
  31. #include <uapi/drm/i915_drm.h>
  32. #include "i915_reg.h"
  33. #include "intel_bios.h"
  34. #include "intel_ringbuffer.h"
  35. #include <linux/io-mapping.h>
  36. #include <linux/i2c.h>
  37. #include <linux/i2c-algo-bit.h>
  38. #include <drm/intel-gtt.h>
  39. #include <linux/backlight.h>
  40. #include <linux/intel-iommu.h>
  41. #include <linux/kref.h>
  42. #include <linux/pm_qos.h>
  43. /* General customization:
  44. */
  45. #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
  46. #define DRIVER_NAME "i915"
  47. #define DRIVER_DESC "Intel Graphics"
  48. #define DRIVER_DATE "20080730"
  49. enum pipe {
  50. PIPE_A = 0,
  51. PIPE_B,
  52. PIPE_C,
  53. I915_MAX_PIPES
  54. };
  55. #define pipe_name(p) ((p) + 'A')
  56. enum transcoder {
  57. TRANSCODER_A = 0,
  58. TRANSCODER_B,
  59. TRANSCODER_C,
  60. TRANSCODER_EDP = 0xF,
  61. };
  62. #define transcoder_name(t) ((t) + 'A')
  63. enum plane {
  64. PLANE_A = 0,
  65. PLANE_B,
  66. PLANE_C,
  67. };
  68. #define plane_name(p) ((p) + 'A')
  69. enum port {
  70. PORT_A = 0,
  71. PORT_B,
  72. PORT_C,
  73. PORT_D,
  74. PORT_E,
  75. I915_MAX_PORTS
  76. };
  77. #define port_name(p) ((p) + 'A')
  78. #define I915_GEM_GPU_DOMAINS \
  79. (I915_GEM_DOMAIN_RENDER | \
  80. I915_GEM_DOMAIN_SAMPLER | \
  81. I915_GEM_DOMAIN_COMMAND | \
  82. I915_GEM_DOMAIN_INSTRUCTION | \
  83. I915_GEM_DOMAIN_VERTEX)
  84. #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  85. #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  86. list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  87. if ((intel_encoder)->base.crtc == (__crtc))
  88. struct intel_pch_pll {
  89. int refcount; /* count of number of CRTCs sharing this PLL */
  90. int active; /* count of number of active CRTCs (i.e. DPMS on) */
  91. bool on; /* is the PLL actually active? Disabled during modeset */
  92. int pll_reg;
  93. int fp0_reg;
  94. int fp1_reg;
  95. };
  96. #define I915_NUM_PLLS 2
  97. /* Used by dp and fdi links */
  98. struct intel_link_m_n {
  99. uint32_t tu;
  100. uint32_t gmch_m;
  101. uint32_t gmch_n;
  102. uint32_t link_m;
  103. uint32_t link_n;
  104. };
  105. void intel_link_compute_m_n(int bpp, int nlanes,
  106. int pixel_clock, int link_clock,
  107. struct intel_link_m_n *m_n);
  108. struct intel_ddi_plls {
  109. int spll_refcount;
  110. int wrpll1_refcount;
  111. int wrpll2_refcount;
  112. };
  113. /* Interface history:
  114. *
  115. * 1.1: Original.
  116. * 1.2: Add Power Management
  117. * 1.3: Add vblank support
  118. * 1.4: Fix cmdbuffer path, add heap destroy
  119. * 1.5: Add vblank pipe configuration
  120. * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  121. * - Support vertical blank on secondary display pipe
  122. */
  123. #define DRIVER_MAJOR 1
  124. #define DRIVER_MINOR 6
  125. #define DRIVER_PATCHLEVEL 0
  126. #define WATCH_COHERENCY 0
  127. #define WATCH_LISTS 0
  128. #define WATCH_GTT 0
  129. #define I915_GEM_PHYS_CURSOR_0 1
  130. #define I915_GEM_PHYS_CURSOR_1 2
  131. #define I915_GEM_PHYS_OVERLAY_REGS 3
  132. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  133. struct drm_i915_gem_phys_object {
  134. int id;
  135. struct page **page_list;
  136. drm_dma_handle_t *handle;
  137. struct drm_i915_gem_object *cur_obj;
  138. };
  139. struct opregion_header;
  140. struct opregion_acpi;
  141. struct opregion_swsci;
  142. struct opregion_asle;
  143. struct drm_i915_private;
  144. struct intel_opregion {
  145. struct opregion_header __iomem *header;
  146. struct opregion_acpi __iomem *acpi;
  147. struct opregion_swsci __iomem *swsci;
  148. struct opregion_asle __iomem *asle;
  149. void __iomem *vbt;
  150. u32 __iomem *lid_state;
  151. };
  152. #define OPREGION_SIZE (8*1024)
  153. struct intel_overlay;
  154. struct intel_overlay_error_state;
  155. struct drm_i915_master_private {
  156. drm_local_map_t *sarea;
  157. struct _drm_i915_sarea *sarea_priv;
  158. };
  159. #define I915_FENCE_REG_NONE -1
  160. #define I915_MAX_NUM_FENCES 16
  161. /* 16 fences + sign bit for FENCE_REG_NONE */
  162. #define I915_MAX_NUM_FENCE_BITS 5
  163. struct drm_i915_fence_reg {
  164. struct list_head lru_list;
  165. struct drm_i915_gem_object *obj;
  166. int pin_count;
  167. };
  168. struct sdvo_device_mapping {
  169. u8 initialized;
  170. u8 dvo_port;
  171. u8 slave_addr;
  172. u8 dvo_wiring;
  173. u8 i2c_pin;
  174. u8 ddc_pin;
  175. };
  176. struct intel_display_error_state;
  177. struct drm_i915_error_state {
  178. struct kref ref;
  179. u32 eir;
  180. u32 pgtbl_er;
  181. u32 ier;
  182. u32 ccid;
  183. u32 derrmr;
  184. u32 forcewake;
  185. bool waiting[I915_NUM_RINGS];
  186. u32 pipestat[I915_MAX_PIPES];
  187. u32 tail[I915_NUM_RINGS];
  188. u32 head[I915_NUM_RINGS];
  189. u32 ctl[I915_NUM_RINGS];
  190. u32 ipeir[I915_NUM_RINGS];
  191. u32 ipehr[I915_NUM_RINGS];
  192. u32 instdone[I915_NUM_RINGS];
  193. u32 acthd[I915_NUM_RINGS];
  194. u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  195. u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
  196. u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
  197. /* our own tracking of ring head and tail */
  198. u32 cpu_ring_head[I915_NUM_RINGS];
  199. u32 cpu_ring_tail[I915_NUM_RINGS];
  200. u32 error; /* gen6+ */
  201. u32 err_int; /* gen7 */
  202. u32 instpm[I915_NUM_RINGS];
  203. u32 instps[I915_NUM_RINGS];
  204. u32 extra_instdone[I915_NUM_INSTDONE_REG];
  205. u32 seqno[I915_NUM_RINGS];
  206. u64 bbaddr;
  207. u32 fault_reg[I915_NUM_RINGS];
  208. u32 done_reg;
  209. u32 faddr[I915_NUM_RINGS];
  210. u64 fence[I915_MAX_NUM_FENCES];
  211. struct timeval time;
  212. struct drm_i915_error_ring {
  213. struct drm_i915_error_object {
  214. int page_count;
  215. u32 gtt_offset;
  216. u32 *pages[0];
  217. } *ringbuffer, *batchbuffer;
  218. struct drm_i915_error_request {
  219. long jiffies;
  220. u32 seqno;
  221. u32 tail;
  222. } *requests;
  223. int num_requests;
  224. } ring[I915_NUM_RINGS];
  225. struct drm_i915_error_buffer {
  226. u32 size;
  227. u32 name;
  228. u32 rseqno, wseqno;
  229. u32 gtt_offset;
  230. u32 read_domains;
  231. u32 write_domain;
  232. s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
  233. s32 pinned:2;
  234. u32 tiling:2;
  235. u32 dirty:1;
  236. u32 purgeable:1;
  237. s32 ring:4;
  238. u32 cache_level:2;
  239. } *active_bo, *pinned_bo;
  240. u32 active_bo_count, pinned_bo_count;
  241. struct intel_overlay_error_state *overlay;
  242. struct intel_display_error_state *display;
  243. };
  244. struct drm_i915_display_funcs {
  245. bool (*fbc_enabled)(struct drm_device *dev);
  246. void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  247. void (*disable_fbc)(struct drm_device *dev);
  248. int (*get_display_clock_speed)(struct drm_device *dev);
  249. int (*get_fifo_size)(struct drm_device *dev, int plane);
  250. void (*update_wm)(struct drm_device *dev);
  251. void (*update_sprite_wm)(struct drm_device *dev, int pipe,
  252. uint32_t sprite_width, int pixel_size);
  253. void (*update_linetime_wm)(struct drm_device *dev, int pipe,
  254. struct drm_display_mode *mode);
  255. void (*modeset_global_resources)(struct drm_device *dev);
  256. int (*crtc_mode_set)(struct drm_crtc *crtc,
  257. struct drm_display_mode *mode,
  258. struct drm_display_mode *adjusted_mode,
  259. int x, int y,
  260. struct drm_framebuffer *old_fb);
  261. void (*crtc_enable)(struct drm_crtc *crtc);
  262. void (*crtc_disable)(struct drm_crtc *crtc);
  263. void (*off)(struct drm_crtc *crtc);
  264. void (*write_eld)(struct drm_connector *connector,
  265. struct drm_crtc *crtc);
  266. void (*fdi_link_train)(struct drm_crtc *crtc);
  267. void (*init_clock_gating)(struct drm_device *dev);
  268. int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
  269. struct drm_framebuffer *fb,
  270. struct drm_i915_gem_object *obj);
  271. int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  272. int x, int y);
  273. void (*hpd_irq_setup)(struct drm_device *dev);
  274. /* clock updates for mode set */
  275. /* cursor updates */
  276. /* render clock increase/decrease */
  277. /* display clock increase/decrease */
  278. /* pll clock increase/decrease */
  279. };
  280. struct drm_i915_gt_funcs {
  281. void (*force_wake_get)(struct drm_i915_private *dev_priv);
  282. void (*force_wake_put)(struct drm_i915_private *dev_priv);
  283. };
  284. #define DEV_INFO_FLAGS \
  285. DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
  286. DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
  287. DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
  288. DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
  289. DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
  290. DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
  291. DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
  292. DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
  293. DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
  294. DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
  295. DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
  296. DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
  297. DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
  298. DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
  299. DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
  300. DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
  301. DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
  302. DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
  303. DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
  304. DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
  305. DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
  306. DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
  307. DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
  308. DEV_INFO_FLAG(has_llc)
  309. struct intel_device_info {
  310. u32 display_mmio_offset;
  311. u8 gen;
  312. u8 is_mobile:1;
  313. u8 is_i85x:1;
  314. u8 is_i915g:1;
  315. u8 is_i945gm:1;
  316. u8 is_g33:1;
  317. u8 need_gfx_hws:1;
  318. u8 is_g4x:1;
  319. u8 is_pineview:1;
  320. u8 is_broadwater:1;
  321. u8 is_crestline:1;
  322. u8 is_ivybridge:1;
  323. u8 is_valleyview:1;
  324. u8 has_force_wake:1;
  325. u8 is_haswell:1;
  326. u8 has_fbc:1;
  327. u8 has_pipe_cxsr:1;
  328. u8 has_hotplug:1;
  329. u8 cursor_needs_physical:1;
  330. u8 has_overlay:1;
  331. u8 overlay_needs_physical:1;
  332. u8 supports_tv:1;
  333. u8 has_bsd_ring:1;
  334. u8 has_blt_ring:1;
  335. u8 has_llc:1;
  336. };
  337. enum i915_cache_level {
  338. I915_CACHE_NONE = 0,
  339. I915_CACHE_LLC,
  340. I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
  341. };
  342. /* The Graphics Translation Table is the way in which GEN hardware translates a
  343. * Graphics Virtual Address into a Physical Address. In addition to the normal
  344. * collateral associated with any va->pa translations GEN hardware also has a
  345. * portion of the GTT which can be mapped by the CPU and remain both coherent
  346. * and correct (in cases like swizzling). That region is referred to as GMADR in
  347. * the spec.
  348. */
  349. struct i915_gtt {
  350. unsigned long start; /* Start offset of used GTT */
  351. size_t total; /* Total size GTT can map */
  352. size_t stolen_size; /* Total size of stolen memory */
  353. unsigned long mappable_end; /* End offset that we can CPU map */
  354. struct io_mapping *mappable; /* Mapping to our CPU mappable region */
  355. phys_addr_t mappable_base; /* PA of our GMADR */
  356. /** "Graphics Stolen Memory" holds the global PTEs */
  357. void __iomem *gsm;
  358. bool do_idle_maps;
  359. dma_addr_t scratch_page_dma;
  360. struct page *scratch_page;
  361. /* global gtt ops */
  362. int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
  363. size_t *stolen, phys_addr_t *mappable_base,
  364. unsigned long *mappable_end);
  365. void (*gtt_remove)(struct drm_device *dev);
  366. void (*gtt_clear_range)(struct drm_device *dev,
  367. unsigned int first_entry,
  368. unsigned int num_entries);
  369. void (*gtt_insert_entries)(struct drm_device *dev,
  370. struct sg_table *st,
  371. unsigned int pg_start,
  372. enum i915_cache_level cache_level);
  373. };
  374. #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
  375. #define I915_PPGTT_PD_ENTRIES 512
  376. #define I915_PPGTT_PT_ENTRIES 1024
  377. struct i915_hw_ppgtt {
  378. struct drm_device *dev;
  379. unsigned num_pd_entries;
  380. struct page **pt_pages;
  381. uint32_t pd_offset;
  382. dma_addr_t *pt_dma_addr;
  383. dma_addr_t scratch_page_dma_addr;
  384. /* pte functions, mirroring the interface of the global gtt. */
  385. void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
  386. unsigned int first_entry,
  387. unsigned int num_entries);
  388. void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
  389. struct sg_table *st,
  390. unsigned int pg_start,
  391. enum i915_cache_level cache_level);
  392. void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
  393. };
  394. /* This must match up with the value previously used for execbuf2.rsvd1. */
  395. #define DEFAULT_CONTEXT_ID 0
  396. struct i915_hw_context {
  397. int id;
  398. bool is_initialized;
  399. struct drm_i915_file_private *file_priv;
  400. struct intel_ring_buffer *ring;
  401. struct drm_i915_gem_object *obj;
  402. };
  403. enum no_fbc_reason {
  404. FBC_NO_OUTPUT, /* no outputs enabled to compress */
  405. FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
  406. FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  407. FBC_MODE_TOO_LARGE, /* mode too large for compression */
  408. FBC_BAD_PLANE, /* fbc not supported on plane */
  409. FBC_NOT_TILED, /* buffer not tiled */
  410. FBC_MULTIPLE_PIPES, /* more than one pipe active */
  411. FBC_MODULE_PARAM,
  412. };
  413. enum intel_pch {
  414. PCH_NONE = 0, /* No PCH present */
  415. PCH_IBX, /* Ibexpeak PCH */
  416. PCH_CPT, /* Cougarpoint PCH */
  417. PCH_LPT, /* Lynxpoint PCH */
  418. };
  419. enum intel_sbi_destination {
  420. SBI_ICLK,
  421. SBI_MPHY,
  422. };
  423. #define QUIRK_PIPEA_FORCE (1<<0)
  424. #define QUIRK_LVDS_SSC_DISABLE (1<<1)
  425. #define QUIRK_INVERT_BRIGHTNESS (1<<2)
  426. struct intel_fbdev;
  427. struct intel_fbc_work;
  428. struct intel_gmbus {
  429. struct i2c_adapter adapter;
  430. u32 force_bit;
  431. u32 reg0;
  432. u32 gpio_reg;
  433. struct i2c_algo_bit_data bit_algo;
  434. struct drm_i915_private *dev_priv;
  435. };
  436. struct i915_suspend_saved_registers {
  437. u8 saveLBB;
  438. u32 saveDSPACNTR;
  439. u32 saveDSPBCNTR;
  440. u32 saveDSPARB;
  441. u32 savePIPEACONF;
  442. u32 savePIPEBCONF;
  443. u32 savePIPEASRC;
  444. u32 savePIPEBSRC;
  445. u32 saveFPA0;
  446. u32 saveFPA1;
  447. u32 saveDPLL_A;
  448. u32 saveDPLL_A_MD;
  449. u32 saveHTOTAL_A;
  450. u32 saveHBLANK_A;
  451. u32 saveHSYNC_A;
  452. u32 saveVTOTAL_A;
  453. u32 saveVBLANK_A;
  454. u32 saveVSYNC_A;
  455. u32 saveBCLRPAT_A;
  456. u32 saveTRANSACONF;
  457. u32 saveTRANS_HTOTAL_A;
  458. u32 saveTRANS_HBLANK_A;
  459. u32 saveTRANS_HSYNC_A;
  460. u32 saveTRANS_VTOTAL_A;
  461. u32 saveTRANS_VBLANK_A;
  462. u32 saveTRANS_VSYNC_A;
  463. u32 savePIPEASTAT;
  464. u32 saveDSPASTRIDE;
  465. u32 saveDSPASIZE;
  466. u32 saveDSPAPOS;
  467. u32 saveDSPAADDR;
  468. u32 saveDSPASURF;
  469. u32 saveDSPATILEOFF;
  470. u32 savePFIT_PGM_RATIOS;
  471. u32 saveBLC_HIST_CTL;
  472. u32 saveBLC_PWM_CTL;
  473. u32 saveBLC_PWM_CTL2;
  474. u32 saveBLC_CPU_PWM_CTL;
  475. u32 saveBLC_CPU_PWM_CTL2;
  476. u32 saveFPB0;
  477. u32 saveFPB1;
  478. u32 saveDPLL_B;
  479. u32 saveDPLL_B_MD;
  480. u32 saveHTOTAL_B;
  481. u32 saveHBLANK_B;
  482. u32 saveHSYNC_B;
  483. u32 saveVTOTAL_B;
  484. u32 saveVBLANK_B;
  485. u32 saveVSYNC_B;
  486. u32 saveBCLRPAT_B;
  487. u32 saveTRANSBCONF;
  488. u32 saveTRANS_HTOTAL_B;
  489. u32 saveTRANS_HBLANK_B;
  490. u32 saveTRANS_HSYNC_B;
  491. u32 saveTRANS_VTOTAL_B;
  492. u32 saveTRANS_VBLANK_B;
  493. u32 saveTRANS_VSYNC_B;
  494. u32 savePIPEBSTAT;
  495. u32 saveDSPBSTRIDE;
  496. u32 saveDSPBSIZE;
  497. u32 saveDSPBPOS;
  498. u32 saveDSPBADDR;
  499. u32 saveDSPBSURF;
  500. u32 saveDSPBTILEOFF;
  501. u32 saveVGA0;
  502. u32 saveVGA1;
  503. u32 saveVGA_PD;
  504. u32 saveVGACNTRL;
  505. u32 saveADPA;
  506. u32 saveLVDS;
  507. u32 savePP_ON_DELAYS;
  508. u32 savePP_OFF_DELAYS;
  509. u32 saveDVOA;
  510. u32 saveDVOB;
  511. u32 saveDVOC;
  512. u32 savePP_ON;
  513. u32 savePP_OFF;
  514. u32 savePP_CONTROL;
  515. u32 savePP_DIVISOR;
  516. u32 savePFIT_CONTROL;
  517. u32 save_palette_a[256];
  518. u32 save_palette_b[256];
  519. u32 saveDPFC_CB_BASE;
  520. u32 saveFBC_CFB_BASE;
  521. u32 saveFBC_LL_BASE;
  522. u32 saveFBC_CONTROL;
  523. u32 saveFBC_CONTROL2;
  524. u32 saveIER;
  525. u32 saveIIR;
  526. u32 saveIMR;
  527. u32 saveDEIER;
  528. u32 saveDEIMR;
  529. u32 saveGTIER;
  530. u32 saveGTIMR;
  531. u32 saveFDI_RXA_IMR;
  532. u32 saveFDI_RXB_IMR;
  533. u32 saveCACHE_MODE_0;
  534. u32 saveMI_ARB_STATE;
  535. u32 saveSWF0[16];
  536. u32 saveSWF1[16];
  537. u32 saveSWF2[3];
  538. u8 saveMSR;
  539. u8 saveSR[8];
  540. u8 saveGR[25];
  541. u8 saveAR_INDEX;
  542. u8 saveAR[21];
  543. u8 saveDACMASK;
  544. u8 saveCR[37];
  545. uint64_t saveFENCE[I915_MAX_NUM_FENCES];
  546. u32 saveCURACNTR;
  547. u32 saveCURAPOS;
  548. u32 saveCURABASE;
  549. u32 saveCURBCNTR;
  550. u32 saveCURBPOS;
  551. u32 saveCURBBASE;
  552. u32 saveCURSIZE;
  553. u32 saveDP_B;
  554. u32 saveDP_C;
  555. u32 saveDP_D;
  556. u32 savePIPEA_GMCH_DATA_M;
  557. u32 savePIPEB_GMCH_DATA_M;
  558. u32 savePIPEA_GMCH_DATA_N;
  559. u32 savePIPEB_GMCH_DATA_N;
  560. u32 savePIPEA_DP_LINK_M;
  561. u32 savePIPEB_DP_LINK_M;
  562. u32 savePIPEA_DP_LINK_N;
  563. u32 savePIPEB_DP_LINK_N;
  564. u32 saveFDI_RXA_CTL;
  565. u32 saveFDI_TXA_CTL;
  566. u32 saveFDI_RXB_CTL;
  567. u32 saveFDI_TXB_CTL;
  568. u32 savePFA_CTL_1;
  569. u32 savePFB_CTL_1;
  570. u32 savePFA_WIN_SZ;
  571. u32 savePFB_WIN_SZ;
  572. u32 savePFA_WIN_POS;
  573. u32 savePFB_WIN_POS;
  574. u32 savePCH_DREF_CONTROL;
  575. u32 saveDISP_ARB_CTL;
  576. u32 savePIPEA_DATA_M1;
  577. u32 savePIPEA_DATA_N1;
  578. u32 savePIPEA_LINK_M1;
  579. u32 savePIPEA_LINK_N1;
  580. u32 savePIPEB_DATA_M1;
  581. u32 savePIPEB_DATA_N1;
  582. u32 savePIPEB_LINK_M1;
  583. u32 savePIPEB_LINK_N1;
  584. u32 saveMCHBAR_RENDER_STANDBY;
  585. u32 savePCH_PORT_HOTPLUG;
  586. };
  587. struct intel_gen6_power_mgmt {
  588. struct work_struct work;
  589. u32 pm_iir;
  590. /* lock - irqsave spinlock that protectects the work_struct and
  591. * pm_iir. */
  592. spinlock_t lock;
  593. /* The below variables an all the rps hw state are protected by
  594. * dev->struct mutext. */
  595. u8 cur_delay;
  596. u8 min_delay;
  597. u8 max_delay;
  598. struct delayed_work delayed_resume_work;
  599. /*
  600. * Protects RPS/RC6 register access and PCU communication.
  601. * Must be taken after struct_mutex if nested.
  602. */
  603. struct mutex hw_lock;
  604. };
  605. /* defined intel_pm.c */
  606. extern spinlock_t mchdev_lock;
  607. struct intel_ilk_power_mgmt {
  608. u8 cur_delay;
  609. u8 min_delay;
  610. u8 max_delay;
  611. u8 fmax;
  612. u8 fstart;
  613. u64 last_count1;
  614. unsigned long last_time1;
  615. unsigned long chipset_power;
  616. u64 last_count2;
  617. struct timespec last_time2;
  618. unsigned long gfx_power;
  619. u8 corr;
  620. int c_m;
  621. int r_t;
  622. struct drm_i915_gem_object *pwrctx;
  623. struct drm_i915_gem_object *renderctx;
  624. };
  625. struct i915_dri1_state {
  626. unsigned allow_batchbuffer : 1;
  627. u32 __iomem *gfx_hws_cpu_addr;
  628. unsigned int cpp;
  629. int back_offset;
  630. int front_offset;
  631. int current_page;
  632. int page_flipping;
  633. uint32_t counter;
  634. };
  635. struct intel_l3_parity {
  636. u32 *remap_info;
  637. struct work_struct error_work;
  638. };
  639. struct i915_gem_mm {
  640. /** Memory allocator for GTT stolen memory */
  641. struct drm_mm stolen;
  642. /** Memory allocator for GTT */
  643. struct drm_mm gtt_space;
  644. /** List of all objects in gtt_space. Used to restore gtt
  645. * mappings on resume */
  646. struct list_head bound_list;
  647. /**
  648. * List of objects which are not bound to the GTT (thus
  649. * are idle and not used by the GPU) but still have
  650. * (presumably uncached) pages still attached.
  651. */
  652. struct list_head unbound_list;
  653. /** Usable portion of the GTT for GEM */
  654. unsigned long stolen_base; /* limited to low memory (32-bit) */
  655. int gtt_mtrr;
  656. /** PPGTT used for aliasing the PPGTT with the GTT */
  657. struct i915_hw_ppgtt *aliasing_ppgtt;
  658. struct shrinker inactive_shrinker;
  659. bool shrinker_no_lock_stealing;
  660. /**
  661. * List of objects currently involved in rendering.
  662. *
  663. * Includes buffers having the contents of their GPU caches
  664. * flushed, not necessarily primitives. last_rendering_seqno
  665. * represents when the rendering involved will be completed.
  666. *
  667. * A reference is held on the buffer while on this list.
  668. */
  669. struct list_head active_list;
  670. /**
  671. * LRU list of objects which are not in the ringbuffer and
  672. * are ready to unbind, but are still in the GTT.
  673. *
  674. * last_rendering_seqno is 0 while an object is in this list.
  675. *
  676. * A reference is not held on the buffer while on this list,
  677. * as merely being GTT-bound shouldn't prevent its being
  678. * freed, and we'll pull it off the list in the free path.
  679. */
  680. struct list_head inactive_list;
  681. /** LRU list of objects with fence regs on them. */
  682. struct list_head fence_list;
  683. /**
  684. * We leave the user IRQ off as much as possible,
  685. * but this means that requests will finish and never
  686. * be retired once the system goes idle. Set a timer to
  687. * fire periodically while the ring is running. When it
  688. * fires, go retire requests.
  689. */
  690. struct delayed_work retire_work;
  691. /**
  692. * Are we in a non-interruptible section of code like
  693. * modesetting?
  694. */
  695. bool interruptible;
  696. /**
  697. * Flag if the X Server, and thus DRM, is not currently in
  698. * control of the device.
  699. *
  700. * This is set between LeaveVT and EnterVT. It needs to be
  701. * replaced with a semaphore. It also needs to be
  702. * transitioned away from for kernel modesetting.
  703. */
  704. int suspended;
  705. /** Bit 6 swizzling required for X tiling */
  706. uint32_t bit_6_swizzle_x;
  707. /** Bit 6 swizzling required for Y tiling */
  708. uint32_t bit_6_swizzle_y;
  709. /* storage for physical objects */
  710. struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  711. /* accounting, useful for userland debugging */
  712. size_t object_memory;
  713. u32 object_count;
  714. };
  715. struct i915_gpu_error {
  716. /* For hangcheck timer */
  717. #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
  718. #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
  719. struct timer_list hangcheck_timer;
  720. int hangcheck_count;
  721. uint32_t last_acthd[I915_NUM_RINGS];
  722. uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
  723. /* For reset and error_state handling. */
  724. spinlock_t lock;
  725. /* Protected by the above dev->gpu_error.lock. */
  726. struct drm_i915_error_state *first_error;
  727. struct work_struct work;
  728. unsigned long last_reset;
  729. /**
  730. * State variable and reset counter controlling the reset flow
  731. *
  732. * Upper bits are for the reset counter. This counter is used by the
  733. * wait_seqno code to race-free noticed that a reset event happened and
  734. * that it needs to restart the entire ioctl (since most likely the
  735. * seqno it waited for won't ever signal anytime soon).
  736. *
  737. * This is important for lock-free wait paths, where no contended lock
  738. * naturally enforces the correct ordering between the bail-out of the
  739. * waiter and the gpu reset work code.
  740. *
  741. * Lowest bit controls the reset state machine: Set means a reset is in
  742. * progress. This state will (presuming we don't have any bugs) decay
  743. * into either unset (successful reset) or the special WEDGED value (hw
  744. * terminally sour). All waiters on the reset_queue will be woken when
  745. * that happens.
  746. */
  747. atomic_t reset_counter;
  748. /**
  749. * Special values/flags for reset_counter
  750. *
  751. * Note that the code relies on
  752. * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
  753. * being true.
  754. */
  755. #define I915_RESET_IN_PROGRESS_FLAG 1
  756. #define I915_WEDGED 0xffffffff
  757. /**
  758. * Waitqueue to signal when the reset has completed. Used by clients
  759. * that wait for dev_priv->mm.wedged to settle.
  760. */
  761. wait_queue_head_t reset_queue;
  762. /* For gpu hang simulation. */
  763. unsigned int stop_rings;
  764. };
  765. enum modeset_restore {
  766. MODESET_ON_LID_OPEN,
  767. MODESET_DONE,
  768. MODESET_SUSPENDED,
  769. };
  770. typedef struct drm_i915_private {
  771. struct drm_device *dev;
  772. struct kmem_cache *slab;
  773. const struct intel_device_info *info;
  774. int relative_constants_mode;
  775. void __iomem *regs;
  776. struct drm_i915_gt_funcs gt;
  777. /** gt_fifo_count and the subsequent register write are synchronized
  778. * with dev->struct_mutex. */
  779. unsigned gt_fifo_count;
  780. /** forcewake_count is protected by gt_lock */
  781. unsigned forcewake_count;
  782. /** gt_lock is also taken in irq contexts. */
  783. spinlock_t gt_lock;
  784. struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
  785. /** gmbus_mutex protects against concurrent usage of the single hw gmbus
  786. * controller on different i2c buses. */
  787. struct mutex gmbus_mutex;
  788. /**
  789. * Base address of the gmbus and gpio block.
  790. */
  791. uint32_t gpio_mmio_base;
  792. wait_queue_head_t gmbus_wait_queue;
  793. struct pci_dev *bridge_dev;
  794. struct intel_ring_buffer ring[I915_NUM_RINGS];
  795. uint32_t last_seqno, next_seqno;
  796. drm_dma_handle_t *status_page_dmah;
  797. struct resource mch_res;
  798. atomic_t irq_received;
  799. /* protects the irq masks */
  800. spinlock_t irq_lock;
  801. /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
  802. struct pm_qos_request pm_qos;
  803. /* DPIO indirect register protection */
  804. struct mutex dpio_lock;
  805. /** Cached value of IMR to avoid reads in updating the bitfield */
  806. u32 pipestat[2];
  807. u32 irq_mask;
  808. u32 gt_irq_mask;
  809. u32 hotplug_supported_mask;
  810. struct work_struct hotplug_work;
  811. bool enable_hotplug_processing;
  812. int num_pipe;
  813. int num_pch_pll;
  814. unsigned long cfb_size;
  815. unsigned int cfb_fb;
  816. enum plane cfb_plane;
  817. int cfb_y;
  818. struct intel_fbc_work *fbc_work;
  819. struct intel_opregion opregion;
  820. /* overlay */
  821. struct intel_overlay *overlay;
  822. unsigned int sprite_scaling_enabled;
  823. /* LVDS info */
  824. int backlight_level; /* restore backlight to this value */
  825. bool backlight_enabled;
  826. struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  827. struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  828. /* Feature bits from the VBIOS */
  829. unsigned int int_tv_support:1;
  830. unsigned int lvds_dither:1;
  831. unsigned int lvds_vbt:1;
  832. unsigned int int_crt_support:1;
  833. unsigned int lvds_use_ssc:1;
  834. unsigned int display_clock_mode:1;
  835. int lvds_ssc_freq;
  836. unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
  837. struct {
  838. int rate;
  839. int lanes;
  840. int preemphasis;
  841. int vswing;
  842. bool initialized;
  843. bool support;
  844. int bpp;
  845. struct edp_power_seq pps;
  846. } edp;
  847. bool no_aux_handshake;
  848. int crt_ddc_pin;
  849. struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
  850. int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  851. int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  852. unsigned int fsb_freq, mem_freq, is_ddr3;
  853. struct workqueue_struct *wq;
  854. /* Display functions */
  855. struct drm_i915_display_funcs display;
  856. /* PCH chipset type */
  857. enum intel_pch pch_type;
  858. unsigned short pch_id;
  859. unsigned long quirks;
  860. enum modeset_restore modeset_restore;
  861. struct mutex modeset_restore_lock;
  862. struct i915_gtt gtt;
  863. struct i915_gem_mm mm;
  864. /* Kernel Modesetting */
  865. struct sdvo_device_mapping sdvo_mappings[2];
  866. /* indicate whether the LVDS_BORDER should be enabled or not */
  867. unsigned int lvds_border_bits;
  868. /* Panel fitter placement and size for Ironlake+ */
  869. u32 pch_pf_pos, pch_pf_size;
  870. struct drm_crtc *plane_to_crtc_mapping[3];
  871. struct drm_crtc *pipe_to_crtc_mapping[3];
  872. wait_queue_head_t pending_flip_queue;
  873. struct intel_pch_pll pch_plls[I915_NUM_PLLS];
  874. struct intel_ddi_plls ddi_plls;
  875. /* Reclocking support */
  876. bool render_reclock_avail;
  877. bool lvds_downclock_avail;
  878. /* indicates the reduced downclock for LVDS*/
  879. int lvds_downclock;
  880. u16 orig_clock;
  881. int child_dev_num;
  882. struct child_device_config *child_dev;
  883. bool mchbar_need_disable;
  884. struct intel_l3_parity l3_parity;
  885. /* gen6+ rps state */
  886. struct intel_gen6_power_mgmt rps;
  887. /* ilk-only ips/rps state. Everything in here is protected by the global
  888. * mchdev_lock in intel_pm.c */
  889. struct intel_ilk_power_mgmt ips;
  890. enum no_fbc_reason no_fbc_reason;
  891. struct drm_mm_node *compressed_fb;
  892. struct drm_mm_node *compressed_llb;
  893. struct i915_gpu_error gpu_error;
  894. /* list of fbdev register on this device */
  895. struct intel_fbdev *fbdev;
  896. /*
  897. * The console may be contended at resume, but we don't
  898. * want it to block on it.
  899. */
  900. struct work_struct console_resume_work;
  901. struct backlight_device *backlight;
  902. struct drm_property *broadcast_rgb_property;
  903. struct drm_property *force_audio_property;
  904. bool hw_contexts_disabled;
  905. uint32_t hw_context_size;
  906. u32 fdi_rx_config;
  907. struct i915_suspend_saved_registers regfile;
  908. /* Old dri1 support infrastructure, beware the dragons ya fools entering
  909. * here! */
  910. struct i915_dri1_state dri1;
  911. } drm_i915_private_t;
  912. /* Iterate over initialised rings */
  913. #define for_each_ring(ring__, dev_priv__, i__) \
  914. for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
  915. if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
  916. enum hdmi_force_audio {
  917. HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
  918. HDMI_AUDIO_OFF, /* force turn off HDMI audio */
  919. HDMI_AUDIO_AUTO, /* trust EDID */
  920. HDMI_AUDIO_ON, /* force turn on HDMI audio */
  921. };
  922. #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
  923. struct drm_i915_gem_object_ops {
  924. /* Interface between the GEM object and its backing storage.
  925. * get_pages() is called once prior to the use of the associated set
  926. * of pages before to binding them into the GTT, and put_pages() is
  927. * called after we no longer need them. As we expect there to be
  928. * associated cost with migrating pages between the backing storage
  929. * and making them available for the GPU (e.g. clflush), we may hold
  930. * onto the pages after they are no longer referenced by the GPU
  931. * in case they may be used again shortly (for example migrating the
  932. * pages to a different memory domain within the GTT). put_pages()
  933. * will therefore most likely be called when the object itself is
  934. * being released or under memory pressure (where we attempt to
  935. * reap pages for the shrinker).
  936. */
  937. int (*get_pages)(struct drm_i915_gem_object *);
  938. void (*put_pages)(struct drm_i915_gem_object *);
  939. };
  940. struct drm_i915_gem_object {
  941. struct drm_gem_object base;
  942. const struct drm_i915_gem_object_ops *ops;
  943. /** Current space allocated to this object in the GTT, if any. */
  944. struct drm_mm_node *gtt_space;
  945. /** Stolen memory for this object, instead of being backed by shmem. */
  946. struct drm_mm_node *stolen;
  947. struct list_head gtt_list;
  948. /** This object's place on the active/inactive lists */
  949. struct list_head ring_list;
  950. struct list_head mm_list;
  951. /** This object's place in the batchbuffer or on the eviction list */
  952. struct list_head exec_list;
  953. /**
  954. * This is set if the object is on the active lists (has pending
  955. * rendering and so a non-zero seqno), and is not set if it i s on
  956. * inactive (ready to be unbound) list.
  957. */
  958. unsigned int active:1;
  959. /**
  960. * This is set if the object has been written to since last bound
  961. * to the GTT
  962. */
  963. unsigned int dirty:1;
  964. /**
  965. * Fence register bits (if any) for this object. Will be set
  966. * as needed when mapped into the GTT.
  967. * Protected by dev->struct_mutex.
  968. */
  969. signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
  970. /**
  971. * Advice: are the backing pages purgeable?
  972. */
  973. unsigned int madv:2;
  974. /**
  975. * Current tiling mode for the object.
  976. */
  977. unsigned int tiling_mode:2;
  978. /**
  979. * Whether the tiling parameters for the currently associated fence
  980. * register have changed. Note that for the purposes of tracking
  981. * tiling changes we also treat the unfenced register, the register
  982. * slot that the object occupies whilst it executes a fenced
  983. * command (such as BLT on gen2/3), as a "fence".
  984. */
  985. unsigned int fence_dirty:1;
  986. /** How many users have pinned this object in GTT space. The following
  987. * users can each hold at most one reference: pwrite/pread, pin_ioctl
  988. * (via user_pin_count), execbuffer (objects are not allowed multiple
  989. * times for the same batchbuffer), and the framebuffer code. When
  990. * switching/pageflipping, the framebuffer code has at most two buffers
  991. * pinned per crtc.
  992. *
  993. * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  994. * bits with absolutely no headroom. So use 4 bits. */
  995. unsigned int pin_count:4;
  996. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  997. /**
  998. * Is the object at the current location in the gtt mappable and
  999. * fenceable? Used to avoid costly recalculations.
  1000. */
  1001. unsigned int map_and_fenceable:1;
  1002. /**
  1003. * Whether the current gtt mapping needs to be mappable (and isn't just
  1004. * mappable by accident). Track pin and fault separate for a more
  1005. * accurate mappable working set.
  1006. */
  1007. unsigned int fault_mappable:1;
  1008. unsigned int pin_mappable:1;
  1009. /*
  1010. * Is the GPU currently using a fence to access this buffer,
  1011. */
  1012. unsigned int pending_fenced_gpu_access:1;
  1013. unsigned int fenced_gpu_access:1;
  1014. unsigned int cache_level:2;
  1015. unsigned int has_aliasing_ppgtt_mapping:1;
  1016. unsigned int has_global_gtt_mapping:1;
  1017. unsigned int has_dma_mapping:1;
  1018. struct sg_table *pages;
  1019. int pages_pin_count;
  1020. /* prime dma-buf support */
  1021. void *dma_buf_vmapping;
  1022. int vmapping_count;
  1023. /**
  1024. * Used for performing relocations during execbuffer insertion.
  1025. */
  1026. struct hlist_node exec_node;
  1027. unsigned long exec_handle;
  1028. struct drm_i915_gem_exec_object2 *exec_entry;
  1029. /**
  1030. * Current offset of the object in GTT space.
  1031. *
  1032. * This is the same as gtt_space->start
  1033. */
  1034. uint32_t gtt_offset;
  1035. struct intel_ring_buffer *ring;
  1036. /** Breadcrumb of last rendering to the buffer. */
  1037. uint32_t last_read_seqno;
  1038. uint32_t last_write_seqno;
  1039. /** Breadcrumb of last fenced GPU access to the buffer. */
  1040. uint32_t last_fenced_seqno;
  1041. /** Current tiling stride for the object, if it's tiled. */
  1042. uint32_t stride;
  1043. /** Record of address bit 17 of each page at last unbind. */
  1044. unsigned long *bit_17;
  1045. /** User space pin count and filp owning the pin */
  1046. uint32_t user_pin_count;
  1047. struct drm_file *pin_filp;
  1048. /** for phy allocated objects */
  1049. struct drm_i915_gem_phys_object *phys_obj;
  1050. };
  1051. #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
  1052. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  1053. /**
  1054. * Request queue structure.
  1055. *
  1056. * The request queue allows us to note sequence numbers that have been emitted
  1057. * and may be associated with active buffers to be retired.
  1058. *
  1059. * By keeping this list, we can avoid having to do questionable
  1060. * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  1061. * an emission time with seqnos for tracking how far ahead of the GPU we are.
  1062. */
  1063. struct drm_i915_gem_request {
  1064. /** On Which ring this request was generated */
  1065. struct intel_ring_buffer *ring;
  1066. /** GEM sequence number associated with this request. */
  1067. uint32_t seqno;
  1068. /** Postion in the ringbuffer of the end of the request */
  1069. u32 tail;
  1070. /** Time at which this request was emitted, in jiffies. */
  1071. unsigned long emitted_jiffies;
  1072. /** global list entry for this request */
  1073. struct list_head list;
  1074. struct drm_i915_file_private *file_priv;
  1075. /** file_priv list entry for this request */
  1076. struct list_head client_list;
  1077. };
  1078. struct drm_i915_file_private {
  1079. struct {
  1080. spinlock_t lock;
  1081. struct list_head request_list;
  1082. } mm;
  1083. struct idr context_idr;
  1084. };
  1085. #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
  1086. #define IS_I830(dev) ((dev)->pci_device == 0x3577)
  1087. #define IS_845G(dev) ((dev)->pci_device == 0x2562)
  1088. #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
  1089. #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
  1090. #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
  1091. #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
  1092. #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
  1093. #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
  1094. #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
  1095. #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
  1096. #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
  1097. #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
  1098. #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
  1099. #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
  1100. #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
  1101. #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
  1102. #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
  1103. #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
  1104. #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
  1105. #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
  1106. (dev)->pci_device == 0x0152 || \
  1107. (dev)->pci_device == 0x015a)
  1108. #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
  1109. (dev)->pci_device == 0x0106 || \
  1110. (dev)->pci_device == 0x010A)
  1111. #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
  1112. #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
  1113. #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
  1114. #define IS_ULT(dev) (IS_HASWELL(dev) && \
  1115. ((dev)->pci_device & 0xFF00) == 0x0A00)
  1116. /*
  1117. * The genX designation typically refers to the render engine, so render
  1118. * capability related checks should use IS_GEN, while display and other checks
  1119. * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
  1120. * chips, etc.).
  1121. */
  1122. #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
  1123. #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
  1124. #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
  1125. #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
  1126. #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
  1127. #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
  1128. #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
  1129. #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
  1130. #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
  1131. #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
  1132. #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
  1133. #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
  1134. #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
  1135. #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
  1136. /* Early gen2 have a totally busted CS tlb and require pinned batches. */
  1137. #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
  1138. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  1139. * rows, which changed the alignment requirements and fence programming.
  1140. */
  1141. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  1142. IS_I915GM(dev)))
  1143. #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  1144. #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
  1145. #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
  1146. #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
  1147. #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
  1148. #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
  1149. /* dsparb controlled by hw only */
  1150. #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  1151. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  1152. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  1153. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  1154. #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
  1155. #define HAS_DDI(dev) (IS_HASWELL(dev))
  1156. #define INTEL_PCH_DEVICE_ID_MASK 0xff00
  1157. #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
  1158. #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
  1159. #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
  1160. #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
  1161. #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
  1162. #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
  1163. #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
  1164. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1165. #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
  1166. #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
  1167. #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
  1168. #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  1169. #define GT_FREQUENCY_MULTIPLIER 50
  1170. #include "i915_trace.h"
  1171. /**
  1172. * RC6 is a special power stage which allows the GPU to enter an very
  1173. * low-voltage mode when idle, using down to 0V while at this stage. This
  1174. * stage is entered automatically when the GPU is idle when RC6 support is
  1175. * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  1176. *
  1177. * There are different RC6 modes available in Intel GPU, which differentiate
  1178. * among each other with the latency required to enter and leave RC6 and
  1179. * voltage consumed by the GPU in different states.
  1180. *
  1181. * The combination of the following flags define which states GPU is allowed
  1182. * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  1183. * RC6pp is deepest RC6. Their support by hardware varies according to the
  1184. * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  1185. * which brings the most power savings; deeper states save more power, but
  1186. * require higher latency to switch to and wake up.
  1187. */
  1188. #define INTEL_RC6_ENABLE (1<<0)
  1189. #define INTEL_RC6p_ENABLE (1<<1)
  1190. #define INTEL_RC6pp_ENABLE (1<<2)
  1191. extern struct drm_ioctl_desc i915_ioctls[];
  1192. extern int i915_max_ioctl;
  1193. extern unsigned int i915_fbpercrtc __always_unused;
  1194. extern int i915_panel_ignore_lid __read_mostly;
  1195. extern unsigned int i915_powersave __read_mostly;
  1196. extern int i915_semaphores __read_mostly;
  1197. extern unsigned int i915_lvds_downclock __read_mostly;
  1198. extern int i915_lvds_channel_mode __read_mostly;
  1199. extern int i915_panel_use_ssc __read_mostly;
  1200. extern int i915_vbt_sdvo_panel_type __read_mostly;
  1201. extern int i915_enable_rc6 __read_mostly;
  1202. extern int i915_enable_fbc __read_mostly;
  1203. extern bool i915_enable_hangcheck __read_mostly;
  1204. extern int i915_enable_ppgtt __read_mostly;
  1205. extern unsigned int i915_preliminary_hw_support __read_mostly;
  1206. extern int i915_suspend(struct drm_device *dev, pm_message_t state);
  1207. extern int i915_resume(struct drm_device *dev);
  1208. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  1209. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  1210. /* i915_dma.c */
  1211. void i915_update_dri1_breadcrumb(struct drm_device *dev);
  1212. extern void i915_kernel_lost_context(struct drm_device * dev);
  1213. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  1214. extern int i915_driver_unload(struct drm_device *);
  1215. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  1216. extern void i915_driver_lastclose(struct drm_device * dev);
  1217. extern void i915_driver_preclose(struct drm_device *dev,
  1218. struct drm_file *file_priv);
  1219. extern void i915_driver_postclose(struct drm_device *dev,
  1220. struct drm_file *file_priv);
  1221. extern int i915_driver_device_is_agp(struct drm_device * dev);
  1222. #ifdef CONFIG_COMPAT
  1223. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  1224. unsigned long arg);
  1225. #endif
  1226. extern int i915_emit_box(struct drm_device *dev,
  1227. struct drm_clip_rect *box,
  1228. int DR1, int DR4);
  1229. extern int intel_gpu_reset(struct drm_device *dev);
  1230. extern int i915_reset(struct drm_device *dev);
  1231. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  1232. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  1233. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  1234. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  1235. extern void intel_console_resume(struct work_struct *work);
  1236. /* i915_irq.c */
  1237. void i915_hangcheck_elapsed(unsigned long data);
  1238. void i915_handle_error(struct drm_device *dev, bool wedged);
  1239. extern void intel_irq_init(struct drm_device *dev);
  1240. extern void intel_hpd_init(struct drm_device *dev);
  1241. extern void intel_gt_init(struct drm_device *dev);
  1242. extern void intel_gt_reset(struct drm_device *dev);
  1243. void i915_error_state_free(struct kref *error_ref);
  1244. void
  1245. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1246. void
  1247. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  1248. void intel_enable_asle(struct drm_device *dev);
  1249. #ifdef CONFIG_DEBUG_FS
  1250. extern void i915_destroy_error_state(struct drm_device *dev);
  1251. #else
  1252. #define i915_destroy_error_state(x)
  1253. #endif
  1254. /* i915_gem.c */
  1255. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  1256. struct drm_file *file_priv);
  1257. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  1258. struct drm_file *file_priv);
  1259. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  1260. struct drm_file *file_priv);
  1261. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  1262. struct drm_file *file_priv);
  1263. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  1264. struct drm_file *file_priv);
  1265. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  1266. struct drm_file *file_priv);
  1267. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  1268. struct drm_file *file_priv);
  1269. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  1270. struct drm_file *file_priv);
  1271. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  1272. struct drm_file *file_priv);
  1273. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  1274. struct drm_file *file_priv);
  1275. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  1276. struct drm_file *file_priv);
  1277. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  1278. struct drm_file *file_priv);
  1279. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  1280. struct drm_file *file_priv);
  1281. int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
  1282. struct drm_file *file);
  1283. int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
  1284. struct drm_file *file);
  1285. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  1286. struct drm_file *file_priv);
  1287. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  1288. struct drm_file *file_priv);
  1289. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  1290. struct drm_file *file_priv);
  1291. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  1292. struct drm_file *file_priv);
  1293. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  1294. struct drm_file *file_priv);
  1295. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  1296. struct drm_file *file_priv);
  1297. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  1298. struct drm_file *file_priv);
  1299. int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
  1300. struct drm_file *file_priv);
  1301. void i915_gem_load(struct drm_device *dev);
  1302. void *i915_gem_object_alloc(struct drm_device *dev);
  1303. void i915_gem_object_free(struct drm_i915_gem_object *obj);
  1304. int i915_gem_init_object(struct drm_gem_object *obj);
  1305. void i915_gem_object_init(struct drm_i915_gem_object *obj,
  1306. const struct drm_i915_gem_object_ops *ops);
  1307. struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  1308. size_t size);
  1309. void i915_gem_free_object(struct drm_gem_object *obj);
  1310. int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
  1311. uint32_t alignment,
  1312. bool map_and_fenceable,
  1313. bool nonblocking);
  1314. void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
  1315. int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
  1316. int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
  1317. void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
  1318. void i915_gem_lastclose(struct drm_device *dev);
  1319. int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
  1320. static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
  1321. {
  1322. struct scatterlist *sg = obj->pages->sgl;
  1323. int nents = obj->pages->nents;
  1324. while (nents > SG_MAX_SINGLE_ALLOC) {
  1325. if (n < SG_MAX_SINGLE_ALLOC - 1)
  1326. break;
  1327. sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
  1328. n -= SG_MAX_SINGLE_ALLOC - 1;
  1329. nents -= SG_MAX_SINGLE_ALLOC - 1;
  1330. }
  1331. return sg_page(sg+n);
  1332. }
  1333. static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
  1334. {
  1335. BUG_ON(obj->pages == NULL);
  1336. obj->pages_pin_count++;
  1337. }
  1338. static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
  1339. {
  1340. BUG_ON(obj->pages_pin_count == 0);
  1341. obj->pages_pin_count--;
  1342. }
  1343. int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
  1344. int i915_gem_object_sync(struct drm_i915_gem_object *obj,
  1345. struct intel_ring_buffer *to);
  1346. void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
  1347. struct intel_ring_buffer *ring);
  1348. int i915_gem_dumb_create(struct drm_file *file_priv,
  1349. struct drm_device *dev,
  1350. struct drm_mode_create_dumb *args);
  1351. int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
  1352. uint32_t handle, uint64_t *offset);
  1353. int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
  1354. uint32_t handle);
  1355. /**
  1356. * Returns true if seq1 is later than seq2.
  1357. */
  1358. static inline bool
  1359. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  1360. {
  1361. return (int32_t)(seq1 - seq2) >= 0;
  1362. }
  1363. int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
  1364. int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
  1365. int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
  1366. int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
  1367. static inline bool
  1368. i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
  1369. {
  1370. if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1371. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1372. dev_priv->fence_regs[obj->fence_reg].pin_count++;
  1373. return true;
  1374. } else
  1375. return false;
  1376. }
  1377. static inline void
  1378. i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
  1379. {
  1380. if (obj->fence_reg != I915_FENCE_REG_NONE) {
  1381. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1382. dev_priv->fence_regs[obj->fence_reg].pin_count--;
  1383. }
  1384. }
  1385. void i915_gem_retire_requests(struct drm_device *dev);
  1386. void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
  1387. int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
  1388. bool interruptible);
  1389. static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
  1390. {
  1391. return unlikely(atomic_read(&error->reset_counter)
  1392. & I915_RESET_IN_PROGRESS_FLAG);
  1393. }
  1394. static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
  1395. {
  1396. return atomic_read(&error->reset_counter) == I915_WEDGED;
  1397. }
  1398. void i915_gem_reset(struct drm_device *dev);
  1399. void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
  1400. int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
  1401. uint32_t read_domains,
  1402. uint32_t write_domain);
  1403. int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
  1404. int __must_check i915_gem_init(struct drm_device *dev);
  1405. int __must_check i915_gem_init_hw(struct drm_device *dev);
  1406. void i915_gem_l3_remap(struct drm_device *dev);
  1407. void i915_gem_init_swizzling(struct drm_device *dev);
  1408. void i915_gem_init_ppgtt(struct drm_device *dev);
  1409. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  1410. int __must_check i915_gpu_idle(struct drm_device *dev);
  1411. int __must_check i915_gem_idle(struct drm_device *dev);
  1412. int i915_add_request(struct intel_ring_buffer *ring,
  1413. struct drm_file *file,
  1414. u32 *seqno);
  1415. int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
  1416. uint32_t seqno);
  1417. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  1418. int __must_check
  1419. i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
  1420. bool write);
  1421. int __must_check
  1422. i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
  1423. int __must_check
  1424. i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
  1425. u32 alignment,
  1426. struct intel_ring_buffer *pipelined);
  1427. int i915_gem_attach_phys_object(struct drm_device *dev,
  1428. struct drm_i915_gem_object *obj,
  1429. int id,
  1430. int align);
  1431. void i915_gem_detach_phys_object(struct drm_device *dev,
  1432. struct drm_i915_gem_object *obj);
  1433. void i915_gem_free_all_phys_object(struct drm_device *dev);
  1434. void i915_gem_release(struct drm_device *dev, struct drm_file *file);
  1435. uint32_t
  1436. i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
  1437. uint32_t
  1438. i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
  1439. int tiling_mode, bool fenced);
  1440. int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  1441. enum i915_cache_level cache_level);
  1442. struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
  1443. struct dma_buf *dma_buf);
  1444. struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
  1445. struct drm_gem_object *gem_obj, int flags);
  1446. /* i915_gem_context.c */
  1447. void i915_gem_context_init(struct drm_device *dev);
  1448. void i915_gem_context_fini(struct drm_device *dev);
  1449. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
  1450. int i915_switch_context(struct intel_ring_buffer *ring,
  1451. struct drm_file *file, int to_id);
  1452. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  1453. struct drm_file *file);
  1454. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  1455. struct drm_file *file);
  1456. /* i915_gem_gtt.c */
  1457. void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
  1458. void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
  1459. struct drm_i915_gem_object *obj,
  1460. enum i915_cache_level cache_level);
  1461. void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
  1462. struct drm_i915_gem_object *obj);
  1463. void i915_gem_restore_gtt_mappings(struct drm_device *dev);
  1464. int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
  1465. void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
  1466. enum i915_cache_level cache_level);
  1467. void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
  1468. void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
  1469. void i915_gem_init_global_gtt(struct drm_device *dev);
  1470. void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
  1471. unsigned long mappable_end, unsigned long end);
  1472. int i915_gem_gtt_init(struct drm_device *dev);
  1473. static inline void i915_gem_chipset_flush(struct drm_device *dev)
  1474. {
  1475. if (INTEL_INFO(dev)->gen < 6)
  1476. intel_gtt_chipset_flush();
  1477. }
  1478. /* i915_gem_evict.c */
  1479. int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
  1480. unsigned alignment,
  1481. unsigned cache_level,
  1482. bool mappable,
  1483. bool nonblock);
  1484. int i915_gem_evict_everything(struct drm_device *dev);
  1485. /* i915_gem_stolen.c */
  1486. int i915_gem_init_stolen(struct drm_device *dev);
  1487. int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
  1488. void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
  1489. void i915_gem_cleanup_stolen(struct drm_device *dev);
  1490. struct drm_i915_gem_object *
  1491. i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
  1492. void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
  1493. /* i915_gem_tiling.c */
  1494. inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
  1495. {
  1496. drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
  1497. return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
  1498. obj->tiling_mode != I915_TILING_NONE;
  1499. }
  1500. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  1501. void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1502. void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
  1503. /* i915_gem_debug.c */
  1504. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1505. const char *where, uint32_t mark);
  1506. #if WATCH_LISTS
  1507. int i915_verify_lists(struct drm_device *dev);
  1508. #else
  1509. #define i915_verify_lists(dev) 0
  1510. #endif
  1511. void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
  1512. int handle);
  1513. void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
  1514. const char *where, uint32_t mark);
  1515. /* i915_debugfs.c */
  1516. int i915_debugfs_init(struct drm_minor *minor);
  1517. void i915_debugfs_cleanup(struct drm_minor *minor);
  1518. /* i915_suspend.c */
  1519. extern int i915_save_state(struct drm_device *dev);
  1520. extern int i915_restore_state(struct drm_device *dev);
  1521. /* i915_ums.c */
  1522. void i915_save_display_reg(struct drm_device *dev);
  1523. void i915_restore_display_reg(struct drm_device *dev);
  1524. /* i915_sysfs.c */
  1525. void i915_setup_sysfs(struct drm_device *dev_priv);
  1526. void i915_teardown_sysfs(struct drm_device *dev_priv);
  1527. /* intel_i2c.c */
  1528. extern int intel_setup_gmbus(struct drm_device *dev);
  1529. extern void intel_teardown_gmbus(struct drm_device *dev);
  1530. extern inline bool intel_gmbus_is_port_valid(unsigned port)
  1531. {
  1532. return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
  1533. }
  1534. extern struct i2c_adapter *intel_gmbus_get_adapter(
  1535. struct drm_i915_private *dev_priv, unsigned port);
  1536. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  1537. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  1538. extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  1539. {
  1540. return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  1541. }
  1542. extern void intel_i2c_reset(struct drm_device *dev);
  1543. /* intel_opregion.c */
  1544. extern int intel_opregion_setup(struct drm_device *dev);
  1545. #ifdef CONFIG_ACPI
  1546. extern void intel_opregion_init(struct drm_device *dev);
  1547. extern void intel_opregion_fini(struct drm_device *dev);
  1548. extern void intel_opregion_asle_intr(struct drm_device *dev);
  1549. extern void intel_opregion_gse_intr(struct drm_device *dev);
  1550. extern void intel_opregion_enable_asle(struct drm_device *dev);
  1551. #else
  1552. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  1553. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  1554. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  1555. static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
  1556. static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
  1557. #endif
  1558. /* intel_acpi.c */
  1559. #ifdef CONFIG_ACPI
  1560. extern void intel_register_dsm_handler(void);
  1561. extern void intel_unregister_dsm_handler(void);
  1562. #else
  1563. static inline void intel_register_dsm_handler(void) { return; }
  1564. static inline void intel_unregister_dsm_handler(void) { return; }
  1565. #endif /* CONFIG_ACPI */
  1566. /* modesetting */
  1567. extern void intel_modeset_init_hw(struct drm_device *dev);
  1568. extern void intel_modeset_init(struct drm_device *dev);
  1569. extern void intel_modeset_gem_init(struct drm_device *dev);
  1570. extern void intel_modeset_cleanup(struct drm_device *dev);
  1571. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  1572. extern void intel_modeset_setup_hw_state(struct drm_device *dev,
  1573. bool force_restore);
  1574. extern void i915_redisable_vga(struct drm_device *dev);
  1575. extern bool intel_fbc_enabled(struct drm_device *dev);
  1576. extern void intel_disable_fbc(struct drm_device *dev);
  1577. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  1578. extern void intel_init_pch_refclk(struct drm_device *dev);
  1579. extern void gen6_set_rps(struct drm_device *dev, u8 val);
  1580. extern void intel_detect_pch(struct drm_device *dev);
  1581. extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
  1582. extern int intel_enable_rc6(const struct drm_device *dev);
  1583. extern bool i915_semaphore_is_enabled(struct drm_device *dev);
  1584. int i915_reg_read_ioctl(struct drm_device *dev, void *data,
  1585. struct drm_file *file);
  1586. /* overlay */
  1587. #ifdef CONFIG_DEBUG_FS
  1588. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  1589. extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
  1590. extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
  1591. extern void intel_display_print_error_state(struct seq_file *m,
  1592. struct drm_device *dev,
  1593. struct intel_display_error_state *error);
  1594. #endif
  1595. /* On SNB platform, before reading ring registers forcewake bit
  1596. * must be set to prevent GT core from power down and stale values being
  1597. * returned.
  1598. */
  1599. void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
  1600. void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
  1601. int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
  1602. int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
  1603. int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
  1604. #define __i915_read(x, y) \
  1605. u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
  1606. __i915_read(8, b)
  1607. __i915_read(16, w)
  1608. __i915_read(32, l)
  1609. __i915_read(64, q)
  1610. #undef __i915_read
  1611. #define __i915_write(x, y) \
  1612. void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
  1613. __i915_write(8, b)
  1614. __i915_write(16, w)
  1615. __i915_write(32, l)
  1616. __i915_write(64, q)
  1617. #undef __i915_write
  1618. #define I915_READ8(reg) i915_read8(dev_priv, (reg))
  1619. #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
  1620. #define I915_READ16(reg) i915_read16(dev_priv, (reg))
  1621. #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
  1622. #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
  1623. #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
  1624. #define I915_READ(reg) i915_read32(dev_priv, (reg))
  1625. #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
  1626. #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
  1627. #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
  1628. #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
  1629. #define I915_READ64(reg) i915_read64(dev_priv, (reg))
  1630. #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
  1631. #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
  1632. /* "Broadcast RGB" property */
  1633. #define INTEL_BROADCAST_RGB_AUTO 0
  1634. #define INTEL_BROADCAST_RGB_FULL 1
  1635. #define INTEL_BROADCAST_RGB_LIMITED 2
  1636. static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
  1637. {
  1638. if (HAS_PCH_SPLIT(dev))
  1639. return CPU_VGACNTRL;
  1640. else if (IS_VALLEYVIEW(dev))
  1641. return VLV_VGACNTRL;
  1642. else
  1643. return VGACNTRL;
  1644. }
  1645. #endif