i915_drv.c 36 KB

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  1. /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #include <linux/device.h>
  30. #include <drm/drmP.h>
  31. #include <drm/i915_drm.h>
  32. #include "i915_drv.h"
  33. #include "i915_trace.h"
  34. #include "intel_drv.h"
  35. #include <linux/console.h>
  36. #include <linux/module.h>
  37. #include <drm/drm_crtc_helper.h>
  38. static int i915_modeset __read_mostly = -1;
  39. module_param_named(modeset, i915_modeset, int, 0400);
  40. MODULE_PARM_DESC(modeset,
  41. "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  42. "1=on, -1=force vga console preference [default])");
  43. unsigned int i915_fbpercrtc __always_unused = 0;
  44. module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  45. int i915_panel_ignore_lid __read_mostly = 1;
  46. module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  47. MODULE_PARM_DESC(panel_ignore_lid,
  48. "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  49. "-1=force lid closed, -2=force lid open)");
  50. unsigned int i915_powersave __read_mostly = 1;
  51. module_param_named(powersave, i915_powersave, int, 0600);
  52. MODULE_PARM_DESC(powersave,
  53. "Enable powersavings, fbc, downclocking, etc. (default: true)");
  54. int i915_semaphores __read_mostly = -1;
  55. module_param_named(semaphores, i915_semaphores, int, 0600);
  56. MODULE_PARM_DESC(semaphores,
  57. "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  58. int i915_enable_rc6 __read_mostly = -1;
  59. module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  60. MODULE_PARM_DESC(i915_enable_rc6,
  61. "Enable power-saving render C-state 6. "
  62. "Different stages can be selected via bitmask values "
  63. "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  64. "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  65. "default: -1 (use per-chip default)");
  66. int i915_enable_fbc __read_mostly = -1;
  67. module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  68. MODULE_PARM_DESC(i915_enable_fbc,
  69. "Enable frame buffer compression for power savings "
  70. "(default: -1 (use per-chip default))");
  71. unsigned int i915_lvds_downclock __read_mostly = 0;
  72. module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  73. MODULE_PARM_DESC(lvds_downclock,
  74. "Use panel (LVDS/eDP) downclocking for power savings "
  75. "(default: false)");
  76. int i915_lvds_channel_mode __read_mostly;
  77. module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  78. MODULE_PARM_DESC(lvds_channel_mode,
  79. "Specify LVDS channel mode "
  80. "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  81. int i915_panel_use_ssc __read_mostly = -1;
  82. module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  83. MODULE_PARM_DESC(lvds_use_ssc,
  84. "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  85. "(default: auto from VBT)");
  86. int i915_vbt_sdvo_panel_type __read_mostly = -1;
  87. module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  88. MODULE_PARM_DESC(vbt_sdvo_panel_type,
  89. "Override/Ignore selection of SDVO panel mode in the VBT "
  90. "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
  91. static bool i915_try_reset __read_mostly = true;
  92. module_param_named(reset, i915_try_reset, bool, 0600);
  93. MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  94. bool i915_enable_hangcheck __read_mostly = true;
  95. module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
  96. MODULE_PARM_DESC(enable_hangcheck,
  97. "Periodically check GPU activity for detecting hangs. "
  98. "WARNING: Disabling this can cause system wide hangs. "
  99. "(default: true)");
  100. int i915_enable_ppgtt __read_mostly = -1;
  101. module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
  102. MODULE_PARM_DESC(i915_enable_ppgtt,
  103. "Enable PPGTT (default: true)");
  104. unsigned int i915_preliminary_hw_support __read_mostly = 0;
  105. module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
  106. MODULE_PARM_DESC(preliminary_hw_support,
  107. "Enable preliminary hardware support. "
  108. "Enable Haswell and ValleyView Support. "
  109. "(default: false)");
  110. static struct drm_driver driver;
  111. extern int intel_agp_enabled;
  112. #define INTEL_VGA_DEVICE(id, info) { \
  113. .class = PCI_BASE_CLASS_DISPLAY << 16, \
  114. .class_mask = 0xff0000, \
  115. .vendor = 0x8086, \
  116. .device = id, \
  117. .subvendor = PCI_ANY_ID, \
  118. .subdevice = PCI_ANY_ID, \
  119. .driver_data = (unsigned long) info }
  120. static const struct intel_device_info intel_i830_info = {
  121. .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  122. .has_overlay = 1, .overlay_needs_physical = 1,
  123. };
  124. static const struct intel_device_info intel_845g_info = {
  125. .gen = 2,
  126. .has_overlay = 1, .overlay_needs_physical = 1,
  127. };
  128. static const struct intel_device_info intel_i85x_info = {
  129. .gen = 2, .is_i85x = 1, .is_mobile = 1,
  130. .cursor_needs_physical = 1,
  131. .has_overlay = 1, .overlay_needs_physical = 1,
  132. };
  133. static const struct intel_device_info intel_i865g_info = {
  134. .gen = 2,
  135. .has_overlay = 1, .overlay_needs_physical = 1,
  136. };
  137. static const struct intel_device_info intel_i915g_info = {
  138. .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  139. .has_overlay = 1, .overlay_needs_physical = 1,
  140. };
  141. static const struct intel_device_info intel_i915gm_info = {
  142. .gen = 3, .is_mobile = 1,
  143. .cursor_needs_physical = 1,
  144. .has_overlay = 1, .overlay_needs_physical = 1,
  145. .supports_tv = 1,
  146. };
  147. static const struct intel_device_info intel_i945g_info = {
  148. .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  149. .has_overlay = 1, .overlay_needs_physical = 1,
  150. };
  151. static const struct intel_device_info intel_i945gm_info = {
  152. .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  153. .has_hotplug = 1, .cursor_needs_physical = 1,
  154. .has_overlay = 1, .overlay_needs_physical = 1,
  155. .supports_tv = 1,
  156. };
  157. static const struct intel_device_info intel_i965g_info = {
  158. .gen = 4, .is_broadwater = 1,
  159. .has_hotplug = 1,
  160. .has_overlay = 1,
  161. };
  162. static const struct intel_device_info intel_i965gm_info = {
  163. .gen = 4, .is_crestline = 1,
  164. .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
  165. .has_overlay = 1,
  166. .supports_tv = 1,
  167. };
  168. static const struct intel_device_info intel_g33_info = {
  169. .gen = 3, .is_g33 = 1,
  170. .need_gfx_hws = 1, .has_hotplug = 1,
  171. .has_overlay = 1,
  172. };
  173. static const struct intel_device_info intel_g45_info = {
  174. .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
  175. .has_pipe_cxsr = 1, .has_hotplug = 1,
  176. .has_bsd_ring = 1,
  177. };
  178. static const struct intel_device_info intel_gm45_info = {
  179. .gen = 4, .is_g4x = 1,
  180. .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
  181. .has_pipe_cxsr = 1, .has_hotplug = 1,
  182. .supports_tv = 1,
  183. .has_bsd_ring = 1,
  184. };
  185. static const struct intel_device_info intel_pineview_info = {
  186. .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
  187. .need_gfx_hws = 1, .has_hotplug = 1,
  188. .has_overlay = 1,
  189. };
  190. static const struct intel_device_info intel_ironlake_d_info = {
  191. .gen = 5,
  192. .need_gfx_hws = 1, .has_hotplug = 1,
  193. .has_bsd_ring = 1,
  194. };
  195. static const struct intel_device_info intel_ironlake_m_info = {
  196. .gen = 5, .is_mobile = 1,
  197. .need_gfx_hws = 1, .has_hotplug = 1,
  198. .has_fbc = 1,
  199. .has_bsd_ring = 1,
  200. };
  201. static const struct intel_device_info intel_sandybridge_d_info = {
  202. .gen = 6,
  203. .need_gfx_hws = 1, .has_hotplug = 1,
  204. .has_bsd_ring = 1,
  205. .has_blt_ring = 1,
  206. .has_llc = 1,
  207. .has_force_wake = 1,
  208. };
  209. static const struct intel_device_info intel_sandybridge_m_info = {
  210. .gen = 6, .is_mobile = 1,
  211. .need_gfx_hws = 1, .has_hotplug = 1,
  212. .has_fbc = 1,
  213. .has_bsd_ring = 1,
  214. .has_blt_ring = 1,
  215. .has_llc = 1,
  216. .has_force_wake = 1,
  217. };
  218. static const struct intel_device_info intel_ivybridge_d_info = {
  219. .is_ivybridge = 1, .gen = 7,
  220. .need_gfx_hws = 1, .has_hotplug = 1,
  221. .has_bsd_ring = 1,
  222. .has_blt_ring = 1,
  223. .has_llc = 1,
  224. .has_force_wake = 1,
  225. };
  226. static const struct intel_device_info intel_ivybridge_m_info = {
  227. .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
  228. .need_gfx_hws = 1, .has_hotplug = 1,
  229. .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
  230. .has_bsd_ring = 1,
  231. .has_blt_ring = 1,
  232. .has_llc = 1,
  233. .has_force_wake = 1,
  234. };
  235. static const struct intel_device_info intel_valleyview_m_info = {
  236. .gen = 7, .is_mobile = 1,
  237. .need_gfx_hws = 1, .has_hotplug = 1,
  238. .has_fbc = 0,
  239. .has_bsd_ring = 1,
  240. .has_blt_ring = 1,
  241. .is_valleyview = 1,
  242. .display_mmio_offset = VLV_DISPLAY_BASE,
  243. };
  244. static const struct intel_device_info intel_valleyview_d_info = {
  245. .gen = 7,
  246. .need_gfx_hws = 1, .has_hotplug = 1,
  247. .has_fbc = 0,
  248. .has_bsd_ring = 1,
  249. .has_blt_ring = 1,
  250. .is_valleyview = 1,
  251. .display_mmio_offset = VLV_DISPLAY_BASE,
  252. };
  253. static const struct intel_device_info intel_haswell_d_info = {
  254. .is_haswell = 1, .gen = 7,
  255. .need_gfx_hws = 1, .has_hotplug = 1,
  256. .has_bsd_ring = 1,
  257. .has_blt_ring = 1,
  258. .has_llc = 1,
  259. .has_force_wake = 1,
  260. };
  261. static const struct intel_device_info intel_haswell_m_info = {
  262. .is_haswell = 1, .gen = 7, .is_mobile = 1,
  263. .need_gfx_hws = 1, .has_hotplug = 1,
  264. .has_bsd_ring = 1,
  265. .has_blt_ring = 1,
  266. .has_llc = 1,
  267. .has_force_wake = 1,
  268. };
  269. static const struct pci_device_id pciidlist[] = { /* aka */
  270. INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
  271. INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
  272. INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
  273. INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
  274. INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
  275. INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
  276. INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
  277. INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
  278. INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
  279. INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
  280. INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
  281. INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
  282. INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
  283. INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
  284. INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
  285. INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
  286. INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
  287. INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
  288. INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
  289. INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
  290. INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
  291. INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
  292. INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
  293. INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
  294. INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
  295. INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
  296. INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
  297. INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
  298. INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
  299. INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
  300. INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
  301. INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
  302. INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
  303. INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
  304. INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
  305. INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
  306. INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
  307. INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
  308. INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
  309. INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
  310. INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
  311. INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
  312. INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
  313. INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
  314. INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
  315. INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
  316. INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
  317. INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
  318. INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
  319. INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
  320. INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
  321. INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
  322. INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
  323. INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
  324. INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
  325. INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
  326. INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
  327. INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
  328. INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
  329. INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
  330. INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
  331. INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
  332. INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
  333. INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
  334. INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
  335. INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
  336. INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
  337. INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
  338. INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
  339. INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
  340. INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
  341. INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
  342. INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
  343. INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
  344. INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
  345. INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
  346. INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
  347. INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
  348. INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
  349. INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
  350. INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
  351. INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
  352. INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
  353. {0, 0, 0}
  354. };
  355. #if defined(CONFIG_DRM_I915_KMS)
  356. MODULE_DEVICE_TABLE(pci, pciidlist);
  357. #endif
  358. void intel_detect_pch(struct drm_device *dev)
  359. {
  360. struct drm_i915_private *dev_priv = dev->dev_private;
  361. struct pci_dev *pch;
  362. /*
  363. * The reason to probe ISA bridge instead of Dev31:Fun0 is to
  364. * make graphics device passthrough work easy for VMM, that only
  365. * need to expose ISA bridge to let driver know the real hardware
  366. * underneath. This is a requirement from virtualization team.
  367. */
  368. pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
  369. if (pch) {
  370. if (pch->vendor == PCI_VENDOR_ID_INTEL) {
  371. unsigned short id;
  372. id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
  373. dev_priv->pch_id = id;
  374. if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
  375. dev_priv->pch_type = PCH_IBX;
  376. dev_priv->num_pch_pll = 2;
  377. DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
  378. WARN_ON(!IS_GEN5(dev));
  379. } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
  380. dev_priv->pch_type = PCH_CPT;
  381. dev_priv->num_pch_pll = 2;
  382. DRM_DEBUG_KMS("Found CougarPoint PCH\n");
  383. WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
  384. } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
  385. /* PantherPoint is CPT compatible */
  386. dev_priv->pch_type = PCH_CPT;
  387. dev_priv->num_pch_pll = 2;
  388. DRM_DEBUG_KMS("Found PatherPoint PCH\n");
  389. WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
  390. } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
  391. dev_priv->pch_type = PCH_LPT;
  392. dev_priv->num_pch_pll = 0;
  393. DRM_DEBUG_KMS("Found LynxPoint PCH\n");
  394. WARN_ON(!IS_HASWELL(dev));
  395. } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
  396. dev_priv->pch_type = PCH_LPT;
  397. dev_priv->num_pch_pll = 0;
  398. DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
  399. WARN_ON(!IS_HASWELL(dev));
  400. }
  401. BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
  402. }
  403. pci_dev_put(pch);
  404. }
  405. }
  406. bool i915_semaphore_is_enabled(struct drm_device *dev)
  407. {
  408. if (INTEL_INFO(dev)->gen < 6)
  409. return 0;
  410. if (i915_semaphores >= 0)
  411. return i915_semaphores;
  412. #ifdef CONFIG_INTEL_IOMMU
  413. /* Enable semaphores on SNB when IO remapping is off */
  414. if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
  415. return false;
  416. #endif
  417. return 1;
  418. }
  419. static int i915_drm_freeze(struct drm_device *dev)
  420. {
  421. struct drm_i915_private *dev_priv = dev->dev_private;
  422. /* ignore lid events during suspend */
  423. mutex_lock(&dev_priv->modeset_restore_lock);
  424. dev_priv->modeset_restore = MODESET_SUSPENDED;
  425. mutex_unlock(&dev_priv->modeset_restore_lock);
  426. intel_set_power_well(dev, true);
  427. drm_kms_helper_poll_disable(dev);
  428. pci_save_state(dev->pdev);
  429. /* If KMS is active, we do the leavevt stuff here */
  430. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  431. int error = i915_gem_idle(dev);
  432. if (error) {
  433. dev_err(&dev->pdev->dev,
  434. "GEM idle failed, resume might fail\n");
  435. return error;
  436. }
  437. cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
  438. intel_modeset_disable(dev);
  439. drm_irq_uninstall(dev);
  440. dev_priv->enable_hotplug_processing = false;
  441. }
  442. i915_save_state(dev);
  443. intel_opregion_fini(dev);
  444. console_lock();
  445. intel_fbdev_set_suspend(dev, 1);
  446. console_unlock();
  447. return 0;
  448. }
  449. int i915_suspend(struct drm_device *dev, pm_message_t state)
  450. {
  451. int error;
  452. if (!dev || !dev->dev_private) {
  453. DRM_ERROR("dev: %p\n", dev);
  454. DRM_ERROR("DRM not initialized, aborting suspend.\n");
  455. return -ENODEV;
  456. }
  457. if (state.event == PM_EVENT_PRETHAW)
  458. return 0;
  459. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  460. return 0;
  461. error = i915_drm_freeze(dev);
  462. if (error)
  463. return error;
  464. if (state.event == PM_EVENT_SUSPEND) {
  465. /* Shut down the device */
  466. pci_disable_device(dev->pdev);
  467. pci_set_power_state(dev->pdev, PCI_D3hot);
  468. }
  469. return 0;
  470. }
  471. void intel_console_resume(struct work_struct *work)
  472. {
  473. struct drm_i915_private *dev_priv =
  474. container_of(work, struct drm_i915_private,
  475. console_resume_work);
  476. struct drm_device *dev = dev_priv->dev;
  477. console_lock();
  478. intel_fbdev_set_suspend(dev, 0);
  479. console_unlock();
  480. }
  481. static int __i915_drm_thaw(struct drm_device *dev)
  482. {
  483. struct drm_i915_private *dev_priv = dev->dev_private;
  484. int error = 0;
  485. i915_restore_state(dev);
  486. intel_opregion_setup(dev);
  487. /* KMS EnterVT equivalent */
  488. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  489. intel_init_pch_refclk(dev);
  490. mutex_lock(&dev->struct_mutex);
  491. dev_priv->mm.suspended = 0;
  492. error = i915_gem_init_hw(dev);
  493. mutex_unlock(&dev->struct_mutex);
  494. /* We need working interrupts for modeset enabling ... */
  495. drm_irq_install(dev);
  496. intel_modeset_init_hw(dev);
  497. intel_modeset_setup_hw_state(dev, false);
  498. /*
  499. * ... but also need to make sure that hotplug processing
  500. * doesn't cause havoc. Like in the driver load code we don't
  501. * bother with the tiny race here where we might loose hotplug
  502. * notifications.
  503. * */
  504. intel_hpd_init(dev);
  505. dev_priv->enable_hotplug_processing = true;
  506. }
  507. intel_opregion_init(dev);
  508. /*
  509. * The console lock can be pretty contented on resume due
  510. * to all the printk activity. Try to keep it out of the hot
  511. * path of resume if possible.
  512. */
  513. if (console_trylock()) {
  514. intel_fbdev_set_suspend(dev, 0);
  515. console_unlock();
  516. } else {
  517. schedule_work(&dev_priv->console_resume_work);
  518. }
  519. mutex_lock(&dev_priv->modeset_restore_lock);
  520. dev_priv->modeset_restore = MODESET_DONE;
  521. mutex_unlock(&dev_priv->modeset_restore_lock);
  522. return error;
  523. }
  524. static int i915_drm_thaw(struct drm_device *dev)
  525. {
  526. int error = 0;
  527. intel_gt_reset(dev);
  528. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  529. mutex_lock(&dev->struct_mutex);
  530. i915_gem_restore_gtt_mappings(dev);
  531. mutex_unlock(&dev->struct_mutex);
  532. }
  533. __i915_drm_thaw(dev);
  534. return error;
  535. }
  536. int i915_resume(struct drm_device *dev)
  537. {
  538. struct drm_i915_private *dev_priv = dev->dev_private;
  539. int ret;
  540. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  541. return 0;
  542. if (pci_enable_device(dev->pdev))
  543. return -EIO;
  544. pci_set_master(dev->pdev);
  545. intel_gt_reset(dev);
  546. /*
  547. * Platforms with opregion should have sane BIOS, older ones (gen3 and
  548. * earlier) need this since the BIOS might clear all our scratch PTEs.
  549. */
  550. if (drm_core_check_feature(dev, DRIVER_MODESET) &&
  551. !dev_priv->opregion.header) {
  552. mutex_lock(&dev->struct_mutex);
  553. i915_gem_restore_gtt_mappings(dev);
  554. mutex_unlock(&dev->struct_mutex);
  555. }
  556. ret = __i915_drm_thaw(dev);
  557. if (ret)
  558. return ret;
  559. drm_kms_helper_poll_enable(dev);
  560. return 0;
  561. }
  562. static int i8xx_do_reset(struct drm_device *dev)
  563. {
  564. struct drm_i915_private *dev_priv = dev->dev_private;
  565. if (IS_I85X(dev))
  566. return -ENODEV;
  567. I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
  568. POSTING_READ(D_STATE);
  569. if (IS_I830(dev) || IS_845G(dev)) {
  570. I915_WRITE(DEBUG_RESET_I830,
  571. DEBUG_RESET_DISPLAY |
  572. DEBUG_RESET_RENDER |
  573. DEBUG_RESET_FULL);
  574. POSTING_READ(DEBUG_RESET_I830);
  575. msleep(1);
  576. I915_WRITE(DEBUG_RESET_I830, 0);
  577. POSTING_READ(DEBUG_RESET_I830);
  578. }
  579. msleep(1);
  580. I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
  581. POSTING_READ(D_STATE);
  582. return 0;
  583. }
  584. static int i965_reset_complete(struct drm_device *dev)
  585. {
  586. u8 gdrst;
  587. pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
  588. return (gdrst & GRDOM_RESET_ENABLE) == 0;
  589. }
  590. static int i965_do_reset(struct drm_device *dev)
  591. {
  592. int ret;
  593. u8 gdrst;
  594. /*
  595. * Set the domains we want to reset (GRDOM/bits 2 and 3) as
  596. * well as the reset bit (GR/bit 0). Setting the GR bit
  597. * triggers the reset; when done, the hardware will clear it.
  598. */
  599. pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
  600. pci_write_config_byte(dev->pdev, I965_GDRST,
  601. gdrst | GRDOM_RENDER |
  602. GRDOM_RESET_ENABLE);
  603. ret = wait_for(i965_reset_complete(dev), 500);
  604. if (ret)
  605. return ret;
  606. /* We can't reset render&media without also resetting display ... */
  607. pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
  608. pci_write_config_byte(dev->pdev, I965_GDRST,
  609. gdrst | GRDOM_MEDIA |
  610. GRDOM_RESET_ENABLE);
  611. return wait_for(i965_reset_complete(dev), 500);
  612. }
  613. static int ironlake_do_reset(struct drm_device *dev)
  614. {
  615. struct drm_i915_private *dev_priv = dev->dev_private;
  616. u32 gdrst;
  617. int ret;
  618. gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
  619. I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
  620. gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
  621. ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
  622. if (ret)
  623. return ret;
  624. /* We can't reset render&media without also resetting display ... */
  625. gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
  626. I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
  627. gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
  628. return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
  629. }
  630. static int gen6_do_reset(struct drm_device *dev)
  631. {
  632. struct drm_i915_private *dev_priv = dev->dev_private;
  633. int ret;
  634. unsigned long irqflags;
  635. /* Hold gt_lock across reset to prevent any register access
  636. * with forcewake not set correctly
  637. */
  638. spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
  639. /* Reset the chip */
  640. /* GEN6_GDRST is not in the gt power well, no need to check
  641. * for fifo space for the write or forcewake the chip for
  642. * the read
  643. */
  644. I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
  645. /* Spin waiting for the device to ack the reset request */
  646. ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
  647. /* If reset with a user forcewake, try to restore, otherwise turn it off */
  648. if (dev_priv->forcewake_count)
  649. dev_priv->gt.force_wake_get(dev_priv);
  650. else
  651. dev_priv->gt.force_wake_put(dev_priv);
  652. /* Restore fifo count */
  653. dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
  654. spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
  655. return ret;
  656. }
  657. int intel_gpu_reset(struct drm_device *dev)
  658. {
  659. struct drm_i915_private *dev_priv = dev->dev_private;
  660. int ret = -ENODEV;
  661. switch (INTEL_INFO(dev)->gen) {
  662. case 7:
  663. case 6:
  664. ret = gen6_do_reset(dev);
  665. break;
  666. case 5:
  667. ret = ironlake_do_reset(dev);
  668. break;
  669. case 4:
  670. ret = i965_do_reset(dev);
  671. break;
  672. case 2:
  673. ret = i8xx_do_reset(dev);
  674. break;
  675. }
  676. /* Also reset the gpu hangman. */
  677. if (dev_priv->gpu_error.stop_rings) {
  678. DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
  679. dev_priv->gpu_error.stop_rings = 0;
  680. if (ret == -ENODEV) {
  681. DRM_ERROR("Reset not implemented, but ignoring "
  682. "error for simulated gpu hangs\n");
  683. ret = 0;
  684. }
  685. }
  686. return ret;
  687. }
  688. /**
  689. * i915_reset - reset chip after a hang
  690. * @dev: drm device to reset
  691. *
  692. * Reset the chip. Useful if a hang is detected. Returns zero on successful
  693. * reset or otherwise an error code.
  694. *
  695. * Procedure is fairly simple:
  696. * - reset the chip using the reset reg
  697. * - re-init context state
  698. * - re-init hardware status page
  699. * - re-init ring buffer
  700. * - re-init interrupt state
  701. * - re-init display
  702. */
  703. int i915_reset(struct drm_device *dev)
  704. {
  705. drm_i915_private_t *dev_priv = dev->dev_private;
  706. int ret;
  707. if (!i915_try_reset)
  708. return 0;
  709. mutex_lock(&dev->struct_mutex);
  710. i915_gem_reset(dev);
  711. ret = -ENODEV;
  712. if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
  713. DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
  714. else
  715. ret = intel_gpu_reset(dev);
  716. dev_priv->gpu_error.last_reset = get_seconds();
  717. if (ret) {
  718. DRM_ERROR("Failed to reset chip.\n");
  719. mutex_unlock(&dev->struct_mutex);
  720. return ret;
  721. }
  722. /* Ok, now get things going again... */
  723. /*
  724. * Everything depends on having the GTT running, so we need to start
  725. * there. Fortunately we don't need to do this unless we reset the
  726. * chip at a PCI level.
  727. *
  728. * Next we need to restore the context, but we don't use those
  729. * yet either...
  730. *
  731. * Ring buffer needs to be re-initialized in the KMS case, or if X
  732. * was running at the time of the reset (i.e. we weren't VT
  733. * switched away).
  734. */
  735. if (drm_core_check_feature(dev, DRIVER_MODESET) ||
  736. !dev_priv->mm.suspended) {
  737. struct intel_ring_buffer *ring;
  738. int i;
  739. dev_priv->mm.suspended = 0;
  740. i915_gem_init_swizzling(dev);
  741. for_each_ring(ring, dev_priv, i)
  742. ring->init(ring);
  743. i915_gem_context_init(dev);
  744. i915_gem_init_ppgtt(dev);
  745. /*
  746. * It would make sense to re-init all the other hw state, at
  747. * least the rps/rc6/emon init done within modeset_init_hw. For
  748. * some unknown reason, this blows up my ilk, so don't.
  749. */
  750. mutex_unlock(&dev->struct_mutex);
  751. drm_irq_uninstall(dev);
  752. drm_irq_install(dev);
  753. intel_hpd_init(dev);
  754. } else {
  755. mutex_unlock(&dev->struct_mutex);
  756. }
  757. return 0;
  758. }
  759. static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  760. {
  761. struct intel_device_info *intel_info =
  762. (struct intel_device_info *) ent->driver_data;
  763. if (intel_info->is_valleyview)
  764. if(!i915_preliminary_hw_support) {
  765. DRM_ERROR("Preliminary hardware support disabled\n");
  766. return -ENODEV;
  767. }
  768. /* Only bind to function 0 of the device. Early generations
  769. * used function 1 as a placeholder for multi-head. This causes
  770. * us confusion instead, especially on the systems where both
  771. * functions have the same PCI-ID!
  772. */
  773. if (PCI_FUNC(pdev->devfn))
  774. return -ENODEV;
  775. /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
  776. * implementation for gen3 (and only gen3) that used legacy drm maps
  777. * (gasp!) to share buffers between X and the client. Hence we need to
  778. * keep around the fake agp stuff for gen3, even when kms is enabled. */
  779. if (intel_info->gen != 3) {
  780. driver.driver_features &=
  781. ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
  782. } else if (!intel_agp_enabled) {
  783. DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
  784. return -ENODEV;
  785. }
  786. return drm_get_pci_dev(pdev, ent, &driver);
  787. }
  788. static void
  789. i915_pci_remove(struct pci_dev *pdev)
  790. {
  791. struct drm_device *dev = pci_get_drvdata(pdev);
  792. drm_put_dev(dev);
  793. }
  794. static int i915_pm_suspend(struct device *dev)
  795. {
  796. struct pci_dev *pdev = to_pci_dev(dev);
  797. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  798. int error;
  799. if (!drm_dev || !drm_dev->dev_private) {
  800. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  801. return -ENODEV;
  802. }
  803. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  804. return 0;
  805. error = i915_drm_freeze(drm_dev);
  806. if (error)
  807. return error;
  808. pci_disable_device(pdev);
  809. pci_set_power_state(pdev, PCI_D3hot);
  810. return 0;
  811. }
  812. static int i915_pm_resume(struct device *dev)
  813. {
  814. struct pci_dev *pdev = to_pci_dev(dev);
  815. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  816. return i915_resume(drm_dev);
  817. }
  818. static int i915_pm_freeze(struct device *dev)
  819. {
  820. struct pci_dev *pdev = to_pci_dev(dev);
  821. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  822. if (!drm_dev || !drm_dev->dev_private) {
  823. dev_err(dev, "DRM not initialized, aborting suspend.\n");
  824. return -ENODEV;
  825. }
  826. return i915_drm_freeze(drm_dev);
  827. }
  828. static int i915_pm_thaw(struct device *dev)
  829. {
  830. struct pci_dev *pdev = to_pci_dev(dev);
  831. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  832. return i915_drm_thaw(drm_dev);
  833. }
  834. static int i915_pm_poweroff(struct device *dev)
  835. {
  836. struct pci_dev *pdev = to_pci_dev(dev);
  837. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  838. return i915_drm_freeze(drm_dev);
  839. }
  840. static const struct dev_pm_ops i915_pm_ops = {
  841. .suspend = i915_pm_suspend,
  842. .resume = i915_pm_resume,
  843. .freeze = i915_pm_freeze,
  844. .thaw = i915_pm_thaw,
  845. .poweroff = i915_pm_poweroff,
  846. .restore = i915_pm_resume,
  847. };
  848. static const struct vm_operations_struct i915_gem_vm_ops = {
  849. .fault = i915_gem_fault,
  850. .open = drm_gem_vm_open,
  851. .close = drm_gem_vm_close,
  852. };
  853. static const struct file_operations i915_driver_fops = {
  854. .owner = THIS_MODULE,
  855. .open = drm_open,
  856. .release = drm_release,
  857. .unlocked_ioctl = drm_ioctl,
  858. .mmap = drm_gem_mmap,
  859. .poll = drm_poll,
  860. .fasync = drm_fasync,
  861. .read = drm_read,
  862. #ifdef CONFIG_COMPAT
  863. .compat_ioctl = i915_compat_ioctl,
  864. #endif
  865. .llseek = noop_llseek,
  866. };
  867. static struct drm_driver driver = {
  868. /* Don't use MTRRs here; the Xserver or userspace app should
  869. * deal with them for Intel hardware.
  870. */
  871. .driver_features =
  872. DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
  873. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
  874. .load = i915_driver_load,
  875. .unload = i915_driver_unload,
  876. .open = i915_driver_open,
  877. .lastclose = i915_driver_lastclose,
  878. .preclose = i915_driver_preclose,
  879. .postclose = i915_driver_postclose,
  880. /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
  881. .suspend = i915_suspend,
  882. .resume = i915_resume,
  883. .device_is_agp = i915_driver_device_is_agp,
  884. .master_create = i915_master_create,
  885. .master_destroy = i915_master_destroy,
  886. #if defined(CONFIG_DEBUG_FS)
  887. .debugfs_init = i915_debugfs_init,
  888. .debugfs_cleanup = i915_debugfs_cleanup,
  889. #endif
  890. .gem_init_object = i915_gem_init_object,
  891. .gem_free_object = i915_gem_free_object,
  892. .gem_vm_ops = &i915_gem_vm_ops,
  893. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  894. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  895. .gem_prime_export = i915_gem_prime_export,
  896. .gem_prime_import = i915_gem_prime_import,
  897. .dumb_create = i915_gem_dumb_create,
  898. .dumb_map_offset = i915_gem_mmap_gtt,
  899. .dumb_destroy = i915_gem_dumb_destroy,
  900. .ioctls = i915_ioctls,
  901. .fops = &i915_driver_fops,
  902. .name = DRIVER_NAME,
  903. .desc = DRIVER_DESC,
  904. .date = DRIVER_DATE,
  905. .major = DRIVER_MAJOR,
  906. .minor = DRIVER_MINOR,
  907. .patchlevel = DRIVER_PATCHLEVEL,
  908. };
  909. static struct pci_driver i915_pci_driver = {
  910. .name = DRIVER_NAME,
  911. .id_table = pciidlist,
  912. .probe = i915_pci_probe,
  913. .remove = i915_pci_remove,
  914. .driver.pm = &i915_pm_ops,
  915. };
  916. static int __init i915_init(void)
  917. {
  918. driver.num_ioctls = i915_max_ioctl;
  919. /*
  920. * If CONFIG_DRM_I915_KMS is set, default to KMS unless
  921. * explicitly disabled with the module pararmeter.
  922. *
  923. * Otherwise, just follow the parameter (defaulting to off).
  924. *
  925. * Allow optional vga_text_mode_force boot option to override
  926. * the default behavior.
  927. */
  928. #if defined(CONFIG_DRM_I915_KMS)
  929. if (i915_modeset != 0)
  930. driver.driver_features |= DRIVER_MODESET;
  931. #endif
  932. if (i915_modeset == 1)
  933. driver.driver_features |= DRIVER_MODESET;
  934. #ifdef CONFIG_VGA_CONSOLE
  935. if (vgacon_text_force() && i915_modeset == -1)
  936. driver.driver_features &= ~DRIVER_MODESET;
  937. #endif
  938. if (!(driver.driver_features & DRIVER_MODESET))
  939. driver.get_vblank_timestamp = NULL;
  940. return drm_pci_init(&driver, &i915_pci_driver);
  941. }
  942. static void __exit i915_exit(void)
  943. {
  944. drm_pci_exit(&driver, &i915_pci_driver);
  945. }
  946. module_init(i915_init);
  947. module_exit(i915_exit);
  948. MODULE_AUTHOR(DRIVER_AUTHOR);
  949. MODULE_DESCRIPTION(DRIVER_DESC);
  950. MODULE_LICENSE("GPL and additional rights");
  951. /* We give fast paths for the really cool registers */
  952. #define NEEDS_FORCE_WAKE(dev_priv, reg) \
  953. ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
  954. ((reg) < 0x40000) && \
  955. ((reg) != FORCEWAKE))
  956. static void
  957. ilk_dummy_write(struct drm_i915_private *dev_priv)
  958. {
  959. /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
  960. * chip from rc6 before touching it for real. MI_MODE is masked, hence
  961. * harmless to write 0 into. */
  962. I915_WRITE_NOTRACE(MI_MODE, 0);
  963. }
  964. #define __i915_read(x, y) \
  965. u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
  966. u##x val = 0; \
  967. if (IS_GEN5(dev_priv->dev)) \
  968. ilk_dummy_write(dev_priv); \
  969. if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
  970. unsigned long irqflags; \
  971. spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
  972. if (dev_priv->forcewake_count == 0) \
  973. dev_priv->gt.force_wake_get(dev_priv); \
  974. val = read##y(dev_priv->regs + reg); \
  975. if (dev_priv->forcewake_count == 0) \
  976. dev_priv->gt.force_wake_put(dev_priv); \
  977. spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
  978. } else { \
  979. val = read##y(dev_priv->regs + reg); \
  980. } \
  981. trace_i915_reg_rw(false, reg, val, sizeof(val)); \
  982. return val; \
  983. }
  984. __i915_read(8, b)
  985. __i915_read(16, w)
  986. __i915_read(32, l)
  987. __i915_read(64, q)
  988. #undef __i915_read
  989. #define __i915_write(x, y) \
  990. void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
  991. u32 __fifo_ret = 0; \
  992. trace_i915_reg_rw(true, reg, val, sizeof(val)); \
  993. if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
  994. __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
  995. } \
  996. if (IS_GEN5(dev_priv->dev)) \
  997. ilk_dummy_write(dev_priv); \
  998. if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
  999. DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
  1000. I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
  1001. } \
  1002. write##y(val, dev_priv->regs + reg); \
  1003. if (unlikely(__fifo_ret)) { \
  1004. gen6_gt_check_fifodbg(dev_priv); \
  1005. } \
  1006. if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
  1007. DRM_ERROR("Unclaimed write to %x\n", reg); \
  1008. writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \
  1009. } \
  1010. }
  1011. __i915_write(8, b)
  1012. __i915_write(16, w)
  1013. __i915_write(32, l)
  1014. __i915_write(64, q)
  1015. #undef __i915_write
  1016. static const struct register_whitelist {
  1017. uint64_t offset;
  1018. uint32_t size;
  1019. uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
  1020. } whitelist[] = {
  1021. { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
  1022. };
  1023. int i915_reg_read_ioctl(struct drm_device *dev,
  1024. void *data, struct drm_file *file)
  1025. {
  1026. struct drm_i915_private *dev_priv = dev->dev_private;
  1027. struct drm_i915_reg_read *reg = data;
  1028. struct register_whitelist const *entry = whitelist;
  1029. int i;
  1030. for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
  1031. if (entry->offset == reg->offset &&
  1032. (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
  1033. break;
  1034. }
  1035. if (i == ARRAY_SIZE(whitelist))
  1036. return -EINVAL;
  1037. switch (entry->size) {
  1038. case 8:
  1039. reg->val = I915_READ64(reg->offset);
  1040. break;
  1041. case 4:
  1042. reg->val = I915_READ(reg->offset);
  1043. break;
  1044. case 2:
  1045. reg->val = I915_READ16(reg->offset);
  1046. break;
  1047. case 1:
  1048. reg->val = I915_READ8(reg->offset);
  1049. break;
  1050. default:
  1051. WARN_ON(1);
  1052. return -EINVAL;
  1053. }
  1054. return 0;
  1055. }