dma-s3c2443.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180
  1. /* linux/arch/arm/mach-s3c2443/dma.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2443 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/io.h>
  19. #include <mach/dma.h>
  20. #include <plat/dma-s3c24xx.h>
  21. #include <plat/cpu.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-gpio.h>
  24. #include <plat/regs-ac97.h>
  25. #include <plat/regs-dma.h>
  26. #include <mach/regs-lcd.h>
  27. #include <plat/regs-iis.h>
  28. #include <plat/regs-spi.h>
  29. #define MAP(x) { \
  30. [0] = (x) | DMA_CH_VALID, \
  31. [1] = (x) | DMA_CH_VALID, \
  32. [2] = (x) | DMA_CH_VALID, \
  33. [3] = (x) | DMA_CH_VALID, \
  34. [4] = (x) | DMA_CH_VALID, \
  35. [5] = (x) | DMA_CH_VALID, \
  36. }
  37. static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
  38. [DMACH_XD0] = {
  39. .name = "xdreq0",
  40. .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
  41. },
  42. [DMACH_XD1] = {
  43. .name = "xdreq1",
  44. .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
  45. },
  46. [DMACH_SDI] = { /* only on S3C2443 */
  47. .name = "sdi",
  48. .channels = MAP(S3C2443_DMAREQSEL_SDI),
  49. },
  50. [DMACH_SPI0_RX] = {
  51. .name = "spi0-rx",
  52. .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
  53. },
  54. [DMACH_SPI0_TX] = {
  55. .name = "spi0-tx",
  56. .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
  57. },
  58. [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
  59. .name = "spi1-rx",
  60. .channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
  61. },
  62. [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
  63. .name = "spi1-tx",
  64. .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
  65. },
  66. [DMACH_UART0] = {
  67. .name = "uart0",
  68. .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
  69. },
  70. [DMACH_UART1] = {
  71. .name = "uart1",
  72. .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
  73. },
  74. [DMACH_UART2] = {
  75. .name = "uart2",
  76. .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
  77. },
  78. [DMACH_UART3] = {
  79. .name = "uart3",
  80. .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
  81. },
  82. [DMACH_UART0_SRC2] = {
  83. .name = "uart0",
  84. .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
  85. },
  86. [DMACH_UART1_SRC2] = {
  87. .name = "uart1",
  88. .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
  89. },
  90. [DMACH_UART2_SRC2] = {
  91. .name = "uart2",
  92. .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
  93. },
  94. [DMACH_UART3_SRC2] = {
  95. .name = "uart3",
  96. .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
  97. },
  98. [DMACH_TIMER] = {
  99. .name = "timer",
  100. .channels = MAP(S3C2443_DMAREQSEL_TIMER),
  101. },
  102. [DMACH_I2S_IN] = {
  103. .name = "i2s-sdi",
  104. .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
  105. },
  106. [DMACH_I2S_OUT] = {
  107. .name = "i2s-sdo",
  108. .channels = MAP(S3C2443_DMAREQSEL_I2STX),
  109. },
  110. [DMACH_PCM_IN] = {
  111. .name = "pcm-in",
  112. .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
  113. },
  114. [DMACH_PCM_OUT] = {
  115. .name = "pcm-out",
  116. .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
  117. },
  118. [DMACH_MIC_IN] = {
  119. .name = "mic-in",
  120. .channels = MAP(S3C2443_DMAREQSEL_MICIN),
  121. },
  122. };
  123. static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
  124. struct s3c24xx_dma_map *map)
  125. {
  126. writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
  127. chan->regs + S3C2443_DMA_DMAREQSEL);
  128. }
  129. static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
  130. .select = s3c2443_dma_select,
  131. .dcon_mask = 0,
  132. .map = s3c2443_dma_mappings,
  133. .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
  134. };
  135. static int __init s3c2443_dma_add(struct device *dev,
  136. struct subsys_interface *sif)
  137. {
  138. s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
  139. return s3c24xx_dma_init_map(&s3c2443_dma_sel);
  140. }
  141. #ifdef CONFIG_CPU_S3C2416
  142. /* S3C2416 DMA contains the same selection table as the S3C2443 */
  143. static struct subsys_interface s3c2416_dma_interface = {
  144. .name = "s3c2416_dma",
  145. .subsys = &s3c2416_subsys,
  146. .add_dev = s3c2443_dma_add,
  147. };
  148. static int __init s3c2416_dma_init(void)
  149. {
  150. return subsys_interface_register(&s3c2416_dma_interface);
  151. }
  152. arch_initcall(s3c2416_dma_init);
  153. #endif
  154. #ifdef CONFIG_CPU_S3C2443
  155. static struct subsys_interface s3c2443_dma_interface = {
  156. .name = "s3c2443_dma",
  157. .subsys = &s3c2443_subsys,
  158. .add_dev = s3c2443_dma_add,
  159. };
  160. static int __init s3c2443_dma_init(void)
  161. {
  162. return subsys_interface_register(&s3c2443_dma_interface);
  163. }
  164. arch_initcall(s3c2443_dma_init);
  165. #endif