platsmp.c 3.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149
  1. /*
  2. * plat smp support for CSR Marco dual-core SMP SoCs
  3. *
  4. * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
  5. *
  6. * Licensed under GPLv2 or later.
  7. */
  8. #include <linux/init.h>
  9. #include <linux/smp.h>
  10. #include <linux/delay.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <asm/page.h>
  14. #include <asm/mach/map.h>
  15. #include <asm/smp_plat.h>
  16. #include <asm/smp_scu.h>
  17. #include <asm/cacheflush.h>
  18. #include <asm/cputype.h>
  19. #include <mach/map.h>
  20. #include "common.h"
  21. static void __iomem *scu_base;
  22. static void __iomem *rsc_base;
  23. static DEFINE_SPINLOCK(boot_lock);
  24. static struct map_desc scu_io_desc __initdata = {
  25. .length = SZ_4K,
  26. .type = MT_DEVICE,
  27. };
  28. void __init sirfsoc_map_scu(void)
  29. {
  30. unsigned long base;
  31. /* Get SCU base */
  32. asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
  33. scu_io_desc.virtual = SIRFSOC_VA(base);
  34. scu_io_desc.pfn = __phys_to_pfn(base);
  35. iotable_init(&scu_io_desc, 1);
  36. scu_base = (void __iomem *)SIRFSOC_VA(base);
  37. }
  38. static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
  39. {
  40. /*
  41. * let the primary processor know we're out of the
  42. * pen, then head off into the C entry point
  43. */
  44. pen_release = -1;
  45. smp_wmb();
  46. /*
  47. * Synchronise with the boot thread.
  48. */
  49. spin_lock(&boot_lock);
  50. spin_unlock(&boot_lock);
  51. }
  52. static struct of_device_id rsc_ids[] = {
  53. { .compatible = "sirf,marco-rsc" },
  54. {},
  55. };
  56. static int __cpuinit sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
  57. {
  58. unsigned long timeout;
  59. struct device_node *np;
  60. np = of_find_matching_node(NULL, rsc_ids);
  61. if (!np)
  62. return -ENODEV;
  63. rsc_base = of_iomap(np, 0);
  64. if (!rsc_base)
  65. return -ENOMEM;
  66. /*
  67. * write the address of secondary startup into the sram register
  68. * at offset 0x2C, then write the magic number 0x3CAF5D62 to the
  69. * RSC register at offset 0x28, which is what boot rom code is
  70. * waiting for. This would wake up the secondary core from WFE
  71. */
  72. #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
  73. __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
  74. rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
  75. #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
  76. __raw_writel(0x3CAF5D62,
  77. rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
  78. /* make sure write buffer is drained */
  79. mb();
  80. spin_lock(&boot_lock);
  81. /*
  82. * The secondary processor is waiting to be released from
  83. * the holding pen - release it, then wait for it to flag
  84. * that it has been released by resetting pen_release.
  85. *
  86. * Note that "pen_release" is the hardware CPU ID, whereas
  87. * "cpu" is Linux's internal ID.
  88. */
  89. pen_release = cpu_logical_map(cpu);
  90. __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  91. outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  92. /*
  93. * Send the secondary CPU SEV, thereby causing the boot monitor to read
  94. * the JUMPADDR and WAKEMAGIC, and branch to the address found there.
  95. */
  96. dsb_sev();
  97. timeout = jiffies + (1 * HZ);
  98. while (time_before(jiffies, timeout)) {
  99. smp_rmb();
  100. if (pen_release == -1)
  101. break;
  102. udelay(10);
  103. }
  104. /*
  105. * now the secondary core is starting up let it run its
  106. * calibrations, then wait for it to finish
  107. */
  108. spin_unlock(&boot_lock);
  109. return pen_release != -1 ? -ENOSYS : 0;
  110. }
  111. static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
  112. {
  113. scu_enable(scu_base);
  114. }
  115. struct smp_operations sirfsoc_smp_ops __initdata = {
  116. .smp_prepare_cpus = sirfsoc_smp_prepare_cpus,
  117. .smp_secondary_init = sirfsoc_secondary_init,
  118. .smp_boot_secondary = sirfsoc_boot_secondary,
  119. #ifdef CONFIG_HOTPLUG_CPU
  120. .cpu_die = sirfsoc_cpu_die,
  121. #endif
  122. };