ql4_mbx.c 58 KB

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  1. /*
  2. * QLogic iSCSI HBA Driver
  3. * Copyright (c) 2003-2012 QLogic Corporation
  4. *
  5. * See LICENSE.qla4xxx for copyright and licensing details.
  6. */
  7. #include "ql4_def.h"
  8. #include "ql4_glbl.h"
  9. #include "ql4_dbg.h"
  10. #include "ql4_inline.h"
  11. #include "ql4_version.h"
  12. void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
  13. int in_count)
  14. {
  15. int i;
  16. /* Load all mailbox registers, except mailbox 0. */
  17. for (i = 1; i < in_count; i++)
  18. writel(mbx_cmd[i], &ha->reg->mailbox[i]);
  19. /* Wakeup firmware */
  20. writel(mbx_cmd[0], &ha->reg->mailbox[0]);
  21. readl(&ha->reg->mailbox[0]);
  22. writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
  23. readl(&ha->reg->ctrl_status);
  24. }
  25. void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
  26. {
  27. int intr_status;
  28. intr_status = readl(&ha->reg->ctrl_status);
  29. if (intr_status & INTR_PENDING) {
  30. /*
  31. * Service the interrupt.
  32. * The ISR will save the mailbox status registers
  33. * to a temporary storage location in the adapter structure.
  34. */
  35. ha->mbox_status_count = out_count;
  36. ha->isp_ops->interrupt_service_routine(ha, intr_status);
  37. }
  38. }
  39. /**
  40. * qla4xxx_mailbox_command - issues mailbox commands
  41. * @ha: Pointer to host adapter structure.
  42. * @inCount: number of mailbox registers to load.
  43. * @outCount: number of mailbox registers to return.
  44. * @mbx_cmd: data pointer for mailbox in registers.
  45. * @mbx_sts: data pointer for mailbox out registers.
  46. *
  47. * This routine issue mailbox commands and waits for completion.
  48. * If outCount is 0, this routine completes successfully WITHOUT waiting
  49. * for the mailbox command to complete.
  50. **/
  51. int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
  52. uint8_t outCount, uint32_t *mbx_cmd,
  53. uint32_t *mbx_sts)
  54. {
  55. int status = QLA_ERROR;
  56. uint8_t i;
  57. u_long wait_count;
  58. unsigned long flags = 0;
  59. uint32_t dev_state;
  60. /* Make sure that pointers are valid */
  61. if (!mbx_cmd || !mbx_sts) {
  62. DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
  63. "pointer\n", ha->host_no, __func__));
  64. return status;
  65. }
  66. if (is_qla40XX(ha)) {
  67. if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
  68. DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
  69. "prematurely completing mbx cmd as "
  70. "adapter removal detected\n",
  71. ha->host_no, __func__));
  72. return status;
  73. }
  74. }
  75. if ((is_aer_supported(ha)) &&
  76. (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
  77. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
  78. "timeout MBX Exiting.\n", ha->host_no, __func__));
  79. return status;
  80. }
  81. /* Mailbox code active */
  82. wait_count = MBOX_TOV * 100;
  83. while (wait_count--) {
  84. mutex_lock(&ha->mbox_sem);
  85. if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  86. set_bit(AF_MBOX_COMMAND, &ha->flags);
  87. mutex_unlock(&ha->mbox_sem);
  88. break;
  89. }
  90. mutex_unlock(&ha->mbox_sem);
  91. if (!wait_count) {
  92. DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
  93. ha->host_no, __func__));
  94. return status;
  95. }
  96. msleep(10);
  97. }
  98. if (is_qla80XX(ha)) {
  99. if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
  100. DEBUG2(ql4_printk(KERN_WARNING, ha,
  101. "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
  102. ha->host_no, __func__));
  103. goto mbox_exit;
  104. }
  105. /* Do not send any mbx cmd if h/w is in failed state*/
  106. ha->isp_ops->idc_lock(ha);
  107. dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
  108. ha->isp_ops->idc_unlock(ha);
  109. if (dev_state == QLA8XXX_DEV_FAILED) {
  110. ql4_printk(KERN_WARNING, ha,
  111. "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
  112. ha->host_no, __func__);
  113. goto mbox_exit;
  114. }
  115. }
  116. spin_lock_irqsave(&ha->hardware_lock, flags);
  117. ha->mbox_status_count = outCount;
  118. for (i = 0; i < outCount; i++)
  119. ha->mbox_status[i] = 0;
  120. /* Queue the mailbox command to the firmware */
  121. ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
  122. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  123. /* Wait for completion */
  124. /*
  125. * If we don't want status, don't wait for the mailbox command to
  126. * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
  127. * you must poll the inbound Interrupt Mask for completion.
  128. */
  129. if (outCount == 0) {
  130. status = QLA_SUCCESS;
  131. goto mbox_exit;
  132. }
  133. /*
  134. * Wait for completion: Poll or completion queue
  135. */
  136. if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
  137. test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
  138. test_bit(AF_ONLINE, &ha->flags) &&
  139. !test_bit(AF_HA_REMOVAL, &ha->flags)) {
  140. /* Do not poll for completion. Use completion queue */
  141. set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  142. wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
  143. clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
  144. } else {
  145. /* Poll for command to complete */
  146. wait_count = jiffies + MBOX_TOV * HZ;
  147. while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
  148. if (time_after_eq(jiffies, wait_count))
  149. break;
  150. /*
  151. * Service the interrupt.
  152. * The ISR will save the mailbox status registers
  153. * to a temporary storage location in the adapter
  154. * structure.
  155. */
  156. spin_lock_irqsave(&ha->hardware_lock, flags);
  157. ha->isp_ops->process_mailbox_interrupt(ha, outCount);
  158. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  159. msleep(10);
  160. }
  161. }
  162. /* Check for mailbox timeout. */
  163. if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
  164. if (is_qla80XX(ha) &&
  165. test_bit(AF_FW_RECOVERY, &ha->flags)) {
  166. DEBUG2(ql4_printk(KERN_INFO, ha,
  167. "scsi%ld: %s: prematurely completing mbx cmd as "
  168. "firmware recovery detected\n",
  169. ha->host_no, __func__));
  170. goto mbox_exit;
  171. }
  172. DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
  173. " Scheduling Adapter Reset\n", ha->host_no,
  174. mbx_cmd[0]));
  175. ha->mailbox_timeout_count++;
  176. mbx_sts[0] = (-1);
  177. set_bit(DPC_RESET_HA, &ha->dpc_flags);
  178. if (is_qla8022(ha)) {
  179. ql4_printk(KERN_INFO, ha,
  180. "disabling pause transmit on port 0 & 1.\n");
  181. qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
  182. CRB_NIU_XG_PAUSE_CTL_P0 |
  183. CRB_NIU_XG_PAUSE_CTL_P1);
  184. }
  185. goto mbox_exit;
  186. }
  187. /*
  188. * Copy the mailbox out registers to the caller's mailbox in/out
  189. * structure.
  190. */
  191. spin_lock_irqsave(&ha->hardware_lock, flags);
  192. for (i = 0; i < outCount; i++)
  193. mbx_sts[i] = ha->mbox_status[i];
  194. /* Set return status and error flags (if applicable). */
  195. switch (ha->mbox_status[0]) {
  196. case MBOX_STS_COMMAND_COMPLETE:
  197. status = QLA_SUCCESS;
  198. break;
  199. case MBOX_STS_INTERMEDIATE_COMPLETION:
  200. status = QLA_SUCCESS;
  201. break;
  202. case MBOX_STS_BUSY:
  203. DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
  204. ha->host_no, __func__, mbx_cmd[0]));
  205. ha->mailbox_timeout_count++;
  206. break;
  207. default:
  208. DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
  209. "sts = %08X ****\n", ha->host_no, __func__,
  210. mbx_cmd[0], mbx_sts[0]));
  211. break;
  212. }
  213. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  214. mbox_exit:
  215. mutex_lock(&ha->mbox_sem);
  216. clear_bit(AF_MBOX_COMMAND, &ha->flags);
  217. mutex_unlock(&ha->mbox_sem);
  218. clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  219. return status;
  220. }
  221. /**
  222. * qla4xxx_get_minidump_template - Get the firmware template
  223. * @ha: Pointer to host adapter structure.
  224. * @phys_addr: dma address for template
  225. *
  226. * Obtain the minidump template from firmware during initialization
  227. * as it may not be available when minidump is desired.
  228. **/
  229. int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
  230. dma_addr_t phys_addr)
  231. {
  232. uint32_t mbox_cmd[MBOX_REG_COUNT];
  233. uint32_t mbox_sts[MBOX_REG_COUNT];
  234. int status;
  235. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  236. memset(&mbox_sts, 0, sizeof(mbox_sts));
  237. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  238. mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
  239. mbox_cmd[2] = LSDW(phys_addr);
  240. mbox_cmd[3] = MSDW(phys_addr);
  241. mbox_cmd[4] = ha->fw_dump_tmplt_size;
  242. mbox_cmd[5] = 0;
  243. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  244. &mbox_sts[0]);
  245. if (status != QLA_SUCCESS) {
  246. DEBUG2(ql4_printk(KERN_INFO, ha,
  247. "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
  248. ha->host_no, __func__, mbox_cmd[0],
  249. mbox_sts[0], mbox_sts[1]));
  250. }
  251. return status;
  252. }
  253. /**
  254. * qla4xxx_req_template_size - Get minidump template size from firmware.
  255. * @ha: Pointer to host adapter structure.
  256. **/
  257. int qla4xxx_req_template_size(struct scsi_qla_host *ha)
  258. {
  259. uint32_t mbox_cmd[MBOX_REG_COUNT];
  260. uint32_t mbox_sts[MBOX_REG_COUNT];
  261. int status;
  262. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  263. memset(&mbox_sts, 0, sizeof(mbox_sts));
  264. mbox_cmd[0] = MBOX_CMD_MINIDUMP;
  265. mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
  266. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
  267. &mbox_sts[0]);
  268. if (status == QLA_SUCCESS) {
  269. ha->fw_dump_tmplt_size = mbox_sts[1];
  270. DEBUG2(ql4_printk(KERN_INFO, ha,
  271. "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
  272. __func__, mbox_sts[0], mbox_sts[1],
  273. mbox_sts[2], mbox_sts[3], mbox_sts[4],
  274. mbox_sts[5], mbox_sts[6], mbox_sts[7]));
  275. if (ha->fw_dump_tmplt_size == 0)
  276. status = QLA_ERROR;
  277. } else {
  278. ql4_printk(KERN_WARNING, ha,
  279. "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
  280. __func__, mbox_sts[0], mbox_sts[1]);
  281. status = QLA_ERROR;
  282. }
  283. return status;
  284. }
  285. void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
  286. {
  287. set_bit(AF_FW_RECOVERY, &ha->flags);
  288. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
  289. ha->host_no, __func__);
  290. if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
  291. if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
  292. complete(&ha->mbx_intr_comp);
  293. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  294. "recovery, doing premature completion of "
  295. "mbx cmd\n", ha->host_no, __func__);
  296. } else {
  297. set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
  298. ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
  299. "recovery, doing premature completion of "
  300. "polling mbx cmd\n", ha->host_no, __func__);
  301. }
  302. }
  303. }
  304. static uint8_t
  305. qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  306. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  307. {
  308. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  309. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  310. if (is_qla8022(ha))
  311. qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
  312. mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
  313. mbox_cmd[1] = 0;
  314. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  315. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  316. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  317. mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
  318. if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
  319. QLA_SUCCESS) {
  320. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  321. "MBOX_CMD_INITIALIZE_FIRMWARE"
  322. " failed w/ status %04X\n",
  323. ha->host_no, __func__, mbox_sts[0]));
  324. return QLA_ERROR;
  325. }
  326. return QLA_SUCCESS;
  327. }
  328. uint8_t
  329. qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  330. uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
  331. {
  332. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  333. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  334. mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
  335. mbox_cmd[2] = LSDW(init_fw_cb_dma);
  336. mbox_cmd[3] = MSDW(init_fw_cb_dma);
  337. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  338. if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
  339. QLA_SUCCESS) {
  340. DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
  341. "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
  342. " failed w/ status %04X\n",
  343. ha->host_no, __func__, mbox_sts[0]));
  344. return QLA_ERROR;
  345. }
  346. return QLA_SUCCESS;
  347. }
  348. static void
  349. qla4xxx_update_local_ip(struct scsi_qla_host *ha,
  350. struct addr_ctrl_blk *init_fw_cb)
  351. {
  352. ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
  353. ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
  354. ha->ip_config.ipv4_addr_state =
  355. le16_to_cpu(init_fw_cb->ipv4_addr_state);
  356. ha->ip_config.eth_mtu_size =
  357. le16_to_cpu(init_fw_cb->eth_mtu_size);
  358. ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
  359. if (ha->acb_version == ACB_SUPPORTED) {
  360. ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
  361. ha->ip_config.ipv6_addl_options =
  362. le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
  363. }
  364. /* Save IPv4 Address Info */
  365. memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
  366. min(sizeof(ha->ip_config.ip_address),
  367. sizeof(init_fw_cb->ipv4_addr)));
  368. memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
  369. min(sizeof(ha->ip_config.subnet_mask),
  370. sizeof(init_fw_cb->ipv4_subnet)));
  371. memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
  372. min(sizeof(ha->ip_config.gateway),
  373. sizeof(init_fw_cb->ipv4_gw_addr)));
  374. ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
  375. if (is_ipv6_enabled(ha)) {
  376. /* Save IPv6 Address */
  377. ha->ip_config.ipv6_link_local_state =
  378. le16_to_cpu(init_fw_cb->ipv6_lnk_lcl_addr_state);
  379. ha->ip_config.ipv6_addr0_state =
  380. le16_to_cpu(init_fw_cb->ipv6_addr0_state);
  381. ha->ip_config.ipv6_addr1_state =
  382. le16_to_cpu(init_fw_cb->ipv6_addr1_state);
  383. ha->ip_config.ipv6_default_router_state =
  384. le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state);
  385. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
  386. ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
  387. memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
  388. init_fw_cb->ipv6_if_id,
  389. min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
  390. sizeof(init_fw_cb->ipv6_if_id)));
  391. memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
  392. min(sizeof(ha->ip_config.ipv6_addr0),
  393. sizeof(init_fw_cb->ipv6_addr0)));
  394. memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
  395. min(sizeof(ha->ip_config.ipv6_addr1),
  396. sizeof(init_fw_cb->ipv6_addr1)));
  397. memcpy(&ha->ip_config.ipv6_default_router_addr,
  398. init_fw_cb->ipv6_dflt_rtr_addr,
  399. min(sizeof(ha->ip_config.ipv6_default_router_addr),
  400. sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
  401. ha->ip_config.ipv6_vlan_tag =
  402. be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
  403. ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
  404. }
  405. }
  406. uint8_t
  407. qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
  408. uint32_t *mbox_cmd,
  409. uint32_t *mbox_sts,
  410. struct addr_ctrl_blk *init_fw_cb,
  411. dma_addr_t init_fw_cb_dma)
  412. {
  413. if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
  414. != QLA_SUCCESS) {
  415. DEBUG2(printk(KERN_WARNING
  416. "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  417. ha->host_no, __func__));
  418. return QLA_ERROR;
  419. }
  420. DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
  421. /* Save some info in adapter structure. */
  422. ha->acb_version = init_fw_cb->acb_version;
  423. ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
  424. ha->heartbeat_interval = init_fw_cb->hb_interval;
  425. memcpy(ha->name_string, init_fw_cb->iscsi_name,
  426. min(sizeof(ha->name_string),
  427. sizeof(init_fw_cb->iscsi_name)));
  428. ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
  429. /*memcpy(ha->alias, init_fw_cb->Alias,
  430. min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
  431. qla4xxx_update_local_ip(ha, init_fw_cb);
  432. return QLA_SUCCESS;
  433. }
  434. /**
  435. * qla4xxx_initialize_fw_cb - initializes firmware control block.
  436. * @ha: Pointer to host adapter structure.
  437. **/
  438. int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
  439. {
  440. struct addr_ctrl_blk *init_fw_cb;
  441. dma_addr_t init_fw_cb_dma;
  442. uint32_t mbox_cmd[MBOX_REG_COUNT];
  443. uint32_t mbox_sts[MBOX_REG_COUNT];
  444. int status = QLA_ERROR;
  445. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  446. sizeof(struct addr_ctrl_blk),
  447. &init_fw_cb_dma, GFP_KERNEL);
  448. if (init_fw_cb == NULL) {
  449. DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
  450. ha->host_no, __func__));
  451. goto exit_init_fw_cb_no_free;
  452. }
  453. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  454. /* Get Initialize Firmware Control Block. */
  455. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  456. memset(&mbox_sts, 0, sizeof(mbox_sts));
  457. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  458. QLA_SUCCESS) {
  459. dma_free_coherent(&ha->pdev->dev,
  460. sizeof(struct addr_ctrl_blk),
  461. init_fw_cb, init_fw_cb_dma);
  462. goto exit_init_fw_cb;
  463. }
  464. /* Initialize request and response queues. */
  465. qla4xxx_init_rings(ha);
  466. /* Fill in the request and response queue information. */
  467. init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
  468. init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
  469. init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
  470. init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
  471. init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
  472. init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
  473. init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
  474. init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
  475. init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
  476. init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
  477. /* Set up required options. */
  478. init_fw_cb->fw_options |=
  479. __constant_cpu_to_le16(FWOPT_SESSION_MODE |
  480. FWOPT_INITIATOR_MODE);
  481. if (is_qla80XX(ha))
  482. init_fw_cb->fw_options |=
  483. __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
  484. init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
  485. init_fw_cb->add_fw_options = 0;
  486. init_fw_cb->add_fw_options |=
  487. __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
  488. init_fw_cb->add_fw_options |=
  489. __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
  490. if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
  491. != QLA_SUCCESS) {
  492. DEBUG2(printk(KERN_WARNING
  493. "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
  494. ha->host_no, __func__));
  495. goto exit_init_fw_cb;
  496. }
  497. if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
  498. init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
  499. DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
  500. ha->host_no, __func__));
  501. goto exit_init_fw_cb;
  502. }
  503. status = QLA_SUCCESS;
  504. exit_init_fw_cb:
  505. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  506. init_fw_cb, init_fw_cb_dma);
  507. exit_init_fw_cb_no_free:
  508. return status;
  509. }
  510. /**
  511. * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
  512. * @ha: Pointer to host adapter structure.
  513. **/
  514. int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
  515. {
  516. struct addr_ctrl_blk *init_fw_cb;
  517. dma_addr_t init_fw_cb_dma;
  518. uint32_t mbox_cmd[MBOX_REG_COUNT];
  519. uint32_t mbox_sts[MBOX_REG_COUNT];
  520. init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
  521. sizeof(struct addr_ctrl_blk),
  522. &init_fw_cb_dma, GFP_KERNEL);
  523. if (init_fw_cb == NULL) {
  524. printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
  525. __func__);
  526. return QLA_ERROR;
  527. }
  528. /* Get Initialize Firmware Control Block. */
  529. memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
  530. if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
  531. QLA_SUCCESS) {
  532. DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
  533. ha->host_no, __func__));
  534. dma_free_coherent(&ha->pdev->dev,
  535. sizeof(struct addr_ctrl_blk),
  536. init_fw_cb, init_fw_cb_dma);
  537. return QLA_ERROR;
  538. }
  539. /* Save IP Address. */
  540. qla4xxx_update_local_ip(ha, init_fw_cb);
  541. dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
  542. init_fw_cb, init_fw_cb_dma);
  543. return QLA_SUCCESS;
  544. }
  545. /**
  546. * qla4xxx_get_firmware_state - gets firmware state of HBA
  547. * @ha: Pointer to host adapter structure.
  548. **/
  549. int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
  550. {
  551. uint32_t mbox_cmd[MBOX_REG_COUNT];
  552. uint32_t mbox_sts[MBOX_REG_COUNT];
  553. /* Get firmware version */
  554. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  555. memset(&mbox_sts, 0, sizeof(mbox_sts));
  556. mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
  557. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
  558. QLA_SUCCESS) {
  559. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
  560. "status %04X\n", ha->host_no, __func__,
  561. mbox_sts[0]));
  562. return QLA_ERROR;
  563. }
  564. ha->firmware_state = mbox_sts[1];
  565. ha->board_id = mbox_sts[2];
  566. ha->addl_fw_state = mbox_sts[3];
  567. DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
  568. ha->host_no, __func__, ha->firmware_state);)
  569. return QLA_SUCCESS;
  570. }
  571. /**
  572. * qla4xxx_get_firmware_status - retrieves firmware status
  573. * @ha: Pointer to host adapter structure.
  574. **/
  575. int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
  576. {
  577. uint32_t mbox_cmd[MBOX_REG_COUNT];
  578. uint32_t mbox_sts[MBOX_REG_COUNT];
  579. /* Get firmware version */
  580. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  581. memset(&mbox_sts, 0, sizeof(mbox_sts));
  582. mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
  583. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
  584. QLA_SUCCESS) {
  585. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
  586. "status %04X\n", ha->host_no, __func__,
  587. mbox_sts[0]));
  588. return QLA_ERROR;
  589. }
  590. ql4_printk(KERN_INFO, ha, "%ld firmware IOCBs available (%d).\n",
  591. ha->host_no, mbox_sts[2]);
  592. return QLA_SUCCESS;
  593. }
  594. /**
  595. * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
  596. * @ha: Pointer to host adapter structure.
  597. * @fw_ddb_index: Firmware's device database index
  598. * @fw_ddb_entry: Pointer to firmware's device database entry structure
  599. * @num_valid_ddb_entries: Pointer to number of valid ddb entries
  600. * @next_ddb_index: Pointer to next valid device database index
  601. * @fw_ddb_device_state: Pointer to device state
  602. **/
  603. int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
  604. uint16_t fw_ddb_index,
  605. struct dev_db_entry *fw_ddb_entry,
  606. dma_addr_t fw_ddb_entry_dma,
  607. uint32_t *num_valid_ddb_entries,
  608. uint32_t *next_ddb_index,
  609. uint32_t *fw_ddb_device_state,
  610. uint32_t *conn_err_detail,
  611. uint16_t *tcp_source_port_num,
  612. uint16_t *connection_id)
  613. {
  614. int status = QLA_ERROR;
  615. uint16_t options;
  616. uint32_t mbox_cmd[MBOX_REG_COUNT];
  617. uint32_t mbox_sts[MBOX_REG_COUNT];
  618. /* Make sure the device index is valid */
  619. if (fw_ddb_index >= MAX_DDB_ENTRIES) {
  620. DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
  621. ha->host_no, __func__, fw_ddb_index));
  622. goto exit_get_fwddb;
  623. }
  624. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  625. memset(&mbox_sts, 0, sizeof(mbox_sts));
  626. if (fw_ddb_entry)
  627. memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
  628. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
  629. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  630. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  631. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  632. mbox_cmd[4] = sizeof(struct dev_db_entry);
  633. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
  634. QLA_ERROR) {
  635. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
  636. " with status 0x%04X\n", ha->host_no, __func__,
  637. mbox_sts[0]));
  638. goto exit_get_fwddb;
  639. }
  640. if (fw_ddb_index != mbox_sts[1]) {
  641. DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
  642. ha->host_no, __func__, fw_ddb_index,
  643. mbox_sts[1]));
  644. goto exit_get_fwddb;
  645. }
  646. if (fw_ddb_entry) {
  647. options = le16_to_cpu(fw_ddb_entry->options);
  648. if (options & DDB_OPT_IPV6_DEVICE) {
  649. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  650. "Next %d State %04x ConnErr %08x %pI6 "
  651. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  652. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  653. mbox_sts[4], mbox_sts[5],
  654. fw_ddb_entry->ip_addr,
  655. le16_to_cpu(fw_ddb_entry->port),
  656. fw_ddb_entry->iscsi_name);
  657. } else {
  658. ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
  659. "Next %d State %04x ConnErr %08x %pI4 "
  660. ":%04d \"%s\"\n", __func__, fw_ddb_index,
  661. mbox_sts[0], mbox_sts[2], mbox_sts[3],
  662. mbox_sts[4], mbox_sts[5],
  663. fw_ddb_entry->ip_addr,
  664. le16_to_cpu(fw_ddb_entry->port),
  665. fw_ddb_entry->iscsi_name);
  666. }
  667. }
  668. if (num_valid_ddb_entries)
  669. *num_valid_ddb_entries = mbox_sts[2];
  670. if (next_ddb_index)
  671. *next_ddb_index = mbox_sts[3];
  672. if (fw_ddb_device_state)
  673. *fw_ddb_device_state = mbox_sts[4];
  674. /*
  675. * RA: This mailbox has been changed to pass connection error and
  676. * details. Its true for ISP4010 as per Version E - Not sure when it
  677. * was changed. Get the time2wait from the fw_dd_entry field :
  678. * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
  679. * struct.
  680. */
  681. if (conn_err_detail)
  682. *conn_err_detail = mbox_sts[5];
  683. if (tcp_source_port_num)
  684. *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
  685. if (connection_id)
  686. *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
  687. status = QLA_SUCCESS;
  688. exit_get_fwddb:
  689. return status;
  690. }
  691. int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
  692. {
  693. uint32_t mbox_cmd[MBOX_REG_COUNT];
  694. uint32_t mbox_sts[MBOX_REG_COUNT];
  695. int status;
  696. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  697. memset(&mbox_sts, 0, sizeof(mbox_sts));
  698. mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
  699. mbox_cmd[1] = fw_ddb_index;
  700. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  701. &mbox_sts[0]);
  702. DEBUG2(ql4_printk(KERN_INFO, ha,
  703. "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
  704. __func__, status, mbox_sts[0], mbox_sts[1]));
  705. return status;
  706. }
  707. /**
  708. * qla4xxx_set_fwddb_entry - sets a ddb entry.
  709. * @ha: Pointer to host adapter structure.
  710. * @fw_ddb_index: Firmware's device database index
  711. * @fw_ddb_entry_dma: dma address of ddb entry
  712. * @mbx_sts: mailbox 0 to be returned or NULL
  713. *
  714. * This routine initializes or updates the adapter's device database
  715. * entry for the specified device.
  716. **/
  717. int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
  718. dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
  719. {
  720. uint32_t mbox_cmd[MBOX_REG_COUNT];
  721. uint32_t mbox_sts[MBOX_REG_COUNT];
  722. int status;
  723. /* Do not wait for completion. The firmware will send us an
  724. * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
  725. */
  726. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  727. memset(&mbox_sts, 0, sizeof(mbox_sts));
  728. mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
  729. mbox_cmd[1] = (uint32_t) fw_ddb_index;
  730. mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
  731. mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
  732. mbox_cmd[4] = sizeof(struct dev_db_entry);
  733. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  734. &mbox_sts[0]);
  735. if (mbx_sts)
  736. *mbx_sts = mbox_sts[0];
  737. DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
  738. ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
  739. return status;
  740. }
  741. int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
  742. struct ddb_entry *ddb_entry, int options)
  743. {
  744. int status;
  745. uint32_t mbox_cmd[MBOX_REG_COUNT];
  746. uint32_t mbox_sts[MBOX_REG_COUNT];
  747. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  748. memset(&mbox_sts, 0, sizeof(mbox_sts));
  749. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  750. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  751. mbox_cmd[3] = options;
  752. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
  753. &mbox_sts[0]);
  754. if (status != QLA_SUCCESS) {
  755. DEBUG2(ql4_printk(KERN_INFO, ha,
  756. "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
  757. "failed sts %04X %04X", __func__,
  758. mbox_sts[0], mbox_sts[1]));
  759. }
  760. return status;
  761. }
  762. /**
  763. * qla4xxx_get_crash_record - retrieves crash record.
  764. * @ha: Pointer to host adapter structure.
  765. *
  766. * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
  767. **/
  768. void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
  769. {
  770. uint32_t mbox_cmd[MBOX_REG_COUNT];
  771. uint32_t mbox_sts[MBOX_REG_COUNT];
  772. struct crash_record *crash_record = NULL;
  773. dma_addr_t crash_record_dma = 0;
  774. uint32_t crash_record_size = 0;
  775. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  776. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  777. /* Get size of crash record. */
  778. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  779. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  780. QLA_SUCCESS) {
  781. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
  782. ha->host_no, __func__));
  783. goto exit_get_crash_record;
  784. }
  785. crash_record_size = mbox_sts[4];
  786. if (crash_record_size == 0) {
  787. DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
  788. ha->host_no, __func__));
  789. goto exit_get_crash_record;
  790. }
  791. /* Alloc Memory for Crash Record. */
  792. crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
  793. &crash_record_dma, GFP_KERNEL);
  794. if (crash_record == NULL)
  795. goto exit_get_crash_record;
  796. /* Get Crash Record. */
  797. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  798. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  799. mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
  800. mbox_cmd[2] = LSDW(crash_record_dma);
  801. mbox_cmd[3] = MSDW(crash_record_dma);
  802. mbox_cmd[4] = crash_record_size;
  803. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  804. QLA_SUCCESS)
  805. goto exit_get_crash_record;
  806. /* Dump Crash Record. */
  807. exit_get_crash_record:
  808. if (crash_record)
  809. dma_free_coherent(&ha->pdev->dev, crash_record_size,
  810. crash_record, crash_record_dma);
  811. }
  812. /**
  813. * qla4xxx_get_conn_event_log - retrieves connection event log
  814. * @ha: Pointer to host adapter structure.
  815. **/
  816. void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
  817. {
  818. uint32_t mbox_cmd[MBOX_REG_COUNT];
  819. uint32_t mbox_sts[MBOX_REG_COUNT];
  820. struct conn_event_log_entry *event_log = NULL;
  821. dma_addr_t event_log_dma = 0;
  822. uint32_t event_log_size = 0;
  823. uint32_t num_valid_entries;
  824. uint32_t oldest_entry = 0;
  825. uint32_t max_event_log_entries;
  826. uint8_t i;
  827. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  828. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  829. /* Get size of crash record. */
  830. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  831. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  832. QLA_SUCCESS)
  833. goto exit_get_event_log;
  834. event_log_size = mbox_sts[4];
  835. if (event_log_size == 0)
  836. goto exit_get_event_log;
  837. /* Alloc Memory for Crash Record. */
  838. event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
  839. &event_log_dma, GFP_KERNEL);
  840. if (event_log == NULL)
  841. goto exit_get_event_log;
  842. /* Get Crash Record. */
  843. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  844. memset(&mbox_sts, 0, sizeof(mbox_cmd));
  845. mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
  846. mbox_cmd[2] = LSDW(event_log_dma);
  847. mbox_cmd[3] = MSDW(event_log_dma);
  848. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
  849. QLA_SUCCESS) {
  850. DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
  851. "log!\n", ha->host_no, __func__));
  852. goto exit_get_event_log;
  853. }
  854. /* Dump Event Log. */
  855. num_valid_entries = mbox_sts[1];
  856. max_event_log_entries = event_log_size /
  857. sizeof(struct conn_event_log_entry);
  858. if (num_valid_entries > max_event_log_entries)
  859. oldest_entry = num_valid_entries % max_event_log_entries;
  860. DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
  861. ha->host_no, num_valid_entries));
  862. if (ql4xextended_error_logging == 3) {
  863. if (oldest_entry == 0) {
  864. /* Circular Buffer has not wrapped around */
  865. for (i=0; i < num_valid_entries; i++) {
  866. qla4xxx_dump_buffer((uint8_t *)event_log+
  867. (i*sizeof(*event_log)),
  868. sizeof(*event_log));
  869. }
  870. }
  871. else {
  872. /* Circular Buffer has wrapped around -
  873. * display accordingly*/
  874. for (i=oldest_entry; i < max_event_log_entries; i++) {
  875. qla4xxx_dump_buffer((uint8_t *)event_log+
  876. (i*sizeof(*event_log)),
  877. sizeof(*event_log));
  878. }
  879. for (i=0; i < oldest_entry; i++) {
  880. qla4xxx_dump_buffer((uint8_t *)event_log+
  881. (i*sizeof(*event_log)),
  882. sizeof(*event_log));
  883. }
  884. }
  885. }
  886. exit_get_event_log:
  887. if (event_log)
  888. dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
  889. event_log_dma);
  890. }
  891. /**
  892. * qla4xxx_abort_task - issues Abort Task
  893. * @ha: Pointer to host adapter structure.
  894. * @srb: Pointer to srb entry
  895. *
  896. * This routine performs a LUN RESET on the specified target/lun.
  897. * The caller must ensure that the ddb_entry and lun_entry pointers
  898. * are valid before calling this routine.
  899. **/
  900. int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
  901. {
  902. uint32_t mbox_cmd[MBOX_REG_COUNT];
  903. uint32_t mbox_sts[MBOX_REG_COUNT];
  904. struct scsi_cmnd *cmd = srb->cmd;
  905. int status = QLA_SUCCESS;
  906. unsigned long flags = 0;
  907. uint32_t index;
  908. /*
  909. * Send abort task command to ISP, so that the ISP will return
  910. * request with ABORT status
  911. */
  912. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  913. memset(&mbox_sts, 0, sizeof(mbox_sts));
  914. spin_lock_irqsave(&ha->hardware_lock, flags);
  915. index = (unsigned long)(unsigned char *)cmd->host_scribble;
  916. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  917. /* Firmware already posted completion on response queue */
  918. if (index == MAX_SRBS)
  919. return status;
  920. mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
  921. mbox_cmd[1] = srb->ddb->fw_ddb_index;
  922. mbox_cmd[2] = index;
  923. /* Immediate Command Enable */
  924. mbox_cmd[5] = 0x01;
  925. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
  926. &mbox_sts[0]);
  927. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
  928. status = QLA_ERROR;
  929. DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
  930. "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
  931. ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
  932. mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
  933. }
  934. return status;
  935. }
  936. /**
  937. * qla4xxx_reset_lun - issues LUN Reset
  938. * @ha: Pointer to host adapter structure.
  939. * @ddb_entry: Pointer to device database entry
  940. * @lun: lun number
  941. *
  942. * This routine performs a LUN RESET on the specified target/lun.
  943. * The caller must ensure that the ddb_entry and lun_entry pointers
  944. * are valid before calling this routine.
  945. **/
  946. int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
  947. int lun)
  948. {
  949. uint32_t mbox_cmd[MBOX_REG_COUNT];
  950. uint32_t mbox_sts[MBOX_REG_COUNT];
  951. int status = QLA_SUCCESS;
  952. DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
  953. ddb_entry->fw_ddb_index, lun));
  954. /*
  955. * Send lun reset command to ISP, so that the ISP will return all
  956. * outstanding requests with RESET status
  957. */
  958. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  959. memset(&mbox_sts, 0, sizeof(mbox_sts));
  960. mbox_cmd[0] = MBOX_CMD_LUN_RESET;
  961. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  962. mbox_cmd[2] = lun << 8;
  963. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  964. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
  965. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  966. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  967. status = QLA_ERROR;
  968. return status;
  969. }
  970. /**
  971. * qla4xxx_reset_target - issues target Reset
  972. * @ha: Pointer to host adapter structure.
  973. * @db_entry: Pointer to device database entry
  974. * @un_entry: Pointer to lun entry structure
  975. *
  976. * This routine performs a TARGET RESET on the specified target.
  977. * The caller must ensure that the ddb_entry pointers
  978. * are valid before calling this routine.
  979. **/
  980. int qla4xxx_reset_target(struct scsi_qla_host *ha,
  981. struct ddb_entry *ddb_entry)
  982. {
  983. uint32_t mbox_cmd[MBOX_REG_COUNT];
  984. uint32_t mbox_sts[MBOX_REG_COUNT];
  985. int status = QLA_SUCCESS;
  986. DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
  987. ddb_entry->fw_ddb_index));
  988. /*
  989. * Send target reset command to ISP, so that the ISP will return all
  990. * outstanding requests with RESET status
  991. */
  992. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  993. memset(&mbox_sts, 0, sizeof(mbox_sts));
  994. mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
  995. mbox_cmd[1] = ddb_entry->fw_ddb_index;
  996. mbox_cmd[5] = 0x01; /* Immediate Command Enable */
  997. qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  998. &mbox_sts[0]);
  999. if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
  1000. mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
  1001. status = QLA_ERROR;
  1002. return status;
  1003. }
  1004. int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
  1005. uint32_t offset, uint32_t len)
  1006. {
  1007. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1008. uint32_t mbox_sts[MBOX_REG_COUNT];
  1009. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1010. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1011. mbox_cmd[0] = MBOX_CMD_READ_FLASH;
  1012. mbox_cmd[1] = LSDW(dma_addr);
  1013. mbox_cmd[2] = MSDW(dma_addr);
  1014. mbox_cmd[3] = offset;
  1015. mbox_cmd[4] = len;
  1016. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
  1017. QLA_SUCCESS) {
  1018. DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
  1019. "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
  1020. __func__, mbox_sts[0], mbox_sts[1], offset, len));
  1021. return QLA_ERROR;
  1022. }
  1023. return QLA_SUCCESS;
  1024. }
  1025. /**
  1026. * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
  1027. * @ha: Pointer to host adapter structure.
  1028. *
  1029. * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
  1030. * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
  1031. * those mailboxes, if unused.
  1032. **/
  1033. int qla4xxx_about_firmware(struct scsi_qla_host *ha)
  1034. {
  1035. struct about_fw_info *about_fw = NULL;
  1036. dma_addr_t about_fw_dma;
  1037. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1038. uint32_t mbox_sts[MBOX_REG_COUNT];
  1039. int status = QLA_ERROR;
  1040. about_fw = dma_alloc_coherent(&ha->pdev->dev,
  1041. sizeof(struct about_fw_info),
  1042. &about_fw_dma, GFP_KERNEL);
  1043. if (!about_fw) {
  1044. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
  1045. "for about_fw\n", __func__));
  1046. return status;
  1047. }
  1048. memset(about_fw, 0, sizeof(struct about_fw_info));
  1049. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1050. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1051. mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
  1052. mbox_cmd[2] = LSDW(about_fw_dma);
  1053. mbox_cmd[3] = MSDW(about_fw_dma);
  1054. mbox_cmd[4] = sizeof(struct about_fw_info);
  1055. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1056. &mbox_cmd[0], &mbox_sts[0]);
  1057. if (status != QLA_SUCCESS) {
  1058. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
  1059. "failed w/ status %04X\n", __func__,
  1060. mbox_sts[0]));
  1061. goto exit_about_fw;
  1062. }
  1063. /* Save version information. */
  1064. ha->firmware_version[0] = le16_to_cpu(about_fw->fw_major);
  1065. ha->firmware_version[1] = le16_to_cpu(about_fw->fw_minor);
  1066. ha->patch_number = le16_to_cpu(about_fw->fw_patch);
  1067. ha->build_number = le16_to_cpu(about_fw->fw_build);
  1068. ha->iscsi_major = le16_to_cpu(about_fw->iscsi_major);
  1069. ha->iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
  1070. ha->bootload_major = le16_to_cpu(about_fw->bootload_major);
  1071. ha->bootload_minor = le16_to_cpu(about_fw->bootload_minor);
  1072. ha->bootload_patch = le16_to_cpu(about_fw->bootload_patch);
  1073. ha->bootload_build = le16_to_cpu(about_fw->bootload_build);
  1074. status = QLA_SUCCESS;
  1075. exit_about_fw:
  1076. dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
  1077. about_fw, about_fw_dma);
  1078. return status;
  1079. }
  1080. static int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
  1081. dma_addr_t dma_addr)
  1082. {
  1083. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1084. uint32_t mbox_sts[MBOX_REG_COUNT];
  1085. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1086. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1087. mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
  1088. mbox_cmd[1] = options;
  1089. mbox_cmd[2] = LSDW(dma_addr);
  1090. mbox_cmd[3] = MSDW(dma_addr);
  1091. if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
  1092. QLA_SUCCESS) {
  1093. DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
  1094. ha->host_no, __func__, mbox_sts[0]));
  1095. return QLA_ERROR;
  1096. }
  1097. return QLA_SUCCESS;
  1098. }
  1099. int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
  1100. uint32_t *mbx_sts)
  1101. {
  1102. int status;
  1103. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1104. uint32_t mbox_sts[MBOX_REG_COUNT];
  1105. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1106. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1107. mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
  1108. mbox_cmd[1] = ddb_index;
  1109. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1110. &mbox_sts[0]);
  1111. if (status != QLA_SUCCESS) {
  1112. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1113. __func__, mbox_sts[0]));
  1114. }
  1115. *mbx_sts = mbox_sts[0];
  1116. return status;
  1117. }
  1118. int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
  1119. {
  1120. int status;
  1121. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1122. uint32_t mbox_sts[MBOX_REG_COUNT];
  1123. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1124. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1125. mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
  1126. mbox_cmd[1] = ddb_index;
  1127. status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
  1128. &mbox_sts[0]);
  1129. if (status != QLA_SUCCESS) {
  1130. DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1131. __func__, mbox_sts[0]));
  1132. }
  1133. return status;
  1134. }
  1135. int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
  1136. uint32_t offset, uint32_t length, uint32_t options)
  1137. {
  1138. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1139. uint32_t mbox_sts[MBOX_REG_COUNT];
  1140. int status = QLA_SUCCESS;
  1141. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1142. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1143. mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
  1144. mbox_cmd[1] = LSDW(dma_addr);
  1145. mbox_cmd[2] = MSDW(dma_addr);
  1146. mbox_cmd[3] = offset;
  1147. mbox_cmd[4] = length;
  1148. mbox_cmd[5] = options;
  1149. status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
  1150. if (status != QLA_SUCCESS) {
  1151. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
  1152. "failed w/ status %04X, mbx1 %04X\n",
  1153. __func__, mbox_sts[0], mbox_sts[1]));
  1154. }
  1155. return status;
  1156. }
  1157. int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
  1158. struct dev_db_entry *fw_ddb_entry,
  1159. dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
  1160. {
  1161. uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
  1162. uint32_t dev_db_end_offset;
  1163. int status = QLA_ERROR;
  1164. memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
  1165. dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
  1166. dev_db_end_offset = FLASH_OFFSET_DB_END;
  1167. if (dev_db_start_offset > dev_db_end_offset) {
  1168. DEBUG2(ql4_printk(KERN_ERR, ha,
  1169. "%s:Invalid DDB index %d", __func__,
  1170. ddb_index));
  1171. goto exit_bootdb_failed;
  1172. }
  1173. if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
  1174. sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
  1175. ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
  1176. "failed\n", ha->host_no, __func__);
  1177. goto exit_bootdb_failed;
  1178. }
  1179. if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
  1180. status = QLA_SUCCESS;
  1181. exit_bootdb_failed:
  1182. return status;
  1183. }
  1184. int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
  1185. uint16_t idx)
  1186. {
  1187. int ret = 0;
  1188. int rval = QLA_ERROR;
  1189. uint32_t offset = 0, chap_size;
  1190. struct ql4_chap_table *chap_table;
  1191. dma_addr_t chap_dma;
  1192. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1193. if (chap_table == NULL) {
  1194. ret = -ENOMEM;
  1195. goto exit_get_chap;
  1196. }
  1197. chap_size = sizeof(struct ql4_chap_table);
  1198. memset(chap_table, 0, chap_size);
  1199. if (is_qla40XX(ha))
  1200. offset = FLASH_CHAP_OFFSET | (idx * chap_size);
  1201. else {
  1202. offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
  1203. /* flt_chap_size is CHAP table size for both ports
  1204. * so divide it by 2 to calculate the offset for second port
  1205. */
  1206. if (ha->port_num == 1)
  1207. offset += (ha->hw.flt_chap_size / 2);
  1208. offset += (idx * chap_size);
  1209. }
  1210. rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
  1211. if (rval != QLA_SUCCESS) {
  1212. ret = -EINVAL;
  1213. goto exit_get_chap;
  1214. }
  1215. DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
  1216. __le16_to_cpu(chap_table->cookie)));
  1217. if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
  1218. ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
  1219. goto exit_get_chap;
  1220. }
  1221. strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
  1222. strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
  1223. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1224. exit_get_chap:
  1225. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1226. return ret;
  1227. }
  1228. static int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username,
  1229. char *password, uint16_t idx, int bidi)
  1230. {
  1231. int ret = 0;
  1232. int rval = QLA_ERROR;
  1233. uint32_t offset = 0;
  1234. struct ql4_chap_table *chap_table;
  1235. dma_addr_t chap_dma;
  1236. chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
  1237. if (chap_table == NULL) {
  1238. ret = -ENOMEM;
  1239. goto exit_set_chap;
  1240. }
  1241. memset(chap_table, 0, sizeof(struct ql4_chap_table));
  1242. if (bidi)
  1243. chap_table->flags |= BIT_6; /* peer */
  1244. else
  1245. chap_table->flags |= BIT_7; /* local */
  1246. chap_table->secret_len = strlen(password);
  1247. strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
  1248. strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
  1249. chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
  1250. offset = FLASH_CHAP_OFFSET | (idx * sizeof(struct ql4_chap_table));
  1251. rval = qla4xxx_set_flash(ha, chap_dma, offset,
  1252. sizeof(struct ql4_chap_table),
  1253. FLASH_OPT_RMW_COMMIT);
  1254. if (rval == QLA_SUCCESS && ha->chap_list) {
  1255. /* Update ha chap_list cache */
  1256. memcpy((struct ql4_chap_table *)ha->chap_list + idx,
  1257. chap_table, sizeof(struct ql4_chap_table));
  1258. }
  1259. dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
  1260. if (rval != QLA_SUCCESS)
  1261. ret = -EINVAL;
  1262. exit_set_chap:
  1263. return ret;
  1264. }
  1265. /**
  1266. * qla4xxx_get_chap_index - Get chap index given username and secret
  1267. * @ha: pointer to adapter structure
  1268. * @username: CHAP username to be searched
  1269. * @password: CHAP password to be searched
  1270. * @bidi: Is this a BIDI CHAP
  1271. * @chap_index: CHAP index to be returned
  1272. *
  1273. * Match the username and password in the chap_list, return the index if a
  1274. * match is found. If a match is not found then add the entry in FLASH and
  1275. * return the index at which entry is written in the FLASH.
  1276. **/
  1277. int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
  1278. char *password, int bidi, uint16_t *chap_index)
  1279. {
  1280. int i, rval;
  1281. int free_index = -1;
  1282. int found_index = 0;
  1283. int max_chap_entries = 0;
  1284. struct ql4_chap_table *chap_table;
  1285. if (is_qla8022(ha))
  1286. max_chap_entries = (ha->hw.flt_chap_size / 2) /
  1287. sizeof(struct ql4_chap_table);
  1288. else
  1289. max_chap_entries = MAX_CHAP_ENTRIES_40XX;
  1290. if (!ha->chap_list) {
  1291. ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
  1292. return QLA_ERROR;
  1293. }
  1294. if (!username || !password) {
  1295. ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
  1296. return QLA_ERROR;
  1297. }
  1298. mutex_lock(&ha->chap_sem);
  1299. for (i = 0; i < max_chap_entries; i++) {
  1300. chap_table = (struct ql4_chap_table *)ha->chap_list + i;
  1301. if (chap_table->cookie !=
  1302. __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
  1303. if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
  1304. free_index = i;
  1305. continue;
  1306. }
  1307. if (bidi) {
  1308. if (chap_table->flags & BIT_7)
  1309. continue;
  1310. } else {
  1311. if (chap_table->flags & BIT_6)
  1312. continue;
  1313. }
  1314. if (!strncmp(chap_table->secret, password,
  1315. MAX_CHAP_SECRET_LEN) &&
  1316. !strncmp(chap_table->name, username,
  1317. MAX_CHAP_NAME_LEN)) {
  1318. *chap_index = i;
  1319. found_index = 1;
  1320. break;
  1321. }
  1322. }
  1323. /* If chap entry is not present and a free index is available then
  1324. * write the entry in flash
  1325. */
  1326. if (!found_index && free_index != -1) {
  1327. rval = qla4xxx_set_chap(ha, username, password,
  1328. free_index, bidi);
  1329. if (!rval) {
  1330. *chap_index = free_index;
  1331. found_index = 1;
  1332. }
  1333. }
  1334. mutex_unlock(&ha->chap_sem);
  1335. if (found_index)
  1336. return QLA_SUCCESS;
  1337. return QLA_ERROR;
  1338. }
  1339. int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
  1340. uint16_t fw_ddb_index,
  1341. uint16_t connection_id,
  1342. uint16_t option)
  1343. {
  1344. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1345. uint32_t mbox_sts[MBOX_REG_COUNT];
  1346. int status = QLA_SUCCESS;
  1347. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1348. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1349. mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
  1350. mbox_cmd[1] = fw_ddb_index;
  1351. mbox_cmd[2] = connection_id;
  1352. mbox_cmd[3] = option;
  1353. status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
  1354. if (status != QLA_SUCCESS) {
  1355. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
  1356. "option %04x failed w/ status %04X %04X\n",
  1357. __func__, option, mbox_sts[0], mbox_sts[1]));
  1358. }
  1359. return status;
  1360. }
  1361. int qla4xxx_disable_acb(struct scsi_qla_host *ha)
  1362. {
  1363. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1364. uint32_t mbox_sts[MBOX_REG_COUNT];
  1365. int status = QLA_SUCCESS;
  1366. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1367. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1368. mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
  1369. status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
  1370. if (status != QLA_SUCCESS) {
  1371. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
  1372. "failed w/ status %04X %04X %04X", __func__,
  1373. mbox_sts[0], mbox_sts[1], mbox_sts[2]));
  1374. }
  1375. return status;
  1376. }
  1377. int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
  1378. uint32_t acb_type, uint32_t len)
  1379. {
  1380. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1381. uint32_t mbox_sts[MBOX_REG_COUNT];
  1382. int status = QLA_SUCCESS;
  1383. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1384. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1385. mbox_cmd[0] = MBOX_CMD_GET_ACB;
  1386. mbox_cmd[1] = acb_type;
  1387. mbox_cmd[2] = LSDW(acb_dma);
  1388. mbox_cmd[3] = MSDW(acb_dma);
  1389. mbox_cmd[4] = len;
  1390. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1391. if (status != QLA_SUCCESS) {
  1392. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
  1393. "failed w/ status %04X\n", __func__,
  1394. mbox_sts[0]));
  1395. }
  1396. return status;
  1397. }
  1398. int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
  1399. uint32_t *mbox_sts, dma_addr_t acb_dma)
  1400. {
  1401. int status = QLA_SUCCESS;
  1402. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1403. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1404. mbox_cmd[0] = MBOX_CMD_SET_ACB;
  1405. mbox_cmd[1] = 0; /* Primary ACB */
  1406. mbox_cmd[2] = LSDW(acb_dma);
  1407. mbox_cmd[3] = MSDW(acb_dma);
  1408. mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
  1409. status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
  1410. if (status != QLA_SUCCESS) {
  1411. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
  1412. "failed w/ status %04X\n", __func__,
  1413. mbox_sts[0]));
  1414. }
  1415. return status;
  1416. }
  1417. int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
  1418. struct ddb_entry *ddb_entry,
  1419. struct iscsi_cls_conn *cls_conn,
  1420. uint32_t *mbx_sts)
  1421. {
  1422. struct dev_db_entry *fw_ddb_entry;
  1423. struct iscsi_conn *conn;
  1424. struct iscsi_session *sess;
  1425. struct qla_conn *qla_conn;
  1426. struct sockaddr *dst_addr;
  1427. dma_addr_t fw_ddb_entry_dma;
  1428. int status = QLA_SUCCESS;
  1429. int rval = 0;
  1430. struct sockaddr_in *addr;
  1431. struct sockaddr_in6 *addr6;
  1432. char *ip;
  1433. uint16_t iscsi_opts = 0;
  1434. uint32_t options = 0;
  1435. uint16_t idx, *ptid;
  1436. fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1437. &fw_ddb_entry_dma, GFP_KERNEL);
  1438. if (!fw_ddb_entry) {
  1439. DEBUG2(ql4_printk(KERN_ERR, ha,
  1440. "%s: Unable to allocate dma buffer.\n",
  1441. __func__));
  1442. rval = -ENOMEM;
  1443. goto exit_set_param_no_free;
  1444. }
  1445. conn = cls_conn->dd_data;
  1446. qla_conn = conn->dd_data;
  1447. sess = conn->session;
  1448. dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
  1449. if (dst_addr->sa_family == AF_INET6)
  1450. options |= IPV6_DEFAULT_DDB_ENTRY;
  1451. status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
  1452. if (status == QLA_ERROR) {
  1453. rval = -EINVAL;
  1454. goto exit_set_param;
  1455. }
  1456. ptid = (uint16_t *)&fw_ddb_entry->isid[1];
  1457. *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
  1458. DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n",
  1459. fw_ddb_entry->isid[5], fw_ddb_entry->isid[4],
  1460. fw_ddb_entry->isid[3], fw_ddb_entry->isid[2],
  1461. fw_ddb_entry->isid[1], fw_ddb_entry->isid[0]));
  1462. iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
  1463. memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
  1464. memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
  1465. if (sess->targetname != NULL) {
  1466. memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
  1467. min(strlen(sess->targetname),
  1468. sizeof(fw_ddb_entry->iscsi_name)));
  1469. }
  1470. memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
  1471. memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
  1472. fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
  1473. if (dst_addr->sa_family == AF_INET) {
  1474. addr = (struct sockaddr_in *)dst_addr;
  1475. ip = (char *)&addr->sin_addr;
  1476. memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
  1477. fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
  1478. DEBUG2(ql4_printk(KERN_INFO, ha,
  1479. "%s: Destination Address [%pI4]: index [%d]\n",
  1480. __func__, fw_ddb_entry->ip_addr,
  1481. ddb_entry->fw_ddb_index));
  1482. } else if (dst_addr->sa_family == AF_INET6) {
  1483. addr6 = (struct sockaddr_in6 *)dst_addr;
  1484. ip = (char *)&addr6->sin6_addr;
  1485. memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
  1486. fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
  1487. fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
  1488. DEBUG2(ql4_printk(KERN_INFO, ha,
  1489. "%s: Destination Address [%pI6]: index [%d]\n",
  1490. __func__, fw_ddb_entry->ip_addr,
  1491. ddb_entry->fw_ddb_index));
  1492. } else {
  1493. ql4_printk(KERN_ERR, ha,
  1494. "%s: Failed to get IP Address\n",
  1495. __func__);
  1496. rval = -EINVAL;
  1497. goto exit_set_param;
  1498. }
  1499. /* CHAP */
  1500. if (sess->username != NULL && sess->password != NULL) {
  1501. if (strlen(sess->username) && strlen(sess->password)) {
  1502. iscsi_opts |= BIT_7;
  1503. rval = qla4xxx_get_chap_index(ha, sess->username,
  1504. sess->password,
  1505. LOCAL_CHAP, &idx);
  1506. if (rval)
  1507. goto exit_set_param;
  1508. fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
  1509. }
  1510. }
  1511. if (sess->username_in != NULL && sess->password_in != NULL) {
  1512. /* Check if BIDI CHAP */
  1513. if (strlen(sess->username_in) && strlen(sess->password_in)) {
  1514. iscsi_opts |= BIT_4;
  1515. rval = qla4xxx_get_chap_index(ha, sess->username_in,
  1516. sess->password_in,
  1517. BIDI_CHAP, &idx);
  1518. if (rval)
  1519. goto exit_set_param;
  1520. }
  1521. }
  1522. if (sess->initial_r2t_en)
  1523. iscsi_opts |= BIT_10;
  1524. if (sess->imm_data_en)
  1525. iscsi_opts |= BIT_11;
  1526. fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
  1527. if (conn->max_recv_dlength)
  1528. fw_ddb_entry->iscsi_max_rcv_data_seg_len =
  1529. __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
  1530. if (sess->max_r2t)
  1531. fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
  1532. if (sess->first_burst)
  1533. fw_ddb_entry->iscsi_first_burst_len =
  1534. __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
  1535. if (sess->max_burst)
  1536. fw_ddb_entry->iscsi_max_burst_len =
  1537. __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
  1538. if (sess->time2wait)
  1539. fw_ddb_entry->iscsi_def_time2wait =
  1540. cpu_to_le16(sess->time2wait);
  1541. if (sess->time2retain)
  1542. fw_ddb_entry->iscsi_def_time2retain =
  1543. cpu_to_le16(sess->time2retain);
  1544. status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
  1545. fw_ddb_entry_dma, mbx_sts);
  1546. if (status != QLA_SUCCESS)
  1547. rval = -EINVAL;
  1548. exit_set_param:
  1549. dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
  1550. fw_ddb_entry, fw_ddb_entry_dma);
  1551. exit_set_param_no_free:
  1552. return rval;
  1553. }
  1554. int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
  1555. uint16_t stats_size, dma_addr_t stats_dma)
  1556. {
  1557. int status = QLA_SUCCESS;
  1558. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1559. uint32_t mbox_sts[MBOX_REG_COUNT];
  1560. memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
  1561. memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
  1562. mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
  1563. mbox_cmd[1] = fw_ddb_index;
  1564. mbox_cmd[2] = LSDW(stats_dma);
  1565. mbox_cmd[3] = MSDW(stats_dma);
  1566. mbox_cmd[4] = stats_size;
  1567. status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
  1568. if (status != QLA_SUCCESS) {
  1569. DEBUG2(ql4_printk(KERN_WARNING, ha,
  1570. "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
  1571. "failed w/ status %04X\n", __func__,
  1572. mbox_sts[0]));
  1573. }
  1574. return status;
  1575. }
  1576. int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
  1577. uint32_t ip_idx, uint32_t *sts)
  1578. {
  1579. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1580. uint32_t mbox_sts[MBOX_REG_COUNT];
  1581. int status = QLA_SUCCESS;
  1582. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1583. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1584. mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
  1585. mbox_cmd[1] = acb_idx;
  1586. mbox_cmd[2] = ip_idx;
  1587. status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
  1588. if (status != QLA_SUCCESS) {
  1589. DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
  1590. "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
  1591. "status %04X\n", __func__, mbox_sts[0]));
  1592. }
  1593. memcpy(sts, mbox_sts, sizeof(mbox_sts));
  1594. return status;
  1595. }
  1596. int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1597. uint32_t offset, uint32_t size)
  1598. {
  1599. int status = QLA_SUCCESS;
  1600. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1601. uint32_t mbox_sts[MBOX_REG_COUNT];
  1602. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1603. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1604. mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
  1605. mbox_cmd[1] = LSDW(nvram_dma);
  1606. mbox_cmd[2] = MSDW(nvram_dma);
  1607. mbox_cmd[3] = offset;
  1608. mbox_cmd[4] = size;
  1609. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1610. &mbox_sts[0]);
  1611. if (status != QLA_SUCCESS) {
  1612. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1613. "status %04X\n", ha->host_no, __func__,
  1614. mbox_sts[0]));
  1615. }
  1616. return status;
  1617. }
  1618. int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
  1619. uint32_t offset, uint32_t size)
  1620. {
  1621. int status = QLA_SUCCESS;
  1622. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1623. uint32_t mbox_sts[MBOX_REG_COUNT];
  1624. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1625. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1626. mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
  1627. mbox_cmd[1] = LSDW(nvram_dma);
  1628. mbox_cmd[2] = MSDW(nvram_dma);
  1629. mbox_cmd[3] = offset;
  1630. mbox_cmd[4] = size;
  1631. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
  1632. &mbox_sts[0]);
  1633. if (status != QLA_SUCCESS) {
  1634. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1635. "status %04X\n", ha->host_no, __func__,
  1636. mbox_sts[0]));
  1637. }
  1638. return status;
  1639. }
  1640. int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
  1641. uint32_t region, uint32_t field0,
  1642. uint32_t field1)
  1643. {
  1644. int status = QLA_SUCCESS;
  1645. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1646. uint32_t mbox_sts[MBOX_REG_COUNT];
  1647. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1648. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1649. mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
  1650. mbox_cmd[3] = region;
  1651. mbox_cmd[4] = field0;
  1652. mbox_cmd[5] = field1;
  1653. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
  1654. &mbox_sts[0]);
  1655. if (status != QLA_SUCCESS) {
  1656. DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
  1657. "status %04X\n", ha->host_no, __func__,
  1658. mbox_sts[0]));
  1659. }
  1660. return status;
  1661. }
  1662. /**
  1663. * qla4_8xxx_set_param - set driver version in firmware.
  1664. * @ha: Pointer to host adapter structure.
  1665. * @param: Parameter to set i.e driver version
  1666. **/
  1667. int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
  1668. {
  1669. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1670. uint32_t mbox_sts[MBOX_REG_COUNT];
  1671. uint32_t status;
  1672. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1673. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1674. mbox_cmd[0] = MBOX_CMD_SET_PARAM;
  1675. if (param == SET_DRVR_VERSION) {
  1676. mbox_cmd[1] = SET_DRVR_VERSION;
  1677. strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
  1678. MAX_DRVR_VER_LEN);
  1679. } else {
  1680. ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
  1681. __func__, param);
  1682. status = QLA_ERROR;
  1683. goto exit_set_param;
  1684. }
  1685. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd,
  1686. mbox_sts);
  1687. if (status == QLA_ERROR)
  1688. ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
  1689. __func__, mbox_sts[0]);
  1690. exit_set_param:
  1691. return status;
  1692. }
  1693. /**
  1694. * qla4_83xx_post_idc_ack - post IDC ACK
  1695. * @ha: Pointer to host adapter structure.
  1696. *
  1697. * Posts IDC ACK for IDC Request Notification AEN.
  1698. **/
  1699. int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
  1700. {
  1701. uint32_t mbox_cmd[MBOX_REG_COUNT];
  1702. uint32_t mbox_sts[MBOX_REG_COUNT];
  1703. int status;
  1704. memset(&mbox_cmd, 0, sizeof(mbox_cmd));
  1705. memset(&mbox_sts, 0, sizeof(mbox_sts));
  1706. mbox_cmd[0] = MBOX_CMD_IDC_ACK;
  1707. mbox_cmd[1] = ha->idc_info.request_desc;
  1708. mbox_cmd[2] = ha->idc_info.info1;
  1709. mbox_cmd[3] = ha->idc_info.info2;
  1710. mbox_cmd[4] = ha->idc_info.info3;
  1711. status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
  1712. mbox_cmd, mbox_sts);
  1713. if (status == QLA_ERROR)
  1714. ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
  1715. mbox_sts[0]);
  1716. else
  1717. DEBUG2(ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n",
  1718. __func__));
  1719. return status;
  1720. }