sdhci.c 33 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /*
  11. * Note that PIO transfer is rather crappy atm. The buffer full/empty
  12. * interrupts aren't reliable so we currently transfer the entire buffer
  13. * directly. Patches to solve the problem are welcome.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/highmem.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/protocol.h>
  21. #include <asm/scatterlist.h>
  22. #include "sdhci.h"
  23. #define DRIVER_NAME "sdhci"
  24. #define DRIVER_VERSION "0.11"
  25. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  26. #define DBG(f, x...) \
  27. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  28. static const struct pci_device_id pci_ids[] __devinitdata = {
  29. /* handle any SD host controller */
  30. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  31. { /* end: all zeroes */ },
  32. };
  33. MODULE_DEVICE_TABLE(pci, pci_ids);
  34. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  35. static void sdhci_finish_data(struct sdhci_host *);
  36. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  37. static void sdhci_finish_command(struct sdhci_host *);
  38. static void sdhci_dumpregs(struct sdhci_host *host)
  39. {
  40. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  41. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  42. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  43. readw(host->ioaddr + SDHCI_HOST_VERSION));
  44. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  45. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  46. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  47. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  48. readl(host->ioaddr + SDHCI_ARGUMENT),
  49. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  50. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  51. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  52. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  53. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  54. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  55. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  56. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  57. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  58. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  59. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  60. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  61. readl(host->ioaddr + SDHCI_INT_STATUS));
  62. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  63. readl(host->ioaddr + SDHCI_INT_ENABLE),
  64. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  65. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  66. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  67. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  68. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  69. readl(host->ioaddr + SDHCI_CAPABILITIES),
  70. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  71. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  72. }
  73. /*****************************************************************************\
  74. * *
  75. * Low level functions *
  76. * *
  77. \*****************************************************************************/
  78. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  79. {
  80. unsigned long timeout;
  81. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  82. if (mask & SDHCI_RESET_ALL)
  83. host->clock = 0;
  84. /* Wait max 100 ms */
  85. timeout = 100;
  86. /* hw clears the bit when it's done */
  87. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  88. if (timeout == 0) {
  89. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  90. "Please report this to " BUGMAIL ".\n",
  91. mmc_hostname(host->mmc), (int)mask);
  92. sdhci_dumpregs(host);
  93. return;
  94. }
  95. timeout--;
  96. mdelay(1);
  97. }
  98. }
  99. static void sdhci_init(struct sdhci_host *host)
  100. {
  101. u32 intmask;
  102. sdhci_reset(host, SDHCI_RESET_ALL);
  103. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  104. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  105. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  106. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  107. SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL |
  108. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  109. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  110. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  111. }
  112. static void sdhci_activate_led(struct sdhci_host *host)
  113. {
  114. u8 ctrl;
  115. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  116. ctrl |= SDHCI_CTRL_LED;
  117. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  118. }
  119. static void sdhci_deactivate_led(struct sdhci_host *host)
  120. {
  121. u8 ctrl;
  122. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  123. ctrl &= ~SDHCI_CTRL_LED;
  124. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  125. }
  126. /*****************************************************************************\
  127. * *
  128. * Core functions *
  129. * *
  130. \*****************************************************************************/
  131. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  132. {
  133. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  134. return host->mapped_sg + host->cur_sg->offset;
  135. }
  136. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  137. {
  138. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  139. }
  140. static inline int sdhci_next_sg(struct sdhci_host* host)
  141. {
  142. /*
  143. * Skip to next SG entry.
  144. */
  145. host->cur_sg++;
  146. host->num_sg--;
  147. /*
  148. * Any entries left?
  149. */
  150. if (host->num_sg > 0) {
  151. host->offset = 0;
  152. host->remain = host->cur_sg->length;
  153. }
  154. return host->num_sg;
  155. }
  156. static void sdhci_transfer_pio(struct sdhci_host *host)
  157. {
  158. char *buffer;
  159. u32 mask;
  160. int bytes, size;
  161. unsigned long max_jiffies;
  162. BUG_ON(!host->data);
  163. if (host->num_sg == 0)
  164. return;
  165. bytes = 0;
  166. if (host->data->flags & MMC_DATA_READ)
  167. mask = SDHCI_DATA_AVAILABLE;
  168. else
  169. mask = SDHCI_SPACE_AVAILABLE;
  170. buffer = sdhci_kmap_sg(host) + host->offset;
  171. /* Transfer shouldn't take more than 5 s */
  172. max_jiffies = jiffies + HZ * 5;
  173. while (host->size > 0) {
  174. if (time_after(jiffies, max_jiffies)) {
  175. printk(KERN_ERR "%s: PIO transfer stalled. "
  176. "Please report this to "
  177. BUGMAIL ".\n", mmc_hostname(host->mmc));
  178. sdhci_dumpregs(host);
  179. sdhci_kunmap_sg(host);
  180. host->data->error = MMC_ERR_FAILED;
  181. sdhci_finish_data(host);
  182. return;
  183. }
  184. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask))
  185. continue;
  186. size = min(host->size, host->remain);
  187. if (size >= 4) {
  188. if (host->data->flags & MMC_DATA_READ)
  189. *(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
  190. else
  191. writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
  192. size = 4;
  193. } else if (size >= 2) {
  194. if (host->data->flags & MMC_DATA_READ)
  195. *(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
  196. else
  197. writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
  198. size = 2;
  199. } else {
  200. if (host->data->flags & MMC_DATA_READ)
  201. *(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
  202. else
  203. writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
  204. size = 1;
  205. }
  206. buffer += size;
  207. host->offset += size;
  208. host->remain -= size;
  209. bytes += size;
  210. host->size -= size;
  211. if (host->remain == 0) {
  212. sdhci_kunmap_sg(host);
  213. if (sdhci_next_sg(host) == 0) {
  214. DBG("PIO transfer: %d bytes\n", bytes);
  215. return;
  216. }
  217. buffer = sdhci_kmap_sg(host);
  218. }
  219. }
  220. sdhci_kunmap_sg(host);
  221. DBG("PIO transfer: %d bytes\n", bytes);
  222. }
  223. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  224. {
  225. u8 count;
  226. unsigned target_timeout, current_timeout;
  227. WARN_ON(host->data);
  228. if (data == NULL)
  229. return;
  230. DBG("blksz %04x blks %04x flags %08x\n",
  231. data->blksz, data->blocks, data->flags);
  232. DBG("tsac %d ms nsac %d clk\n",
  233. data->timeout_ns / 1000000, data->timeout_clks);
  234. /* timeout in us */
  235. target_timeout = data->timeout_ns / 1000 +
  236. data->timeout_clks / host->clock;
  237. /*
  238. * Figure out needed cycles.
  239. * We do this in steps in order to fit inside a 32 bit int.
  240. * The first step is the minimum timeout, which will have a
  241. * minimum resolution of 6 bits:
  242. * (1) 2^13*1000 > 2^22,
  243. * (2) host->timeout_clk < 2^16
  244. * =>
  245. * (1) / (2) > 2^6
  246. */
  247. count = 0;
  248. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  249. while (current_timeout < target_timeout) {
  250. count++;
  251. current_timeout <<= 1;
  252. if (count >= 0xF)
  253. break;
  254. }
  255. if (count >= 0xF) {
  256. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  257. mmc_hostname(host->mmc));
  258. count = 0xE;
  259. }
  260. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  261. if (host->flags & SDHCI_USE_DMA) {
  262. int count;
  263. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  264. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  265. BUG_ON(count != 1);
  266. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  267. } else {
  268. host->size = data->blksz * data->blocks;
  269. host->cur_sg = data->sg;
  270. host->num_sg = data->sg_len;
  271. host->offset = 0;
  272. host->remain = host->cur_sg->length;
  273. }
  274. writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
  275. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  276. }
  277. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  278. struct mmc_data *data)
  279. {
  280. u16 mode;
  281. WARN_ON(host->data);
  282. if (data == NULL)
  283. return;
  284. mode = SDHCI_TRNS_BLK_CNT_EN;
  285. if (data->blocks > 1)
  286. mode |= SDHCI_TRNS_MULTI;
  287. if (data->flags & MMC_DATA_READ)
  288. mode |= SDHCI_TRNS_READ;
  289. if (host->flags & SDHCI_USE_DMA)
  290. mode |= SDHCI_TRNS_DMA;
  291. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  292. }
  293. static void sdhci_finish_data(struct sdhci_host *host)
  294. {
  295. struct mmc_data *data;
  296. u16 blocks;
  297. BUG_ON(!host->data);
  298. data = host->data;
  299. host->data = NULL;
  300. if (host->flags & SDHCI_USE_DMA) {
  301. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  302. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  303. }
  304. /*
  305. * Controller doesn't count down when in single block mode.
  306. */
  307. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  308. blocks = 0;
  309. else
  310. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  311. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  312. if ((data->error == MMC_ERR_NONE) && blocks) {
  313. printk(KERN_ERR "%s: Controller signalled completion even "
  314. "though there were blocks left. Please report this "
  315. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  316. data->error = MMC_ERR_FAILED;
  317. }
  318. if (host->size != 0) {
  319. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  320. "Please report this to " BUGMAIL ".\n",
  321. mmc_hostname(host->mmc), host->size);
  322. data->error = MMC_ERR_FAILED;
  323. }
  324. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  325. if (data->stop) {
  326. /*
  327. * The controller needs a reset of internal state machines
  328. * upon error conditions.
  329. */
  330. if (data->error != MMC_ERR_NONE) {
  331. sdhci_reset(host, SDHCI_RESET_CMD);
  332. sdhci_reset(host, SDHCI_RESET_DATA);
  333. }
  334. sdhci_send_command(host, data->stop);
  335. } else
  336. tasklet_schedule(&host->finish_tasklet);
  337. }
  338. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  339. {
  340. int flags;
  341. unsigned long timeout;
  342. WARN_ON(host->cmd);
  343. DBG("Sending cmd (%x)\n", cmd->opcode);
  344. /* Wait max 10 ms */
  345. timeout = 10;
  346. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  347. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  348. if (timeout == 0) {
  349. printk(KERN_ERR "%s: Controller never released "
  350. "inhibit bits. Please report this to "
  351. BUGMAIL ".\n", mmc_hostname(host->mmc));
  352. sdhci_dumpregs(host);
  353. cmd->error = MMC_ERR_FAILED;
  354. tasklet_schedule(&host->finish_tasklet);
  355. return;
  356. }
  357. timeout--;
  358. mdelay(1);
  359. }
  360. mod_timer(&host->timer, jiffies + 10 * HZ);
  361. host->cmd = cmd;
  362. sdhci_prepare_data(host, cmd->data);
  363. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  364. sdhci_set_transfer_mode(host, cmd->data);
  365. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  366. printk(KERN_ERR "%s: Unsupported response type! "
  367. "Please report this to " BUGMAIL ".\n",
  368. mmc_hostname(host->mmc));
  369. cmd->error = MMC_ERR_INVALID;
  370. tasklet_schedule(&host->finish_tasklet);
  371. return;
  372. }
  373. if (!(cmd->flags & MMC_RSP_PRESENT))
  374. flags = SDHCI_CMD_RESP_NONE;
  375. else if (cmd->flags & MMC_RSP_136)
  376. flags = SDHCI_CMD_RESP_LONG;
  377. else if (cmd->flags & MMC_RSP_BUSY)
  378. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  379. else
  380. flags = SDHCI_CMD_RESP_SHORT;
  381. if (cmd->flags & MMC_RSP_CRC)
  382. flags |= SDHCI_CMD_CRC;
  383. if (cmd->flags & MMC_RSP_OPCODE)
  384. flags |= SDHCI_CMD_INDEX;
  385. if (cmd->data)
  386. flags |= SDHCI_CMD_DATA;
  387. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  388. host->ioaddr + SDHCI_COMMAND);
  389. }
  390. static void sdhci_finish_command(struct sdhci_host *host)
  391. {
  392. int i;
  393. BUG_ON(host->cmd == NULL);
  394. if (host->cmd->flags & MMC_RSP_PRESENT) {
  395. if (host->cmd->flags & MMC_RSP_136) {
  396. /* CRC is stripped so we need to do some shifting. */
  397. for (i = 0;i < 4;i++) {
  398. host->cmd->resp[i] = readl(host->ioaddr +
  399. SDHCI_RESPONSE + (3-i)*4) << 8;
  400. if (i != 3)
  401. host->cmd->resp[i] |=
  402. readb(host->ioaddr +
  403. SDHCI_RESPONSE + (3-i)*4-1);
  404. }
  405. } else {
  406. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  407. }
  408. }
  409. host->cmd->error = MMC_ERR_NONE;
  410. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  411. if (host->cmd->data)
  412. host->data = host->cmd->data;
  413. else
  414. tasklet_schedule(&host->finish_tasklet);
  415. host->cmd = NULL;
  416. }
  417. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  418. {
  419. int div;
  420. u16 clk;
  421. unsigned long timeout;
  422. if (clock == host->clock)
  423. return;
  424. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  425. if (clock == 0)
  426. goto out;
  427. for (div = 1;div < 256;div *= 2) {
  428. if ((host->max_clk / div) <= clock)
  429. break;
  430. }
  431. div >>= 1;
  432. clk = div << SDHCI_DIVIDER_SHIFT;
  433. clk |= SDHCI_CLOCK_INT_EN;
  434. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  435. /* Wait max 10 ms */
  436. timeout = 10;
  437. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  438. & SDHCI_CLOCK_INT_STABLE)) {
  439. if (timeout == 0) {
  440. printk(KERN_ERR "%s: Internal clock never stabilised. "
  441. "Please report this to " BUGMAIL ".\n",
  442. mmc_hostname(host->mmc));
  443. sdhci_dumpregs(host);
  444. return;
  445. }
  446. timeout--;
  447. mdelay(1);
  448. }
  449. clk |= SDHCI_CLOCK_CARD_EN;
  450. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  451. out:
  452. host->clock = clock;
  453. }
  454. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  455. {
  456. u8 pwr;
  457. if (host->power == power)
  458. return;
  459. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  460. if (power == (unsigned short)-1)
  461. goto out;
  462. pwr = SDHCI_POWER_ON;
  463. switch (power) {
  464. case MMC_VDD_170:
  465. case MMC_VDD_180:
  466. case MMC_VDD_190:
  467. pwr |= SDHCI_POWER_180;
  468. break;
  469. case MMC_VDD_290:
  470. case MMC_VDD_300:
  471. case MMC_VDD_310:
  472. pwr |= SDHCI_POWER_300;
  473. break;
  474. case MMC_VDD_320:
  475. case MMC_VDD_330:
  476. case MMC_VDD_340:
  477. pwr |= SDHCI_POWER_330;
  478. break;
  479. default:
  480. BUG();
  481. }
  482. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  483. out:
  484. host->power = power;
  485. }
  486. /*****************************************************************************\
  487. * *
  488. * MMC callbacks *
  489. * *
  490. \*****************************************************************************/
  491. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  492. {
  493. struct sdhci_host *host;
  494. unsigned long flags;
  495. host = mmc_priv(mmc);
  496. spin_lock_irqsave(&host->lock, flags);
  497. WARN_ON(host->mrq != NULL);
  498. sdhci_activate_led(host);
  499. host->mrq = mrq;
  500. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  501. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  502. tasklet_schedule(&host->finish_tasklet);
  503. } else
  504. sdhci_send_command(host, mrq->cmd);
  505. spin_unlock_irqrestore(&host->lock, flags);
  506. }
  507. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  508. {
  509. struct sdhci_host *host;
  510. unsigned long flags;
  511. u8 ctrl;
  512. host = mmc_priv(mmc);
  513. spin_lock_irqsave(&host->lock, flags);
  514. /*
  515. * Reset the chip on each power off.
  516. * Should clear out any weird states.
  517. */
  518. if (ios->power_mode == MMC_POWER_OFF) {
  519. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  520. sdhci_init(host);
  521. }
  522. sdhci_set_clock(host, ios->clock);
  523. if (ios->power_mode == MMC_POWER_OFF)
  524. sdhci_set_power(host, -1);
  525. else
  526. sdhci_set_power(host, ios->vdd);
  527. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  528. if (ios->bus_width == MMC_BUS_WIDTH_4)
  529. ctrl |= SDHCI_CTRL_4BITBUS;
  530. else
  531. ctrl &= ~SDHCI_CTRL_4BITBUS;
  532. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  533. spin_unlock_irqrestore(&host->lock, flags);
  534. }
  535. static int sdhci_get_ro(struct mmc_host *mmc)
  536. {
  537. struct sdhci_host *host;
  538. unsigned long flags;
  539. int present;
  540. host = mmc_priv(mmc);
  541. spin_lock_irqsave(&host->lock, flags);
  542. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  543. spin_unlock_irqrestore(&host->lock, flags);
  544. return !(present & SDHCI_WRITE_PROTECT);
  545. }
  546. static struct mmc_host_ops sdhci_ops = {
  547. .request = sdhci_request,
  548. .set_ios = sdhci_set_ios,
  549. .get_ro = sdhci_get_ro,
  550. };
  551. /*****************************************************************************\
  552. * *
  553. * Tasklets *
  554. * *
  555. \*****************************************************************************/
  556. static void sdhci_tasklet_card(unsigned long param)
  557. {
  558. struct sdhci_host *host;
  559. unsigned long flags;
  560. host = (struct sdhci_host*)param;
  561. spin_lock_irqsave(&host->lock, flags);
  562. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  563. if (host->mrq) {
  564. printk(KERN_ERR "%s: Card removed during transfer!\n",
  565. mmc_hostname(host->mmc));
  566. printk(KERN_ERR "%s: Resetting controller.\n",
  567. mmc_hostname(host->mmc));
  568. sdhci_reset(host, SDHCI_RESET_CMD);
  569. sdhci_reset(host, SDHCI_RESET_DATA);
  570. host->mrq->cmd->error = MMC_ERR_FAILED;
  571. tasklet_schedule(&host->finish_tasklet);
  572. }
  573. }
  574. spin_unlock_irqrestore(&host->lock, flags);
  575. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  576. }
  577. static void sdhci_tasklet_finish(unsigned long param)
  578. {
  579. struct sdhci_host *host;
  580. unsigned long flags;
  581. struct mmc_request *mrq;
  582. host = (struct sdhci_host*)param;
  583. spin_lock_irqsave(&host->lock, flags);
  584. del_timer(&host->timer);
  585. mrq = host->mrq;
  586. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  587. /*
  588. * The controller needs a reset of internal state machines
  589. * upon error conditions.
  590. */
  591. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  592. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  593. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  594. sdhci_reset(host, SDHCI_RESET_CMD);
  595. sdhci_reset(host, SDHCI_RESET_DATA);
  596. }
  597. host->mrq = NULL;
  598. host->cmd = NULL;
  599. host->data = NULL;
  600. sdhci_deactivate_led(host);
  601. spin_unlock_irqrestore(&host->lock, flags);
  602. mmc_request_done(host->mmc, mrq);
  603. }
  604. static void sdhci_timeout_timer(unsigned long data)
  605. {
  606. struct sdhci_host *host;
  607. unsigned long flags;
  608. host = (struct sdhci_host*)data;
  609. spin_lock_irqsave(&host->lock, flags);
  610. if (host->mrq) {
  611. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  612. "Please report this to " BUGMAIL ".\n",
  613. mmc_hostname(host->mmc));
  614. sdhci_dumpregs(host);
  615. if (host->data) {
  616. host->data->error = MMC_ERR_TIMEOUT;
  617. sdhci_finish_data(host);
  618. } else {
  619. if (host->cmd)
  620. host->cmd->error = MMC_ERR_TIMEOUT;
  621. else
  622. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  623. tasklet_schedule(&host->finish_tasklet);
  624. }
  625. }
  626. spin_unlock_irqrestore(&host->lock, flags);
  627. }
  628. /*****************************************************************************\
  629. * *
  630. * Interrupt handling *
  631. * *
  632. \*****************************************************************************/
  633. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  634. {
  635. BUG_ON(intmask == 0);
  636. if (!host->cmd) {
  637. printk(KERN_ERR "%s: Got command interrupt even though no "
  638. "command operation was in progress.\n",
  639. mmc_hostname(host->mmc));
  640. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  641. mmc_hostname(host->mmc));
  642. sdhci_dumpregs(host);
  643. return;
  644. }
  645. if (intmask & SDHCI_INT_RESPONSE)
  646. sdhci_finish_command(host);
  647. else {
  648. if (intmask & SDHCI_INT_TIMEOUT)
  649. host->cmd->error = MMC_ERR_TIMEOUT;
  650. else if (intmask & SDHCI_INT_CRC)
  651. host->cmd->error = MMC_ERR_BADCRC;
  652. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  653. host->cmd->error = MMC_ERR_FAILED;
  654. else
  655. host->cmd->error = MMC_ERR_INVALID;
  656. tasklet_schedule(&host->finish_tasklet);
  657. }
  658. }
  659. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  660. {
  661. BUG_ON(intmask == 0);
  662. if (!host->data) {
  663. /*
  664. * A data end interrupt is sent together with the response
  665. * for the stop command.
  666. */
  667. if (intmask & SDHCI_INT_DATA_END)
  668. return;
  669. printk(KERN_ERR "%s: Got data interrupt even though no "
  670. "data operation was in progress.\n",
  671. mmc_hostname(host->mmc));
  672. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  673. mmc_hostname(host->mmc));
  674. sdhci_dumpregs(host);
  675. return;
  676. }
  677. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  678. host->data->error = MMC_ERR_TIMEOUT;
  679. else if (intmask & SDHCI_INT_DATA_CRC)
  680. host->data->error = MMC_ERR_BADCRC;
  681. else if (intmask & SDHCI_INT_DATA_END_BIT)
  682. host->data->error = MMC_ERR_FAILED;
  683. if (host->data->error != MMC_ERR_NONE)
  684. sdhci_finish_data(host);
  685. else {
  686. if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY))
  687. sdhci_transfer_pio(host);
  688. if (intmask & SDHCI_INT_DATA_END)
  689. sdhci_finish_data(host);
  690. }
  691. }
  692. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  693. {
  694. irqreturn_t result;
  695. struct sdhci_host* host = dev_id;
  696. u32 intmask;
  697. spin_lock(&host->lock);
  698. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  699. if (!intmask) {
  700. result = IRQ_NONE;
  701. goto out;
  702. }
  703. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  704. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  705. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  706. host->ioaddr + SDHCI_INT_STATUS);
  707. tasklet_schedule(&host->card_tasklet);
  708. }
  709. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  710. if (intmask & SDHCI_INT_CMD_MASK) {
  711. writel(intmask & SDHCI_INT_CMD_MASK,
  712. host->ioaddr + SDHCI_INT_STATUS);
  713. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  714. }
  715. if (intmask & SDHCI_INT_DATA_MASK) {
  716. writel(intmask & SDHCI_INT_DATA_MASK,
  717. host->ioaddr + SDHCI_INT_STATUS);
  718. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  719. }
  720. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  721. if (intmask & SDHCI_INT_BUS_POWER) {
  722. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  723. mmc_hostname(host->mmc));
  724. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  725. }
  726. intmask &= SDHCI_INT_BUS_POWER;
  727. if (intmask) {
  728. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  729. "report this to " BUGMAIL ".\n",
  730. mmc_hostname(host->mmc), intmask);
  731. sdhci_dumpregs(host);
  732. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  733. }
  734. result = IRQ_HANDLED;
  735. out:
  736. spin_unlock(&host->lock);
  737. return result;
  738. }
  739. /*****************************************************************************\
  740. * *
  741. * Suspend/resume *
  742. * *
  743. \*****************************************************************************/
  744. #ifdef CONFIG_PM
  745. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  746. {
  747. struct sdhci_chip *chip;
  748. int i, ret;
  749. chip = pci_get_drvdata(pdev);
  750. if (!chip)
  751. return 0;
  752. DBG("Suspending...\n");
  753. for (i = 0;i < chip->num_slots;i++) {
  754. if (!chip->hosts[i])
  755. continue;
  756. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  757. if (ret) {
  758. for (i--;i >= 0;i--)
  759. mmc_resume_host(chip->hosts[i]->mmc);
  760. return ret;
  761. }
  762. }
  763. pci_save_state(pdev);
  764. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  765. pci_disable_device(pdev);
  766. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  767. return 0;
  768. }
  769. static int sdhci_resume (struct pci_dev *pdev)
  770. {
  771. struct sdhci_chip *chip;
  772. int i, ret;
  773. chip = pci_get_drvdata(pdev);
  774. if (!chip)
  775. return 0;
  776. DBG("Resuming...\n");
  777. pci_set_power_state(pdev, PCI_D0);
  778. pci_restore_state(pdev);
  779. pci_enable_device(pdev);
  780. for (i = 0;i < chip->num_slots;i++) {
  781. if (!chip->hosts[i])
  782. continue;
  783. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  784. pci_set_master(pdev);
  785. sdhci_init(chip->hosts[i]);
  786. ret = mmc_resume_host(chip->hosts[i]->mmc);
  787. if (ret)
  788. return ret;
  789. }
  790. return 0;
  791. }
  792. #else /* CONFIG_PM */
  793. #define sdhci_suspend NULL
  794. #define sdhci_resume NULL
  795. #endif /* CONFIG_PM */
  796. /*****************************************************************************\
  797. * *
  798. * Device probing/removal *
  799. * *
  800. \*****************************************************************************/
  801. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  802. {
  803. int ret;
  804. struct sdhci_chip *chip;
  805. struct mmc_host *mmc;
  806. struct sdhci_host *host;
  807. u8 first_bar;
  808. unsigned int caps;
  809. chip = pci_get_drvdata(pdev);
  810. BUG_ON(!chip);
  811. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  812. if (ret)
  813. return ret;
  814. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  815. if (first_bar > 5) {
  816. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  817. return -ENODEV;
  818. }
  819. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  820. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  821. return -ENODEV;
  822. }
  823. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  824. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  825. return -ENODEV;
  826. }
  827. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  828. if (!mmc)
  829. return -ENOMEM;
  830. host = mmc_priv(mmc);
  831. host->mmc = mmc;
  832. host->bar = first_bar + slot;
  833. host->addr = pci_resource_start(pdev, host->bar);
  834. host->irq = pdev->irq;
  835. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  836. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  837. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  838. if (ret)
  839. goto free;
  840. host->ioaddr = ioremap_nocache(host->addr,
  841. pci_resource_len(pdev, host->bar));
  842. if (!host->ioaddr) {
  843. ret = -ENOMEM;
  844. goto release;
  845. }
  846. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  847. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  848. host->flags |= SDHCI_USE_DMA;
  849. if (host->flags & SDHCI_USE_DMA) {
  850. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  851. printk(KERN_WARNING "%s: No suitable DMA available. "
  852. "Falling back to PIO.\n", host->slot_descr);
  853. host->flags &= ~SDHCI_USE_DMA;
  854. }
  855. }
  856. if (host->flags & SDHCI_USE_DMA)
  857. pci_set_master(pdev);
  858. else /* XXX: Hack to get MMC layer to avoid highmem */
  859. pdev->dma_mask = 0;
  860. host->max_clk =
  861. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  862. if (host->max_clk == 0) {
  863. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  864. "frequency.\n", host->slot_descr);
  865. ret = -ENODEV;
  866. goto unmap;
  867. }
  868. host->max_clk *= 1000000;
  869. host->timeout_clk =
  870. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  871. if (host->timeout_clk == 0) {
  872. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  873. "frequency.\n", host->slot_descr);
  874. ret = -ENODEV;
  875. goto unmap;
  876. }
  877. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  878. host->timeout_clk *= 1000;
  879. /*
  880. * Set host parameters.
  881. */
  882. mmc->ops = &sdhci_ops;
  883. mmc->f_min = host->max_clk / 256;
  884. mmc->f_max = host->max_clk;
  885. mmc->caps = MMC_CAP_4_BIT_DATA;
  886. mmc->ocr_avail = 0;
  887. if (caps & SDHCI_CAN_VDD_330)
  888. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  889. else if (caps & SDHCI_CAN_VDD_300)
  890. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  891. else if (caps & SDHCI_CAN_VDD_180)
  892. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  893. if (mmc->ocr_avail == 0) {
  894. printk(KERN_ERR "%s: Hardware doesn't report any "
  895. "support voltages.\n", host->slot_descr);
  896. ret = -ENODEV;
  897. goto unmap;
  898. }
  899. spin_lock_init(&host->lock);
  900. /*
  901. * Maximum number of segments. Hardware cannot do scatter lists.
  902. */
  903. if (host->flags & SDHCI_USE_DMA)
  904. mmc->max_hw_segs = 1;
  905. else
  906. mmc->max_hw_segs = 16;
  907. mmc->max_phys_segs = 16;
  908. /*
  909. * Maximum number of sectors in one transfer. Limited by sector
  910. * count register.
  911. */
  912. mmc->max_sectors = 0x3FFF;
  913. /*
  914. * Maximum segment size. Could be one segment with the maximum number
  915. * of sectors.
  916. */
  917. mmc->max_seg_size = mmc->max_sectors * 512;
  918. /*
  919. * Init tasklets.
  920. */
  921. tasklet_init(&host->card_tasklet,
  922. sdhci_tasklet_card, (unsigned long)host);
  923. tasklet_init(&host->finish_tasklet,
  924. sdhci_tasklet_finish, (unsigned long)host);
  925. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  926. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  927. host->slot_descr, host);
  928. if (ret)
  929. goto untasklet;
  930. sdhci_init(host);
  931. #ifdef CONFIG_MMC_DEBUG
  932. sdhci_dumpregs(host);
  933. #endif
  934. host->chip = chip;
  935. chip->hosts[slot] = host;
  936. mmc_add_host(mmc);
  937. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  938. host->addr, host->irq,
  939. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  940. return 0;
  941. untasklet:
  942. tasklet_kill(&host->card_tasklet);
  943. tasklet_kill(&host->finish_tasklet);
  944. unmap:
  945. iounmap(host->ioaddr);
  946. release:
  947. pci_release_region(pdev, host->bar);
  948. free:
  949. mmc_free_host(mmc);
  950. return ret;
  951. }
  952. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  953. {
  954. struct sdhci_chip *chip;
  955. struct mmc_host *mmc;
  956. struct sdhci_host *host;
  957. chip = pci_get_drvdata(pdev);
  958. host = chip->hosts[slot];
  959. mmc = host->mmc;
  960. chip->hosts[slot] = NULL;
  961. mmc_remove_host(mmc);
  962. sdhci_reset(host, SDHCI_RESET_ALL);
  963. free_irq(host->irq, host);
  964. del_timer_sync(&host->timer);
  965. tasklet_kill(&host->card_tasklet);
  966. tasklet_kill(&host->finish_tasklet);
  967. iounmap(host->ioaddr);
  968. pci_release_region(pdev, host->bar);
  969. mmc_free_host(mmc);
  970. }
  971. static int __devinit sdhci_probe(struct pci_dev *pdev,
  972. const struct pci_device_id *ent)
  973. {
  974. int ret, i;
  975. u8 slots, rev;
  976. struct sdhci_chip *chip;
  977. BUG_ON(pdev == NULL);
  978. BUG_ON(ent == NULL);
  979. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  980. printk(KERN_INFO DRIVER_NAME
  981. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  982. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  983. (int)rev);
  984. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  985. if (ret)
  986. return ret;
  987. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  988. DBG("found %d slot(s)\n", slots);
  989. if (slots == 0)
  990. return -ENODEV;
  991. ret = pci_enable_device(pdev);
  992. if (ret)
  993. return ret;
  994. chip = kzalloc(sizeof(struct sdhci_chip) +
  995. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  996. if (!chip) {
  997. ret = -ENOMEM;
  998. goto err;
  999. }
  1000. chip->pdev = pdev;
  1001. chip->num_slots = slots;
  1002. pci_set_drvdata(pdev, chip);
  1003. for (i = 0;i < slots;i++) {
  1004. ret = sdhci_probe_slot(pdev, i);
  1005. if (ret) {
  1006. for (i--;i >= 0;i--)
  1007. sdhci_remove_slot(pdev, i);
  1008. goto free;
  1009. }
  1010. }
  1011. return 0;
  1012. free:
  1013. pci_set_drvdata(pdev, NULL);
  1014. kfree(chip);
  1015. err:
  1016. pci_disable_device(pdev);
  1017. return ret;
  1018. }
  1019. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1020. {
  1021. int i;
  1022. struct sdhci_chip *chip;
  1023. chip = pci_get_drvdata(pdev);
  1024. if (chip) {
  1025. for (i = 0;i < chip->num_slots;i++)
  1026. sdhci_remove_slot(pdev, i);
  1027. pci_set_drvdata(pdev, NULL);
  1028. kfree(chip);
  1029. }
  1030. pci_disable_device(pdev);
  1031. }
  1032. static struct pci_driver sdhci_driver = {
  1033. .name = DRIVER_NAME,
  1034. .id_table = pci_ids,
  1035. .probe = sdhci_probe,
  1036. .remove = __devexit_p(sdhci_remove),
  1037. .suspend = sdhci_suspend,
  1038. .resume = sdhci_resume,
  1039. };
  1040. /*****************************************************************************\
  1041. * *
  1042. * Driver init/exit *
  1043. * *
  1044. \*****************************************************************************/
  1045. static int __init sdhci_drv_init(void)
  1046. {
  1047. printk(KERN_INFO DRIVER_NAME
  1048. ": Secure Digital Host Controller Interface driver, "
  1049. DRIVER_VERSION "\n");
  1050. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1051. return pci_register_driver(&sdhci_driver);
  1052. }
  1053. static void __exit sdhci_drv_exit(void)
  1054. {
  1055. DBG("Exiting\n");
  1056. pci_unregister_driver(&sdhci_driver);
  1057. }
  1058. module_init(sdhci_drv_init);
  1059. module_exit(sdhci_drv_exit);
  1060. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1061. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1062. MODULE_VERSION(DRIVER_VERSION);
  1063. MODULE_LICENSE("GPL");