r8152.c 41 KB

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  1. /*
  2. * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/init.h>
  10. #include <linux/signal.h>
  11. #include <linux/slab.h>
  12. #include <linux/module.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/mii.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/usb.h>
  18. #include <linux/crc32.h>
  19. #include <linux/if_vlan.h>
  20. #include <linux/uaccess.h>
  21. /* Version Information */
  22. #define DRIVER_VERSION "v1.0.0 (2013/05/03)"
  23. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  24. #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters"
  25. #define MODULENAME "r8152"
  26. #define R8152_PHY_ID 32
  27. #define PLA_IDR 0xc000
  28. #define PLA_RCR 0xc010
  29. #define PLA_RMS 0xc016
  30. #define PLA_RXFIFO_CTRL0 0xc0a0
  31. #define PLA_RXFIFO_CTRL1 0xc0a4
  32. #define PLA_RXFIFO_CTRL2 0xc0a8
  33. #define PLA_FMC 0xc0b4
  34. #define PLA_CFG_WOL 0xc0b6
  35. #define PLA_MAR 0xcd00
  36. #define PAL_BDC_CR 0xd1a0
  37. #define PLA_LEDSEL 0xdd90
  38. #define PLA_LED_FEATURE 0xdd92
  39. #define PLA_PHYAR 0xde00
  40. #define PLA_GPHY_INTR_IMR 0xe022
  41. #define PLA_EEE_CR 0xe040
  42. #define PLA_EEEP_CR 0xe080
  43. #define PLA_MAC_PWR_CTRL 0xe0c0
  44. #define PLA_TCR0 0xe610
  45. #define PLA_TCR1 0xe612
  46. #define PLA_TXFIFO_CTRL 0xe618
  47. #define PLA_RSTTELLY 0xe800
  48. #define PLA_CR 0xe813
  49. #define PLA_CRWECR 0xe81c
  50. #define PLA_CONFIG5 0xe822
  51. #define PLA_PHY_PWR 0xe84c
  52. #define PLA_OOB_CTRL 0xe84f
  53. #define PLA_CPCR 0xe854
  54. #define PLA_MISC_0 0xe858
  55. #define PLA_MISC_1 0xe85a
  56. #define PLA_OCP_GPHY_BASE 0xe86c
  57. #define PLA_TELLYCNT 0xe890
  58. #define PLA_SFF_STS_7 0xe8de
  59. #define PLA_PHYSTATUS 0xe908
  60. #define PLA_BP_BA 0xfc26
  61. #define PLA_BP_0 0xfc28
  62. #define PLA_BP_1 0xfc2a
  63. #define PLA_BP_2 0xfc2c
  64. #define PLA_BP_3 0xfc2e
  65. #define PLA_BP_4 0xfc30
  66. #define PLA_BP_5 0xfc32
  67. #define PLA_BP_6 0xfc34
  68. #define PLA_BP_7 0xfc36
  69. #define USB_DEV_STAT 0xb808
  70. #define USB_USB_CTRL 0xd406
  71. #define USB_PHY_CTRL 0xd408
  72. #define USB_TX_AGG 0xd40a
  73. #define USB_RX_BUF_TH 0xd40c
  74. #define USB_USB_TIMER 0xd428
  75. #define USB_PM_CTRL_STATUS 0xd432
  76. #define USB_TX_DMA 0xd434
  77. #define USB_UPS_CTRL 0xd800
  78. #define USB_BP_BA 0xfc26
  79. #define USB_BP_0 0xfc28
  80. #define USB_BP_1 0xfc2a
  81. #define USB_BP_2 0xfc2c
  82. #define USB_BP_3 0xfc2e
  83. #define USB_BP_4 0xfc30
  84. #define USB_BP_5 0xfc32
  85. #define USB_BP_6 0xfc34
  86. #define USB_BP_7 0xfc36
  87. /* OCP Registers */
  88. #define OCP_ALDPS_CONFIG 0x2010
  89. #define OCP_EEE_CONFIG1 0x2080
  90. #define OCP_EEE_CONFIG2 0x2092
  91. #define OCP_EEE_CONFIG3 0x2094
  92. #define OCP_EEE_AR 0xa41a
  93. #define OCP_EEE_DATA 0xa41c
  94. /* PLA_RCR */
  95. #define RCR_AAP 0x00000001
  96. #define RCR_APM 0x00000002
  97. #define RCR_AM 0x00000004
  98. #define RCR_AB 0x00000008
  99. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  100. /* PLA_RXFIFO_CTRL0 */
  101. #define RXFIFO_THR1_NORMAL 0x00080002
  102. #define RXFIFO_THR1_OOB 0x01800003
  103. /* PLA_RXFIFO_CTRL1 */
  104. #define RXFIFO_THR2_FULL 0x00000060
  105. #define RXFIFO_THR2_HIGH 0x00000038
  106. #define RXFIFO_THR2_OOB 0x0000004a
  107. /* PLA_RXFIFO_CTRL2 */
  108. #define RXFIFO_THR3_FULL 0x00000078
  109. #define RXFIFO_THR3_HIGH 0x00000048
  110. #define RXFIFO_THR3_OOB 0x0000005a
  111. /* PLA_TXFIFO_CTRL */
  112. #define TXFIFO_THR_NORMAL 0x00400008
  113. /* PLA_FMC */
  114. #define FMC_FCR_MCU_EN 0x0001
  115. /* PLA_EEEP_CR */
  116. #define EEEP_CR_EEEP_TX 0x0002
  117. /* PLA_TCR0 */
  118. #define TCR0_TX_EMPTY 0x0800
  119. #define TCR0_AUTO_FIFO 0x0080
  120. /* PLA_TCR1 */
  121. #define VERSION_MASK 0x7cf0
  122. /* PLA_CR */
  123. #define CR_RST 0x10
  124. #define CR_RE 0x08
  125. #define CR_TE 0x04
  126. /* PLA_CRWECR */
  127. #define CRWECR_NORAML 0x00
  128. #define CRWECR_CONFIG 0xc0
  129. /* PLA_OOB_CTRL */
  130. #define NOW_IS_OOB 0x80
  131. #define TXFIFO_EMPTY 0x20
  132. #define RXFIFO_EMPTY 0x10
  133. #define LINK_LIST_READY 0x02
  134. #define DIS_MCU_CLROOB 0x01
  135. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  136. /* PLA_MISC_1 */
  137. #define RXDY_GATED_EN 0x0008
  138. /* PLA_SFF_STS_7 */
  139. #define RE_INIT_LL 0x8000
  140. #define MCU_BORW_EN 0x4000
  141. /* PLA_CPCR */
  142. #define CPCR_RX_VLAN 0x0040
  143. /* PLA_CFG_WOL */
  144. #define MAGIC_EN 0x0001
  145. /* PAL_BDC_CR */
  146. #define ALDPS_PROXY_MODE 0x0001
  147. /* PLA_CONFIG5 */
  148. #define LAN_WAKE_EN 0x0002
  149. /* PLA_LED_FEATURE */
  150. #define LED_MODE_MASK 0x0700
  151. /* PLA_PHY_PWR */
  152. #define TX_10M_IDLE_EN 0x0080
  153. #define PFM_PWM_SWITCH 0x0040
  154. /* PLA_MAC_PWR_CTRL */
  155. #define D3_CLK_GATED_EN 0x00004000
  156. #define MCU_CLK_RATIO 0x07010f07
  157. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  158. /* PLA_GPHY_INTR_IMR */
  159. #define GPHY_STS_MSK 0x0001
  160. #define SPEED_DOWN_MSK 0x0002
  161. #define SPDWN_RXDV_MSK 0x0004
  162. #define SPDWN_LINKCHG_MSK 0x0008
  163. /* PLA_PHYAR */
  164. #define PHYAR_FLAG 0x80000000
  165. /* PLA_EEE_CR */
  166. #define EEE_RX_EN 0x0001
  167. #define EEE_TX_EN 0x0002
  168. /* USB_DEV_STAT */
  169. #define STAT_SPEED_MASK 0x0006
  170. #define STAT_SPEED_HIGH 0x0000
  171. #define STAT_SPEED_FULL 0x0001
  172. /* USB_TX_AGG */
  173. #define TX_AGG_MAX_THRESHOLD 0x03
  174. /* USB_RX_BUF_TH */
  175. #define RX_BUF_THR 0x7a120180
  176. /* USB_TX_DMA */
  177. #define TEST_MODE_DISABLE 0x00000001
  178. #define TX_SIZE_ADJUST1 0x00000100
  179. /* USB_UPS_CTRL */
  180. #define POWER_CUT 0x0100
  181. /* USB_PM_CTRL_STATUS */
  182. #define RWSUME_INDICATE 0x0001
  183. /* USB_USB_CTRL */
  184. #define RX_AGG_DISABLE 0x0010
  185. /* OCP_ALDPS_CONFIG */
  186. #define ENPWRSAVE 0x8000
  187. #define ENPDNPS 0x0200
  188. #define LINKENA 0x0100
  189. #define DIS_SDSAVE 0x0010
  190. /* OCP_EEE_CONFIG1 */
  191. #define RG_TXLPI_MSK_HFDUP 0x8000
  192. #define RG_MATCLR_EN 0x4000
  193. #define EEE_10_CAP 0x2000
  194. #define EEE_NWAY_EN 0x1000
  195. #define TX_QUIET_EN 0x0200
  196. #define RX_QUIET_EN 0x0100
  197. #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
  198. #define RG_RXLPI_MSK_HFDUP 0x0008
  199. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  200. /* OCP_EEE_CONFIG2 */
  201. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  202. #define RG_DACQUIET_EN 0x0400
  203. #define RG_LDVQUIET_EN 0x0200
  204. #define RG_CKRSEL 0x0020
  205. #define RG_EEEPRG_EN 0x0010
  206. /* OCP_EEE_CONFIG3 */
  207. #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
  208. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  209. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  210. /* OCP_EEE_AR */
  211. /* bit[15:14] function */
  212. #define FUN_ADDR 0x0000
  213. #define FUN_DATA 0x4000
  214. /* bit[4:0] device addr */
  215. #define DEVICE_ADDR 0x0007
  216. /* OCP_EEE_DATA */
  217. #define EEE_ADDR 0x003C
  218. #define EEE_DATA 0x0002
  219. enum rtl_register_content {
  220. _100bps = 0x08,
  221. _10bps = 0x04,
  222. LINK_STATUS = 0x02,
  223. FULL_DUP = 0x01,
  224. };
  225. #define RTL8152_REQT_READ 0xc0
  226. #define RTL8152_REQT_WRITE 0x40
  227. #define RTL8152_REQ_GET_REGS 0x05
  228. #define RTL8152_REQ_SET_REGS 0x05
  229. #define BYTE_EN_DWORD 0xff
  230. #define BYTE_EN_WORD 0x33
  231. #define BYTE_EN_BYTE 0x11
  232. #define BYTE_EN_SIX_BYTES 0x3f
  233. #define BYTE_EN_START_MASK 0x0f
  234. #define BYTE_EN_END_MASK 0xf0
  235. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  236. #define RTL8152_TX_TIMEOUT (HZ)
  237. /* rtl8152 flags */
  238. enum rtl8152_flags {
  239. RTL8152_UNPLUG = 0,
  240. RX_URB_FAIL,
  241. RTL8152_SET_RX_MODE,
  242. WORK_ENABLE
  243. };
  244. /* Define these values to match your device */
  245. #define VENDOR_ID_REALTEK 0x0bda
  246. #define PRODUCT_ID_RTL8152 0x8152
  247. #define MCU_TYPE_PLA 0x0100
  248. #define MCU_TYPE_USB 0x0000
  249. struct rx_desc {
  250. u32 opts1;
  251. #define RX_LEN_MASK 0x7fff
  252. u32 opts2;
  253. u32 opts3;
  254. u32 opts4;
  255. u32 opts5;
  256. u32 opts6;
  257. };
  258. struct tx_desc {
  259. u32 opts1;
  260. #define TX_FS (1 << 31) /* First segment of a packet */
  261. #define TX_LS (1 << 30) /* Final segment of a packet */
  262. #define TX_LEN_MASK 0xffff
  263. u32 opts2;
  264. };
  265. struct r8152 {
  266. unsigned long flags;
  267. struct usb_device *udev;
  268. struct tasklet_struct tl;
  269. struct net_device *netdev;
  270. struct urb *rx_urb, *tx_urb;
  271. struct sk_buff *tx_skb, *rx_skb;
  272. struct delayed_work schedule;
  273. struct mii_if_info mii;
  274. u32 msg_enable;
  275. u16 ocp_base;
  276. u8 version;
  277. u8 speed;
  278. };
  279. enum rtl_version {
  280. RTL_VER_UNKNOWN = 0,
  281. RTL_VER_01,
  282. RTL_VER_02
  283. };
  284. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  285. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  286. */
  287. static const int multicast_filter_limit = 32;
  288. static
  289. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  290. {
  291. int ret;
  292. void *tmp;
  293. tmp = kmalloc(size, GFP_KERNEL);
  294. if (!tmp)
  295. return -ENOMEM;
  296. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  297. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  298. value, index, tmp, size, 500);
  299. memcpy(data, tmp, size);
  300. kfree(tmp);
  301. return ret;
  302. }
  303. static
  304. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  305. {
  306. int ret;
  307. void *tmp;
  308. tmp = kmalloc(size, GFP_KERNEL);
  309. if (!tmp)
  310. return -ENOMEM;
  311. memcpy(tmp, data, size);
  312. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  313. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  314. value, index, tmp, size, 500);
  315. kfree(tmp);
  316. return ret;
  317. }
  318. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  319. void *data, u16 type)
  320. {
  321. u16 limit = 64;
  322. int ret = 0;
  323. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  324. return -ENODEV;
  325. /* both size and indix must be 4 bytes align */
  326. if ((size & 3) || !size || (index & 3) || !data)
  327. return -EPERM;
  328. if ((u32)index + (u32)size > 0xffff)
  329. return -EPERM;
  330. while (size) {
  331. if (size > limit) {
  332. ret = get_registers(tp, index, type, limit, data);
  333. if (ret < 0)
  334. break;
  335. index += limit;
  336. data += limit;
  337. size -= limit;
  338. } else {
  339. ret = get_registers(tp, index, type, size, data);
  340. if (ret < 0)
  341. break;
  342. index += size;
  343. data += size;
  344. size = 0;
  345. break;
  346. }
  347. }
  348. return ret;
  349. }
  350. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  351. u16 size, void *data, u16 type)
  352. {
  353. int ret;
  354. u16 byteen_start, byteen_end, byen;
  355. u16 limit = 512;
  356. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  357. return -ENODEV;
  358. /* both size and indix must be 4 bytes align */
  359. if ((size & 3) || !size || (index & 3) || !data)
  360. return -EPERM;
  361. if ((u32)index + (u32)size > 0xffff)
  362. return -EPERM;
  363. byteen_start = byteen & BYTE_EN_START_MASK;
  364. byteen_end = byteen & BYTE_EN_END_MASK;
  365. byen = byteen_start | (byteen_start << 4);
  366. ret = set_registers(tp, index, type | byen, 4, data);
  367. if (ret < 0)
  368. goto error1;
  369. index += 4;
  370. data += 4;
  371. size -= 4;
  372. if (size) {
  373. size -= 4;
  374. while (size) {
  375. if (size > limit) {
  376. ret = set_registers(tp, index,
  377. type | BYTE_EN_DWORD,
  378. limit, data);
  379. if (ret < 0)
  380. goto error1;
  381. index += limit;
  382. data += limit;
  383. size -= limit;
  384. } else {
  385. ret = set_registers(tp, index,
  386. type | BYTE_EN_DWORD,
  387. size, data);
  388. if (ret < 0)
  389. goto error1;
  390. index += size;
  391. data += size;
  392. size = 0;
  393. break;
  394. }
  395. }
  396. byen = byteen_end | (byteen_end >> 4);
  397. ret = set_registers(tp, index, type | byen, 4, data);
  398. if (ret < 0)
  399. goto error1;
  400. }
  401. error1:
  402. return ret;
  403. }
  404. static inline
  405. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  406. {
  407. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  408. }
  409. static inline
  410. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  411. {
  412. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  413. }
  414. static inline
  415. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  416. {
  417. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  418. }
  419. static inline
  420. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  421. {
  422. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  423. }
  424. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  425. {
  426. u32 data;
  427. if (type == MCU_TYPE_PLA)
  428. pla_ocp_read(tp, index, sizeof(data), &data);
  429. else
  430. usb_ocp_read(tp, index, sizeof(data), &data);
  431. return __le32_to_cpu(data);
  432. }
  433. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  434. {
  435. if (type == MCU_TYPE_PLA)
  436. pla_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(data), &data);
  437. else
  438. usb_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(data), &data);
  439. }
  440. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  441. {
  442. u32 data;
  443. u8 shift = index & 2;
  444. index &= ~3;
  445. if (type == MCU_TYPE_PLA)
  446. pla_ocp_read(tp, index, sizeof(data), &data);
  447. else
  448. usb_ocp_read(tp, index, sizeof(data), &data);
  449. data = __le32_to_cpu(data);
  450. data >>= (shift * 8);
  451. data &= 0xffff;
  452. return (u16)data;
  453. }
  454. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  455. {
  456. u32 tmp, mask = 0xffff;
  457. u16 byen = BYTE_EN_WORD;
  458. u8 shift = index & 2;
  459. data &= mask;
  460. if (index & 2) {
  461. byen <<= shift;
  462. mask <<= (shift * 8);
  463. data <<= (shift * 8);
  464. index &= ~3;
  465. }
  466. if (type == MCU_TYPE_PLA)
  467. pla_ocp_read(tp, index, sizeof(tmp), &tmp);
  468. else
  469. usb_ocp_read(tp, index, sizeof(tmp), &tmp);
  470. tmp = __le32_to_cpu(tmp) & ~mask;
  471. tmp |= data;
  472. tmp = __cpu_to_le32(tmp);
  473. if (type == MCU_TYPE_PLA)
  474. pla_ocp_write(tp, index, byen, sizeof(tmp), &tmp);
  475. else
  476. usb_ocp_write(tp, index, byen, sizeof(tmp), &tmp);
  477. }
  478. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  479. {
  480. u32 data;
  481. u8 shift = index & 3;
  482. index &= ~3;
  483. if (type == MCU_TYPE_PLA)
  484. pla_ocp_read(tp, index, sizeof(data), &data);
  485. else
  486. usb_ocp_read(tp, index, sizeof(data), &data);
  487. data = __le32_to_cpu(data);
  488. data >>= (shift * 8);
  489. data &= 0xff;
  490. return (u8)data;
  491. }
  492. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  493. {
  494. u32 tmp, mask = 0xff;
  495. u16 byen = BYTE_EN_BYTE;
  496. u8 shift = index & 3;
  497. data &= mask;
  498. if (index & 3) {
  499. byen <<= shift;
  500. mask <<= (shift * 8);
  501. data <<= (shift * 8);
  502. index &= ~3;
  503. }
  504. if (type == MCU_TYPE_PLA)
  505. pla_ocp_read(tp, index, sizeof(tmp), &tmp);
  506. else
  507. usb_ocp_read(tp, index, sizeof(tmp), &tmp);
  508. tmp = __le32_to_cpu(tmp) & ~mask;
  509. tmp |= data;
  510. tmp = __cpu_to_le32(tmp);
  511. if (type == MCU_TYPE_PLA)
  512. pla_ocp_write(tp, index, byen, sizeof(tmp), &tmp);
  513. else
  514. usb_ocp_write(tp, index, byen, sizeof(tmp), &tmp);
  515. }
  516. static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  517. {
  518. u32 ocp_data;
  519. int i;
  520. ocp_data = PHYAR_FLAG | ((reg_addr & 0x1f) << 16) |
  521. (value & 0xffff);
  522. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  523. for (i = 20; i > 0; i--) {
  524. udelay(25);
  525. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  526. if (!(ocp_data & PHYAR_FLAG))
  527. break;
  528. }
  529. udelay(20);
  530. }
  531. static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  532. {
  533. u32 ocp_data;
  534. int i;
  535. ocp_data = (reg_addr & 0x1f) << 16;
  536. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_PHYAR, ocp_data);
  537. for (i = 20; i > 0; i--) {
  538. udelay(25);
  539. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_PHYAR);
  540. if (ocp_data & PHYAR_FLAG)
  541. break;
  542. }
  543. udelay(20);
  544. if (!(ocp_data & PHYAR_FLAG))
  545. return -EAGAIN;
  546. return (u16)(ocp_data & 0xffff);
  547. }
  548. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  549. {
  550. struct r8152 *tp = netdev_priv(netdev);
  551. if (phy_id != R8152_PHY_ID)
  552. return -EINVAL;
  553. return r8152_mdio_read(tp, reg);
  554. }
  555. static
  556. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  557. {
  558. struct r8152 *tp = netdev_priv(netdev);
  559. if (phy_id != R8152_PHY_ID)
  560. return;
  561. r8152_mdio_write(tp, reg, val);
  562. }
  563. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  564. {
  565. u16 ocp_base, ocp_index;
  566. ocp_base = addr & 0xf000;
  567. if (ocp_base != tp->ocp_base) {
  568. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  569. tp->ocp_base = ocp_base;
  570. }
  571. ocp_index = (addr & 0x0fff) | 0xb000;
  572. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  573. }
  574. static inline void set_ethernet_addr(struct r8152 *tp)
  575. {
  576. struct net_device *dev = tp->netdev;
  577. u8 node_id[8] = {0};
  578. if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
  579. netif_notice(tp, probe, dev, "inet addr fail\n");
  580. else {
  581. memcpy(dev->dev_addr, node_id, dev->addr_len);
  582. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  583. }
  584. }
  585. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  586. {
  587. struct r8152 *tp = netdev_priv(netdev);
  588. struct sockaddr *addr = p;
  589. if (!is_valid_ether_addr(addr->sa_data))
  590. return -EADDRNOTAVAIL;
  591. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  592. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  593. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  594. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  595. return 0;
  596. }
  597. static int alloc_all_urbs(struct r8152 *tp)
  598. {
  599. tp->rx_urb = usb_alloc_urb(0, GFP_KERNEL);
  600. if (!tp->rx_urb)
  601. return 0;
  602. tp->tx_urb = usb_alloc_urb(0, GFP_KERNEL);
  603. if (!tp->tx_urb) {
  604. usb_free_urb(tp->rx_urb);
  605. return 0;
  606. }
  607. return 1;
  608. }
  609. static void free_all_urbs(struct r8152 *tp)
  610. {
  611. usb_free_urb(tp->rx_urb);
  612. usb_free_urb(tp->tx_urb);
  613. }
  614. static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
  615. {
  616. return &dev->stats;
  617. }
  618. static void read_bulk_callback(struct urb *urb)
  619. {
  620. struct r8152 *tp;
  621. unsigned pkt_len;
  622. struct sk_buff *skb;
  623. struct net_device *netdev;
  624. struct net_device_stats *stats;
  625. int status = urb->status;
  626. int result;
  627. struct rx_desc *rx_desc;
  628. tp = urb->context;
  629. if (!tp)
  630. return;
  631. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  632. return;
  633. netdev = tp->netdev;
  634. if (!netif_device_present(netdev))
  635. return;
  636. stats = rtl8152_get_stats(netdev);
  637. switch (status) {
  638. case 0:
  639. break;
  640. case -ESHUTDOWN:
  641. set_bit(RTL8152_UNPLUG, &tp->flags);
  642. netif_device_detach(tp->netdev);
  643. case -ENOENT:
  644. return; /* the urb is in unlink state */
  645. case -ETIME:
  646. pr_warn_ratelimited("may be reset is needed?..\n");
  647. goto goon;
  648. default:
  649. pr_warn_ratelimited("Rx status %d\n", status);
  650. goto goon;
  651. }
  652. /* protect against short packets (tell me why we got some?!?) */
  653. if (urb->actual_length < sizeof(*rx_desc))
  654. goto goon;
  655. rx_desc = (struct rx_desc *)urb->transfer_buffer;
  656. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  657. if (urb->actual_length < sizeof(struct rx_desc) + pkt_len)
  658. goto goon;
  659. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  660. if (!skb)
  661. goto goon;
  662. memcpy(skb->data, tp->rx_skb->data + sizeof(struct rx_desc), pkt_len);
  663. skb_put(skb, pkt_len);
  664. skb->protocol = eth_type_trans(skb, netdev);
  665. netif_rx(skb);
  666. stats->rx_packets++;
  667. stats->rx_bytes += pkt_len;
  668. goon:
  669. usb_fill_bulk_urb(tp->rx_urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  670. tp->rx_skb->data, RTL8152_RMS + sizeof(struct rx_desc),
  671. (usb_complete_t)read_bulk_callback, tp);
  672. result = usb_submit_urb(tp->rx_urb, GFP_ATOMIC);
  673. if (result == -ENODEV) {
  674. netif_device_detach(tp->netdev);
  675. } else if (result) {
  676. set_bit(RX_URB_FAIL, &tp->flags);
  677. goto resched;
  678. } else {
  679. clear_bit(RX_URB_FAIL, &tp->flags);
  680. }
  681. return;
  682. resched:
  683. tasklet_schedule(&tp->tl);
  684. }
  685. static void rx_fixup(unsigned long data)
  686. {
  687. struct r8152 *tp;
  688. int status;
  689. tp = (struct r8152 *)data;
  690. if (!test_bit(WORK_ENABLE, &tp->flags))
  691. return;
  692. status = usb_submit_urb(tp->rx_urb, GFP_ATOMIC);
  693. if (status == -ENODEV) {
  694. netif_device_detach(tp->netdev);
  695. } else if (status) {
  696. set_bit(RX_URB_FAIL, &tp->flags);
  697. goto tlsched;
  698. } else {
  699. clear_bit(RX_URB_FAIL, &tp->flags);
  700. }
  701. return;
  702. tlsched:
  703. tasklet_schedule(&tp->tl);
  704. }
  705. static void write_bulk_callback(struct urb *urb)
  706. {
  707. struct r8152 *tp;
  708. int status = urb->status;
  709. tp = urb->context;
  710. if (!tp)
  711. return;
  712. dev_kfree_skb_irq(tp->tx_skb);
  713. if (!netif_device_present(tp->netdev))
  714. return;
  715. if (status)
  716. dev_info(&urb->dev->dev, "%s: Tx status %d\n",
  717. tp->netdev->name, status);
  718. tp->netdev->trans_start = jiffies;
  719. netif_wake_queue(tp->netdev);
  720. }
  721. static void rtl8152_tx_timeout(struct net_device *netdev)
  722. {
  723. struct r8152 *tp = netdev_priv(netdev);
  724. struct net_device_stats *stats = rtl8152_get_stats(netdev);
  725. netif_warn(tp, tx_err, netdev, "Tx timeout.\n");
  726. usb_unlink_urb(tp->tx_urb);
  727. stats->tx_errors++;
  728. }
  729. static void rtl8152_set_rx_mode(struct net_device *netdev)
  730. {
  731. struct r8152 *tp = netdev_priv(netdev);
  732. if (tp->speed & LINK_STATUS)
  733. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  734. }
  735. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  736. {
  737. struct r8152 *tp = netdev_priv(netdev);
  738. u32 mc_filter[2]; /* Multicast hash filter */
  739. __le32 tmp[2];
  740. u32 ocp_data;
  741. clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
  742. netif_stop_queue(netdev);
  743. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  744. ocp_data &= ~RCR_ACPT_ALL;
  745. ocp_data |= RCR_AB | RCR_APM;
  746. if (netdev->flags & IFF_PROMISC) {
  747. /* Unconditionally log net taps. */
  748. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  749. ocp_data |= RCR_AM | RCR_AAP;
  750. mc_filter[1] = mc_filter[0] = 0xffffffff;
  751. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  752. (netdev->flags & IFF_ALLMULTI)) {
  753. /* Too many to filter perfectly -- accept all multicasts. */
  754. ocp_data |= RCR_AM;
  755. mc_filter[1] = mc_filter[0] = 0xffffffff;
  756. } else {
  757. struct netdev_hw_addr *ha;
  758. mc_filter[1] = mc_filter[0] = 0;
  759. netdev_for_each_mc_addr(ha, netdev) {
  760. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  761. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  762. ocp_data |= RCR_AM;
  763. }
  764. }
  765. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  766. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  767. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  768. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  769. netif_wake_queue(netdev);
  770. }
  771. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  772. struct net_device *netdev)
  773. {
  774. struct r8152 *tp = netdev_priv(netdev);
  775. struct net_device_stats *stats = rtl8152_get_stats(netdev);
  776. struct tx_desc *tx_desc;
  777. unsigned int len;
  778. int res;
  779. netif_stop_queue(netdev);
  780. len = skb->len;
  781. if (skb_header_cloned(skb) || skb_headroom(skb) < sizeof(*tx_desc)) {
  782. struct sk_buff *tx_skb;
  783. tx_skb = skb_copy_expand(skb, sizeof(*tx_desc), 0, GFP_ATOMIC);
  784. dev_kfree_skb_any(skb);
  785. if (!tx_skb) {
  786. stats->tx_dropped++;
  787. netif_wake_queue(netdev);
  788. return NETDEV_TX_OK;
  789. }
  790. skb = tx_skb;
  791. }
  792. tx_desc = (struct tx_desc *)skb_push(skb, sizeof(*tx_desc));
  793. memset(tx_desc, 0, sizeof(*tx_desc));
  794. tx_desc->opts1 = cpu_to_le32((len & TX_LEN_MASK) | TX_FS | TX_LS);
  795. tp->tx_skb = skb;
  796. skb_tx_timestamp(skb);
  797. usb_fill_bulk_urb(tp->tx_urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  798. skb->data, skb->len,
  799. (usb_complete_t)write_bulk_callback, tp);
  800. res = usb_submit_urb(tp->tx_urb, GFP_ATOMIC);
  801. if (res) {
  802. /* Can we get/handle EPIPE here? */
  803. if (res == -ENODEV) {
  804. netif_device_detach(tp->netdev);
  805. } else {
  806. netif_warn(tp, tx_err, netdev,
  807. "failed tx_urb %d\n", res);
  808. stats->tx_errors++;
  809. netif_start_queue(netdev);
  810. }
  811. } else {
  812. stats->tx_packets++;
  813. stats->tx_bytes += skb->len;
  814. }
  815. return NETDEV_TX_OK;
  816. }
  817. static void r8152b_reset_packet_filter(struct r8152 *tp)
  818. {
  819. u32 ocp_data;
  820. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  821. ocp_data &= ~FMC_FCR_MCU_EN;
  822. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  823. ocp_data |= FMC_FCR_MCU_EN;
  824. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  825. }
  826. static void rtl8152_nic_reset(struct r8152 *tp)
  827. {
  828. int i;
  829. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  830. for (i = 0; i < 1000; i++) {
  831. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  832. break;
  833. udelay(100);
  834. }
  835. }
  836. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  837. {
  838. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  839. }
  840. static int rtl8152_enable(struct r8152 *tp)
  841. {
  842. u32 ocp_data;
  843. u8 speed;
  844. speed = rtl8152_get_speed(tp);
  845. if (speed & _100bps) {
  846. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  847. ocp_data &= ~EEEP_CR_EEEP_TX;
  848. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  849. } else {
  850. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  851. ocp_data |= EEEP_CR_EEEP_TX;
  852. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  853. }
  854. r8152b_reset_packet_filter(tp);
  855. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  856. ocp_data |= CR_RE | CR_TE;
  857. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  858. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  859. ocp_data &= ~RXDY_GATED_EN;
  860. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  861. usb_fill_bulk_urb(tp->rx_urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  862. tp->rx_skb->data, RTL8152_RMS + sizeof(struct rx_desc),
  863. (usb_complete_t)read_bulk_callback, tp);
  864. return usb_submit_urb(tp->rx_urb, GFP_KERNEL);
  865. }
  866. static void rtl8152_disable(struct r8152 *tp)
  867. {
  868. u32 ocp_data;
  869. int i;
  870. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  871. ocp_data &= ~RCR_ACPT_ALL;
  872. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  873. usb_kill_urb(tp->tx_urb);
  874. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  875. ocp_data |= RXDY_GATED_EN;
  876. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  877. for (i = 0; i < 1000; i++) {
  878. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  879. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  880. break;
  881. mdelay(1);
  882. }
  883. for (i = 0; i < 1000; i++) {
  884. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  885. break;
  886. mdelay(1);
  887. }
  888. usb_kill_urb(tp->rx_urb);
  889. rtl8152_nic_reset(tp);
  890. }
  891. static void r8152b_exit_oob(struct r8152 *tp)
  892. {
  893. u32 ocp_data;
  894. int i;
  895. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  896. ocp_data &= ~RCR_ACPT_ALL;
  897. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  898. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  899. ocp_data |= RXDY_GATED_EN;
  900. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  901. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  902. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  903. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  904. ocp_data &= ~NOW_IS_OOB;
  905. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  906. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  907. ocp_data &= ~MCU_BORW_EN;
  908. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  909. for (i = 0; i < 1000; i++) {
  910. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  911. if (ocp_data & LINK_LIST_READY)
  912. break;
  913. mdelay(1);
  914. }
  915. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  916. ocp_data |= RE_INIT_LL;
  917. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  918. for (i = 0; i < 1000; i++) {
  919. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  920. if (ocp_data & LINK_LIST_READY)
  921. break;
  922. mdelay(1);
  923. }
  924. rtl8152_nic_reset(tp);
  925. /* rx share fifo credit full threshold */
  926. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  927. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
  928. ocp_data &= STAT_SPEED_MASK;
  929. if (ocp_data == STAT_SPEED_FULL) {
  930. /* rx share fifo credit near full threshold */
  931. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  932. RXFIFO_THR2_FULL);
  933. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  934. RXFIFO_THR3_FULL);
  935. } else {
  936. /* rx share fifo credit near full threshold */
  937. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  938. RXFIFO_THR2_HIGH);
  939. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  940. RXFIFO_THR3_HIGH);
  941. }
  942. /* TX share fifo free credit full threshold */
  943. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  944. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  945. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_BUF_THR);
  946. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  947. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  948. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  949. ocp_data &= ~CPCR_RX_VLAN;
  950. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  951. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  952. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  953. ocp_data |= TCR0_AUTO_FIFO;
  954. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  955. }
  956. static void r8152b_enter_oob(struct r8152 *tp)
  957. {
  958. u32 ocp_data;
  959. int i;
  960. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  961. ocp_data &= ~NOW_IS_OOB;
  962. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  963. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  964. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  965. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  966. rtl8152_disable(tp);
  967. for (i = 0; i < 1000; i++) {
  968. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  969. if (ocp_data & LINK_LIST_READY)
  970. break;
  971. mdelay(1);
  972. }
  973. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  974. ocp_data |= RE_INIT_LL;
  975. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  976. for (i = 0; i < 1000; i++) {
  977. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  978. if (ocp_data & LINK_LIST_READY)
  979. break;
  980. mdelay(1);
  981. }
  982. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  983. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  984. ocp_data |= MAGIC_EN;
  985. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  986. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  987. ocp_data |= CPCR_RX_VLAN;
  988. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  989. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  990. ocp_data |= ALDPS_PROXY_MODE;
  991. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  992. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  993. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  994. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  995. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
  996. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  997. ocp_data &= ~RXDY_GATED_EN;
  998. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  999. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1000. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  1001. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1002. }
  1003. static void r8152b_disable_aldps(struct r8152 *tp)
  1004. {
  1005. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1006. msleep(20);
  1007. }
  1008. static inline void r8152b_enable_aldps(struct r8152 *tp)
  1009. {
  1010. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1011. LINKENA | DIS_SDSAVE);
  1012. }
  1013. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  1014. {
  1015. u16 bmcr, anar;
  1016. int ret = 0;
  1017. cancel_delayed_work_sync(&tp->schedule);
  1018. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1019. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1020. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1021. if (autoneg == AUTONEG_DISABLE) {
  1022. if (speed == SPEED_10) {
  1023. bmcr = 0;
  1024. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1025. } else if (speed == SPEED_100) {
  1026. bmcr = BMCR_SPEED100;
  1027. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1028. } else {
  1029. ret = -EINVAL;
  1030. goto out;
  1031. }
  1032. if (duplex == DUPLEX_FULL)
  1033. bmcr |= BMCR_FULLDPLX;
  1034. } else {
  1035. if (speed == SPEED_10) {
  1036. if (duplex == DUPLEX_FULL)
  1037. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1038. else
  1039. anar |= ADVERTISE_10HALF;
  1040. } else if (speed == SPEED_100) {
  1041. if (duplex == DUPLEX_FULL) {
  1042. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1043. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1044. } else {
  1045. anar |= ADVERTISE_10HALF;
  1046. anar |= ADVERTISE_100HALF;
  1047. }
  1048. } else {
  1049. ret = -EINVAL;
  1050. goto out;
  1051. }
  1052. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  1053. }
  1054. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1055. r8152_mdio_write(tp, MII_BMCR, bmcr);
  1056. out:
  1057. schedule_delayed_work(&tp->schedule, 5 * HZ);
  1058. return ret;
  1059. }
  1060. static void rtl8152_down(struct r8152 *tp)
  1061. {
  1062. u32 ocp_data;
  1063. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1064. ocp_data &= ~POWER_CUT;
  1065. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1066. r8152b_disable_aldps(tp);
  1067. r8152b_enter_oob(tp);
  1068. r8152b_enable_aldps(tp);
  1069. }
  1070. static void set_carrier(struct r8152 *tp)
  1071. {
  1072. struct net_device *netdev = tp->netdev;
  1073. u8 speed;
  1074. speed = rtl8152_get_speed(tp);
  1075. if (speed & LINK_STATUS) {
  1076. if (!(tp->speed & LINK_STATUS)) {
  1077. rtl8152_enable(tp);
  1078. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1079. netif_carrier_on(netdev);
  1080. }
  1081. } else {
  1082. if (tp->speed & LINK_STATUS) {
  1083. netif_carrier_off(netdev);
  1084. rtl8152_disable(tp);
  1085. }
  1086. }
  1087. tp->speed = speed;
  1088. }
  1089. static void rtl_work_func_t(struct work_struct *work)
  1090. {
  1091. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  1092. if (!test_bit(WORK_ENABLE, &tp->flags))
  1093. goto out1;
  1094. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1095. goto out1;
  1096. set_carrier(tp);
  1097. if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
  1098. _rtl8152_set_rx_mode(tp->netdev);
  1099. schedule_delayed_work(&tp->schedule, HZ);
  1100. out1:
  1101. return;
  1102. }
  1103. static int rtl8152_open(struct net_device *netdev)
  1104. {
  1105. struct r8152 *tp = netdev_priv(netdev);
  1106. int res = 0;
  1107. tp->speed = rtl8152_get_speed(tp);
  1108. if (tp->speed & LINK_STATUS) {
  1109. res = rtl8152_enable(tp);
  1110. if (res) {
  1111. if (res == -ENODEV)
  1112. netif_device_detach(tp->netdev);
  1113. netif_err(tp, ifup, netdev,
  1114. "rtl8152_open failed: %d\n", res);
  1115. return res;
  1116. }
  1117. netif_carrier_on(netdev);
  1118. } else {
  1119. netif_stop_queue(netdev);
  1120. netif_carrier_off(netdev);
  1121. }
  1122. rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL);
  1123. netif_start_queue(netdev);
  1124. set_bit(WORK_ENABLE, &tp->flags);
  1125. schedule_delayed_work(&tp->schedule, 0);
  1126. return res;
  1127. }
  1128. static int rtl8152_close(struct net_device *netdev)
  1129. {
  1130. struct r8152 *tp = netdev_priv(netdev);
  1131. int res = 0;
  1132. clear_bit(WORK_ENABLE, &tp->flags);
  1133. cancel_delayed_work_sync(&tp->schedule);
  1134. netif_stop_queue(netdev);
  1135. rtl8152_disable(tp);
  1136. return res;
  1137. }
  1138. static void rtl_clear_bp(struct r8152 *tp)
  1139. {
  1140. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
  1141. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
  1142. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
  1143. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
  1144. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
  1145. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
  1146. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
  1147. ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
  1148. mdelay(3);
  1149. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
  1150. ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
  1151. }
  1152. static void r8152b_enable_eee(struct r8152 *tp)
  1153. {
  1154. u32 ocp_data;
  1155. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  1156. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  1157. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  1158. ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
  1159. EEE_10_CAP | EEE_NWAY_EN |
  1160. TX_QUIET_EN | RX_QUIET_EN |
  1161. SDRISETIME | RG_RXLPI_MSK_HFDUP |
  1162. SDFALLTIME);
  1163. ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
  1164. RG_LDVQUIET_EN | RG_CKRSEL |
  1165. RG_EEEPRG_EN);
  1166. ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
  1167. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
  1168. ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
  1169. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
  1170. ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
  1171. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  1172. }
  1173. static void r8152b_enable_fc(struct r8152 *tp)
  1174. {
  1175. u16 anar;
  1176. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1177. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1178. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1179. }
  1180. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1181. {
  1182. r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
  1183. r8152b_disable_aldps(tp);
  1184. }
  1185. static void r8152b_init(struct r8152 *tp)
  1186. {
  1187. u32 ocp_data;
  1188. int i;
  1189. rtl_clear_bp(tp);
  1190. if (tp->version == RTL_VER_01) {
  1191. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  1192. ocp_data &= ~LED_MODE_MASK;
  1193. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  1194. }
  1195. r8152b_hw_phy_cfg(tp);
  1196. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1197. ocp_data &= ~POWER_CUT;
  1198. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1199. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1200. ocp_data &= ~RWSUME_INDICATE;
  1201. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1202. r8152b_exit_oob(tp);
  1203. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  1204. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  1205. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  1206. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  1207. ocp_data &= ~MCU_CLK_RATIO_MASK;
  1208. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  1209. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  1210. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  1211. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  1212. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  1213. r8152b_enable_eee(tp);
  1214. r8152b_enable_aldps(tp);
  1215. r8152b_enable_fc(tp);
  1216. r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
  1217. BMCR_ANRESTART);
  1218. for (i = 0; i < 100; i++) {
  1219. udelay(100);
  1220. if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
  1221. break;
  1222. }
  1223. /* disable rx aggregation */
  1224. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1225. ocp_data |= RX_AGG_DISABLE;
  1226. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1227. }
  1228. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  1229. {
  1230. struct r8152 *tp = usb_get_intfdata(intf);
  1231. netif_device_detach(tp->netdev);
  1232. if (netif_running(tp->netdev)) {
  1233. clear_bit(WORK_ENABLE, &tp->flags);
  1234. cancel_delayed_work_sync(&tp->schedule);
  1235. }
  1236. rtl8152_down(tp);
  1237. return 0;
  1238. }
  1239. static int rtl8152_resume(struct usb_interface *intf)
  1240. {
  1241. struct r8152 *tp = usb_get_intfdata(intf);
  1242. r8152b_init(tp);
  1243. netif_device_attach(tp->netdev);
  1244. if (netif_running(tp->netdev)) {
  1245. rtl8152_enable(tp);
  1246. set_bit(WORK_ENABLE, &tp->flags);
  1247. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1248. schedule_delayed_work(&tp->schedule, 0);
  1249. }
  1250. return 0;
  1251. }
  1252. static void rtl8152_get_drvinfo(struct net_device *netdev,
  1253. struct ethtool_drvinfo *info)
  1254. {
  1255. struct r8152 *tp = netdev_priv(netdev);
  1256. strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
  1257. strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
  1258. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  1259. }
  1260. static
  1261. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  1262. {
  1263. struct r8152 *tp = netdev_priv(netdev);
  1264. if (!tp->mii.mdio_read)
  1265. return -EOPNOTSUPP;
  1266. return mii_ethtool_gset(&tp->mii, cmd);
  1267. }
  1268. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1269. {
  1270. struct r8152 *tp = netdev_priv(dev);
  1271. return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  1272. }
  1273. static struct ethtool_ops ops = {
  1274. .get_drvinfo = rtl8152_get_drvinfo,
  1275. .get_settings = rtl8152_get_settings,
  1276. .set_settings = rtl8152_set_settings,
  1277. .get_link = ethtool_op_get_link,
  1278. };
  1279. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  1280. {
  1281. struct r8152 *tp = netdev_priv(netdev);
  1282. struct mii_ioctl_data *data = if_mii(rq);
  1283. int res = 0;
  1284. switch (cmd) {
  1285. case SIOCGMIIPHY:
  1286. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  1287. break;
  1288. case SIOCGMIIREG:
  1289. data->val_out = r8152_mdio_read(tp, data->reg_num);
  1290. break;
  1291. case SIOCSMIIREG:
  1292. if (!capable(CAP_NET_ADMIN)) {
  1293. res = -EPERM;
  1294. break;
  1295. }
  1296. r8152_mdio_write(tp, data->reg_num, data->val_in);
  1297. break;
  1298. default:
  1299. res = -EOPNOTSUPP;
  1300. }
  1301. return res;
  1302. }
  1303. static const struct net_device_ops rtl8152_netdev_ops = {
  1304. .ndo_open = rtl8152_open,
  1305. .ndo_stop = rtl8152_close,
  1306. .ndo_do_ioctl = rtl8152_ioctl,
  1307. .ndo_start_xmit = rtl8152_start_xmit,
  1308. .ndo_tx_timeout = rtl8152_tx_timeout,
  1309. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  1310. .ndo_set_mac_address = rtl8152_set_mac_address,
  1311. .ndo_change_mtu = eth_change_mtu,
  1312. .ndo_validate_addr = eth_validate_addr,
  1313. };
  1314. static void r8152b_get_version(struct r8152 *tp)
  1315. {
  1316. u32 ocp_data;
  1317. u16 version;
  1318. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  1319. version = (u16)(ocp_data & VERSION_MASK);
  1320. switch (version) {
  1321. case 0x4c00:
  1322. tp->version = RTL_VER_01;
  1323. break;
  1324. case 0x4c10:
  1325. tp->version = RTL_VER_02;
  1326. break;
  1327. default:
  1328. netif_info(tp, probe, tp->netdev,
  1329. "Unknown version 0x%04x\n", version);
  1330. break;
  1331. }
  1332. }
  1333. static int rtl8152_probe(struct usb_interface *intf,
  1334. const struct usb_device_id *id)
  1335. {
  1336. struct usb_device *udev = interface_to_usbdev(intf);
  1337. struct r8152 *tp;
  1338. struct net_device *netdev;
  1339. if (udev->actconfig->desc.bConfigurationValue != 1) {
  1340. usb_driver_set_configuration(udev, 1);
  1341. return -ENODEV;
  1342. }
  1343. netdev = alloc_etherdev(sizeof(struct r8152));
  1344. if (!netdev) {
  1345. dev_err(&intf->dev, "Out of memory");
  1346. return -ENOMEM;
  1347. }
  1348. tp = netdev_priv(netdev);
  1349. tp->msg_enable = 0x7FFF;
  1350. tasklet_init(&tp->tl, rx_fixup, (unsigned long)tp);
  1351. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  1352. tp->udev = udev;
  1353. tp->netdev = netdev;
  1354. netdev->netdev_ops = &rtl8152_netdev_ops;
  1355. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  1356. netdev->features &= ~NETIF_F_IP_CSUM;
  1357. SET_ETHTOOL_OPS(netdev, &ops);
  1358. tp->speed = 0;
  1359. tp->mii.dev = netdev;
  1360. tp->mii.mdio_read = read_mii_word;
  1361. tp->mii.mdio_write = write_mii_word;
  1362. tp->mii.phy_id_mask = 0x3f;
  1363. tp->mii.reg_num_mask = 0x1f;
  1364. tp->mii.phy_id = R8152_PHY_ID;
  1365. tp->mii.supports_gmii = 0;
  1366. r8152b_get_version(tp);
  1367. r8152b_init(tp);
  1368. set_ethernet_addr(tp);
  1369. if (!alloc_all_urbs(tp)) {
  1370. netif_err(tp, probe, netdev, "out of memory");
  1371. goto out;
  1372. }
  1373. tp->rx_skb = netdev_alloc_skb(netdev,
  1374. RTL8152_RMS + sizeof(struct rx_desc));
  1375. if (!tp->rx_skb)
  1376. goto out1;
  1377. usb_set_intfdata(intf, tp);
  1378. SET_NETDEV_DEV(netdev, &intf->dev);
  1379. if (register_netdev(netdev) != 0) {
  1380. netif_err(tp, probe, netdev, "couldn't register the device");
  1381. goto out2;
  1382. }
  1383. netif_info(tp, probe, netdev, "%s", DRIVER_VERSION);
  1384. return 0;
  1385. out2:
  1386. usb_set_intfdata(intf, NULL);
  1387. dev_kfree_skb(tp->rx_skb);
  1388. out1:
  1389. free_all_urbs(tp);
  1390. out:
  1391. free_netdev(netdev);
  1392. return -EIO;
  1393. }
  1394. static void rtl8152_unload(struct r8152 *tp)
  1395. {
  1396. u32 ocp_data;
  1397. if (tp->version != RTL_VER_01) {
  1398. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1399. ocp_data |= POWER_CUT;
  1400. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1401. }
  1402. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1403. ocp_data &= ~RWSUME_INDICATE;
  1404. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1405. }
  1406. static void rtl8152_disconnect(struct usb_interface *intf)
  1407. {
  1408. struct r8152 *tp = usb_get_intfdata(intf);
  1409. usb_set_intfdata(intf, NULL);
  1410. if (tp) {
  1411. set_bit(RTL8152_UNPLUG, &tp->flags);
  1412. tasklet_kill(&tp->tl);
  1413. unregister_netdev(tp->netdev);
  1414. rtl8152_unload(tp);
  1415. free_all_urbs(tp);
  1416. if (tp->rx_skb)
  1417. dev_kfree_skb(tp->rx_skb);
  1418. free_netdev(tp->netdev);
  1419. }
  1420. }
  1421. /* table of devices that work with this driver */
  1422. static struct usb_device_id rtl8152_table[] = {
  1423. {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
  1424. {}
  1425. };
  1426. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  1427. static struct usb_driver rtl8152_driver = {
  1428. .name = MODULENAME,
  1429. .probe = rtl8152_probe,
  1430. .disconnect = rtl8152_disconnect,
  1431. .id_table = rtl8152_table,
  1432. .suspend = rtl8152_suspend,
  1433. .resume = rtl8152_resume
  1434. };
  1435. module_usb_driver(rtl8152_driver);
  1436. MODULE_AUTHOR(DRIVER_AUTHOR);
  1437. MODULE_DESCRIPTION(DRIVER_DESC);
  1438. MODULE_LICENSE("GPL");