netxen_nic_hw.c 30 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to access the Phantom hardware
  31. *
  32. */
  33. #include "netxen_nic.h"
  34. #include "netxen_nic_hw.h"
  35. #define DEFINE_GLOBAL_RECV_CRB
  36. #include "netxen_nic_phan_reg.h"
  37. #include <net/ip.h>
  38. struct netxen_recv_crb recv_crb_registers[] = {
  39. /*
  40. * Instance 0.
  41. */
  42. {
  43. /* rcv_desc_crb: */
  44. {
  45. {
  46. /* crb_rcv_producer_offset: */
  47. NETXEN_NIC_REG(0x100),
  48. /* crb_rcv_consumer_offset: */
  49. NETXEN_NIC_REG(0x104),
  50. /* crb_gloablrcv_ring: */
  51. NETXEN_NIC_REG(0x108),
  52. /* crb_rcv_ring_size */
  53. NETXEN_NIC_REG(0x10c),
  54. },
  55. /* Jumbo frames */
  56. {
  57. /* crb_rcv_producer_offset: */
  58. NETXEN_NIC_REG(0x110),
  59. /* crb_rcv_consumer_offset: */
  60. NETXEN_NIC_REG(0x114),
  61. /* crb_gloablrcv_ring: */
  62. NETXEN_NIC_REG(0x118),
  63. /* crb_rcv_ring_size */
  64. NETXEN_NIC_REG(0x11c),
  65. },
  66. /* LRO */
  67. {
  68. /* crb_rcv_producer_offset: */
  69. NETXEN_NIC_REG(0x120),
  70. /* crb_rcv_consumer_offset: */
  71. NETXEN_NIC_REG(0x124),
  72. /* crb_gloablrcv_ring: */
  73. NETXEN_NIC_REG(0x128),
  74. /* crb_rcv_ring_size */
  75. NETXEN_NIC_REG(0x12c),
  76. }
  77. },
  78. /* crb_rcvstatus_ring: */
  79. NETXEN_NIC_REG(0x130),
  80. /* crb_rcv_status_producer: */
  81. NETXEN_NIC_REG(0x134),
  82. /* crb_rcv_status_consumer: */
  83. NETXEN_NIC_REG(0x138),
  84. /* crb_rcvpeg_state: */
  85. NETXEN_NIC_REG(0x13c),
  86. /* crb_status_ring_size */
  87. NETXEN_NIC_REG(0x140),
  88. },
  89. /*
  90. * Instance 1,
  91. */
  92. {
  93. /* rcv_desc_crb: */
  94. {
  95. {
  96. /* crb_rcv_producer_offset: */
  97. NETXEN_NIC_REG(0x144),
  98. /* crb_rcv_consumer_offset: */
  99. NETXEN_NIC_REG(0x148),
  100. /* crb_globalrcv_ring: */
  101. NETXEN_NIC_REG(0x14c),
  102. /* crb_rcv_ring_size */
  103. NETXEN_NIC_REG(0x150),
  104. },
  105. /* Jumbo frames */
  106. {
  107. /* crb_rcv_producer_offset: */
  108. NETXEN_NIC_REG(0x154),
  109. /* crb_rcv_consumer_offset: */
  110. NETXEN_NIC_REG(0x158),
  111. /* crb_globalrcv_ring: */
  112. NETXEN_NIC_REG(0x15c),
  113. /* crb_rcv_ring_size */
  114. NETXEN_NIC_REG(0x160),
  115. },
  116. /* LRO */
  117. {
  118. /* crb_rcv_producer_offset: */
  119. NETXEN_NIC_REG(0x164),
  120. /* crb_rcv_consumer_offset: */
  121. NETXEN_NIC_REG(0x168),
  122. /* crb_globalrcv_ring: */
  123. NETXEN_NIC_REG(0x16c),
  124. /* crb_rcv_ring_size */
  125. NETXEN_NIC_REG(0x170),
  126. }
  127. },
  128. /* crb_rcvstatus_ring: */
  129. NETXEN_NIC_REG(0x174),
  130. /* crb_rcv_status_producer: */
  131. NETXEN_NIC_REG(0x178),
  132. /* crb_rcv_status_consumer: */
  133. NETXEN_NIC_REG(0x17c),
  134. /* crb_rcvpeg_state: */
  135. NETXEN_NIC_REG(0x180),
  136. /* crb_status_ring_size */
  137. NETXEN_NIC_REG(0x184),
  138. },
  139. };
  140. u64 ctx_addr_sig_regs[][3] = {
  141. {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
  142. {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
  143. {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
  144. {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
  145. };
  146. /* PCI Windowing for DDR regions. */
  147. #define ADDR_IN_RANGE(addr, low, high) \
  148. (((addr) <= (high)) && ((addr) >= (low)))
  149. #define NETXEN_FLASH_BASE (BOOTLD_START)
  150. #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
  151. #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
  152. #define NETXEN_MIN_MTU 64
  153. #define NETXEN_ETH_FCS_SIZE 4
  154. #define NETXEN_ENET_HEADER_SIZE 14
  155. #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
  156. #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
  157. #define NETXEN_NIU_HDRSIZE (0x1 << 6)
  158. #define NETXEN_NIU_TLRSIZE (0x1 << 5)
  159. #define lower32(x) ((u32)((x) & 0xffffffff))
  160. #define upper32(x) \
  161. ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
  162. #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
  163. #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
  164. #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
  165. #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
  166. #define NETXEN_NIC_WINDOW_MARGIN 0x100000
  167. unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
  168. unsigned long long addr);
  169. void netxen_free_hw_resources(struct netxen_adapter *adapter);
  170. int netxen_nic_set_mac(struct net_device *netdev, void *p)
  171. {
  172. struct netxen_adapter *adapter = netdev_priv(netdev);
  173. struct sockaddr *addr = p;
  174. if (netif_running(netdev))
  175. return -EBUSY;
  176. if (!is_valid_ether_addr(addr->sa_data))
  177. return -EADDRNOTAVAIL;
  178. DPRINTK(INFO, "valid ether addr\n");
  179. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  180. if (adapter->macaddr_set)
  181. adapter->macaddr_set(adapter, addr->sa_data);
  182. return 0;
  183. }
  184. /*
  185. * netxen_nic_set_multi - Multicast
  186. */
  187. void netxen_nic_set_multi(struct net_device *netdev)
  188. {
  189. struct netxen_adapter *adapter = netdev_priv(netdev);
  190. struct dev_mc_list *mc_ptr;
  191. __u32 netxen_mac_addr_cntl_data = 0;
  192. mc_ptr = netdev->mc_list;
  193. if (netdev->flags & IFF_PROMISC) {
  194. if (adapter->set_promisc)
  195. adapter->set_promisc(adapter,
  196. NETXEN_NIU_PROMISC_MODE);
  197. } else {
  198. if (adapter->unset_promisc &&
  199. adapter->ahw.boardcfg.board_type
  200. != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
  201. adapter->unset_promisc(adapter,
  202. NETXEN_NIU_NON_PROMISC_MODE);
  203. }
  204. if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
  205. netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
  206. netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
  207. netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00);
  208. netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00);
  209. netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00);
  210. netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data);
  211. netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data);
  212. netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data);
  213. netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data);
  214. } else {
  215. netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00);
  216. netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
  217. netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01);
  218. netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02);
  219. netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03);
  220. }
  221. writel(netxen_mac_addr_cntl_data,
  222. NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG));
  223. if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
  224. writel(netxen_mac_addr_cntl_data,
  225. NETXEN_CRB_NORMALIZE(adapter,
  226. NETXEN_MULTICAST_ADDR_HI_0));
  227. } else {
  228. writel(netxen_mac_addr_cntl_data,
  229. NETXEN_CRB_NORMALIZE(adapter,
  230. NETXEN_MULTICAST_ADDR_HI_1));
  231. }
  232. netxen_mac_addr_cntl_data = 0;
  233. writel(netxen_mac_addr_cntl_data,
  234. NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR));
  235. }
  236. /*
  237. * netxen_nic_change_mtu - Change the Maximum Transfer Unit
  238. * @returns 0 on success, negative on failure
  239. */
  240. int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
  241. {
  242. struct netxen_adapter *adapter = netdev_priv(netdev);
  243. int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
  244. if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
  245. printk(KERN_ERR "%s: %s %d is not supported.\n",
  246. netxen_nic_driver_name, netdev->name, mtu);
  247. return -EINVAL;
  248. }
  249. if (adapter->set_mtu)
  250. adapter->set_mtu(adapter, mtu);
  251. netdev->mtu = mtu;
  252. return 0;
  253. }
  254. /*
  255. * check if the firmware has been downloaded and ready to run and
  256. * setup the address for the descriptors in the adapter
  257. */
  258. int netxen_nic_hw_resources(struct netxen_adapter *adapter)
  259. {
  260. struct netxen_hardware_context *hw = &adapter->ahw;
  261. u32 state = 0;
  262. void *addr;
  263. int loops = 0, err = 0;
  264. int ctx, ring;
  265. u32 card_cmdring = 0;
  266. struct netxen_recv_context *recv_ctx;
  267. struct netxen_rcv_desc_ctx *rcv_desc;
  268. DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
  269. PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
  270. DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
  271. pci_base_offset(adapter, NETXEN_CRB_CAM));
  272. DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
  273. pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
  274. /* Window 1 call */
  275. card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
  276. DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n",
  277. card_cmdring);
  278. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  279. DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
  280. loops = 0;
  281. state = 0;
  282. /* Window 1 call */
  283. state = readl(NETXEN_CRB_NORMALIZE(adapter,
  284. recv_crb_registers[ctx].
  285. crb_rcvpeg_state));
  286. while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
  287. udelay(100);
  288. /* Window 1 call */
  289. state = readl(NETXEN_CRB_NORMALIZE(adapter,
  290. recv_crb_registers
  291. [ctx].
  292. crb_rcvpeg_state));
  293. loops++;
  294. }
  295. if (loops >= 20) {
  296. printk(KERN_ERR "Rcv Peg initialization not complete:"
  297. "%x.\n", state);
  298. err = -EIO;
  299. return err;
  300. }
  301. }
  302. DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
  303. addr = netxen_alloc(adapter->ahw.pdev,
  304. sizeof(struct netxen_ring_ctx) +
  305. sizeof(uint32_t),
  306. (dma_addr_t *) & adapter->ctx_desc_phys_addr,
  307. &adapter->ctx_desc_pdev);
  308. printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
  309. (unsigned long long) adapter->ctx_desc_phys_addr);
  310. if (addr == NULL) {
  311. DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
  312. err = -ENOMEM;
  313. return err;
  314. }
  315. memset(addr, 0, sizeof(struct netxen_ring_ctx));
  316. adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
  317. adapter->ctx_desc->cmd_consumer_offset =
  318. cpu_to_le64(adapter->ctx_desc_phys_addr +
  319. sizeof(struct netxen_ring_ctx));
  320. adapter->cmd_consumer = (uint32_t *) (((char *)addr) +
  321. sizeof(struct netxen_ring_ctx));
  322. addr = netxen_alloc(adapter->ahw.pdev,
  323. sizeof(struct cmd_desc_type0) *
  324. adapter->max_tx_desc_count,
  325. (dma_addr_t *) & hw->cmd_desc_phys_addr,
  326. &adapter->ahw.cmd_desc_pdev);
  327. printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
  328. (unsigned long long) hw->cmd_desc_phys_addr);
  329. if (addr == NULL) {
  330. DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
  331. netxen_free_hw_resources(adapter);
  332. return -ENOMEM;
  333. }
  334. adapter->ctx_desc->cmd_ring_addr =
  335. cpu_to_le64(hw->cmd_desc_phys_addr);
  336. adapter->ctx_desc->cmd_ring_size =
  337. cpu_to_le32(adapter->max_tx_desc_count);
  338. hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
  339. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  340. recv_ctx = &adapter->recv_ctx[ctx];
  341. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  342. rcv_desc = &recv_ctx->rcv_desc[ring];
  343. addr = netxen_alloc(adapter->ahw.pdev,
  344. RCV_DESC_RINGSIZE,
  345. &rcv_desc->phys_addr,
  346. &rcv_desc->phys_pdev);
  347. if (addr == NULL) {
  348. DPRINTK(ERR, "bad return from "
  349. "pci_alloc_consistent\n");
  350. netxen_free_hw_resources(adapter);
  351. err = -ENOMEM;
  352. return err;
  353. }
  354. rcv_desc->desc_head = (struct rcv_desc *)addr;
  355. adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
  356. cpu_to_le64(rcv_desc->phys_addr);
  357. adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
  358. cpu_to_le32(rcv_desc->max_rx_desc_count);
  359. }
  360. addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
  361. &recv_ctx->rcv_status_desc_phys_addr,
  362. &recv_ctx->rcv_status_desc_pdev);
  363. if (addr == NULL) {
  364. DPRINTK(ERR, "bad return from"
  365. " pci_alloc_consistent\n");
  366. netxen_free_hw_resources(adapter);
  367. err = -ENOMEM;
  368. return err;
  369. }
  370. recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
  371. adapter->ctx_desc->sts_ring_addr =
  372. cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
  373. adapter->ctx_desc->sts_ring_size =
  374. cpu_to_le32(adapter->max_rx_desc_count);
  375. }
  376. /* Window = 1 */
  377. writel(lower32(adapter->ctx_desc_phys_addr),
  378. NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO));
  379. writel(upper32(adapter->ctx_desc_phys_addr),
  380. NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI));
  381. writel(NETXEN_CTX_SIGNATURE,
  382. NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG));
  383. return err;
  384. }
  385. void netxen_free_hw_resources(struct netxen_adapter *adapter)
  386. {
  387. struct netxen_recv_context *recv_ctx;
  388. struct netxen_rcv_desc_ctx *rcv_desc;
  389. int ctx, ring;
  390. if (adapter->ctx_desc != NULL) {
  391. pci_free_consistent(adapter->ctx_desc_pdev,
  392. sizeof(struct netxen_ring_ctx) +
  393. sizeof(uint32_t),
  394. adapter->ctx_desc,
  395. adapter->ctx_desc_phys_addr);
  396. adapter->ctx_desc = NULL;
  397. }
  398. if (adapter->ahw.cmd_desc_head != NULL) {
  399. pci_free_consistent(adapter->ahw.cmd_desc_pdev,
  400. sizeof(struct cmd_desc_type0) *
  401. adapter->max_tx_desc_count,
  402. adapter->ahw.cmd_desc_head,
  403. adapter->ahw.cmd_desc_phys_addr);
  404. adapter->ahw.cmd_desc_head = NULL;
  405. }
  406. /* Special handling: there are 2 ports on this board */
  407. if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
  408. adapter->ahw.max_ports = 2;
  409. }
  410. for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
  411. recv_ctx = &adapter->recv_ctx[ctx];
  412. for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
  413. rcv_desc = &recv_ctx->rcv_desc[ring];
  414. if (rcv_desc->desc_head != NULL) {
  415. pci_free_consistent(rcv_desc->phys_pdev,
  416. RCV_DESC_RINGSIZE,
  417. rcv_desc->desc_head,
  418. rcv_desc->phys_addr);
  419. rcv_desc->desc_head = NULL;
  420. }
  421. }
  422. if (recv_ctx->rcv_status_desc_head != NULL) {
  423. pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
  424. STATUS_DESC_RINGSIZE,
  425. recv_ctx->rcv_status_desc_head,
  426. recv_ctx->
  427. rcv_status_desc_phys_addr);
  428. recv_ctx->rcv_status_desc_head = NULL;
  429. }
  430. }
  431. }
  432. void netxen_tso_check(struct netxen_adapter *adapter,
  433. struct cmd_desc_type0 *desc, struct sk_buff *skb)
  434. {
  435. if (desc->mss) {
  436. desc->total_hdr_length = (sizeof(struct ethhdr) +
  437. ip_hdrlen(skb) + tcp_hdrlen(skb));
  438. netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
  439. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  440. if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
  441. netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
  442. } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
  443. netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
  444. } else {
  445. return;
  446. }
  447. }
  448. desc->tcp_hdr_offset = skb_transport_offset(skb);
  449. desc->ip_hdr_offset = skb_network_offset(skb);
  450. }
  451. int netxen_is_flash_supported(struct netxen_adapter *adapter)
  452. {
  453. const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
  454. int addr, val01, val02, i, j;
  455. /* if the flash size less than 4Mb, make huge war cry and die */
  456. for (j = 1; j < 4; j++) {
  457. addr = j * NETXEN_NIC_WINDOW_MARGIN;
  458. for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
  459. if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
  460. && netxen_rom_fast_read(adapter, (addr + locs[i]),
  461. &val02) == 0) {
  462. if (val01 == val02)
  463. return -1;
  464. } else
  465. return -1;
  466. }
  467. }
  468. return 0;
  469. }
  470. static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
  471. int size, u32 * buf)
  472. {
  473. int i, addr;
  474. u32 *ptr32;
  475. addr = base;
  476. ptr32 = buf;
  477. for (i = 0; i < size / sizeof(u32); i++) {
  478. if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
  479. return -1;
  480. *ptr32 = cpu_to_le32(*ptr32);
  481. ptr32++;
  482. addr += sizeof(u32);
  483. }
  484. if ((char *)buf + size > (char *)ptr32) {
  485. u32 local;
  486. if (netxen_rom_fast_read(adapter, addr, &local) == -1)
  487. return -1;
  488. local = cpu_to_le32(local);
  489. memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
  490. }
  491. return 0;
  492. }
  493. int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
  494. {
  495. u32 *pmac = (u32 *) & mac[0];
  496. if (netxen_get_flash_block(adapter,
  497. USER_START +
  498. offsetof(struct netxen_new_user_info,
  499. mac_addr),
  500. FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
  501. return -1;
  502. }
  503. if (*mac == ~0ULL) {
  504. if (netxen_get_flash_block(adapter,
  505. USER_START_OLD +
  506. offsetof(struct netxen_user_old_info,
  507. mac_addr),
  508. FLASH_NUM_PORTS * sizeof(u64),
  509. pmac) == -1)
  510. return -1;
  511. if (*mac == ~0ULL)
  512. return -1;
  513. }
  514. return 0;
  515. }
  516. /*
  517. * Changes the CRB window to the specified window.
  518. */
  519. void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
  520. {
  521. void __iomem *offset;
  522. u32 tmp;
  523. int count = 0;
  524. if (adapter->curr_window == wndw)
  525. return;
  526. switch(adapter->portnum) {
  527. case 0:
  528. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  529. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
  530. break;
  531. case 1:
  532. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  533. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
  534. break;
  535. case 2:
  536. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  537. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
  538. break;
  539. case 3:
  540. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  541. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
  542. break;
  543. default:
  544. printk(KERN_INFO "Changing the window for PCI function"
  545. "%d\n", adapter->portnum);
  546. offset = PCI_OFFSET_SECOND_RANGE(adapter,
  547. NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
  548. break;
  549. }
  550. /*
  551. * Move the CRB window.
  552. * We need to write to the "direct access" region of PCI
  553. * to avoid a race condition where the window register has
  554. * not been successfully written across CRB before the target
  555. * register address is received by PCI. The direct region bypasses
  556. * the CRB bus.
  557. */
  558. if (wndw & 0x1)
  559. wndw = NETXEN_WINDOW_ONE;
  560. writel(wndw, offset);
  561. /* MUST make sure window is set before we forge on... */
  562. while ((tmp = readl(offset)) != wndw) {
  563. printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
  564. "registered properly: 0x%08x.\n",
  565. netxen_nic_driver_name, __FUNCTION__, tmp);
  566. mdelay(1);
  567. if (count >= 10)
  568. break;
  569. count++;
  570. }
  571. adapter->curr_window = wndw;
  572. }
  573. void netxen_load_firmware(struct netxen_adapter *adapter)
  574. {
  575. int i;
  576. u32 data, size = 0;
  577. u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
  578. u64 off;
  579. void __iomem *addr;
  580. size = NETXEN_FIRMWARE_LEN;
  581. writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
  582. for (i = 0; i < size; i++) {
  583. if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
  584. DPRINTK(ERR,
  585. "Error in netxen_rom_fast_read(). Will skip"
  586. "loading flash image\n");
  587. return;
  588. }
  589. off = netxen_nic_pci_set_window(adapter, memaddr);
  590. addr = pci_base_offset(adapter, off);
  591. writel(data, addr);
  592. flashaddr += 4;
  593. memaddr += 4;
  594. }
  595. udelay(100);
  596. /* make sure Casper is powered on */
  597. writel(0x3fff,
  598. NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
  599. writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
  600. udelay(100);
  601. }
  602. int
  603. netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
  604. int len)
  605. {
  606. void __iomem *addr;
  607. if (ADDR_IN_WINDOW1(off)) {
  608. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  609. } else { /* Window 0 */
  610. addr = pci_base_offset(adapter, off);
  611. netxen_nic_pci_change_crbwindow(adapter, 0);
  612. }
  613. DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
  614. " data %llx len %d\n",
  615. pci_base(adapter, off), off, addr,
  616. *(unsigned long long *)data, len);
  617. if (!addr) {
  618. netxen_nic_pci_change_crbwindow(adapter, 1);
  619. return 1;
  620. }
  621. switch (len) {
  622. case 1:
  623. writeb(*(u8 *) data, addr);
  624. break;
  625. case 2:
  626. writew(*(u16 *) data, addr);
  627. break;
  628. case 4:
  629. writel(*(u32 *) data, addr);
  630. break;
  631. case 8:
  632. writeq(*(u64 *) data, addr);
  633. break;
  634. default:
  635. DPRINTK(INFO,
  636. "writing data %lx to offset %llx, num words=%d\n",
  637. *(unsigned long *)data, off, (len >> 3));
  638. netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
  639. (len >> 3));
  640. break;
  641. }
  642. if (!ADDR_IN_WINDOW1(off))
  643. netxen_nic_pci_change_crbwindow(adapter, 1);
  644. return 0;
  645. }
  646. int
  647. netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
  648. int len)
  649. {
  650. void __iomem *addr;
  651. if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
  652. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  653. } else { /* Window 0 */
  654. addr = pci_base_offset(adapter, off);
  655. netxen_nic_pci_change_crbwindow(adapter, 0);
  656. }
  657. DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
  658. pci_base(adapter, off), off, addr);
  659. if (!addr) {
  660. netxen_nic_pci_change_crbwindow(adapter, 1);
  661. return 1;
  662. }
  663. switch (len) {
  664. case 1:
  665. *(u8 *) data = readb(addr);
  666. break;
  667. case 2:
  668. *(u16 *) data = readw(addr);
  669. break;
  670. case 4:
  671. *(u32 *) data = readl(addr);
  672. break;
  673. case 8:
  674. *(u64 *) data = readq(addr);
  675. break;
  676. default:
  677. netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
  678. (len >> 3));
  679. break;
  680. }
  681. DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
  682. if (!ADDR_IN_WINDOW1(off))
  683. netxen_nic_pci_change_crbwindow(adapter, 1);
  684. return 0;
  685. }
  686. void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
  687. { /* Only for window 1 */
  688. void __iomem *addr;
  689. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  690. DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
  691. pci_base(adapter, off), off, addr, val);
  692. writel(val, addr);
  693. }
  694. int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
  695. { /* Only for window 1 */
  696. void __iomem *addr;
  697. int val;
  698. addr = NETXEN_CRB_NORMALIZE(adapter, off);
  699. DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
  700. pci_base(adapter, off), off, addr);
  701. val = readl(addr);
  702. writel(val, addr);
  703. return val;
  704. }
  705. /* Change the window to 0, write and change back to window 1. */
  706. void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
  707. {
  708. void __iomem *addr;
  709. netxen_nic_pci_change_crbwindow(adapter, 0);
  710. addr = pci_base_offset(adapter, index);
  711. writel(value, addr);
  712. netxen_nic_pci_change_crbwindow(adapter, 1);
  713. }
  714. /* Change the window to 0, read and change back to window 1. */
  715. void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
  716. {
  717. void __iomem *addr;
  718. addr = pci_base_offset(adapter, index);
  719. netxen_nic_pci_change_crbwindow(adapter, 0);
  720. *value = readl(addr);
  721. netxen_nic_pci_change_crbwindow(adapter, 1);
  722. }
  723. int netxen_pci_set_window_warning_count = 0;
  724. unsigned long
  725. netxen_nic_pci_set_window(struct netxen_adapter *adapter,
  726. unsigned long long addr)
  727. {
  728. static int ddr_mn_window = -1;
  729. static int qdr_sn_window = -1;
  730. int window;
  731. if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
  732. /* DDR network side */
  733. addr -= NETXEN_ADDR_DDR_NET;
  734. window = (addr >> 25) & 0x3ff;
  735. if (ddr_mn_window != window) {
  736. ddr_mn_window = window;
  737. writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
  738. NETXEN_PCIX_PH_REG
  739. (PCIX_MN_WINDOW)));
  740. /* MUST make sure window is set before we forge on... */
  741. readl(PCI_OFFSET_SECOND_RANGE(adapter,
  742. NETXEN_PCIX_PH_REG
  743. (PCIX_MN_WINDOW)));
  744. }
  745. addr -= (window * NETXEN_WINDOW_ONE);
  746. addr += NETXEN_PCI_DDR_NET;
  747. } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
  748. addr -= NETXEN_ADDR_OCM0;
  749. addr += NETXEN_PCI_OCM0;
  750. } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
  751. addr -= NETXEN_ADDR_OCM1;
  752. addr += NETXEN_PCI_OCM1;
  753. } else
  754. if (ADDR_IN_RANGE
  755. (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
  756. /* QDR network side */
  757. addr -= NETXEN_ADDR_QDR_NET;
  758. window = (addr >> 22) & 0x3f;
  759. if (qdr_sn_window != window) {
  760. qdr_sn_window = window;
  761. writel((window << 22),
  762. PCI_OFFSET_SECOND_RANGE(adapter,
  763. NETXEN_PCIX_PH_REG
  764. (PCIX_SN_WINDOW)));
  765. /* MUST make sure window is set before we forge on... */
  766. readl(PCI_OFFSET_SECOND_RANGE(adapter,
  767. NETXEN_PCIX_PH_REG
  768. (PCIX_SN_WINDOW)));
  769. }
  770. addr -= (window * 0x400000);
  771. addr += NETXEN_PCI_QDR_NET;
  772. } else {
  773. /*
  774. * peg gdb frequently accesses memory that doesn't exist,
  775. * this limits the chit chat so debugging isn't slowed down.
  776. */
  777. if ((netxen_pci_set_window_warning_count++ < 8)
  778. || (netxen_pci_set_window_warning_count % 64 == 0))
  779. printk("%s: Warning:netxen_nic_pci_set_window()"
  780. " Unknown address range!\n",
  781. netxen_nic_driver_name);
  782. }
  783. return addr;
  784. }
  785. int netxen_nic_get_board_info(struct netxen_adapter *adapter)
  786. {
  787. int rv = 0;
  788. int addr = BRDCFG_START;
  789. struct netxen_board_info *boardinfo;
  790. int index;
  791. u32 *ptr32;
  792. boardinfo = &adapter->ahw.boardcfg;
  793. ptr32 = (u32 *) boardinfo;
  794. for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
  795. index++) {
  796. if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
  797. return -EIO;
  798. }
  799. ptr32++;
  800. addr += sizeof(u32);
  801. }
  802. if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
  803. printk("%s: ERROR reading %s board config."
  804. " Read %x, expected %x\n", netxen_nic_driver_name,
  805. netxen_nic_driver_name,
  806. boardinfo->magic, NETXEN_BDINFO_MAGIC);
  807. rv = -1;
  808. }
  809. if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
  810. printk("%s: Unknown board config version."
  811. " Read %x, expected %x\n", netxen_nic_driver_name,
  812. boardinfo->header_version, NETXEN_BDINFO_VERSION);
  813. rv = -1;
  814. }
  815. DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
  816. switch ((netxen_brdtype_t) boardinfo->board_type) {
  817. case NETXEN_BRDTYPE_P2_SB35_4G:
  818. adapter->ahw.board_type = NETXEN_NIC_GBE;
  819. break;
  820. case NETXEN_BRDTYPE_P2_SB31_10G:
  821. case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
  822. case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
  823. case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
  824. adapter->ahw.board_type = NETXEN_NIC_XGBE;
  825. break;
  826. case NETXEN_BRDTYPE_P1_BD:
  827. case NETXEN_BRDTYPE_P1_SB:
  828. case NETXEN_BRDTYPE_P1_SMAX:
  829. case NETXEN_BRDTYPE_P1_SOCK:
  830. adapter->ahw.board_type = NETXEN_NIC_GBE;
  831. break;
  832. default:
  833. printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
  834. boardinfo->board_type);
  835. break;
  836. }
  837. return rv;
  838. }
  839. /* NIU access sections */
  840. int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
  841. {
  842. netxen_nic_write_w0(adapter,
  843. NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->portnum),
  844. new_mtu);
  845. return 0;
  846. }
  847. int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
  848. {
  849. new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
  850. if (adapter->portnum == 0)
  851. netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
  852. else if (adapter->portnum == 1)
  853. netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
  854. return 0;
  855. }
  856. void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
  857. {
  858. netxen_niu_gbe_init_port(adapter, adapter->portnum);
  859. }
  860. void
  861. netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
  862. int data)
  863. {
  864. void __iomem *addr;
  865. if (ADDR_IN_WINDOW1(off)) {
  866. writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
  867. } else {
  868. netxen_nic_pci_change_crbwindow(adapter, 0);
  869. addr = pci_base_offset(adapter, off);
  870. writel(data, addr);
  871. netxen_nic_pci_change_crbwindow(adapter, 1);
  872. }
  873. }
  874. void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
  875. {
  876. __u32 status;
  877. __u32 autoneg;
  878. __u32 mode;
  879. netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
  880. if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
  881. if (adapter->phy_read
  882. && adapter->
  883. phy_read(adapter, adapter->portnum,
  884. NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
  885. &status) == 0) {
  886. if (netxen_get_phy_link(status)) {
  887. switch (netxen_get_phy_speed(status)) {
  888. case 0:
  889. adapter->link_speed = SPEED_10;
  890. break;
  891. case 1:
  892. adapter->link_speed = SPEED_100;
  893. break;
  894. case 2:
  895. adapter->link_speed = SPEED_1000;
  896. break;
  897. default:
  898. adapter->link_speed = -1;
  899. break;
  900. }
  901. switch (netxen_get_phy_duplex(status)) {
  902. case 0:
  903. adapter->link_duplex = DUPLEX_HALF;
  904. break;
  905. case 1:
  906. adapter->link_duplex = DUPLEX_FULL;
  907. break;
  908. default:
  909. adapter->link_duplex = -1;
  910. break;
  911. }
  912. if (adapter->phy_read
  913. && adapter->
  914. phy_read(adapter, adapter->portnum,
  915. NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
  916. &autoneg) != 0)
  917. adapter->link_autoneg = autoneg;
  918. } else
  919. goto link_down;
  920. } else {
  921. link_down:
  922. adapter->link_speed = -1;
  923. adapter->link_duplex = -1;
  924. }
  925. }
  926. }
  927. void netxen_nic_flash_print(struct netxen_adapter *adapter)
  928. {
  929. int valid = 1;
  930. u32 fw_major = 0;
  931. u32 fw_minor = 0;
  932. u32 fw_build = 0;
  933. char brd_name[NETXEN_MAX_SHORT_NAME];
  934. struct netxen_new_user_info user_info;
  935. int i, addr = USER_START;
  936. u32 *ptr32;
  937. struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
  938. if (board_info->magic != NETXEN_BDINFO_MAGIC) {
  939. printk
  940. ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
  941. board_info->magic, NETXEN_BDINFO_MAGIC);
  942. valid = 0;
  943. }
  944. if (board_info->header_version != NETXEN_BDINFO_VERSION) {
  945. printk("NetXen Unknown board config version."
  946. " Read %x, expected %x\n",
  947. board_info->header_version, NETXEN_BDINFO_VERSION);
  948. valid = 0;
  949. }
  950. if (valid) {
  951. ptr32 = (u32 *) & user_info;
  952. for (i = 0;
  953. i < sizeof(struct netxen_new_user_info) / sizeof(u32);
  954. i++) {
  955. if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
  956. printk("%s: ERROR reading %s board userarea.\n",
  957. netxen_nic_driver_name,
  958. netxen_nic_driver_name);
  959. return;
  960. }
  961. *ptr32 = le32_to_cpu(*ptr32);
  962. ptr32++;
  963. addr += sizeof(u32);
  964. }
  965. get_brd_name_by_type(board_info->board_type, brd_name);
  966. printk("NetXen %s Board S/N %s Chip id 0x%x\n",
  967. brd_name, user_info.serial_num, board_info->chip_id);
  968. printk("NetXen %s Board #%d, Chip id 0x%x\n",
  969. board_info->board_type == 0x0b ? "XGB" : "GBE",
  970. board_info->board_num, board_info->chip_id);
  971. fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
  972. NETXEN_FW_VERSION_MAJOR));
  973. fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
  974. NETXEN_FW_VERSION_MINOR));
  975. fw_build =
  976. readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
  977. printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
  978. fw_build);
  979. }
  980. if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
  981. printk(KERN_ERR "The mismatch in driver version and firmware "
  982. "version major number\n"
  983. "Driver version major number = %d \t"
  984. "Firmware version major number = %d \n",
  985. _NETXEN_NIC_LINUX_MAJOR, fw_major);
  986. adapter->driver_mismatch = 1;
  987. }
  988. if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
  989. fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
  990. printk(KERN_ERR "The mismatch in driver version and firmware "
  991. "version minor number\n"
  992. "Driver version minor number = %d \t"
  993. "Firmware version minor number = %d \n",
  994. _NETXEN_NIC_LINUX_MINOR, fw_minor);
  995. adapter->driver_mismatch = 1;
  996. }
  997. if (adapter->driver_mismatch)
  998. printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
  999. fw_major, fw_minor);
  1000. }