sdhci.c 31 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. /*
  11. * Note that PIO transfer is rather crappy atm. The buffer full/empty
  12. * interrupts aren't reliable so we currently transfer the entire buffer
  13. * directly. Patches to solve the problem are welcome.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/highmem.h>
  17. #include <linux/pci.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/mmc/host.h>
  20. #include <linux/mmc/protocol.h>
  21. #include <asm/scatterlist.h>
  22. #include "sdhci.h"
  23. #define DRIVER_NAME "sdhci"
  24. #define DRIVER_VERSION "0.11"
  25. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  26. #ifdef CONFIG_MMC_DEBUG
  27. #define DBG(f, x...) \
  28. printk(KERN_DEBUG DRIVER_NAME " [%s()]: " f, __func__,## x)
  29. #else
  30. #define DBG(f, x...) do { } while (0)
  31. #endif
  32. static const struct pci_device_id pci_ids[] __devinitdata = {
  33. /* handle any SD host controller */
  34. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  35. { /* end: all zeroes */ },
  36. };
  37. MODULE_DEVICE_TABLE(pci, pci_ids);
  38. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  39. static void sdhci_finish_data(struct sdhci_host *);
  40. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  41. static void sdhci_finish_command(struct sdhci_host *);
  42. static void sdhci_dumpregs(struct sdhci_host *host)
  43. {
  44. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  45. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  46. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  47. readw(host->ioaddr + SDHCI_HOST_VERSION));
  48. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  49. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  50. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  51. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  52. readl(host->ioaddr + SDHCI_ARGUMENT),
  53. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  54. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  55. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  56. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  57. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  58. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  59. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  60. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  61. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  62. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  63. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  64. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  65. readl(host->ioaddr + SDHCI_INT_STATUS));
  66. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  67. readl(host->ioaddr + SDHCI_INT_ENABLE),
  68. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  69. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  70. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  71. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  72. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  73. readl(host->ioaddr + SDHCI_CAPABILITIES),
  74. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  75. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  76. }
  77. /*****************************************************************************\
  78. * *
  79. * Low level functions *
  80. * *
  81. \*****************************************************************************/
  82. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  83. {
  84. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  85. if (mask & SDHCI_RESET_ALL) {
  86. host->clock = 0;
  87. mdelay(50);
  88. }
  89. }
  90. static void sdhci_init(struct sdhci_host *host)
  91. {
  92. u32 intmask;
  93. sdhci_reset(host, SDHCI_RESET_ALL);
  94. intmask = ~(SDHCI_INT_CARD_INT | SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  95. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  96. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  97. /* This is unknown magic. */
  98. writeb(0xE, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  99. }
  100. static void sdhci_activate_led(struct sdhci_host *host)
  101. {
  102. u8 ctrl;
  103. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  104. ctrl |= SDHCI_CTRL_LED;
  105. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  106. }
  107. static void sdhci_deactivate_led(struct sdhci_host *host)
  108. {
  109. u8 ctrl;
  110. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  111. ctrl &= ~SDHCI_CTRL_LED;
  112. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  113. }
  114. /*****************************************************************************\
  115. * *
  116. * Core functions *
  117. * *
  118. \*****************************************************************************/
  119. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  120. {
  121. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  122. return host->mapped_sg + host->cur_sg->offset;
  123. }
  124. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  125. {
  126. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  127. }
  128. static inline int sdhci_next_sg(struct sdhci_host* host)
  129. {
  130. /*
  131. * Skip to next SG entry.
  132. */
  133. host->cur_sg++;
  134. host->num_sg--;
  135. /*
  136. * Any entries left?
  137. */
  138. if (host->num_sg > 0) {
  139. host->offset = 0;
  140. host->remain = host->cur_sg->length;
  141. }
  142. return host->num_sg;
  143. }
  144. static void sdhci_transfer_pio(struct sdhci_host *host)
  145. {
  146. char *buffer;
  147. u32 mask;
  148. int bytes, size;
  149. unsigned long max_jiffies;
  150. BUG_ON(!host->data);
  151. if (host->num_sg == 0)
  152. return;
  153. bytes = 0;
  154. if (host->data->flags & MMC_DATA_READ)
  155. mask = SDHCI_DATA_AVAILABLE;
  156. else
  157. mask = SDHCI_SPACE_AVAILABLE;
  158. buffer = sdhci_kmap_sg(host) + host->offset;
  159. /* Transfer shouldn't take more than 5 s */
  160. max_jiffies = jiffies + HZ * 5;
  161. while (host->size > 0) {
  162. if (time_after(jiffies, max_jiffies)) {
  163. printk(KERN_ERR "%s: PIO transfer stalled. "
  164. "Please report this to "
  165. BUGMAIL ".\n", mmc_hostname(host->mmc));
  166. sdhci_dumpregs(host);
  167. sdhci_kunmap_sg(host);
  168. host->data->error = MMC_ERR_FAILED;
  169. sdhci_finish_data(host);
  170. return;
  171. }
  172. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask))
  173. continue;
  174. size = min(host->size, host->remain);
  175. if (size >= 4) {
  176. if (host->data->flags & MMC_DATA_READ)
  177. *(u32*)buffer = readl(host->ioaddr + SDHCI_BUFFER);
  178. else
  179. writel(*(u32*)buffer, host->ioaddr + SDHCI_BUFFER);
  180. size = 4;
  181. } else if (size >= 2) {
  182. if (host->data->flags & MMC_DATA_READ)
  183. *(u16*)buffer = readw(host->ioaddr + SDHCI_BUFFER);
  184. else
  185. writew(*(u16*)buffer, host->ioaddr + SDHCI_BUFFER);
  186. size = 2;
  187. } else {
  188. if (host->data->flags & MMC_DATA_READ)
  189. *(u8*)buffer = readb(host->ioaddr + SDHCI_BUFFER);
  190. else
  191. writeb(*(u8*)buffer, host->ioaddr + SDHCI_BUFFER);
  192. size = 1;
  193. }
  194. buffer += size;
  195. host->offset += size;
  196. host->remain -= size;
  197. bytes += size;
  198. host->size -= size;
  199. if (host->remain == 0) {
  200. sdhci_kunmap_sg(host);
  201. if (sdhci_next_sg(host) == 0) {
  202. DBG("PIO transfer: %d bytes\n", bytes);
  203. return;
  204. }
  205. buffer = sdhci_kmap_sg(host);
  206. }
  207. }
  208. sdhci_kunmap_sg(host);
  209. DBG("PIO transfer: %d bytes\n", bytes);
  210. }
  211. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  212. {
  213. u16 mode;
  214. WARN_ON(host->data);
  215. if (data == NULL) {
  216. writew(0, host->ioaddr + SDHCI_TRANSFER_MODE);
  217. return;
  218. }
  219. DBG("blksz %04x blks %04x flags %08x\n",
  220. 1 << data->blksz_bits, data->blocks, data->flags);
  221. DBG("tsac %d ms nsac %d clk\n",
  222. data->timeout_ns / 1000000, data->timeout_clks);
  223. mode = SDHCI_TRNS_BLK_CNT_EN;
  224. if (data->blocks > 1)
  225. mode |= SDHCI_TRNS_MULTI;
  226. if (data->flags & MMC_DATA_READ)
  227. mode |= SDHCI_TRNS_READ;
  228. if (host->flags & SDHCI_USE_DMA)
  229. mode |= SDHCI_TRNS_DMA;
  230. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  231. writew(1 << data->blksz_bits, host->ioaddr + SDHCI_BLOCK_SIZE);
  232. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  233. if (host->flags & SDHCI_USE_DMA) {
  234. int count;
  235. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  236. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  237. BUG_ON(count != 1);
  238. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  239. } else {
  240. host->size = (1 << data->blksz_bits) * data->blocks;
  241. host->cur_sg = data->sg;
  242. host->num_sg = data->sg_len;
  243. host->offset = 0;
  244. host->remain = host->cur_sg->length;
  245. }
  246. }
  247. static void sdhci_finish_data(struct sdhci_host *host)
  248. {
  249. struct mmc_data *data;
  250. u32 intmask;
  251. u16 blocks;
  252. BUG_ON(!host->data);
  253. data = host->data;
  254. host->data = NULL;
  255. if (host->flags & SDHCI_USE_DMA) {
  256. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  257. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  258. } else {
  259. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  260. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  261. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  262. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  263. intmask &= ~(SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL);
  264. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  265. }
  266. /*
  267. * Controller doesn't count down when in single block mode.
  268. */
  269. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  270. blocks = 0;
  271. else
  272. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  273. data->bytes_xfered = (1 << data->blksz_bits) * (data->blocks - blocks);
  274. if ((data->error == MMC_ERR_NONE) && blocks) {
  275. printk(KERN_ERR "%s: Controller signalled completion even "
  276. "though there were blocks left. Please report this "
  277. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  278. data->error = MMC_ERR_FAILED;
  279. }
  280. if (host->size != 0) {
  281. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  282. "Please report this to " BUGMAIL ".\n",
  283. mmc_hostname(host->mmc), host->size);
  284. data->error = MMC_ERR_FAILED;
  285. }
  286. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  287. if (data->stop) {
  288. /*
  289. * The controller needs a reset of internal state machines
  290. * upon error conditions.
  291. */
  292. if (data->error != MMC_ERR_NONE) {
  293. sdhci_reset(host, SDHCI_RESET_CMD);
  294. sdhci_reset(host, SDHCI_RESET_DATA);
  295. }
  296. sdhci_send_command(host, data->stop);
  297. } else
  298. tasklet_schedule(&host->finish_tasklet);
  299. }
  300. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  301. {
  302. int flags;
  303. u32 present;
  304. unsigned long max_jiffies;
  305. WARN_ON(host->cmd);
  306. DBG("Sending cmd (%x)\n", cmd->opcode);
  307. /* Wait max 10 ms */
  308. max_jiffies = jiffies + (HZ + 99)/100;
  309. do {
  310. if (time_after(jiffies, max_jiffies)) {
  311. printk(KERN_ERR "%s: Controller never released "
  312. "inhibit bits. Please report this to "
  313. BUGMAIL ".\n", mmc_hostname(host->mmc));
  314. sdhci_dumpregs(host);
  315. cmd->error = MMC_ERR_FAILED;
  316. tasklet_schedule(&host->finish_tasklet);
  317. return;
  318. }
  319. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  320. } while (present & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT));
  321. mod_timer(&host->timer, jiffies + 10 * HZ);
  322. host->cmd = cmd;
  323. sdhci_prepare_data(host, cmd->data);
  324. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  325. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  326. printk(KERN_ERR "%s: Unsupported response type! "
  327. "Please report this to " BUGMAIL ".\n",
  328. mmc_hostname(host->mmc));
  329. cmd->error = MMC_ERR_INVALID;
  330. tasklet_schedule(&host->finish_tasklet);
  331. return;
  332. }
  333. if (!(cmd->flags & MMC_RSP_PRESENT))
  334. flags = SDHCI_CMD_RESP_NONE;
  335. else if (cmd->flags & MMC_RSP_136)
  336. flags = SDHCI_CMD_RESP_LONG;
  337. else if (cmd->flags & MMC_RSP_BUSY)
  338. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  339. else
  340. flags = SDHCI_CMD_RESP_SHORT;
  341. if (cmd->flags & MMC_RSP_CRC)
  342. flags |= SDHCI_CMD_CRC;
  343. if (cmd->flags & MMC_RSP_OPCODE)
  344. flags |= SDHCI_CMD_INDEX;
  345. if (cmd->data)
  346. flags |= SDHCI_CMD_DATA;
  347. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  348. host->ioaddr + SDHCI_COMMAND);
  349. }
  350. static void sdhci_finish_command(struct sdhci_host *host)
  351. {
  352. int i;
  353. BUG_ON(host->cmd == NULL);
  354. if (host->cmd->flags & MMC_RSP_PRESENT) {
  355. if (host->cmd->flags & MMC_RSP_136) {
  356. /* CRC is stripped so we need to do some shifting. */
  357. for (i = 0;i < 4;i++) {
  358. host->cmd->resp[i] = readl(host->ioaddr +
  359. SDHCI_RESPONSE + (3-i)*4) << 8;
  360. if (i != 3)
  361. host->cmd->resp[i] |=
  362. readb(host->ioaddr +
  363. SDHCI_RESPONSE + (3-i)*4-1);
  364. }
  365. } else {
  366. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  367. }
  368. }
  369. host->cmd->error = MMC_ERR_NONE;
  370. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  371. if (host->cmd->data) {
  372. u32 intmask;
  373. host->data = host->cmd->data;
  374. if (!(host->flags & SDHCI_USE_DMA)) {
  375. /*
  376. * Don't enable the interrupts until now to make sure we
  377. * get stable handling of the FIFO.
  378. */
  379. intmask = readl(host->ioaddr + SDHCI_INT_ENABLE);
  380. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  381. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  382. intmask = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
  383. intmask |= SDHCI_INT_BUF_EMPTY | SDHCI_INT_BUF_FULL;
  384. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  385. /*
  386. * The buffer interrupts are to unreliable so we
  387. * start the transfer immediatly.
  388. */
  389. sdhci_transfer_pio(host);
  390. }
  391. } else
  392. tasklet_schedule(&host->finish_tasklet);
  393. host->cmd = NULL;
  394. }
  395. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  396. {
  397. int div;
  398. u16 clk;
  399. unsigned long max_jiffies;
  400. if (clock == host->clock)
  401. return;
  402. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  403. if (clock == 0)
  404. goto out;
  405. for (div = 1;div < 256;div *= 2) {
  406. if ((host->max_clk / div) <= clock)
  407. break;
  408. }
  409. div >>= 1;
  410. clk = div << SDHCI_DIVIDER_SHIFT;
  411. clk |= SDHCI_CLOCK_INT_EN;
  412. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  413. /* Wait max 10 ms */
  414. max_jiffies = jiffies + (HZ + 99)/100;
  415. do {
  416. if (time_after(jiffies, max_jiffies)) {
  417. printk(KERN_ERR "%s: Internal clock never stabilised. "
  418. "Please report this to " BUGMAIL ".\n",
  419. mmc_hostname(host->mmc));
  420. sdhci_dumpregs(host);
  421. return;
  422. }
  423. clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL);
  424. } while (!(clk & SDHCI_CLOCK_INT_STABLE));
  425. clk |= SDHCI_CLOCK_CARD_EN;
  426. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  427. out:
  428. host->clock = clock;
  429. }
  430. /*****************************************************************************\
  431. * *
  432. * MMC callbacks *
  433. * *
  434. \*****************************************************************************/
  435. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  436. {
  437. struct sdhci_host *host;
  438. unsigned long flags;
  439. host = mmc_priv(mmc);
  440. spin_lock_irqsave(&host->lock, flags);
  441. WARN_ON(host->mrq != NULL);
  442. sdhci_activate_led(host);
  443. host->mrq = mrq;
  444. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  445. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  446. tasklet_schedule(&host->finish_tasklet);
  447. } else
  448. sdhci_send_command(host, mrq->cmd);
  449. spin_unlock_irqrestore(&host->lock, flags);
  450. }
  451. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  452. {
  453. struct sdhci_host *host;
  454. unsigned long flags;
  455. u8 ctrl;
  456. host = mmc_priv(mmc);
  457. spin_lock_irqsave(&host->lock, flags);
  458. DBG("clock %uHz busmode %u powermode %u cs %u Vdd %u width %u\n",
  459. ios->clock, ios->bus_mode, ios->power_mode, ios->chip_select,
  460. ios->vdd, ios->bus_width);
  461. /*
  462. * Reset the chip on each power off.
  463. * Should clear out any weird states.
  464. */
  465. if (ios->power_mode == MMC_POWER_OFF) {
  466. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  467. spin_unlock_irqrestore(&host->lock, flags);
  468. sdhci_init(host);
  469. spin_lock_irqsave(&host->lock, flags);
  470. }
  471. sdhci_set_clock(host, ios->clock);
  472. if (ios->power_mode == MMC_POWER_OFF)
  473. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  474. else
  475. writeb(0xFF, host->ioaddr + SDHCI_POWER_CONTROL);
  476. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  477. if (ios->bus_width == MMC_BUS_WIDTH_4)
  478. ctrl |= SDHCI_CTRL_4BITBUS;
  479. else
  480. ctrl &= ~SDHCI_CTRL_4BITBUS;
  481. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  482. spin_unlock_irqrestore(&host->lock, flags);
  483. }
  484. static int sdhci_get_ro(struct mmc_host *mmc)
  485. {
  486. struct sdhci_host *host;
  487. unsigned long flags;
  488. int present;
  489. host = mmc_priv(mmc);
  490. spin_lock_irqsave(&host->lock, flags);
  491. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  492. spin_unlock_irqrestore(&host->lock, flags);
  493. return !(present & SDHCI_WRITE_PROTECT);
  494. }
  495. static struct mmc_host_ops sdhci_ops = {
  496. .request = sdhci_request,
  497. .set_ios = sdhci_set_ios,
  498. .get_ro = sdhci_get_ro,
  499. };
  500. /*****************************************************************************\
  501. * *
  502. * Tasklets *
  503. * *
  504. \*****************************************************************************/
  505. static void sdhci_tasklet_card(unsigned long param)
  506. {
  507. struct sdhci_host *host;
  508. unsigned long flags;
  509. host = (struct sdhci_host*)param;
  510. spin_lock_irqsave(&host->lock, flags);
  511. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  512. if (host->mrq) {
  513. printk(KERN_ERR "%s: Card removed during transfer!\n",
  514. mmc_hostname(host->mmc));
  515. printk(KERN_ERR "%s: Resetting controller.\n",
  516. mmc_hostname(host->mmc));
  517. sdhci_reset(host, SDHCI_RESET_CMD);
  518. sdhci_reset(host, SDHCI_RESET_DATA);
  519. host->mrq->cmd->error = MMC_ERR_FAILED;
  520. tasklet_schedule(&host->finish_tasklet);
  521. }
  522. }
  523. spin_unlock_irqrestore(&host->lock, flags);
  524. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  525. }
  526. static void sdhci_tasklet_finish(unsigned long param)
  527. {
  528. struct sdhci_host *host;
  529. unsigned long flags;
  530. struct mmc_request *mrq;
  531. host = (struct sdhci_host*)param;
  532. spin_lock_irqsave(&host->lock, flags);
  533. del_timer(&host->timer);
  534. mrq = host->mrq;
  535. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  536. /*
  537. * The controller needs a reset of internal state machines
  538. * upon error conditions.
  539. */
  540. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  541. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  542. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  543. sdhci_reset(host, SDHCI_RESET_CMD);
  544. sdhci_reset(host, SDHCI_RESET_DATA);
  545. }
  546. host->mrq = NULL;
  547. host->cmd = NULL;
  548. host->data = NULL;
  549. sdhci_deactivate_led(host);
  550. spin_unlock_irqrestore(&host->lock, flags);
  551. mmc_request_done(host->mmc, mrq);
  552. }
  553. static void sdhci_timeout_timer(unsigned long data)
  554. {
  555. struct sdhci_host *host;
  556. unsigned long flags;
  557. host = (struct sdhci_host*)data;
  558. spin_lock_irqsave(&host->lock, flags);
  559. if (host->mrq) {
  560. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  561. "Please report this to " BUGMAIL ".\n",
  562. mmc_hostname(host->mmc));
  563. sdhci_dumpregs(host);
  564. if (host->data) {
  565. host->data->error = MMC_ERR_TIMEOUT;
  566. sdhci_finish_data(host);
  567. } else {
  568. if (host->cmd)
  569. host->cmd->error = MMC_ERR_TIMEOUT;
  570. else
  571. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  572. tasklet_schedule(&host->finish_tasklet);
  573. }
  574. }
  575. spin_unlock_irqrestore(&host->lock, flags);
  576. }
  577. /*****************************************************************************\
  578. * *
  579. * Interrupt handling *
  580. * *
  581. \*****************************************************************************/
  582. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  583. {
  584. BUG_ON(intmask == 0);
  585. if (!host->cmd) {
  586. printk(KERN_ERR "%s: Got command interrupt even though no "
  587. "command operation was in progress.\n",
  588. mmc_hostname(host->mmc));
  589. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  590. mmc_hostname(host->mmc));
  591. sdhci_dumpregs(host);
  592. return;
  593. }
  594. if (intmask & SDHCI_INT_RESPONSE)
  595. sdhci_finish_command(host);
  596. else {
  597. if (intmask & SDHCI_INT_TIMEOUT)
  598. host->cmd->error = MMC_ERR_TIMEOUT;
  599. else if (intmask & SDHCI_INT_CRC)
  600. host->cmd->error = MMC_ERR_BADCRC;
  601. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  602. host->cmd->error = MMC_ERR_FAILED;
  603. else
  604. host->cmd->error = MMC_ERR_INVALID;
  605. tasklet_schedule(&host->finish_tasklet);
  606. }
  607. }
  608. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  609. {
  610. BUG_ON(intmask == 0);
  611. if (!host->data) {
  612. /*
  613. * A data end interrupt is sent together with the response
  614. * for the stop command.
  615. */
  616. if (intmask & SDHCI_INT_DATA_END)
  617. return;
  618. printk(KERN_ERR "%s: Got data interrupt even though no "
  619. "data operation was in progress.\n",
  620. mmc_hostname(host->mmc));
  621. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  622. mmc_hostname(host->mmc));
  623. sdhci_dumpregs(host);
  624. return;
  625. }
  626. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  627. host->data->error = MMC_ERR_TIMEOUT;
  628. else if (intmask & SDHCI_INT_DATA_CRC)
  629. host->data->error = MMC_ERR_BADCRC;
  630. else if (intmask & SDHCI_INT_DATA_END_BIT)
  631. host->data->error = MMC_ERR_FAILED;
  632. if (host->data->error != MMC_ERR_NONE)
  633. sdhci_finish_data(host);
  634. else {
  635. if (intmask & (SDHCI_INT_BUF_FULL | SDHCI_INT_BUF_EMPTY))
  636. sdhci_transfer_pio(host);
  637. if (intmask & SDHCI_INT_DATA_END)
  638. sdhci_finish_data(host);
  639. }
  640. }
  641. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  642. {
  643. irqreturn_t result;
  644. struct sdhci_host* host = dev_id;
  645. u32 intmask;
  646. spin_lock(&host->lock);
  647. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  648. if (!intmask) {
  649. result = IRQ_NONE;
  650. goto out;
  651. }
  652. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  653. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
  654. tasklet_schedule(&host->card_tasklet);
  655. if (intmask & SDHCI_INT_CMD_MASK) {
  656. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  657. writel(intmask & SDHCI_INT_CMD_MASK,
  658. host->ioaddr + SDHCI_INT_STATUS);
  659. }
  660. if (intmask & SDHCI_INT_DATA_MASK) {
  661. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  662. writel(intmask & SDHCI_INT_DATA_MASK,
  663. host->ioaddr + SDHCI_INT_STATUS);
  664. }
  665. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  666. if (intmask & SDHCI_INT_CARD_INT) {
  667. printk(KERN_ERR "%s: Unexpected card interrupt. Please "
  668. "report this to " BUGMAIL ".\n",
  669. mmc_hostname(host->mmc));
  670. sdhci_dumpregs(host);
  671. }
  672. if (intmask & SDHCI_INT_BUS_POWER) {
  673. printk(KERN_ERR "%s: Unexpected bus power interrupt. Please "
  674. "report this to " BUGMAIL ".\n",
  675. mmc_hostname(host->mmc));
  676. sdhci_dumpregs(host);
  677. }
  678. if (intmask & SDHCI_INT_ACMD12ERR) {
  679. printk(KERN_ERR "%s: Unexpected auto CMD12 error. Please "
  680. "report this to " BUGMAIL ".\n",
  681. mmc_hostname(host->mmc));
  682. sdhci_dumpregs(host);
  683. writew(~0, host->ioaddr + SDHCI_ACMD12_ERR);
  684. }
  685. if (intmask)
  686. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  687. result = IRQ_HANDLED;
  688. out:
  689. spin_unlock(&host->lock);
  690. return result;
  691. }
  692. /*****************************************************************************\
  693. * *
  694. * Suspend/resume *
  695. * *
  696. \*****************************************************************************/
  697. #ifdef CONFIG_PM
  698. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  699. {
  700. struct sdhci_chip *chip;
  701. int i, ret;
  702. chip = pci_get_drvdata(pdev);
  703. if (!chip)
  704. return 0;
  705. DBG("Suspending...\n");
  706. for (i = 0;i < chip->num_slots;i++) {
  707. if (!chip->hosts[i])
  708. continue;
  709. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  710. if (ret) {
  711. for (i--;i >= 0;i--)
  712. mmc_resume_host(chip->hosts[i]->mmc);
  713. return ret;
  714. }
  715. }
  716. pci_save_state(pdev);
  717. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  718. pci_disable_device(pdev);
  719. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  720. return 0;
  721. }
  722. static int sdhci_resume (struct pci_dev *pdev)
  723. {
  724. struct sdhci_chip *chip;
  725. int i, ret;
  726. chip = pci_get_drvdata(pdev);
  727. if (!chip)
  728. return 0;
  729. DBG("Resuming...\n");
  730. pci_set_power_state(pdev, PCI_D0);
  731. pci_restore_state(pdev);
  732. pci_enable_device(pdev);
  733. for (i = 0;i < chip->num_slots;i++) {
  734. if (!chip->hosts[i])
  735. continue;
  736. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  737. pci_set_master(pdev);
  738. sdhci_init(chip->hosts[i]);
  739. ret = mmc_resume_host(chip->hosts[i]->mmc);
  740. if (ret)
  741. return ret;
  742. }
  743. return 0;
  744. }
  745. #else /* CONFIG_PM */
  746. #define sdhci_suspend NULL
  747. #define sdhci_resume NULL
  748. #endif /* CONFIG_PM */
  749. /*****************************************************************************\
  750. * *
  751. * Device probing/removal *
  752. * *
  753. \*****************************************************************************/
  754. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  755. {
  756. int ret;
  757. struct sdhci_chip *chip;
  758. struct mmc_host *mmc;
  759. struct sdhci_host *host;
  760. u8 first_bar;
  761. unsigned int caps;
  762. chip = pci_get_drvdata(pdev);
  763. BUG_ON(!chip);
  764. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  765. if (ret)
  766. return ret;
  767. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  768. if (first_bar > 5) {
  769. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  770. return -ENODEV;
  771. }
  772. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  773. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  774. return -ENODEV;
  775. }
  776. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  777. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  778. return -ENODEV;
  779. }
  780. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  781. if (!mmc)
  782. return -ENOMEM;
  783. host = mmc_priv(mmc);
  784. host->mmc = mmc;
  785. host->bar = first_bar + slot;
  786. host->addr = pci_resource_start(pdev, host->bar);
  787. host->irq = pdev->irq;
  788. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  789. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  790. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  791. if (ret)
  792. goto free;
  793. host->ioaddr = ioremap_nocache(host->addr,
  794. pci_resource_len(pdev, host->bar));
  795. if (!host->ioaddr) {
  796. ret = -ENOMEM;
  797. goto release;
  798. }
  799. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  800. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  801. host->flags |= SDHCI_USE_DMA;
  802. if (host->flags & SDHCI_USE_DMA) {
  803. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  804. printk(KERN_WARNING "%s: No suitable DMA available. "
  805. "Falling back to PIO.\n", host->slot_descr);
  806. host->flags &= ~SDHCI_USE_DMA;
  807. }
  808. }
  809. if (host->flags & SDHCI_USE_DMA)
  810. pci_set_master(pdev);
  811. else /* XXX: Hack to get MMC layer to avoid highmem */
  812. pdev->dma_mask = 0;
  813. host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  814. host->max_clk *= 1000000;
  815. /*
  816. * Set host parameters.
  817. */
  818. mmc->ops = &sdhci_ops;
  819. mmc->f_min = host->max_clk / 256;
  820. mmc->f_max = host->max_clk;
  821. mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
  822. mmc->caps = MMC_CAP_4_BIT_DATA;
  823. spin_lock_init(&host->lock);
  824. /*
  825. * Maximum number of segments. Hardware cannot do scatter lists.
  826. */
  827. if (host->flags & SDHCI_USE_DMA)
  828. mmc->max_hw_segs = 1;
  829. else
  830. mmc->max_hw_segs = 16;
  831. mmc->max_phys_segs = 16;
  832. /*
  833. * Maximum number of sectors in one transfer. Limited by sector
  834. * count register.
  835. */
  836. mmc->max_sectors = 0x3FFF;
  837. /*
  838. * Maximum segment size. Could be one segment with the maximum number
  839. * of sectors.
  840. */
  841. mmc->max_seg_size = mmc->max_sectors * 512;
  842. /*
  843. * Init tasklets.
  844. */
  845. tasklet_init(&host->card_tasklet,
  846. sdhci_tasklet_card, (unsigned long)host);
  847. tasklet_init(&host->finish_tasklet,
  848. sdhci_tasklet_finish, (unsigned long)host);
  849. setup_timer(&host->timer, sdhci_timeout_timer, (int)host);
  850. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  851. host->slot_descr, host);
  852. if (ret)
  853. goto unmap;
  854. sdhci_init(host);
  855. #ifdef CONFIG_MMC_DEBUG
  856. sdhci_dumpregs(host);
  857. #endif
  858. host->chip = chip;
  859. chip->hosts[slot] = host;
  860. mmc_add_host(mmc);
  861. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  862. host->addr, host->irq,
  863. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  864. return 0;
  865. unmap:
  866. tasklet_kill(&host->card_tasklet);
  867. tasklet_kill(&host->finish_tasklet);
  868. iounmap(host->ioaddr);
  869. release:
  870. pci_release_region(pdev, host->bar);
  871. free:
  872. mmc_free_host(mmc);
  873. return ret;
  874. }
  875. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  876. {
  877. struct sdhci_chip *chip;
  878. struct mmc_host *mmc;
  879. struct sdhci_host *host;
  880. chip = pci_get_drvdata(pdev);
  881. host = chip->hosts[slot];
  882. mmc = host->mmc;
  883. chip->hosts[slot] = NULL;
  884. mmc_remove_host(mmc);
  885. sdhci_reset(host, SDHCI_RESET_ALL);
  886. free_irq(host->irq, host);
  887. del_timer_sync(&host->timer);
  888. tasklet_kill(&host->card_tasklet);
  889. tasklet_kill(&host->finish_tasklet);
  890. iounmap(host->ioaddr);
  891. pci_release_region(pdev, host->bar);
  892. mmc_free_host(mmc);
  893. }
  894. static int __devinit sdhci_probe(struct pci_dev *pdev,
  895. const struct pci_device_id *ent)
  896. {
  897. int ret, i;
  898. u8 slots;
  899. struct sdhci_chip *chip;
  900. BUG_ON(pdev == NULL);
  901. BUG_ON(ent == NULL);
  902. DBG("found at %s\n", pci_name(pdev));
  903. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  904. if (ret)
  905. return ret;
  906. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  907. DBG("found %d slot(s)\n", slots);
  908. if (slots == 0)
  909. return -ENODEV;
  910. ret = pci_enable_device(pdev);
  911. if (ret)
  912. return ret;
  913. chip = kzalloc(sizeof(struct sdhci_chip) +
  914. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  915. if (!chip) {
  916. ret = -ENOMEM;
  917. goto err;
  918. }
  919. chip->pdev = pdev;
  920. chip->num_slots = slots;
  921. pci_set_drvdata(pdev, chip);
  922. for (i = 0;i < slots;i++) {
  923. ret = sdhci_probe_slot(pdev, i);
  924. if (ret) {
  925. for (i--;i >= 0;i--)
  926. sdhci_remove_slot(pdev, i);
  927. goto free;
  928. }
  929. }
  930. return 0;
  931. free:
  932. pci_set_drvdata(pdev, NULL);
  933. kfree(chip);
  934. err:
  935. pci_disable_device(pdev);
  936. return ret;
  937. }
  938. static void __devexit sdhci_remove(struct pci_dev *pdev)
  939. {
  940. int i;
  941. struct sdhci_chip *chip;
  942. chip = pci_get_drvdata(pdev);
  943. if (chip) {
  944. for (i = 0;i < chip->num_slots;i++)
  945. sdhci_remove_slot(pdev, i);
  946. pci_set_drvdata(pdev, NULL);
  947. kfree(chip);
  948. }
  949. pci_disable_device(pdev);
  950. }
  951. static struct pci_driver sdhci_driver = {
  952. .name = DRIVER_NAME,
  953. .id_table = pci_ids,
  954. .probe = sdhci_probe,
  955. .remove = __devexit_p(sdhci_remove),
  956. .suspend = sdhci_suspend,
  957. .resume = sdhci_resume,
  958. };
  959. /*****************************************************************************\
  960. * *
  961. * Driver init/exit *
  962. * *
  963. \*****************************************************************************/
  964. static int __init sdhci_drv_init(void)
  965. {
  966. printk(KERN_INFO DRIVER_NAME
  967. ": Secure Digital Host Controller Interface driver, "
  968. DRIVER_VERSION "\n");
  969. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  970. return pci_register_driver(&sdhci_driver);
  971. }
  972. static void __exit sdhci_drv_exit(void)
  973. {
  974. DBG("Exiting\n");
  975. pci_unregister_driver(&sdhci_driver);
  976. }
  977. module_init(sdhci_drv_init);
  978. module_exit(sdhci_drv_exit);
  979. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  980. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  981. MODULE_VERSION(DRIVER_VERSION);
  982. MODULE_LICENSE("GPL");