radeon_object.c 13 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30. * Dave Airlie
  31. */
  32. #include <linux/list.h>
  33. #include <drm/drmP.h>
  34. #include "radeon_drm.h"
  35. #include "radeon.h"
  36. int radeon_ttm_init(struct radeon_device *rdev);
  37. void radeon_ttm_fini(struct radeon_device *rdev);
  38. static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  39. /*
  40. * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  41. * function are calling it.
  42. */
  43. static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  44. {
  45. struct radeon_bo *bo;
  46. bo = container_of(tbo, struct radeon_bo, tbo);
  47. mutex_lock(&bo->rdev->gem.mutex);
  48. list_del_init(&bo->list);
  49. mutex_unlock(&bo->rdev->gem.mutex);
  50. radeon_bo_clear_surface_reg(bo);
  51. kfree(bo);
  52. }
  53. static inline u32 radeon_ttm_flags_from_domain(u32 domain)
  54. {
  55. u32 flags = 0;
  56. if (domain & RADEON_GEM_DOMAIN_VRAM) {
  57. flags |= TTM_PL_FLAG_VRAM | TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
  58. }
  59. if (domain & RADEON_GEM_DOMAIN_GTT) {
  60. flags |= TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  61. }
  62. if (domain & RADEON_GEM_DOMAIN_CPU) {
  63. flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
  64. }
  65. if (!flags) {
  66. flags |= TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING;
  67. }
  68. return flags;
  69. }
  70. void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  71. {
  72. u32 c = 0;
  73. rbo->placement.fpfn = 0;
  74. rbo->placement.lpfn = 0;
  75. rbo->placement.placement = rbo->placements;
  76. rbo->placement.busy_placement = rbo->placements;
  77. if (domain & RADEON_GEM_DOMAIN_VRAM)
  78. rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  79. TTM_PL_FLAG_VRAM;
  80. if (domain & RADEON_GEM_DOMAIN_GTT)
  81. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  82. if (domain & RADEON_GEM_DOMAIN_CPU)
  83. rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  84. rbo->placement.num_placement = c;
  85. rbo->placement.num_busy_placement = c;
  86. }
  87. int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
  88. unsigned long size, bool kernel, u32 domain,
  89. struct radeon_bo **bo_ptr)
  90. {
  91. struct radeon_bo *bo;
  92. enum ttm_bo_type type;
  93. u32 flags;
  94. int r;
  95. if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
  96. rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
  97. }
  98. if (kernel) {
  99. type = ttm_bo_type_kernel;
  100. } else {
  101. type = ttm_bo_type_device;
  102. }
  103. *bo_ptr = NULL;
  104. bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
  105. if (bo == NULL)
  106. return -ENOMEM;
  107. bo->rdev = rdev;
  108. bo->gobj = gobj;
  109. bo->surface_reg = -1;
  110. INIT_LIST_HEAD(&bo->list);
  111. flags = radeon_ttm_flags_from_domain(domain);
  112. retry:
  113. r = ttm_buffer_object_init(&rdev->mman.bdev, &bo->tbo, size, type,
  114. flags, 0, 0, true, NULL, size,
  115. &radeon_ttm_bo_destroy);
  116. if (unlikely(r != 0)) {
  117. if (r == -ERESTART)
  118. goto retry;
  119. /* ttm call radeon_ttm_object_object_destroy if error happen */
  120. dev_err(rdev->dev, "object_init failed for (%ld, 0x%08X)\n",
  121. size, flags);
  122. return r;
  123. }
  124. *bo_ptr = bo;
  125. if (gobj) {
  126. mutex_lock(&bo->rdev->gem.mutex);
  127. list_add_tail(&bo->list, &rdev->gem.objects);
  128. mutex_unlock(&bo->rdev->gem.mutex);
  129. }
  130. return 0;
  131. }
  132. int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
  133. {
  134. bool is_iomem;
  135. int r;
  136. if (bo->kptr) {
  137. if (ptr) {
  138. *ptr = bo->kptr;
  139. }
  140. return 0;
  141. }
  142. r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
  143. if (r) {
  144. return r;
  145. }
  146. bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
  147. if (ptr) {
  148. *ptr = bo->kptr;
  149. }
  150. radeon_bo_check_tiling(bo, 0, 0);
  151. return 0;
  152. }
  153. void radeon_bo_kunmap(struct radeon_bo *bo)
  154. {
  155. if (bo->kptr == NULL)
  156. return;
  157. bo->kptr = NULL;
  158. radeon_bo_check_tiling(bo, 0, 0);
  159. ttm_bo_kunmap(&bo->kmap);
  160. }
  161. void radeon_bo_unref(struct radeon_bo **bo)
  162. {
  163. struct ttm_buffer_object *tbo;
  164. if ((*bo) == NULL)
  165. return;
  166. tbo = &((*bo)->tbo);
  167. ttm_bo_unref(&tbo);
  168. if (tbo == NULL)
  169. *bo = NULL;
  170. }
  171. int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
  172. {
  173. int r, i;
  174. radeon_ttm_placement_from_domain(bo, domain);
  175. if (bo->pin_count) {
  176. bo->pin_count++;
  177. if (gpu_addr)
  178. *gpu_addr = radeon_bo_gpu_offset(bo);
  179. return 0;
  180. }
  181. radeon_ttm_placement_from_domain(bo, domain);
  182. for (i = 0; i < bo->placement.num_placement; i++)
  183. bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
  184. retry:
  185. r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false);
  186. if (likely(r == 0)) {
  187. bo->pin_count = 1;
  188. if (gpu_addr != NULL)
  189. *gpu_addr = radeon_bo_gpu_offset(bo);
  190. }
  191. if (unlikely(r != 0)) {
  192. if (r == -ERESTART)
  193. goto retry;
  194. dev_err(bo->rdev->dev, "%p pin failed\n", bo);
  195. }
  196. return r;
  197. }
  198. int radeon_bo_unpin(struct radeon_bo *bo)
  199. {
  200. int r, i;
  201. if (!bo->pin_count) {
  202. dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
  203. return 0;
  204. }
  205. bo->pin_count--;
  206. if (bo->pin_count)
  207. return 0;
  208. for (i = 0; i < bo->placement.num_placement; i++)
  209. bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
  210. retry:
  211. r = ttm_buffer_object_validate(&bo->tbo, &bo->placement, true, false);
  212. if (unlikely(r != 0)) {
  213. if (r == -ERESTART)
  214. goto retry;
  215. dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
  216. return r;
  217. }
  218. return 0;
  219. }
  220. int radeon_bo_evict_vram(struct radeon_device *rdev)
  221. {
  222. if (rdev->flags & RADEON_IS_IGP) {
  223. /* Useless to evict on IGP chips */
  224. return 0;
  225. }
  226. return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
  227. }
  228. void radeon_bo_force_delete(struct radeon_device *rdev)
  229. {
  230. struct radeon_bo *bo, *n;
  231. struct drm_gem_object *gobj;
  232. if (list_empty(&rdev->gem.objects)) {
  233. return;
  234. }
  235. dev_err(rdev->dev, "Userspace still has active objects !\n");
  236. list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  237. mutex_lock(&rdev->ddev->struct_mutex);
  238. gobj = bo->gobj;
  239. dev_err(rdev->dev, "%p %p %lu %lu force free\n",
  240. gobj, bo, (unsigned long)gobj->size,
  241. *((unsigned long *)&gobj->refcount));
  242. mutex_lock(&bo->rdev->gem.mutex);
  243. list_del_init(&bo->list);
  244. mutex_unlock(&bo->rdev->gem.mutex);
  245. radeon_bo_unref(&bo);
  246. gobj->driver_private = NULL;
  247. drm_gem_object_unreference(gobj);
  248. mutex_unlock(&rdev->ddev->struct_mutex);
  249. }
  250. }
  251. int radeon_bo_init(struct radeon_device *rdev)
  252. {
  253. /* Add an MTRR for the VRAM */
  254. rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
  255. MTRR_TYPE_WRCOMB, 1);
  256. DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
  257. rdev->mc.mc_vram_size >> 20,
  258. (unsigned long long)rdev->mc.aper_size >> 20);
  259. DRM_INFO("RAM width %dbits %cDR\n",
  260. rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
  261. return radeon_ttm_init(rdev);
  262. }
  263. void radeon_bo_fini(struct radeon_device *rdev)
  264. {
  265. radeon_ttm_fini(rdev);
  266. }
  267. void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
  268. struct list_head *head)
  269. {
  270. if (lobj->wdomain) {
  271. list_add(&lobj->list, head);
  272. } else {
  273. list_add_tail(&lobj->list, head);
  274. }
  275. }
  276. int radeon_bo_list_reserve(struct list_head *head)
  277. {
  278. struct radeon_bo_list *lobj;
  279. int r;
  280. list_for_each_entry(lobj, head, list){
  281. r = radeon_bo_reserve(lobj->bo, false);
  282. if (unlikely(r != 0))
  283. return r;
  284. }
  285. return 0;
  286. }
  287. void radeon_bo_list_unreserve(struct list_head *head)
  288. {
  289. struct radeon_bo_list *lobj;
  290. list_for_each_entry(lobj, head, list) {
  291. /* only unreserve object we successfully reserved */
  292. if (radeon_bo_is_reserved(lobj->bo))
  293. radeon_bo_unreserve(lobj->bo);
  294. }
  295. }
  296. int radeon_bo_list_validate(struct list_head *head, void *fence)
  297. {
  298. struct radeon_bo_list *lobj;
  299. struct radeon_bo *bo;
  300. struct radeon_fence *old_fence = NULL;
  301. int r;
  302. r = radeon_bo_list_reserve(head);
  303. if (unlikely(r != 0)) {
  304. return r;
  305. }
  306. list_for_each_entry(lobj, head, list) {
  307. bo = lobj->bo;
  308. if (!bo->pin_count) {
  309. if (lobj->wdomain) {
  310. radeon_ttm_placement_from_domain(bo,
  311. lobj->wdomain);
  312. } else {
  313. radeon_ttm_placement_from_domain(bo,
  314. lobj->rdomain);
  315. }
  316. retry:
  317. r = ttm_buffer_object_validate(&bo->tbo,
  318. &bo->placement,
  319. true, false);
  320. if (unlikely(r)) {
  321. if (r == -ERESTART)
  322. goto retry;
  323. return r;
  324. }
  325. }
  326. lobj->gpu_offset = radeon_bo_gpu_offset(bo);
  327. lobj->tiling_flags = bo->tiling_flags;
  328. if (fence) {
  329. old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
  330. bo->tbo.sync_obj = radeon_fence_ref(fence);
  331. bo->tbo.sync_obj_arg = NULL;
  332. }
  333. if (old_fence) {
  334. radeon_fence_unref(&old_fence);
  335. }
  336. }
  337. return 0;
  338. }
  339. void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
  340. {
  341. struct radeon_bo_list *lobj;
  342. struct radeon_fence *old_fence;
  343. if (fence)
  344. list_for_each_entry(lobj, head, list) {
  345. old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
  346. if (old_fence == fence) {
  347. lobj->bo->tbo.sync_obj = NULL;
  348. radeon_fence_unref(&old_fence);
  349. }
  350. }
  351. radeon_bo_list_unreserve(head);
  352. }
  353. int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
  354. struct vm_area_struct *vma)
  355. {
  356. return ttm_fbdev_mmap(vma, &bo->tbo);
  357. }
  358. static int radeon_bo_get_surface_reg(struct radeon_bo *bo)
  359. {
  360. struct radeon_device *rdev = bo->rdev;
  361. struct radeon_surface_reg *reg;
  362. struct radeon_bo *old_object;
  363. int steal;
  364. int i;
  365. BUG_ON(!atomic_read(&bo->tbo.reserved));
  366. if (!bo->tiling_flags)
  367. return 0;
  368. if (bo->surface_reg >= 0) {
  369. reg = &rdev->surface_regs[bo->surface_reg];
  370. i = bo->surface_reg;
  371. goto out;
  372. }
  373. steal = -1;
  374. for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  375. reg = &rdev->surface_regs[i];
  376. if (!reg->bo)
  377. break;
  378. old_object = reg->bo;
  379. if (old_object->pin_count == 0)
  380. steal = i;
  381. }
  382. /* if we are all out */
  383. if (i == RADEON_GEM_MAX_SURFACES) {
  384. if (steal == -1)
  385. return -ENOMEM;
  386. /* find someone with a surface reg and nuke their BO */
  387. reg = &rdev->surface_regs[steal];
  388. old_object = reg->bo;
  389. /* blow away the mapping */
  390. DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
  391. ttm_bo_unmap_virtual(&old_object->tbo);
  392. old_object->surface_reg = -1;
  393. i = steal;
  394. }
  395. bo->surface_reg = i;
  396. reg->bo = bo;
  397. out:
  398. radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
  399. bo->tbo.mem.mm_node->start << PAGE_SHIFT,
  400. bo->tbo.num_pages << PAGE_SHIFT);
  401. return 0;
  402. }
  403. static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
  404. {
  405. struct radeon_device *rdev = bo->rdev;
  406. struct radeon_surface_reg *reg;
  407. if (bo->surface_reg == -1)
  408. return;
  409. reg = &rdev->surface_regs[bo->surface_reg];
  410. radeon_clear_surface_reg(rdev, bo->surface_reg);
  411. reg->bo = NULL;
  412. bo->surface_reg = -1;
  413. }
  414. int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
  415. uint32_t tiling_flags, uint32_t pitch)
  416. {
  417. int r;
  418. r = radeon_bo_reserve(bo, false);
  419. if (unlikely(r != 0))
  420. return r;
  421. bo->tiling_flags = tiling_flags;
  422. bo->pitch = pitch;
  423. radeon_bo_unreserve(bo);
  424. return 0;
  425. }
  426. void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
  427. uint32_t *tiling_flags,
  428. uint32_t *pitch)
  429. {
  430. BUG_ON(!atomic_read(&bo->tbo.reserved));
  431. if (tiling_flags)
  432. *tiling_flags = bo->tiling_flags;
  433. if (pitch)
  434. *pitch = bo->pitch;
  435. }
  436. int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
  437. bool force_drop)
  438. {
  439. BUG_ON(!atomic_read(&bo->tbo.reserved));
  440. if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
  441. return 0;
  442. if (force_drop) {
  443. radeon_bo_clear_surface_reg(bo);
  444. return 0;
  445. }
  446. if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
  447. if (!has_moved)
  448. return 0;
  449. if (bo->surface_reg >= 0)
  450. radeon_bo_clear_surface_reg(bo);
  451. return 0;
  452. }
  453. if ((bo->surface_reg >= 0) && !has_moved)
  454. return 0;
  455. return radeon_bo_get_surface_reg(bo);
  456. }
  457. void radeon_bo_move_notify(struct ttm_buffer_object *bo,
  458. struct ttm_mem_reg *mem)
  459. {
  460. struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
  461. radeon_bo_check_tiling(rbo, 0, 1);
  462. }
  463. void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
  464. {
  465. struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
  466. radeon_bo_check_tiling(rbo, 0, 0);
  467. }