wm8958-dsp2.c 27 KB

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  1. /*
  2. * wm8958-dsp2.c -- WM8958 DSP2 support
  3. *
  4. * Copyright 2011 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <sound/soc.h>
  21. #include <sound/initval.h>
  22. #include <sound/tlv.h>
  23. #include <trace/events/asoc.h>
  24. #include <linux/mfd/wm8994/core.h>
  25. #include <linux/mfd/wm8994/registers.h>
  26. #include <linux/mfd/wm8994/pdata.h>
  27. #include <linux/mfd/wm8994/gpio.h>
  28. #include "wm8994.h"
  29. #define WM_FW_BLOCK_INFO 0xff
  30. #define WM_FW_BLOCK_PM 0x00
  31. #define WM_FW_BLOCK_X 0x01
  32. #define WM_FW_BLOCK_Y 0x02
  33. #define WM_FW_BLOCK_Z 0x03
  34. #define WM_FW_BLOCK_I 0x06
  35. #define WM_FW_BLOCK_A 0x08
  36. #define WM_FW_BLOCK_C 0x0c
  37. static int wm8958_dsp2_fw(struct snd_soc_codec *codec, const char *name,
  38. const struct firmware *fw, bool check)
  39. {
  40. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  41. u64 data64;
  42. u32 data32;
  43. const u8 *data;
  44. char *str;
  45. size_t block_len, len;
  46. int ret = 0;
  47. /* Suppress unneeded downloads */
  48. if (wm8994->cur_fw == fw)
  49. return 0;
  50. if (fw->size < 32) {
  51. dev_err(codec->dev, "%s: firmware too short\n", name);
  52. goto err;
  53. }
  54. if (memcmp(fw->data, "WMFW", 4) != 0) {
  55. dev_err(codec->dev, "%s: firmware has bad file magic %08x\n",
  56. name, data32);
  57. goto err;
  58. }
  59. memcpy(&data32, fw->data + 4, sizeof(data32));
  60. len = be32_to_cpu(data32);
  61. memcpy(&data32, fw->data + 8, sizeof(data32));
  62. data32 = be32_to_cpu(data32);
  63. if ((data32 >> 24) & 0xff) {
  64. dev_err(codec->dev, "%s: unsupported firmware version %d\n",
  65. name, (data32 >> 24) & 0xff);
  66. goto err;
  67. }
  68. if ((data32 & 0xffff) != 8958) {
  69. dev_err(codec->dev, "%s: unsupported target device %d\n",
  70. name, data32 & 0xffff);
  71. goto err;
  72. }
  73. if (((data32 >> 16) & 0xff) != 0xc) {
  74. dev_err(codec->dev, "%s: unsupported target core %d\n",
  75. name, (data32 >> 16) & 0xff);
  76. goto err;
  77. }
  78. if (check) {
  79. memcpy(&data64, fw->data + 24, sizeof(u64));
  80. dev_info(codec->dev, "%s timestamp %llx\n",
  81. name, be64_to_cpu(data64));
  82. } else {
  83. snd_soc_write(codec, 0x102, 0x2);
  84. snd_soc_write(codec, 0x900, 0x2);
  85. }
  86. data = fw->data + len;
  87. len = fw->size - len;
  88. while (len) {
  89. if (len < 12) {
  90. dev_err(codec->dev, "%s short data block of %d\n",
  91. name, len);
  92. goto err;
  93. }
  94. memcpy(&data32, data + 4, sizeof(data32));
  95. block_len = be32_to_cpu(data32);
  96. if (block_len + 8 > len) {
  97. dev_err(codec->dev, "%d byte block longer than file\n",
  98. block_len);
  99. goto err;
  100. }
  101. if (block_len == 0) {
  102. dev_err(codec->dev, "Zero length block\n");
  103. goto err;
  104. }
  105. memcpy(&data32, data, sizeof(data32));
  106. data32 = be32_to_cpu(data32);
  107. switch ((data32 >> 24) & 0xff) {
  108. case WM_FW_BLOCK_INFO:
  109. /* Informational text */
  110. if (!check)
  111. break;
  112. str = kzalloc(block_len + 1, GFP_KERNEL);
  113. if (str) {
  114. memcpy(str, data + 8, block_len);
  115. dev_info(codec->dev, "%s: %s\n", name, str);
  116. kfree(str);
  117. } else {
  118. dev_err(codec->dev, "Out of memory\n");
  119. }
  120. break;
  121. case WM_FW_BLOCK_PM:
  122. case WM_FW_BLOCK_X:
  123. case WM_FW_BLOCK_Y:
  124. case WM_FW_BLOCK_Z:
  125. case WM_FW_BLOCK_I:
  126. case WM_FW_BLOCK_A:
  127. case WM_FW_BLOCK_C:
  128. dev_dbg(codec->dev, "%s: %d bytes of %x@%x\n", name,
  129. block_len, (data32 >> 24) & 0xff,
  130. data32 & 0xffffff);
  131. if (check)
  132. break;
  133. data32 &= 0xffffff;
  134. wm8994_bulk_write(codec->control_data,
  135. data32 & 0xffffff,
  136. block_len / 2,
  137. (void *)(data + 8));
  138. break;
  139. default:
  140. dev_warn(codec->dev, "%s: unknown block type %d\n",
  141. name, (data32 >> 24) & 0xff);
  142. break;
  143. }
  144. /* Round up to the next 32 bit word */
  145. block_len += block_len % 4;
  146. data += block_len + 8;
  147. len -= block_len + 8;
  148. }
  149. if (!check) {
  150. dev_dbg(codec->dev, "%s: download done\n", name);
  151. wm8994->cur_fw = fw;
  152. } else {
  153. dev_info(codec->dev, "%s: got firmware\n", name);
  154. }
  155. goto ok;
  156. err:
  157. ret = -EINVAL;
  158. ok:
  159. if (!check) {
  160. snd_soc_write(codec, 0x900, 0x0);
  161. snd_soc_write(codec, 0x102, 0x0);
  162. }
  163. return ret;
  164. }
  165. static void wm8958_dsp_start_mbc(struct snd_soc_codec *codec, int path)
  166. {
  167. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  168. struct wm8994_pdata *pdata = wm8994->pdata;
  169. int i;
  170. /* If the DSP is already running then noop */
  171. if (snd_soc_read(codec, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
  172. return;
  173. /* If we have MBC firmware download it */
  174. if (wm8994->mbc)
  175. wm8958_dsp2_fw(codec, "MBC", wm8994->mbc, false);
  176. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  177. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  178. /* If we've got user supplied MBC settings use them */
  179. if (pdata && pdata->num_mbc_cfgs) {
  180. struct wm8958_mbc_cfg *cfg
  181. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  182. for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
  183. snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
  184. cfg->coeff_regs[i]);
  185. for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
  186. snd_soc_write(codec,
  187. i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
  188. cfg->cutoff_regs[i]);
  189. }
  190. /* Run the DSP */
  191. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  192. WM8958_DSP2_RUNR);
  193. /* And we're off! */
  194. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  195. WM8958_MBC_ENA |
  196. WM8958_MBC_SEL_MASK,
  197. path << WM8958_MBC_SEL_SHIFT |
  198. WM8958_MBC_ENA);
  199. }
  200. static void wm8958_dsp_start_vss(struct snd_soc_codec *codec, int path)
  201. {
  202. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  203. struct wm8994_pdata *pdata = wm8994->pdata;
  204. int i, ena;
  205. if (wm8994->mbc_vss)
  206. wm8958_dsp2_fw(codec, "MBC+VSS", wm8994->mbc_vss, false);
  207. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  208. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  209. /* If we've got user supplied settings use them */
  210. if (pdata && pdata->num_mbc_cfgs) {
  211. struct wm8958_mbc_cfg *cfg
  212. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  213. for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
  214. snd_soc_write(codec, i + 0x2800,
  215. cfg->combined_regs[i]);
  216. }
  217. if (pdata && pdata->num_vss_cfgs) {
  218. struct wm8958_vss_cfg *cfg
  219. = &pdata->vss_cfgs[wm8994->vss_cfg];
  220. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  221. snd_soc_write(codec, i + 0x2600, cfg->regs[i]);
  222. }
  223. if (pdata && pdata->num_vss_hpf_cfgs) {
  224. struct wm8958_vss_hpf_cfg *cfg
  225. = &pdata->vss_hpf_cfgs[wm8994->vss_hpf_cfg];
  226. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  227. snd_soc_write(codec, i + 0x2400, cfg->regs[i]);
  228. }
  229. /* Run the DSP */
  230. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  231. WM8958_DSP2_RUNR);
  232. /* Enable the algorithms we've selected */
  233. ena = 0;
  234. if (wm8994->mbc_ena[path])
  235. ena |= 0x8;
  236. if (wm8994->hpf2_ena[path])
  237. ena |= 0x4;
  238. if (wm8994->hpf1_ena[path])
  239. ena |= 0x2;
  240. if (wm8994->vss_ena[path])
  241. ena |= 0x1;
  242. snd_soc_write(codec, 0x2201, ena);
  243. /* Switch the DSP into the data path */
  244. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  245. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  246. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  247. }
  248. static void wm8958_dsp_start_enh_eq(struct snd_soc_codec *codec, int path)
  249. {
  250. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  251. struct wm8994_pdata *pdata = wm8994->pdata;
  252. int i;
  253. wm8958_dsp2_fw(codec, "ENH_EQ", wm8994->enh_eq, false);
  254. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  255. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  256. /* If we've got user supplied settings use them */
  257. if (pdata && pdata->num_enh_eq_cfgs) {
  258. struct wm8958_enh_eq_cfg *cfg
  259. = &pdata->enh_eq_cfgs[wm8994->enh_eq_cfg];
  260. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  261. snd_soc_write(codec, i + 0x2200,
  262. cfg->regs[i]);
  263. }
  264. /* Run the DSP */
  265. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  266. WM8958_DSP2_RUNR);
  267. /* Switch the DSP into the data path */
  268. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  269. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  270. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  271. }
  272. static void wm8958_dsp_apply(struct snd_soc_codec *codec, int path, int start)
  273. {
  274. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  275. int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
  276. int ena, reg, aif;
  277. switch (path) {
  278. case 0:
  279. pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
  280. aif = 0;
  281. break;
  282. case 1:
  283. pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
  284. aif = 0;
  285. break;
  286. case 2:
  287. pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
  288. aif = 1;
  289. break;
  290. default:
  291. BUG();
  292. return;
  293. }
  294. /* Do we have both an active AIF and an active algorithm? */
  295. ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
  296. wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
  297. wm8994->enh_eq_ena[path];
  298. if (!pwr_reg)
  299. ena = 0;
  300. reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
  301. dev_dbg(codec->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
  302. path, wm8994->dsp_active, start, pwr_reg, reg);
  303. if (start && ena) {
  304. /* If either AIFnCLK is not yet enabled postpone */
  305. if (!(snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
  306. & WM8994_AIF1CLK_ENA_MASK) &&
  307. !(snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
  308. & WM8994_AIF2CLK_ENA_MASK))
  309. return;
  310. /* Switch the clock over to the appropriate AIF */
  311. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  312. WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
  313. aif << WM8958_DSP2CLK_SRC_SHIFT |
  314. WM8958_DSP2CLK_ENA);
  315. if (wm8994->enh_eq_ena[path])
  316. wm8958_dsp_start_enh_eq(codec, path);
  317. else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
  318. wm8994->hpf2_ena[path])
  319. wm8958_dsp_start_vss(codec, path);
  320. else if (wm8994->mbc_ena[path])
  321. wm8958_dsp_start_mbc(codec, path);
  322. wm8994->dsp_active = path;
  323. dev_dbg(codec->dev, "DSP running in path %d\n", path);
  324. }
  325. if (!start && wm8994->dsp_active == path) {
  326. /* If the DSP is already stopped then noop */
  327. if (!(reg & WM8958_DSP2_ENA))
  328. return;
  329. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  330. WM8958_MBC_ENA, 0);
  331. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  332. WM8958_DSP2_STOP);
  333. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  334. WM8958_DSP2_ENA, 0);
  335. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  336. WM8958_DSP2CLK_ENA, 0);
  337. wm8994->dsp_active = -1;
  338. dev_dbg(codec->dev, "DSP stopped\n");
  339. }
  340. }
  341. int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
  342. struct snd_kcontrol *kcontrol, int event)
  343. {
  344. struct snd_soc_codec *codec = w->codec;
  345. int i;
  346. switch (event) {
  347. case SND_SOC_DAPM_POST_PMU:
  348. case SND_SOC_DAPM_PRE_PMU:
  349. for (i = 0; i < 3; i++)
  350. wm8958_dsp_apply(codec, i, 1);
  351. break;
  352. case SND_SOC_DAPM_POST_PMD:
  353. case SND_SOC_DAPM_PRE_PMD:
  354. for (i = 0; i < 3; i++)
  355. wm8958_dsp_apply(codec, i, 0);
  356. break;
  357. }
  358. return 0;
  359. }
  360. /* Check if DSP2 is in use on another AIF */
  361. static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
  362. {
  363. int i;
  364. for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
  365. if (i == aif)
  366. continue;
  367. if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
  368. wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
  369. return 1;
  370. }
  371. return 0;
  372. }
  373. static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
  374. struct snd_ctl_elem_value *ucontrol)
  375. {
  376. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  377. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  378. struct wm8994_pdata *pdata = wm8994->pdata;
  379. int value = ucontrol->value.integer.value[0];
  380. int reg;
  381. /* Don't allow on the fly reconfiguration */
  382. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  383. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  384. return -EBUSY;
  385. if (value >= pdata->num_mbc_cfgs)
  386. return -EINVAL;
  387. wm8994->mbc_cfg = value;
  388. return 0;
  389. }
  390. static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
  391. struct snd_ctl_elem_value *ucontrol)
  392. {
  393. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  394. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  395. ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
  396. return 0;
  397. }
  398. static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
  399. struct snd_ctl_elem_info *uinfo)
  400. {
  401. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  402. uinfo->count = 1;
  403. uinfo->value.integer.min = 0;
  404. uinfo->value.integer.max = 1;
  405. return 0;
  406. }
  407. static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
  408. struct snd_ctl_elem_value *ucontrol)
  409. {
  410. int mbc = kcontrol->private_value;
  411. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  412. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  413. ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
  414. return 0;
  415. }
  416. static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
  417. struct snd_ctl_elem_value *ucontrol)
  418. {
  419. int mbc = kcontrol->private_value;
  420. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  421. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  422. if (ucontrol->value.integer.value[0] > 1)
  423. return -EINVAL;
  424. if (wm8958_dsp2_busy(wm8994, mbc)) {
  425. dev_dbg(codec->dev, "DSP2 active on %d already\n", mbc);
  426. return -EBUSY;
  427. }
  428. if (wm8994->enh_eq_ena[mbc])
  429. return -EBUSY;
  430. wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
  431. wm8958_dsp_apply(codec, mbc, wm8994->mbc_ena[mbc]);
  432. return 0;
  433. }
  434. #define WM8958_MBC_SWITCH(xname, xval) {\
  435. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  436. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  437. .info = wm8958_mbc_info, \
  438. .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
  439. .private_value = xval }
  440. static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
  441. struct snd_ctl_elem_value *ucontrol)
  442. {
  443. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  444. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  445. struct wm8994_pdata *pdata = wm8994->pdata;
  446. int value = ucontrol->value.integer.value[0];
  447. int reg;
  448. /* Don't allow on the fly reconfiguration */
  449. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  450. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  451. return -EBUSY;
  452. if (value >= pdata->num_vss_cfgs)
  453. return -EINVAL;
  454. wm8994->vss_cfg = value;
  455. return 0;
  456. }
  457. static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
  458. struct snd_ctl_elem_value *ucontrol)
  459. {
  460. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  461. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  462. ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
  463. return 0;
  464. }
  465. static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  466. struct snd_ctl_elem_value *ucontrol)
  467. {
  468. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  469. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  470. struct wm8994_pdata *pdata = wm8994->pdata;
  471. int value = ucontrol->value.integer.value[0];
  472. int reg;
  473. /* Don't allow on the fly reconfiguration */
  474. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  475. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  476. return -EBUSY;
  477. if (value >= pdata->num_vss_hpf_cfgs)
  478. return -EINVAL;
  479. wm8994->vss_hpf_cfg = value;
  480. return 0;
  481. }
  482. static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  483. struct snd_ctl_elem_value *ucontrol)
  484. {
  485. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  486. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  487. ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
  488. return 0;
  489. }
  490. static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
  491. struct snd_ctl_elem_info *uinfo)
  492. {
  493. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  494. uinfo->count = 1;
  495. uinfo->value.integer.min = 0;
  496. uinfo->value.integer.max = 1;
  497. return 0;
  498. }
  499. static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
  500. struct snd_ctl_elem_value *ucontrol)
  501. {
  502. int vss = kcontrol->private_value;
  503. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  504. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  505. ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
  506. return 0;
  507. }
  508. static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
  509. struct snd_ctl_elem_value *ucontrol)
  510. {
  511. int vss = kcontrol->private_value;
  512. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  513. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  514. if (ucontrol->value.integer.value[0] > 1)
  515. return -EINVAL;
  516. if (!wm8994->mbc_vss)
  517. return -ENODEV;
  518. if (wm8958_dsp2_busy(wm8994, vss)) {
  519. dev_dbg(codec->dev, "DSP2 active on %d already\n", vss);
  520. return -EBUSY;
  521. }
  522. if (wm8994->enh_eq_ena[vss])
  523. return -EBUSY;
  524. wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
  525. wm8958_dsp_apply(codec, vss, wm8994->vss_ena[vss]);
  526. return 0;
  527. }
  528. #define WM8958_VSS_SWITCH(xname, xval) {\
  529. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  530. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  531. .info = wm8958_vss_info, \
  532. .get = wm8958_vss_get, .put = wm8958_vss_put, \
  533. .private_value = xval }
  534. static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
  535. struct snd_ctl_elem_info *uinfo)
  536. {
  537. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  538. uinfo->count = 1;
  539. uinfo->value.integer.min = 0;
  540. uinfo->value.integer.max = 1;
  541. return 0;
  542. }
  543. static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
  544. struct snd_ctl_elem_value *ucontrol)
  545. {
  546. int hpf = kcontrol->private_value;
  547. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  548. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  549. if (hpf < 3)
  550. ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
  551. else
  552. ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
  553. return 0;
  554. }
  555. static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
  556. struct snd_ctl_elem_value *ucontrol)
  557. {
  558. int hpf = kcontrol->private_value;
  559. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  560. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  561. if (ucontrol->value.integer.value[0] > 1)
  562. return -EINVAL;
  563. if (!wm8994->mbc_vss)
  564. return -ENODEV;
  565. if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
  566. dev_dbg(codec->dev, "DSP2 active on %d already\n", hpf);
  567. return -EBUSY;
  568. }
  569. if (wm8994->enh_eq_ena[hpf % 3])
  570. return -EBUSY;
  571. if (hpf < 3)
  572. wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
  573. else
  574. wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
  575. wm8958_dsp_apply(codec, hpf % 3, ucontrol->value.integer.value[0]);
  576. return 0;
  577. }
  578. #define WM8958_HPF_SWITCH(xname, xval) {\
  579. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  580. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  581. .info = wm8958_hpf_info, \
  582. .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
  583. .private_value = xval }
  584. static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
  585. struct snd_ctl_elem_value *ucontrol)
  586. {
  587. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  588. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  589. struct wm8994_pdata *pdata = wm8994->pdata;
  590. int value = ucontrol->value.integer.value[0];
  591. int reg;
  592. /* Don't allow on the fly reconfiguration */
  593. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  594. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  595. return -EBUSY;
  596. if (value >= pdata->num_enh_eq_cfgs)
  597. return -EINVAL;
  598. wm8994->enh_eq_cfg = value;
  599. return 0;
  600. }
  601. static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
  602. struct snd_ctl_elem_value *ucontrol)
  603. {
  604. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  605. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  606. ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
  607. return 0;
  608. }
  609. static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
  610. struct snd_ctl_elem_info *uinfo)
  611. {
  612. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  613. uinfo->count = 1;
  614. uinfo->value.integer.min = 0;
  615. uinfo->value.integer.max = 1;
  616. return 0;
  617. }
  618. static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
  619. struct snd_ctl_elem_value *ucontrol)
  620. {
  621. int eq = kcontrol->private_value;
  622. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  623. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  624. ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
  625. return 0;
  626. }
  627. static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
  628. struct snd_ctl_elem_value *ucontrol)
  629. {
  630. int eq = kcontrol->private_value;
  631. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  632. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  633. if (ucontrol->value.integer.value[0] > 1)
  634. return -EINVAL;
  635. if (!wm8994->enh_eq)
  636. return -ENODEV;
  637. if (wm8958_dsp2_busy(wm8994, eq)) {
  638. dev_dbg(codec->dev, "DSP2 active on %d already\n", eq);
  639. return -EBUSY;
  640. }
  641. if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
  642. wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
  643. return -EBUSY;
  644. wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
  645. wm8958_dsp_apply(codec, eq, ucontrol->value.integer.value[0]);
  646. return 0;
  647. }
  648. #define WM8958_ENH_EQ_SWITCH(xname, xval) {\
  649. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  650. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  651. .info = wm8958_enh_eq_info, \
  652. .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
  653. .private_value = xval }
  654. static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
  655. WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
  656. WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
  657. WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
  658. };
  659. static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
  660. WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
  661. WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
  662. WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
  663. WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
  664. WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
  665. WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
  666. WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
  667. WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
  668. WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
  669. };
  670. static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
  671. WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
  672. WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
  673. WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
  674. };
  675. static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
  676. {
  677. struct snd_soc_codec *codec = context;
  678. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  679. if (fw && (wm8958_dsp2_fw(codec, "ENH_EQ", fw, true) == 0)) {
  680. mutex_lock(&codec->mutex);
  681. wm8994->enh_eq = fw;
  682. mutex_unlock(&codec->mutex);
  683. }
  684. }
  685. static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
  686. {
  687. struct snd_soc_codec *codec = context;
  688. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  689. if (fw && (wm8958_dsp2_fw(codec, "MBC+VSS", fw, true) == 0)) {
  690. mutex_lock(&codec->mutex);
  691. wm8994->mbc_vss = fw;
  692. mutex_unlock(&codec->mutex);
  693. }
  694. /* We can't have more than one request outstanding at once so
  695. * we daisy chain.
  696. */
  697. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  698. "wm8958_enh_eq.wfw", codec->dev, GFP_KERNEL,
  699. codec, wm8958_enh_eq_loaded);
  700. }
  701. static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
  702. {
  703. struct snd_soc_codec *codec = context;
  704. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  705. if (wm8958_dsp2_fw(codec, "MBC", fw, true) != 0)
  706. return;
  707. mutex_lock(&codec->mutex);
  708. wm8994->mbc = fw;
  709. mutex_unlock(&codec->mutex);
  710. /* We can't have more than one request outstanding at once so
  711. * we daisy chain.
  712. */
  713. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  714. "wm8958_mbc_vss.wfw", codec->dev, GFP_KERNEL,
  715. codec, wm8958_mbc_vss_loaded);
  716. }
  717. void wm8958_dsp2_init(struct snd_soc_codec *codec)
  718. {
  719. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  720. struct wm8994_pdata *pdata = wm8994->pdata;
  721. int ret, i;
  722. wm8994->dsp_active = -1;
  723. snd_soc_add_controls(codec, wm8958_mbc_snd_controls,
  724. ARRAY_SIZE(wm8958_mbc_snd_controls));
  725. snd_soc_add_controls(codec, wm8958_vss_snd_controls,
  726. ARRAY_SIZE(wm8958_vss_snd_controls));
  727. snd_soc_add_controls(codec, wm8958_enh_eq_snd_controls,
  728. ARRAY_SIZE(wm8958_enh_eq_snd_controls));
  729. /* We don't *require* firmware and don't want to delay boot */
  730. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  731. "wm8958_mbc.wfw", codec->dev, GFP_KERNEL,
  732. codec, wm8958_mbc_loaded);
  733. if (!pdata)
  734. return;
  735. if (pdata->num_mbc_cfgs) {
  736. struct snd_kcontrol_new control[] = {
  737. SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
  738. wm8958_get_mbc_enum, wm8958_put_mbc_enum),
  739. };
  740. /* We need an array of texts for the enum API */
  741. wm8994->mbc_texts = kmalloc(sizeof(char *)
  742. * pdata->num_mbc_cfgs, GFP_KERNEL);
  743. if (!wm8994->mbc_texts) {
  744. dev_err(wm8994->codec->dev,
  745. "Failed to allocate %d MBC config texts\n",
  746. pdata->num_mbc_cfgs);
  747. return;
  748. }
  749. for (i = 0; i < pdata->num_mbc_cfgs; i++)
  750. wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
  751. wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
  752. wm8994->mbc_enum.texts = wm8994->mbc_texts;
  753. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  754. if (ret != 0)
  755. dev_err(wm8994->codec->dev,
  756. "Failed to add MBC mode controls: %d\n", ret);
  757. }
  758. if (pdata->num_vss_cfgs) {
  759. struct snd_kcontrol_new control[] = {
  760. SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
  761. wm8958_get_vss_enum, wm8958_put_vss_enum),
  762. };
  763. /* We need an array of texts for the enum API */
  764. wm8994->vss_texts = kmalloc(sizeof(char *)
  765. * pdata->num_vss_cfgs, GFP_KERNEL);
  766. if (!wm8994->vss_texts) {
  767. dev_err(wm8994->codec->dev,
  768. "Failed to allocate %d VSS config texts\n",
  769. pdata->num_vss_cfgs);
  770. return;
  771. }
  772. for (i = 0; i < pdata->num_vss_cfgs; i++)
  773. wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
  774. wm8994->vss_enum.max = pdata->num_vss_cfgs;
  775. wm8994->vss_enum.texts = wm8994->vss_texts;
  776. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  777. if (ret != 0)
  778. dev_err(wm8994->codec->dev,
  779. "Failed to add VSS mode controls: %d\n", ret);
  780. }
  781. if (pdata->num_vss_hpf_cfgs) {
  782. struct snd_kcontrol_new control[] = {
  783. SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
  784. wm8958_get_vss_hpf_enum,
  785. wm8958_put_vss_hpf_enum),
  786. };
  787. /* We need an array of texts for the enum API */
  788. wm8994->vss_hpf_texts = kmalloc(sizeof(char *)
  789. * pdata->num_vss_hpf_cfgs, GFP_KERNEL);
  790. if (!wm8994->vss_hpf_texts) {
  791. dev_err(wm8994->codec->dev,
  792. "Failed to allocate %d VSS HPF config texts\n",
  793. pdata->num_vss_hpf_cfgs);
  794. return;
  795. }
  796. for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
  797. wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
  798. wm8994->vss_hpf_enum.max = pdata->num_vss_hpf_cfgs;
  799. wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
  800. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  801. if (ret != 0)
  802. dev_err(wm8994->codec->dev,
  803. "Failed to add VSS HPFmode controls: %d\n",
  804. ret);
  805. }
  806. if (pdata->num_enh_eq_cfgs) {
  807. struct snd_kcontrol_new control[] = {
  808. SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
  809. wm8958_get_enh_eq_enum,
  810. wm8958_put_enh_eq_enum),
  811. };
  812. /* We need an array of texts for the enum API */
  813. wm8994->enh_eq_texts = kmalloc(sizeof(char *)
  814. * pdata->num_enh_eq_cfgs, GFP_KERNEL);
  815. if (!wm8994->enh_eq_texts) {
  816. dev_err(wm8994->codec->dev,
  817. "Failed to allocate %d enhanced EQ config texts\n",
  818. pdata->num_enh_eq_cfgs);
  819. return;
  820. }
  821. for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
  822. wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
  823. wm8994->enh_eq_enum.max = pdata->num_enh_eq_cfgs;
  824. wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
  825. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  826. if (ret != 0)
  827. dev_err(wm8994->codec->dev,
  828. "Failed to add enhanced EQ controls: %d\n",
  829. ret);
  830. }
  831. }