edac_mc_sysfs.c 29 KB

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  1. /*
  2. * edac_mc kernel module
  3. * (C) 2005-2007 Linux Networx (http://lnxi.com)
  4. *
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
  9. *
  10. * (c) 2012 - Mauro Carvalho Chehab <mchehab@redhat.com>
  11. * The entire API were re-written, and ported to use struct device
  12. *
  13. */
  14. #include <linux/ctype.h>
  15. #include <linux/slab.h>
  16. #include <linux/edac.h>
  17. #include <linux/bug.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/uaccess.h>
  20. #include "edac_core.h"
  21. #include "edac_module.h"
  22. /* MC EDAC Controls, setable by module parameter, and sysfs */
  23. static int edac_mc_log_ue = 1;
  24. static int edac_mc_log_ce = 1;
  25. static int edac_mc_panic_on_ue;
  26. static int edac_mc_poll_msec = 1000;
  27. /* Getter functions for above */
  28. int edac_mc_get_log_ue(void)
  29. {
  30. return edac_mc_log_ue;
  31. }
  32. int edac_mc_get_log_ce(void)
  33. {
  34. return edac_mc_log_ce;
  35. }
  36. int edac_mc_get_panic_on_ue(void)
  37. {
  38. return edac_mc_panic_on_ue;
  39. }
  40. /* this is temporary */
  41. int edac_mc_get_poll_msec(void)
  42. {
  43. return edac_mc_poll_msec;
  44. }
  45. static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
  46. {
  47. long l;
  48. int ret;
  49. if (!val)
  50. return -EINVAL;
  51. ret = strict_strtol(val, 0, &l);
  52. if (ret == -EINVAL || ((int)l != l))
  53. return -EINVAL;
  54. *((int *)kp->arg) = l;
  55. /* notify edac_mc engine to reset the poll period */
  56. edac_mc_reset_delay_period(l);
  57. return 0;
  58. }
  59. /* Parameter declarations for above */
  60. module_param(edac_mc_panic_on_ue, int, 0644);
  61. MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
  62. module_param(edac_mc_log_ue, int, 0644);
  63. MODULE_PARM_DESC(edac_mc_log_ue,
  64. "Log uncorrectable error to console: 0=off 1=on");
  65. module_param(edac_mc_log_ce, int, 0644);
  66. MODULE_PARM_DESC(edac_mc_log_ce,
  67. "Log correctable error to console: 0=off 1=on");
  68. module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
  69. &edac_mc_poll_msec, 0644);
  70. MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
  71. static struct device *mci_pdev;
  72. /*
  73. * various constants for Memory Controllers
  74. */
  75. static const char *mem_types[] = {
  76. [MEM_EMPTY] = "Empty",
  77. [MEM_RESERVED] = "Reserved",
  78. [MEM_UNKNOWN] = "Unknown",
  79. [MEM_FPM] = "FPM",
  80. [MEM_EDO] = "EDO",
  81. [MEM_BEDO] = "BEDO",
  82. [MEM_SDR] = "Unbuffered-SDR",
  83. [MEM_RDR] = "Registered-SDR",
  84. [MEM_DDR] = "Unbuffered-DDR",
  85. [MEM_RDDR] = "Registered-DDR",
  86. [MEM_RMBS] = "RMBS",
  87. [MEM_DDR2] = "Unbuffered-DDR2",
  88. [MEM_FB_DDR2] = "FullyBuffered-DDR2",
  89. [MEM_RDDR2] = "Registered-DDR2",
  90. [MEM_XDR] = "XDR",
  91. [MEM_DDR3] = "Unbuffered-DDR3",
  92. [MEM_RDDR3] = "Registered-DDR3"
  93. };
  94. static const char *dev_types[] = {
  95. [DEV_UNKNOWN] = "Unknown",
  96. [DEV_X1] = "x1",
  97. [DEV_X2] = "x2",
  98. [DEV_X4] = "x4",
  99. [DEV_X8] = "x8",
  100. [DEV_X16] = "x16",
  101. [DEV_X32] = "x32",
  102. [DEV_X64] = "x64"
  103. };
  104. static const char *edac_caps[] = {
  105. [EDAC_UNKNOWN] = "Unknown",
  106. [EDAC_NONE] = "None",
  107. [EDAC_RESERVED] = "Reserved",
  108. [EDAC_PARITY] = "PARITY",
  109. [EDAC_EC] = "EC",
  110. [EDAC_SECDED] = "SECDED",
  111. [EDAC_S2ECD2ED] = "S2ECD2ED",
  112. [EDAC_S4ECD4ED] = "S4ECD4ED",
  113. [EDAC_S8ECD8ED] = "S8ECD8ED",
  114. [EDAC_S16ECD16ED] = "S16ECD16ED"
  115. };
  116. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  117. /*
  118. * EDAC sysfs CSROW data structures and methods
  119. */
  120. #define to_csrow(k) container_of(k, struct csrow_info, dev)
  121. /*
  122. * We need it to avoid namespace conflicts between the legacy API
  123. * and the per-dimm/per-rank one
  124. */
  125. #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
  126. struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
  127. struct dev_ch_attribute {
  128. struct device_attribute attr;
  129. int channel;
  130. };
  131. #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
  132. struct dev_ch_attribute dev_attr_legacy_##_name = \
  133. { __ATTR(_name, _mode, _show, _store), (_var) }
  134. #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
  135. /* Set of more default csrow<id> attribute show/store functions */
  136. static ssize_t csrow_ue_count_show(struct device *dev,
  137. struct device_attribute *mattr, char *data)
  138. {
  139. struct csrow_info *csrow = to_csrow(dev);
  140. return sprintf(data, "%u\n", csrow->ue_count);
  141. }
  142. static ssize_t csrow_ce_count_show(struct device *dev,
  143. struct device_attribute *mattr, char *data)
  144. {
  145. struct csrow_info *csrow = to_csrow(dev);
  146. return sprintf(data, "%u\n", csrow->ce_count);
  147. }
  148. static ssize_t csrow_size_show(struct device *dev,
  149. struct device_attribute *mattr, char *data)
  150. {
  151. struct csrow_info *csrow = to_csrow(dev);
  152. int i;
  153. u32 nr_pages = 0;
  154. if (csrow->mci->csbased)
  155. return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages));
  156. for (i = 0; i < csrow->nr_channels; i++)
  157. nr_pages += csrow->channels[i]->dimm->nr_pages;
  158. return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
  159. }
  160. static ssize_t csrow_mem_type_show(struct device *dev,
  161. struct device_attribute *mattr, char *data)
  162. {
  163. struct csrow_info *csrow = to_csrow(dev);
  164. return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
  165. }
  166. static ssize_t csrow_dev_type_show(struct device *dev,
  167. struct device_attribute *mattr, char *data)
  168. {
  169. struct csrow_info *csrow = to_csrow(dev);
  170. return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
  171. }
  172. static ssize_t csrow_edac_mode_show(struct device *dev,
  173. struct device_attribute *mattr,
  174. char *data)
  175. {
  176. struct csrow_info *csrow = to_csrow(dev);
  177. return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
  178. }
  179. /* show/store functions for DIMM Label attributes */
  180. static ssize_t channel_dimm_label_show(struct device *dev,
  181. struct device_attribute *mattr,
  182. char *data)
  183. {
  184. struct csrow_info *csrow = to_csrow(dev);
  185. unsigned chan = to_channel(mattr);
  186. struct rank_info *rank = csrow->channels[chan];
  187. /* if field has not been initialized, there is nothing to send */
  188. if (!rank->dimm->label[0])
  189. return 0;
  190. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
  191. rank->dimm->label);
  192. }
  193. static ssize_t channel_dimm_label_store(struct device *dev,
  194. struct device_attribute *mattr,
  195. const char *data, size_t count)
  196. {
  197. struct csrow_info *csrow = to_csrow(dev);
  198. unsigned chan = to_channel(mattr);
  199. struct rank_info *rank = csrow->channels[chan];
  200. ssize_t max_size = 0;
  201. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  202. strncpy(rank->dimm->label, data, max_size);
  203. rank->dimm->label[max_size] = '\0';
  204. return max_size;
  205. }
  206. /* show function for dynamic chX_ce_count attribute */
  207. static ssize_t channel_ce_count_show(struct device *dev,
  208. struct device_attribute *mattr, char *data)
  209. {
  210. struct csrow_info *csrow = to_csrow(dev);
  211. unsigned chan = to_channel(mattr);
  212. struct rank_info *rank = csrow->channels[chan];
  213. return sprintf(data, "%u\n", rank->ce_count);
  214. }
  215. /* cwrow<id>/attribute files */
  216. DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
  217. DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
  218. DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
  219. DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
  220. DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
  221. DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
  222. /* default attributes of the CSROW<id> object */
  223. static struct attribute *csrow_attrs[] = {
  224. &dev_attr_legacy_dev_type.attr,
  225. &dev_attr_legacy_mem_type.attr,
  226. &dev_attr_legacy_edac_mode.attr,
  227. &dev_attr_legacy_size_mb.attr,
  228. &dev_attr_legacy_ue_count.attr,
  229. &dev_attr_legacy_ce_count.attr,
  230. NULL,
  231. };
  232. static struct attribute_group csrow_attr_grp = {
  233. .attrs = csrow_attrs,
  234. };
  235. static const struct attribute_group *csrow_attr_groups[] = {
  236. &csrow_attr_grp,
  237. NULL
  238. };
  239. static void csrow_attr_release(struct device *dev)
  240. {
  241. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  242. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  243. kfree(csrow);
  244. }
  245. static struct device_type csrow_attr_type = {
  246. .groups = csrow_attr_groups,
  247. .release = csrow_attr_release,
  248. };
  249. /*
  250. * possible dynamic channel DIMM Label attribute files
  251. *
  252. */
  253. #define EDAC_NR_CHANNELS 6
  254. DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
  255. channel_dimm_label_show, channel_dimm_label_store, 0);
  256. DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
  257. channel_dimm_label_show, channel_dimm_label_store, 1);
  258. DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
  259. channel_dimm_label_show, channel_dimm_label_store, 2);
  260. DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
  261. channel_dimm_label_show, channel_dimm_label_store, 3);
  262. DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
  263. channel_dimm_label_show, channel_dimm_label_store, 4);
  264. DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
  265. channel_dimm_label_show, channel_dimm_label_store, 5);
  266. /* Total possible dynamic DIMM Label attribute file table */
  267. static struct device_attribute *dynamic_csrow_dimm_attr[] = {
  268. &dev_attr_legacy_ch0_dimm_label.attr,
  269. &dev_attr_legacy_ch1_dimm_label.attr,
  270. &dev_attr_legacy_ch2_dimm_label.attr,
  271. &dev_attr_legacy_ch3_dimm_label.attr,
  272. &dev_attr_legacy_ch4_dimm_label.attr,
  273. &dev_attr_legacy_ch5_dimm_label.attr
  274. };
  275. /* possible dynamic channel ce_count attribute files */
  276. DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
  277. channel_ce_count_show, NULL, 0);
  278. DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
  279. channel_ce_count_show, NULL, 1);
  280. DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
  281. channel_ce_count_show, NULL, 2);
  282. DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
  283. channel_ce_count_show, NULL, 3);
  284. DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
  285. channel_ce_count_show, NULL, 4);
  286. DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
  287. channel_ce_count_show, NULL, 5);
  288. /* Total possible dynamic ce_count attribute file table */
  289. static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
  290. &dev_attr_legacy_ch0_ce_count.attr,
  291. &dev_attr_legacy_ch1_ce_count.attr,
  292. &dev_attr_legacy_ch2_ce_count.attr,
  293. &dev_attr_legacy_ch3_ce_count.attr,
  294. &dev_attr_legacy_ch4_ce_count.attr,
  295. &dev_attr_legacy_ch5_ce_count.attr
  296. };
  297. static inline int nr_pages_per_csrow(struct csrow_info *csrow)
  298. {
  299. int chan, nr_pages = 0;
  300. for (chan = 0; chan < csrow->nr_channels; chan++)
  301. nr_pages += csrow->channels[chan]->dimm->nr_pages;
  302. return nr_pages;
  303. }
  304. /* Create a CSROW object under specifed edac_mc_device */
  305. static int edac_create_csrow_object(struct mem_ctl_info *mci,
  306. struct csrow_info *csrow, int index)
  307. {
  308. int err, chan;
  309. if (csrow->nr_channels >= EDAC_NR_CHANNELS)
  310. return -ENODEV;
  311. csrow->dev.type = &csrow_attr_type;
  312. csrow->dev.bus = &mci->bus;
  313. device_initialize(&csrow->dev);
  314. csrow->dev.parent = &mci->dev;
  315. csrow->mci = mci;
  316. dev_set_name(&csrow->dev, "csrow%d", index);
  317. dev_set_drvdata(&csrow->dev, csrow);
  318. edac_dbg(0, "creating (virtual) csrow node %s\n",
  319. dev_name(&csrow->dev));
  320. err = device_add(&csrow->dev);
  321. if (err < 0)
  322. return err;
  323. for (chan = 0; chan < csrow->nr_channels; chan++) {
  324. /* Only expose populated DIMMs */
  325. if (!csrow->channels[chan]->dimm->nr_pages)
  326. continue;
  327. err = device_create_file(&csrow->dev,
  328. dynamic_csrow_dimm_attr[chan]);
  329. if (err < 0)
  330. goto error;
  331. err = device_create_file(&csrow->dev,
  332. dynamic_csrow_ce_count_attr[chan]);
  333. if (err < 0) {
  334. device_remove_file(&csrow->dev,
  335. dynamic_csrow_dimm_attr[chan]);
  336. goto error;
  337. }
  338. }
  339. return 0;
  340. error:
  341. for (--chan; chan >= 0; chan--) {
  342. device_remove_file(&csrow->dev,
  343. dynamic_csrow_dimm_attr[chan]);
  344. device_remove_file(&csrow->dev,
  345. dynamic_csrow_ce_count_attr[chan]);
  346. }
  347. put_device(&csrow->dev);
  348. return err;
  349. }
  350. /* Create a CSROW object under specifed edac_mc_device */
  351. static int edac_create_csrow_objects(struct mem_ctl_info *mci)
  352. {
  353. int err, i, chan;
  354. struct csrow_info *csrow;
  355. for (i = 0; i < mci->nr_csrows; i++) {
  356. csrow = mci->csrows[i];
  357. if (!nr_pages_per_csrow(csrow))
  358. continue;
  359. err = edac_create_csrow_object(mci, mci->csrows[i], i);
  360. if (err < 0)
  361. goto error;
  362. }
  363. return 0;
  364. error:
  365. for (--i; i >= 0; i--) {
  366. csrow = mci->csrows[i];
  367. if (!nr_pages_per_csrow(csrow))
  368. continue;
  369. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  370. if (!csrow->channels[chan]->dimm->nr_pages)
  371. continue;
  372. device_remove_file(&csrow->dev,
  373. dynamic_csrow_dimm_attr[chan]);
  374. device_remove_file(&csrow->dev,
  375. dynamic_csrow_ce_count_attr[chan]);
  376. }
  377. put_device(&mci->csrows[i]->dev);
  378. }
  379. return err;
  380. }
  381. static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
  382. {
  383. int i, chan;
  384. struct csrow_info *csrow;
  385. for (i = mci->nr_csrows - 1; i >= 0; i--) {
  386. csrow = mci->csrows[i];
  387. if (!nr_pages_per_csrow(csrow))
  388. continue;
  389. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  390. if (!csrow->channels[chan]->dimm->nr_pages)
  391. continue;
  392. edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
  393. i, chan);
  394. device_remove_file(&csrow->dev,
  395. dynamic_csrow_dimm_attr[chan]);
  396. device_remove_file(&csrow->dev,
  397. dynamic_csrow_ce_count_attr[chan]);
  398. }
  399. put_device(&mci->csrows[i]->dev);
  400. device_del(&mci->csrows[i]->dev);
  401. }
  402. }
  403. #endif
  404. /*
  405. * Per-dimm (or per-rank) devices
  406. */
  407. #define to_dimm(k) container_of(k, struct dimm_info, dev)
  408. /* show/store functions for DIMM Label attributes */
  409. static ssize_t dimmdev_location_show(struct device *dev,
  410. struct device_attribute *mattr, char *data)
  411. {
  412. struct dimm_info *dimm = to_dimm(dev);
  413. return edac_dimm_info_location(dimm, data, PAGE_SIZE);
  414. }
  415. static ssize_t dimmdev_label_show(struct device *dev,
  416. struct device_attribute *mattr, char *data)
  417. {
  418. struct dimm_info *dimm = to_dimm(dev);
  419. /* if field has not been initialized, there is nothing to send */
  420. if (!dimm->label[0])
  421. return 0;
  422. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
  423. }
  424. static ssize_t dimmdev_label_store(struct device *dev,
  425. struct device_attribute *mattr,
  426. const char *data,
  427. size_t count)
  428. {
  429. struct dimm_info *dimm = to_dimm(dev);
  430. ssize_t max_size = 0;
  431. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  432. strncpy(dimm->label, data, max_size);
  433. dimm->label[max_size] = '\0';
  434. return max_size;
  435. }
  436. static ssize_t dimmdev_size_show(struct device *dev,
  437. struct device_attribute *mattr, char *data)
  438. {
  439. struct dimm_info *dimm = to_dimm(dev);
  440. return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
  441. }
  442. static ssize_t dimmdev_mem_type_show(struct device *dev,
  443. struct device_attribute *mattr, char *data)
  444. {
  445. struct dimm_info *dimm = to_dimm(dev);
  446. return sprintf(data, "%s\n", mem_types[dimm->mtype]);
  447. }
  448. static ssize_t dimmdev_dev_type_show(struct device *dev,
  449. struct device_attribute *mattr, char *data)
  450. {
  451. struct dimm_info *dimm = to_dimm(dev);
  452. return sprintf(data, "%s\n", dev_types[dimm->dtype]);
  453. }
  454. static ssize_t dimmdev_edac_mode_show(struct device *dev,
  455. struct device_attribute *mattr,
  456. char *data)
  457. {
  458. struct dimm_info *dimm = to_dimm(dev);
  459. return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
  460. }
  461. /* dimm/rank attribute files */
  462. static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
  463. dimmdev_label_show, dimmdev_label_store);
  464. static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
  465. static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
  466. static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
  467. static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
  468. static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
  469. /* attributes of the dimm<id>/rank<id> object */
  470. static struct attribute *dimm_attrs[] = {
  471. &dev_attr_dimm_label.attr,
  472. &dev_attr_dimm_location.attr,
  473. &dev_attr_size.attr,
  474. &dev_attr_dimm_mem_type.attr,
  475. &dev_attr_dimm_dev_type.attr,
  476. &dev_attr_dimm_edac_mode.attr,
  477. NULL,
  478. };
  479. static struct attribute_group dimm_attr_grp = {
  480. .attrs = dimm_attrs,
  481. };
  482. static const struct attribute_group *dimm_attr_groups[] = {
  483. &dimm_attr_grp,
  484. NULL
  485. };
  486. static void dimm_attr_release(struct device *dev)
  487. {
  488. struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
  489. edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
  490. kfree(dimm);
  491. }
  492. static struct device_type dimm_attr_type = {
  493. .groups = dimm_attr_groups,
  494. .release = dimm_attr_release,
  495. };
  496. /* Create a DIMM object under specifed memory controller device */
  497. static int edac_create_dimm_object(struct mem_ctl_info *mci,
  498. struct dimm_info *dimm,
  499. int index)
  500. {
  501. int err;
  502. dimm->mci = mci;
  503. dimm->dev.type = &dimm_attr_type;
  504. dimm->dev.bus = &mci->bus;
  505. device_initialize(&dimm->dev);
  506. dimm->dev.parent = &mci->dev;
  507. if (mci->mem_is_per_rank)
  508. dev_set_name(&dimm->dev, "rank%d", index);
  509. else
  510. dev_set_name(&dimm->dev, "dimm%d", index);
  511. dev_set_drvdata(&dimm->dev, dimm);
  512. pm_runtime_forbid(&mci->dev);
  513. err = device_add(&dimm->dev);
  514. edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
  515. return err;
  516. }
  517. /*
  518. * Memory controller device
  519. */
  520. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  521. static ssize_t mci_reset_counters_store(struct device *dev,
  522. struct device_attribute *mattr,
  523. const char *data, size_t count)
  524. {
  525. struct mem_ctl_info *mci = to_mci(dev);
  526. int cnt, row, chan, i;
  527. mci->ue_mc = 0;
  528. mci->ce_mc = 0;
  529. mci->ue_noinfo_count = 0;
  530. mci->ce_noinfo_count = 0;
  531. for (row = 0; row < mci->nr_csrows; row++) {
  532. struct csrow_info *ri = mci->csrows[row];
  533. ri->ue_count = 0;
  534. ri->ce_count = 0;
  535. for (chan = 0; chan < ri->nr_channels; chan++)
  536. ri->channels[chan]->ce_count = 0;
  537. }
  538. cnt = 1;
  539. for (i = 0; i < mci->n_layers; i++) {
  540. cnt *= mci->layers[i].size;
  541. memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
  542. memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
  543. }
  544. mci->start_time = jiffies;
  545. return count;
  546. }
  547. /* Memory scrubbing interface:
  548. *
  549. * A MC driver can limit the scrubbing bandwidth based on the CPU type.
  550. * Therefore, ->set_sdram_scrub_rate should be made to return the actual
  551. * bandwidth that is accepted or 0 when scrubbing is to be disabled.
  552. *
  553. * Negative value still means that an error has occurred while setting
  554. * the scrub rate.
  555. */
  556. static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
  557. struct device_attribute *mattr,
  558. const char *data, size_t count)
  559. {
  560. struct mem_ctl_info *mci = to_mci(dev);
  561. unsigned long bandwidth = 0;
  562. int new_bw = 0;
  563. if (!mci->set_sdram_scrub_rate)
  564. return -ENODEV;
  565. if (strict_strtoul(data, 10, &bandwidth) < 0)
  566. return -EINVAL;
  567. new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
  568. if (new_bw < 0) {
  569. edac_printk(KERN_WARNING, EDAC_MC,
  570. "Error setting scrub rate to: %lu\n", bandwidth);
  571. return -EINVAL;
  572. }
  573. return count;
  574. }
  575. /*
  576. * ->get_sdram_scrub_rate() return value semantics same as above.
  577. */
  578. static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
  579. struct device_attribute *mattr,
  580. char *data)
  581. {
  582. struct mem_ctl_info *mci = to_mci(dev);
  583. int bandwidth = 0;
  584. if (!mci->get_sdram_scrub_rate)
  585. return -ENODEV;
  586. bandwidth = mci->get_sdram_scrub_rate(mci);
  587. if (bandwidth < 0) {
  588. edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
  589. return bandwidth;
  590. }
  591. return sprintf(data, "%d\n", bandwidth);
  592. }
  593. /* default attribute files for the MCI object */
  594. static ssize_t mci_ue_count_show(struct device *dev,
  595. struct device_attribute *mattr,
  596. char *data)
  597. {
  598. struct mem_ctl_info *mci = to_mci(dev);
  599. return sprintf(data, "%d\n", mci->ue_mc);
  600. }
  601. static ssize_t mci_ce_count_show(struct device *dev,
  602. struct device_attribute *mattr,
  603. char *data)
  604. {
  605. struct mem_ctl_info *mci = to_mci(dev);
  606. return sprintf(data, "%d\n", mci->ce_mc);
  607. }
  608. static ssize_t mci_ce_noinfo_show(struct device *dev,
  609. struct device_attribute *mattr,
  610. char *data)
  611. {
  612. struct mem_ctl_info *mci = to_mci(dev);
  613. return sprintf(data, "%d\n", mci->ce_noinfo_count);
  614. }
  615. static ssize_t mci_ue_noinfo_show(struct device *dev,
  616. struct device_attribute *mattr,
  617. char *data)
  618. {
  619. struct mem_ctl_info *mci = to_mci(dev);
  620. return sprintf(data, "%d\n", mci->ue_noinfo_count);
  621. }
  622. static ssize_t mci_seconds_show(struct device *dev,
  623. struct device_attribute *mattr,
  624. char *data)
  625. {
  626. struct mem_ctl_info *mci = to_mci(dev);
  627. return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
  628. }
  629. static ssize_t mci_ctl_name_show(struct device *dev,
  630. struct device_attribute *mattr,
  631. char *data)
  632. {
  633. struct mem_ctl_info *mci = to_mci(dev);
  634. return sprintf(data, "%s\n", mci->ctl_name);
  635. }
  636. static ssize_t mci_size_mb_show(struct device *dev,
  637. struct device_attribute *mattr,
  638. char *data)
  639. {
  640. struct mem_ctl_info *mci = to_mci(dev);
  641. int total_pages = 0, csrow_idx, j;
  642. for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
  643. struct csrow_info *csrow = mci->csrows[csrow_idx];
  644. if (csrow->mci->csbased) {
  645. total_pages += csrow->nr_pages;
  646. } else {
  647. for (j = 0; j < csrow->nr_channels; j++) {
  648. struct dimm_info *dimm = csrow->channels[j]->dimm;
  649. total_pages += dimm->nr_pages;
  650. }
  651. }
  652. }
  653. return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
  654. }
  655. static ssize_t mci_max_location_show(struct device *dev,
  656. struct device_attribute *mattr,
  657. char *data)
  658. {
  659. struct mem_ctl_info *mci = to_mci(dev);
  660. int i;
  661. char *p = data;
  662. for (i = 0; i < mci->n_layers; i++) {
  663. p += sprintf(p, "%s %d ",
  664. edac_layer_name[mci->layers[i].type],
  665. mci->layers[i].size - 1);
  666. }
  667. return p - data;
  668. }
  669. #ifdef CONFIG_EDAC_DEBUG
  670. static ssize_t edac_fake_inject_write(struct file *file,
  671. const char __user *data,
  672. size_t count, loff_t *ppos)
  673. {
  674. struct device *dev = file->private_data;
  675. struct mem_ctl_info *mci = to_mci(dev);
  676. static enum hw_event_mc_err_type type;
  677. u16 errcount = mci->fake_inject_count;
  678. if (!errcount)
  679. errcount = 1;
  680. type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
  681. : HW_EVENT_ERR_CORRECTED;
  682. printk(KERN_DEBUG
  683. "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
  684. errcount,
  685. (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
  686. errcount > 1 ? "s" : "",
  687. mci->fake_inject_layer[0],
  688. mci->fake_inject_layer[1],
  689. mci->fake_inject_layer[2]
  690. );
  691. edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
  692. mci->fake_inject_layer[0],
  693. mci->fake_inject_layer[1],
  694. mci->fake_inject_layer[2],
  695. "FAKE ERROR", "for EDAC testing only");
  696. return count;
  697. }
  698. static const struct file_operations debug_fake_inject_fops = {
  699. .open = simple_open,
  700. .write = edac_fake_inject_write,
  701. .llseek = generic_file_llseek,
  702. };
  703. #endif
  704. /* default Control file */
  705. DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
  706. /* default Attribute files */
  707. DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
  708. DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
  709. DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
  710. DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
  711. DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
  712. DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
  713. DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
  714. DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
  715. /* memory scrubber attribute file */
  716. DEVICE_ATTR(sdram_scrub_rate, S_IRUGO | S_IWUSR, mci_sdram_scrub_rate_show,
  717. mci_sdram_scrub_rate_store);
  718. static struct attribute *mci_attrs[] = {
  719. &dev_attr_reset_counters.attr,
  720. &dev_attr_mc_name.attr,
  721. &dev_attr_size_mb.attr,
  722. &dev_attr_seconds_since_reset.attr,
  723. &dev_attr_ue_noinfo_count.attr,
  724. &dev_attr_ce_noinfo_count.attr,
  725. &dev_attr_ue_count.attr,
  726. &dev_attr_ce_count.attr,
  727. &dev_attr_sdram_scrub_rate.attr,
  728. &dev_attr_max_location.attr,
  729. NULL
  730. };
  731. static struct attribute_group mci_attr_grp = {
  732. .attrs = mci_attrs,
  733. };
  734. static const struct attribute_group *mci_attr_groups[] = {
  735. &mci_attr_grp,
  736. NULL
  737. };
  738. static void mci_attr_release(struct device *dev)
  739. {
  740. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  741. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  742. kfree(mci);
  743. }
  744. static struct device_type mci_attr_type = {
  745. .groups = mci_attr_groups,
  746. .release = mci_attr_release,
  747. };
  748. #ifdef CONFIG_EDAC_DEBUG
  749. static struct dentry *edac_debugfs;
  750. int __init edac_debugfs_init(void)
  751. {
  752. edac_debugfs = debugfs_create_dir("edac", NULL);
  753. if (IS_ERR(edac_debugfs)) {
  754. edac_debugfs = NULL;
  755. return -ENOMEM;
  756. }
  757. return 0;
  758. }
  759. void __exit edac_debugfs_exit(void)
  760. {
  761. debugfs_remove(edac_debugfs);
  762. }
  763. int edac_create_debug_nodes(struct mem_ctl_info *mci)
  764. {
  765. struct dentry *d, *parent;
  766. char name[80];
  767. int i;
  768. if (!edac_debugfs)
  769. return -ENODEV;
  770. d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
  771. if (!d)
  772. return -ENOMEM;
  773. parent = d;
  774. for (i = 0; i < mci->n_layers; i++) {
  775. sprintf(name, "fake_inject_%s",
  776. edac_layer_name[mci->layers[i].type]);
  777. d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
  778. &mci->fake_inject_layer[i]);
  779. if (!d)
  780. goto nomem;
  781. }
  782. d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
  783. &mci->fake_inject_ue);
  784. if (!d)
  785. goto nomem;
  786. d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
  787. &mci->fake_inject_count);
  788. if (!d)
  789. goto nomem;
  790. d = debugfs_create_file("fake_inject", S_IWUSR, parent,
  791. &mci->dev,
  792. &debug_fake_inject_fops);
  793. if (!d)
  794. goto nomem;
  795. mci->debugfs = parent;
  796. return 0;
  797. nomem:
  798. debugfs_remove(mci->debugfs);
  799. return -ENOMEM;
  800. }
  801. #endif
  802. /*
  803. * Create a new Memory Controller kobject instance,
  804. * mc<id> under the 'mc' directory
  805. *
  806. * Return:
  807. * 0 Success
  808. * !0 Failure
  809. */
  810. int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
  811. {
  812. int i, err;
  813. /*
  814. * The memory controller needs its own bus, in order to avoid
  815. * namespace conflicts at /sys/bus/edac.
  816. */
  817. mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
  818. if (!mci->bus.name)
  819. return -ENOMEM;
  820. edac_dbg(0, "creating bus %s\n", mci->bus.name);
  821. err = bus_register(&mci->bus);
  822. if (err < 0)
  823. return err;
  824. /* get the /sys/devices/system/edac subsys reference */
  825. mci->dev.type = &mci_attr_type;
  826. device_initialize(&mci->dev);
  827. mci->dev.parent = mci_pdev;
  828. mci->dev.bus = &mci->bus;
  829. dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
  830. dev_set_drvdata(&mci->dev, mci);
  831. pm_runtime_forbid(&mci->dev);
  832. edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
  833. err = device_add(&mci->dev);
  834. if (err < 0) {
  835. bus_unregister(&mci->bus);
  836. kfree(mci->bus.name);
  837. return err;
  838. }
  839. /*
  840. * Create the dimm/rank devices
  841. */
  842. for (i = 0; i < mci->tot_dimms; i++) {
  843. struct dimm_info *dimm = mci->dimms[i];
  844. /* Only expose populated DIMMs */
  845. if (dimm->nr_pages == 0)
  846. continue;
  847. #ifdef CONFIG_EDAC_DEBUG
  848. edac_dbg(1, "creating dimm%d, located at ", i);
  849. if (edac_debug_level >= 1) {
  850. int lay;
  851. for (lay = 0; lay < mci->n_layers; lay++)
  852. printk(KERN_CONT "%s %d ",
  853. edac_layer_name[mci->layers[lay].type],
  854. dimm->location[lay]);
  855. printk(KERN_CONT "\n");
  856. }
  857. #endif
  858. err = edac_create_dimm_object(mci, dimm, i);
  859. if (err) {
  860. edac_dbg(1, "failure: create dimm %d obj\n", i);
  861. goto fail;
  862. }
  863. }
  864. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  865. err = edac_create_csrow_objects(mci);
  866. if (err < 0)
  867. goto fail;
  868. #endif
  869. #ifdef CONFIG_EDAC_DEBUG
  870. edac_create_debug_nodes(mci);
  871. #endif
  872. return 0;
  873. fail:
  874. for (i--; i >= 0; i--) {
  875. struct dimm_info *dimm = mci->dimms[i];
  876. if (dimm->nr_pages == 0)
  877. continue;
  878. put_device(&dimm->dev);
  879. device_del(&dimm->dev);
  880. }
  881. put_device(&mci->dev);
  882. device_del(&mci->dev);
  883. bus_unregister(&mci->bus);
  884. kfree(mci->bus.name);
  885. return err;
  886. }
  887. /*
  888. * remove a Memory Controller instance
  889. */
  890. void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  891. {
  892. int i;
  893. edac_dbg(0, "\n");
  894. #ifdef CONFIG_EDAC_DEBUG
  895. debugfs_remove(mci->debugfs);
  896. #endif
  897. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  898. edac_delete_csrow_objects(mci);
  899. #endif
  900. for (i = 0; i < mci->tot_dimms; i++) {
  901. struct dimm_info *dimm = mci->dimms[i];
  902. if (dimm->nr_pages == 0)
  903. continue;
  904. edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
  905. put_device(&dimm->dev);
  906. device_del(&dimm->dev);
  907. }
  908. }
  909. void edac_unregister_sysfs(struct mem_ctl_info *mci)
  910. {
  911. edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
  912. put_device(&mci->dev);
  913. device_del(&mci->dev);
  914. bus_unregister(&mci->bus);
  915. kfree(mci->bus.name);
  916. }
  917. static void mc_attr_release(struct device *dev)
  918. {
  919. /*
  920. * There's no container structure here, as this is just the mci
  921. * parent device, used to create the /sys/devices/mc sysfs node.
  922. * So, there are no attributes on it.
  923. */
  924. edac_dbg(1, "Releasing device %s\n", dev_name(dev));
  925. kfree(dev);
  926. }
  927. static struct device_type mc_attr_type = {
  928. .release = mc_attr_release,
  929. };
  930. /*
  931. * Init/exit code for the module. Basically, creates/removes /sys/class/rc
  932. */
  933. int __init edac_mc_sysfs_init(void)
  934. {
  935. struct bus_type *edac_subsys;
  936. int err;
  937. /* get the /sys/devices/system/edac subsys reference */
  938. edac_subsys = edac_get_sysfs_subsys();
  939. if (edac_subsys == NULL) {
  940. edac_dbg(1, "no edac_subsys\n");
  941. err = -EINVAL;
  942. goto out;
  943. }
  944. mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
  945. if (!mci_pdev) {
  946. err = -ENOMEM;
  947. goto out_put_sysfs;
  948. }
  949. mci_pdev->bus = edac_subsys;
  950. mci_pdev->type = &mc_attr_type;
  951. device_initialize(mci_pdev);
  952. dev_set_name(mci_pdev, "mc");
  953. err = device_add(mci_pdev);
  954. if (err < 0)
  955. goto out_dev_free;
  956. edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
  957. return 0;
  958. out_dev_free:
  959. kfree(mci_pdev);
  960. out_put_sysfs:
  961. edac_put_sysfs_subsys();
  962. out:
  963. return err;
  964. }
  965. void __exit edac_mc_sysfs_exit(void)
  966. {
  967. device_del(mci_pdev);
  968. put_device(mci_pdev);
  969. edac_put_sysfs_subsys();
  970. }