rt2x00pci.c 11 KB

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  1. /*
  2. Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00pci
  19. Abstract: rt2x00 generic pci device routines.
  20. */
  21. #include <linux/dma-mapping.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/pci.h>
  25. #include "rt2x00.h"
  26. #include "rt2x00pci.h"
  27. /*
  28. * TX data handlers.
  29. */
  30. int rt2x00pci_write_tx_data(struct queue_entry *entry)
  31. {
  32. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  33. struct skb_frame_desc *skbdesc;
  34. u32 word;
  35. rt2x00_desc_read(entry_priv->desc, 0, &word);
  36. /*
  37. * This should not happen, we already checked the entry
  38. * was ours. When the hardware disagrees there has been
  39. * a queue corruption!
  40. */
  41. if (unlikely(rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
  42. rt2x00_get_field32(word, TXD_ENTRY_VALID))) {
  43. ERROR(entry->queue->rt2x00dev,
  44. "Corrupt queue %d, accessing entry which is not ours.\n"
  45. "Please file bug report to %s.\n",
  46. entry->queue->qid, DRV_PROJECT);
  47. return -EINVAL;
  48. }
  49. /*
  50. * Fill in skb descriptor
  51. */
  52. skbdesc = get_skb_frame_desc(entry->skb);
  53. memset(skbdesc, 0, sizeof(*skbdesc));
  54. skbdesc->desc = entry_priv->desc;
  55. skbdesc->desc_len = entry->queue->desc_size;
  56. skbdesc->entry = entry;
  57. memcpy(entry_priv->data, entry->skb->data, entry->skb->len);
  58. return 0;
  59. }
  60. EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
  61. /*
  62. * TX/RX data handlers.
  63. */
  64. static void rt2x00pci_rxdone_entry(struct rt2x00_dev *rt2x00dev,
  65. struct queue_entry *entry)
  66. {
  67. struct sk_buff *skb;
  68. struct skb_frame_desc *skbdesc;
  69. struct rxdone_entry_desc rxdesc;
  70. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  71. /*
  72. * Allocate a new sk_buffer. If no new buffer available, drop the
  73. * received frame and reuse the existing buffer.
  74. */
  75. skb = rt2x00queue_alloc_skb(entry->queue);
  76. if (!skb)
  77. return;
  78. /*
  79. * Extract the RXD details.
  80. */
  81. memset(&rxdesc, 0, sizeof(rxdesc));
  82. rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
  83. /*
  84. * Copy the received data to the entries' skb.
  85. */
  86. memcpy(entry->skb->data, entry_priv->data, rxdesc.size);
  87. skb_trim(entry->skb, rxdesc.size);
  88. /*
  89. * Fill in skb descriptor
  90. */
  91. skbdesc = get_skb_frame_desc(entry->skb);
  92. memset(skbdesc, 0, sizeof(*skbdesc));
  93. skbdesc->desc = entry_priv->desc;
  94. skbdesc->desc_len = entry->queue->desc_size;
  95. skbdesc->entry = entry;
  96. /*
  97. * Send the frame to rt2x00lib for further processing.
  98. */
  99. rt2x00lib_rxdone(entry, &rxdesc);
  100. /*
  101. * Replace the entries' skb with the newly allocated one.
  102. */
  103. entry->skb = skb;
  104. }
  105. void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
  106. {
  107. struct data_queue *queue = rt2x00dev->rx;
  108. struct queue_entry *entry;
  109. struct queue_entry_priv_pci *entry_priv;
  110. u32 word;
  111. while (1) {
  112. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  113. entry_priv = entry->priv_data;
  114. rt2x00_desc_read(entry_priv->desc, 0, &word);
  115. if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
  116. break;
  117. rt2x00pci_rxdone_entry(rt2x00dev, entry);
  118. if (test_bit(DEVICE_ENABLED_RADIO, &queue->rt2x00dev->flags)) {
  119. rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
  120. rt2x00_desc_write(entry_priv->desc, 0, word);
  121. }
  122. rt2x00queue_index_inc(queue, Q_INDEX);
  123. }
  124. }
  125. EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
  126. void rt2x00pci_txdone(struct rt2x00_dev *rt2x00dev, struct queue_entry *entry,
  127. struct txdone_entry_desc *txdesc)
  128. {
  129. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  130. enum data_queue_qid qid = skb_get_queue_mapping(entry->skb);
  131. u32 word;
  132. rt2x00lib_txdone(entry, txdesc);
  133. /*
  134. * Make this entry available for reuse.
  135. */
  136. entry->flags = 0;
  137. rt2x00_desc_read(entry_priv->desc, 0, &word);
  138. rt2x00_set_field32(&word, TXD_ENTRY_OWNER_NIC, 0);
  139. rt2x00_set_field32(&word, TXD_ENTRY_VALID, 0);
  140. rt2x00_desc_write(entry_priv->desc, 0, word);
  141. __clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
  142. rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
  143. /*
  144. * If the data queue was below the threshold before the txdone
  145. * handler we must make sure the packet queue in the mac80211 stack
  146. * is reenabled when the txdone handler has finished.
  147. */
  148. if (!rt2x00queue_threshold(entry->queue))
  149. ieee80211_wake_queue(rt2x00dev->hw, qid);
  150. }
  151. EXPORT_SYMBOL_GPL(rt2x00pci_txdone);
  152. /*
  153. * Device initialization handlers.
  154. */
  155. #define desc_size(__queue) \
  156. ({ \
  157. ((__queue)->limit * (__queue)->desc_size);\
  158. })
  159. #define data_size(__queue) \
  160. ({ \
  161. ((__queue)->limit * (__queue)->data_size);\
  162. })
  163. #define dma_size(__queue) \
  164. ({ \
  165. data_size(__queue) + desc_size(__queue);\
  166. })
  167. #define desc_offset(__queue, __base, __i) \
  168. ({ \
  169. (__base) + data_size(__queue) + \
  170. ((__i) * (__queue)->desc_size); \
  171. })
  172. #define data_offset(__queue, __base, __i) \
  173. ({ \
  174. (__base) + \
  175. ((__i) * (__queue)->data_size); \
  176. })
  177. static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
  178. struct data_queue *queue)
  179. {
  180. struct queue_entry_priv_pci *entry_priv;
  181. void *addr;
  182. dma_addr_t dma;
  183. unsigned int i;
  184. /*
  185. * Allocate DMA memory for descriptor and buffer.
  186. */
  187. addr = dma_alloc_coherent(rt2x00dev->dev, dma_size(queue), &dma,
  188. GFP_KERNEL | GFP_DMA);
  189. if (!addr)
  190. return -ENOMEM;
  191. memset(addr, 0, dma_size(queue));
  192. /*
  193. * Initialize all queue entries to contain valid addresses.
  194. */
  195. for (i = 0; i < queue->limit; i++) {
  196. entry_priv = queue->entries[i].priv_data;
  197. entry_priv->desc = desc_offset(queue, addr, i);
  198. entry_priv->desc_dma = desc_offset(queue, dma, i);
  199. entry_priv->data = data_offset(queue, addr, i);
  200. entry_priv->data_dma = data_offset(queue, dma, i);
  201. }
  202. return 0;
  203. }
  204. static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
  205. struct data_queue *queue)
  206. {
  207. struct queue_entry_priv_pci *entry_priv =
  208. queue->entries[0].priv_data;
  209. if (entry_priv->data)
  210. dma_free_coherent(rt2x00dev->dev, dma_size(queue),
  211. entry_priv->data, entry_priv->data_dma);
  212. entry_priv->data = NULL;
  213. }
  214. int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
  215. {
  216. struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
  217. struct data_queue *queue;
  218. int status;
  219. /*
  220. * Allocate DMA
  221. */
  222. queue_for_each(rt2x00dev, queue) {
  223. status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
  224. if (status)
  225. goto exit;
  226. }
  227. /*
  228. * Register interrupt handler.
  229. */
  230. status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
  231. IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
  232. if (status) {
  233. ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
  234. pci_dev->irq, status);
  235. goto exit;
  236. }
  237. return 0;
  238. exit:
  239. queue_for_each(rt2x00dev, queue)
  240. rt2x00pci_free_queue_dma(rt2x00dev, queue);
  241. return status;
  242. }
  243. EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
  244. void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
  245. {
  246. struct data_queue *queue;
  247. /*
  248. * Free irq line.
  249. */
  250. free_irq(to_pci_dev(rt2x00dev->dev)->irq, rt2x00dev);
  251. /*
  252. * Free DMA
  253. */
  254. queue_for_each(rt2x00dev, queue)
  255. rt2x00pci_free_queue_dma(rt2x00dev, queue);
  256. }
  257. EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
  258. /*
  259. * PCI driver handlers.
  260. */
  261. static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
  262. {
  263. kfree(rt2x00dev->rf);
  264. rt2x00dev->rf = NULL;
  265. kfree(rt2x00dev->eeprom);
  266. rt2x00dev->eeprom = NULL;
  267. if (rt2x00dev->csr.base) {
  268. iounmap(rt2x00dev->csr.base);
  269. rt2x00dev->csr.base = NULL;
  270. }
  271. }
  272. static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
  273. {
  274. struct pci_dev *pci_dev = to_pci_dev(rt2x00dev->dev);
  275. rt2x00dev->csr.base = ioremap(pci_resource_start(pci_dev, 0),
  276. pci_resource_len(pci_dev, 0));
  277. if (!rt2x00dev->csr.base)
  278. goto exit;
  279. rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
  280. if (!rt2x00dev->eeprom)
  281. goto exit;
  282. rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
  283. if (!rt2x00dev->rf)
  284. goto exit;
  285. return 0;
  286. exit:
  287. ERROR_PROBE("Failed to allocate registers.\n");
  288. rt2x00pci_free_reg(rt2x00dev);
  289. return -ENOMEM;
  290. }
  291. int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  292. {
  293. struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
  294. struct ieee80211_hw *hw;
  295. struct rt2x00_dev *rt2x00dev;
  296. int retval;
  297. retval = pci_request_regions(pci_dev, pci_name(pci_dev));
  298. if (retval) {
  299. ERROR_PROBE("PCI request regions failed.\n");
  300. return retval;
  301. }
  302. retval = pci_enable_device(pci_dev);
  303. if (retval) {
  304. ERROR_PROBE("Enable device failed.\n");
  305. goto exit_release_regions;
  306. }
  307. pci_set_master(pci_dev);
  308. if (pci_set_mwi(pci_dev))
  309. ERROR_PROBE("MWI not available.\n");
  310. if (dma_set_mask(&pci_dev->dev, DMA_32BIT_MASK)) {
  311. ERROR_PROBE("PCI DMA not supported.\n");
  312. retval = -EIO;
  313. goto exit_disable_device;
  314. }
  315. hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
  316. if (!hw) {
  317. ERROR_PROBE("Failed to allocate hardware.\n");
  318. retval = -ENOMEM;
  319. goto exit_disable_device;
  320. }
  321. pci_set_drvdata(pci_dev, hw);
  322. rt2x00dev = hw->priv;
  323. rt2x00dev->dev = &pci_dev->dev;
  324. rt2x00dev->ops = ops;
  325. rt2x00dev->hw = hw;
  326. retval = rt2x00pci_alloc_reg(rt2x00dev);
  327. if (retval)
  328. goto exit_free_device;
  329. retval = rt2x00lib_probe_dev(rt2x00dev);
  330. if (retval)
  331. goto exit_free_reg;
  332. return 0;
  333. exit_free_reg:
  334. rt2x00pci_free_reg(rt2x00dev);
  335. exit_free_device:
  336. ieee80211_free_hw(hw);
  337. exit_disable_device:
  338. if (retval != -EBUSY)
  339. pci_disable_device(pci_dev);
  340. exit_release_regions:
  341. pci_release_regions(pci_dev);
  342. pci_set_drvdata(pci_dev, NULL);
  343. return retval;
  344. }
  345. EXPORT_SYMBOL_GPL(rt2x00pci_probe);
  346. void rt2x00pci_remove(struct pci_dev *pci_dev)
  347. {
  348. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  349. struct rt2x00_dev *rt2x00dev = hw->priv;
  350. /*
  351. * Free all allocated data.
  352. */
  353. rt2x00lib_remove_dev(rt2x00dev);
  354. rt2x00pci_free_reg(rt2x00dev);
  355. ieee80211_free_hw(hw);
  356. /*
  357. * Free the PCI device data.
  358. */
  359. pci_set_drvdata(pci_dev, NULL);
  360. pci_disable_device(pci_dev);
  361. pci_release_regions(pci_dev);
  362. }
  363. EXPORT_SYMBOL_GPL(rt2x00pci_remove);
  364. #ifdef CONFIG_PM
  365. int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
  366. {
  367. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  368. struct rt2x00_dev *rt2x00dev = hw->priv;
  369. int retval;
  370. retval = rt2x00lib_suspend(rt2x00dev, state);
  371. if (retval)
  372. return retval;
  373. rt2x00pci_free_reg(rt2x00dev);
  374. pci_save_state(pci_dev);
  375. pci_disable_device(pci_dev);
  376. return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
  377. }
  378. EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
  379. int rt2x00pci_resume(struct pci_dev *pci_dev)
  380. {
  381. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  382. struct rt2x00_dev *rt2x00dev = hw->priv;
  383. int retval;
  384. if (pci_set_power_state(pci_dev, PCI_D0) ||
  385. pci_enable_device(pci_dev) ||
  386. pci_restore_state(pci_dev)) {
  387. ERROR(rt2x00dev, "Failed to resume device.\n");
  388. return -EIO;
  389. }
  390. retval = rt2x00pci_alloc_reg(rt2x00dev);
  391. if (retval)
  392. return retval;
  393. retval = rt2x00lib_resume(rt2x00dev);
  394. if (retval)
  395. goto exit_free_reg;
  396. return 0;
  397. exit_free_reg:
  398. rt2x00pci_free_reg(rt2x00dev);
  399. return retval;
  400. }
  401. EXPORT_SYMBOL_GPL(rt2x00pci_resume);
  402. #endif /* CONFIG_PM */
  403. /*
  404. * rt2x00pci module information.
  405. */
  406. MODULE_AUTHOR(DRV_PROJECT);
  407. MODULE_VERSION(DRV_VERSION);
  408. MODULE_DESCRIPTION("rt2x00 pci library");
  409. MODULE_LICENSE("GPL");