rt2x00pci.c 12 KB

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  1. /*
  2. Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00pci
  19. Abstract: rt2x00 generic pci device routines.
  20. */
  21. #include <linux/dma-mapping.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/pci.h>
  25. #include "rt2x00.h"
  26. #include "rt2x00pci.h"
  27. /*
  28. * TX data handlers.
  29. */
  30. int rt2x00pci_write_tx_data(struct rt2x00_dev *rt2x00dev,
  31. struct data_queue *queue, struct sk_buff *skb,
  32. struct ieee80211_tx_control *control)
  33. {
  34. struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
  35. struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
  36. struct skb_frame_desc *skbdesc;
  37. u32 word;
  38. if (rt2x00queue_full(queue))
  39. return -EINVAL;
  40. rt2x00_desc_read(priv_tx->desc, 0, &word);
  41. if (rt2x00_get_field32(word, TXD_ENTRY_OWNER_NIC) ||
  42. rt2x00_get_field32(word, TXD_ENTRY_VALID)) {
  43. ERROR(rt2x00dev,
  44. "Arrived at non-free entry in the non-full queue %d.\n"
  45. "Please file bug report to %s.\n",
  46. control->queue, DRV_PROJECT);
  47. return -EINVAL;
  48. }
  49. /*
  50. * Fill in skb descriptor
  51. */
  52. skbdesc = get_skb_frame_desc(skb);
  53. skbdesc->data = skb->data;
  54. skbdesc->data_len = skb->len;
  55. skbdesc->desc = priv_tx->desc;
  56. skbdesc->desc_len = queue->desc_size;
  57. skbdesc->entry = entry;
  58. memcpy(priv_tx->data, skb->data, skb->len);
  59. rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
  60. rt2x00queue_index_inc(queue, Q_INDEX);
  61. return 0;
  62. }
  63. EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
  64. /*
  65. * TX/RX data handlers.
  66. */
  67. void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
  68. {
  69. struct data_queue *queue = rt2x00dev->rx;
  70. struct queue_entry *entry;
  71. struct queue_entry_priv_pci_rx *priv_rx;
  72. struct ieee80211_hdr *hdr;
  73. struct skb_frame_desc *skbdesc;
  74. struct rxdone_entry_desc rxdesc;
  75. int header_size;
  76. int align;
  77. u32 word;
  78. while (1) {
  79. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  80. priv_rx = entry->priv_data;
  81. rt2x00_desc_read(priv_rx->desc, 0, &word);
  82. if (rt2x00_get_field32(word, RXD_ENTRY_OWNER_NIC))
  83. break;
  84. memset(&rxdesc, 0, sizeof(rxdesc));
  85. rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
  86. hdr = (struct ieee80211_hdr *)priv_rx->data;
  87. header_size =
  88. ieee80211_get_hdrlen(le16_to_cpu(hdr->frame_control));
  89. /*
  90. * The data behind the ieee80211 header must be
  91. * aligned on a 4 byte boundary.
  92. */
  93. align = header_size % 4;
  94. /*
  95. * Allocate the sk_buffer, initialize it and copy
  96. * all data into it.
  97. */
  98. entry->skb = dev_alloc_skb(rxdesc.size + align);
  99. if (!entry->skb)
  100. return;
  101. skb_reserve(entry->skb, align);
  102. memcpy(skb_put(entry->skb, rxdesc.size),
  103. priv_rx->data, rxdesc.size);
  104. /*
  105. * Fill in skb descriptor
  106. */
  107. skbdesc = get_skb_frame_desc(entry->skb);
  108. memset(skbdesc, 0, sizeof(*skbdesc));
  109. skbdesc->data = entry->skb->data;
  110. skbdesc->data_len = entry->skb->len;
  111. skbdesc->desc = priv_rx->desc;
  112. skbdesc->desc_len = queue->desc_size;
  113. skbdesc->entry = entry;
  114. /*
  115. * Send the frame to rt2x00lib for further processing.
  116. */
  117. rt2x00lib_rxdone(entry, &rxdesc);
  118. if (test_bit(DEVICE_ENABLED_RADIO, &queue->rt2x00dev->flags)) {
  119. rt2x00_set_field32(&word, RXD_ENTRY_OWNER_NIC, 1);
  120. rt2x00_desc_write(priv_rx->desc, 0, word);
  121. }
  122. rt2x00queue_index_inc(queue, Q_INDEX);
  123. }
  124. }
  125. EXPORT_SYMBOL_GPL(rt2x00pci_rxdone);
  126. void rt2x00pci_txdone(struct rt2x00_dev *rt2x00dev, struct queue_entry *entry,
  127. struct txdone_entry_desc *txdesc)
  128. {
  129. struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
  130. u32 word;
  131. txdesc->control = &priv_tx->control;
  132. rt2x00lib_txdone(entry, txdesc);
  133. /*
  134. * Make this entry available for reuse.
  135. */
  136. entry->flags = 0;
  137. rt2x00_desc_read(priv_tx->desc, 0, &word);
  138. rt2x00_set_field32(&word, TXD_ENTRY_OWNER_NIC, 0);
  139. rt2x00_set_field32(&word, TXD_ENTRY_VALID, 0);
  140. rt2x00_desc_write(priv_tx->desc, 0, word);
  141. rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
  142. /*
  143. * If the data queue was full before the txdone handler
  144. * we must make sure the packet queue in the mac80211 stack
  145. * is reenabled when the txdone handler has finished.
  146. */
  147. if (!rt2x00queue_full(entry->queue))
  148. ieee80211_wake_queue(rt2x00dev->hw, priv_tx->control.queue);
  149. }
  150. EXPORT_SYMBOL_GPL(rt2x00pci_txdone);
  151. /*
  152. * Device initialization handlers.
  153. */
  154. #define desc_size(__queue) \
  155. ({ \
  156. ((__queue)->limit * (__queue)->desc_size);\
  157. })
  158. #define data_size(__queue) \
  159. ({ \
  160. ((__queue)->limit * (__queue)->data_size);\
  161. })
  162. #define dma_size(__queue) \
  163. ({ \
  164. data_size(__queue) + desc_size(__queue);\
  165. })
  166. #define desc_offset(__queue, __base, __i) \
  167. ({ \
  168. (__base) + data_size(__queue) + \
  169. ((__i) * (__queue)->desc_size); \
  170. })
  171. #define data_offset(__queue, __base, __i) \
  172. ({ \
  173. (__base) + \
  174. ((__i) * (__queue)->data_size); \
  175. })
  176. static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
  177. struct data_queue *queue)
  178. {
  179. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  180. struct queue_entry_priv_pci_rx *priv_rx;
  181. struct queue_entry_priv_pci_tx *priv_tx;
  182. void *addr;
  183. dma_addr_t dma;
  184. void *desc_addr;
  185. dma_addr_t desc_dma;
  186. void *data_addr;
  187. dma_addr_t data_dma;
  188. unsigned int i;
  189. /*
  190. * Allocate DMA memory for descriptor and buffer.
  191. */
  192. addr = pci_alloc_consistent(pci_dev, dma_size(queue), &dma);
  193. if (!addr)
  194. return -ENOMEM;
  195. memset(addr, 0, dma_size(queue));
  196. /*
  197. * Initialize all queue entries to contain valid addresses.
  198. */
  199. for (i = 0; i < queue->limit; i++) {
  200. desc_addr = desc_offset(queue, addr, i);
  201. desc_dma = desc_offset(queue, dma, i);
  202. data_addr = data_offset(queue, addr, i);
  203. data_dma = data_offset(queue, dma, i);
  204. if (queue->qid == QID_RX) {
  205. priv_rx = queue->entries[i].priv_data;
  206. priv_rx->desc = desc_addr;
  207. priv_rx->desc_dma = desc_dma;
  208. priv_rx->data = data_addr;
  209. priv_rx->data_dma = data_dma;
  210. } else {
  211. priv_tx = queue->entries[i].priv_data;
  212. priv_tx->desc = desc_addr;
  213. priv_tx->desc_dma = desc_dma;
  214. priv_tx->data = data_addr;
  215. priv_tx->data_dma = data_dma;
  216. }
  217. }
  218. return 0;
  219. }
  220. static void rt2x00pci_free_queue_dma(struct rt2x00_dev *rt2x00dev,
  221. struct data_queue *queue)
  222. {
  223. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  224. struct queue_entry_priv_pci_rx *priv_rx;
  225. struct queue_entry_priv_pci_tx *priv_tx;
  226. void *data_addr;
  227. dma_addr_t data_dma;
  228. if (queue->qid == QID_RX) {
  229. priv_rx = queue->entries[0].priv_data;
  230. data_addr = priv_rx->data;
  231. data_dma = priv_rx->data_dma;
  232. priv_rx->data = NULL;
  233. } else {
  234. priv_tx = queue->entries[0].priv_data;
  235. data_addr = priv_tx->data;
  236. data_dma = priv_tx->data_dma;
  237. priv_tx->data = NULL;
  238. }
  239. if (data_addr)
  240. pci_free_consistent(pci_dev, dma_size(queue),
  241. data_addr, data_dma);
  242. }
  243. int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
  244. {
  245. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  246. struct data_queue *queue;
  247. int status;
  248. /*
  249. * Allocate DMA
  250. */
  251. queue_for_each(rt2x00dev, queue) {
  252. status = rt2x00pci_alloc_queue_dma(rt2x00dev, queue);
  253. if (status)
  254. goto exit;
  255. }
  256. /*
  257. * Register interrupt handler.
  258. */
  259. status = request_irq(pci_dev->irq, rt2x00dev->ops->lib->irq_handler,
  260. IRQF_SHARED, pci_name(pci_dev), rt2x00dev);
  261. if (status) {
  262. ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
  263. pci_dev->irq, status);
  264. return status;
  265. }
  266. return 0;
  267. exit:
  268. rt2x00pci_uninitialize(rt2x00dev);
  269. return status;
  270. }
  271. EXPORT_SYMBOL_GPL(rt2x00pci_initialize);
  272. void rt2x00pci_uninitialize(struct rt2x00_dev *rt2x00dev)
  273. {
  274. struct data_queue *queue;
  275. /*
  276. * Free irq line.
  277. */
  278. free_irq(rt2x00dev_pci(rt2x00dev)->irq, rt2x00dev);
  279. /*
  280. * Free DMA
  281. */
  282. queue_for_each(rt2x00dev, queue)
  283. rt2x00pci_free_queue_dma(rt2x00dev, queue);
  284. }
  285. EXPORT_SYMBOL_GPL(rt2x00pci_uninitialize);
  286. /*
  287. * PCI driver handlers.
  288. */
  289. static void rt2x00pci_free_reg(struct rt2x00_dev *rt2x00dev)
  290. {
  291. kfree(rt2x00dev->rf);
  292. rt2x00dev->rf = NULL;
  293. kfree(rt2x00dev->eeprom);
  294. rt2x00dev->eeprom = NULL;
  295. if (rt2x00dev->csr.base) {
  296. iounmap(rt2x00dev->csr.base);
  297. rt2x00dev->csr.base = NULL;
  298. }
  299. }
  300. static int rt2x00pci_alloc_reg(struct rt2x00_dev *rt2x00dev)
  301. {
  302. struct pci_dev *pci_dev = rt2x00dev_pci(rt2x00dev);
  303. rt2x00dev->csr.base = ioremap(pci_resource_start(pci_dev, 0),
  304. pci_resource_len(pci_dev, 0));
  305. if (!rt2x00dev->csr.base)
  306. goto exit;
  307. rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
  308. if (!rt2x00dev->eeprom)
  309. goto exit;
  310. rt2x00dev->rf = kzalloc(rt2x00dev->ops->rf_size, GFP_KERNEL);
  311. if (!rt2x00dev->rf)
  312. goto exit;
  313. return 0;
  314. exit:
  315. ERROR_PROBE("Failed to allocate registers.\n");
  316. rt2x00pci_free_reg(rt2x00dev);
  317. return -ENOMEM;
  318. }
  319. int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  320. {
  321. struct rt2x00_ops *ops = (struct rt2x00_ops *)id->driver_data;
  322. struct ieee80211_hw *hw;
  323. struct rt2x00_dev *rt2x00dev;
  324. int retval;
  325. retval = pci_request_regions(pci_dev, pci_name(pci_dev));
  326. if (retval) {
  327. ERROR_PROBE("PCI request regions failed.\n");
  328. return retval;
  329. }
  330. retval = pci_enable_device(pci_dev);
  331. if (retval) {
  332. ERROR_PROBE("Enable device failed.\n");
  333. goto exit_release_regions;
  334. }
  335. pci_set_master(pci_dev);
  336. if (pci_set_mwi(pci_dev))
  337. ERROR_PROBE("MWI not available.\n");
  338. if (pci_set_dma_mask(pci_dev, DMA_64BIT_MASK) &&
  339. pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
  340. ERROR_PROBE("PCI DMA not supported.\n");
  341. retval = -EIO;
  342. goto exit_disable_device;
  343. }
  344. hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
  345. if (!hw) {
  346. ERROR_PROBE("Failed to allocate hardware.\n");
  347. retval = -ENOMEM;
  348. goto exit_disable_device;
  349. }
  350. pci_set_drvdata(pci_dev, hw);
  351. rt2x00dev = hw->priv;
  352. rt2x00dev->dev = pci_dev;
  353. rt2x00dev->ops = ops;
  354. rt2x00dev->hw = hw;
  355. retval = rt2x00pci_alloc_reg(rt2x00dev);
  356. if (retval)
  357. goto exit_free_device;
  358. retval = rt2x00lib_probe_dev(rt2x00dev);
  359. if (retval)
  360. goto exit_free_reg;
  361. return 0;
  362. exit_free_reg:
  363. rt2x00pci_free_reg(rt2x00dev);
  364. exit_free_device:
  365. ieee80211_free_hw(hw);
  366. exit_disable_device:
  367. if (retval != -EBUSY)
  368. pci_disable_device(pci_dev);
  369. exit_release_regions:
  370. pci_release_regions(pci_dev);
  371. pci_set_drvdata(pci_dev, NULL);
  372. return retval;
  373. }
  374. EXPORT_SYMBOL_GPL(rt2x00pci_probe);
  375. void rt2x00pci_remove(struct pci_dev *pci_dev)
  376. {
  377. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  378. struct rt2x00_dev *rt2x00dev = hw->priv;
  379. /*
  380. * Free all allocated data.
  381. */
  382. rt2x00lib_remove_dev(rt2x00dev);
  383. rt2x00pci_free_reg(rt2x00dev);
  384. ieee80211_free_hw(hw);
  385. /*
  386. * Free the PCI device data.
  387. */
  388. pci_set_drvdata(pci_dev, NULL);
  389. pci_disable_device(pci_dev);
  390. pci_release_regions(pci_dev);
  391. }
  392. EXPORT_SYMBOL_GPL(rt2x00pci_remove);
  393. #ifdef CONFIG_PM
  394. int rt2x00pci_suspend(struct pci_dev *pci_dev, pm_message_t state)
  395. {
  396. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  397. struct rt2x00_dev *rt2x00dev = hw->priv;
  398. int retval;
  399. retval = rt2x00lib_suspend(rt2x00dev, state);
  400. if (retval)
  401. return retval;
  402. rt2x00pci_free_reg(rt2x00dev);
  403. pci_save_state(pci_dev);
  404. pci_disable_device(pci_dev);
  405. return pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
  406. }
  407. EXPORT_SYMBOL_GPL(rt2x00pci_suspend);
  408. int rt2x00pci_resume(struct pci_dev *pci_dev)
  409. {
  410. struct ieee80211_hw *hw = pci_get_drvdata(pci_dev);
  411. struct rt2x00_dev *rt2x00dev = hw->priv;
  412. int retval;
  413. if (pci_set_power_state(pci_dev, PCI_D0) ||
  414. pci_enable_device(pci_dev) ||
  415. pci_restore_state(pci_dev)) {
  416. ERROR(rt2x00dev, "Failed to resume device.\n");
  417. return -EIO;
  418. }
  419. retval = rt2x00pci_alloc_reg(rt2x00dev);
  420. if (retval)
  421. return retval;
  422. retval = rt2x00lib_resume(rt2x00dev);
  423. if (retval)
  424. goto exit_free_reg;
  425. return 0;
  426. exit_free_reg:
  427. rt2x00pci_free_reg(rt2x00dev);
  428. return retval;
  429. }
  430. EXPORT_SYMBOL_GPL(rt2x00pci_resume);
  431. #endif /* CONFIG_PM */
  432. /*
  433. * rt2x00pci module information.
  434. */
  435. MODULE_AUTHOR(DRV_PROJECT);
  436. MODULE_VERSION(DRV_VERSION);
  437. MODULE_DESCRIPTION("rt2x00 pci library");
  438. MODULE_LICENSE("GPL");