gdth.c 180 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: Command priority
  87. * buffer: unused
  88. * dma_handle: will drop in !use_sg patch.
  89. * buffers_residual: Timeout value
  90. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  91. * Message: Additional info (gdth_do_cmd()), DMA direction
  92. * have_data_in: Flag for gdth_wait_completion()
  93. * sent_command: Opcode special command
  94. * phase: Service/parameter/return code special command
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #ifdef GDTH_RTC
  117. #include <linux/mc146818rtc.h>
  118. #endif
  119. #include <linux/reboot.h>
  120. #include <asm/dma.h>
  121. #include <asm/system.h>
  122. #include <asm/io.h>
  123. #include <asm/uaccess.h>
  124. #include <linux/spinlock.h>
  125. #include <linux/blkdev.h>
  126. #include "scsi.h"
  127. #include <scsi/scsi_host.h>
  128. #include "gdth.h"
  129. static void gdth_delay(int milliseconds);
  130. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  131. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  132. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
  133. int gdth_from_wait, int* pIndex);
  134. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  135. Scsi_Cmnd *scp);
  136. static int gdth_async_event(gdth_ha_str *ha);
  137. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  138. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  139. static void gdth_next(gdth_ha_str *ha);
  140. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  141. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  142. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  143. ushort idx, gdth_evt_data *evt);
  144. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  145. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  146. gdth_evt_str *estr);
  147. static void gdth_clear_events(void);
  148. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  149. char *buffer,ushort count);
  150. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  151. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  152. static void gdth_enable_int(gdth_ha_str *ha);
  153. static unchar gdth_get_status(gdth_ha_str *ha, int irq);
  154. static int gdth_test_busy(gdth_ha_str *ha);
  155. static int gdth_get_cmd_index(gdth_ha_str *ha);
  156. static void gdth_release_event(gdth_ha_str *ha);
  157. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  158. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  159. ulong32 p1, ulong64 p2,ulong64 p3);
  160. static int gdth_search_drives(gdth_ha_str *ha);
  161. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  162. static const char *gdth_ctr_name(gdth_ha_str *ha);
  163. static int gdth_open(struct inode *inode, struct file *filep);
  164. static int gdth_close(struct inode *inode, struct file *filep);
  165. static int gdth_ioctl(struct inode *inode, struct file *filep,
  166. unsigned int cmd, unsigned long arg);
  167. static void gdth_flush(gdth_ha_str *ha);
  168. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  169. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  170. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  171. struct gdth_cmndinfo *cmndinfo);
  172. static void gdth_scsi_done(struct scsi_cmnd *scp);
  173. #ifdef DEBUG_GDTH
  174. static unchar DebugState = DEBUG_GDTH;
  175. #ifdef __SERIAL__
  176. #define MAX_SERBUF 160
  177. static void ser_init(void);
  178. static void ser_puts(char *str);
  179. static void ser_putc(char c);
  180. static int ser_printk(const char *fmt, ...);
  181. static char strbuf[MAX_SERBUF+1];
  182. #ifdef __COM2__
  183. #define COM_BASE 0x2f8
  184. #else
  185. #define COM_BASE 0x3f8
  186. #endif
  187. static void ser_init()
  188. {
  189. unsigned port=COM_BASE;
  190. outb(0x80,port+3);
  191. outb(0,port+1);
  192. /* 19200 Baud, if 9600: outb(12,port) */
  193. outb(6, port);
  194. outb(3,port+3);
  195. outb(0,port+1);
  196. /*
  197. ser_putc('I');
  198. ser_putc(' ');
  199. */
  200. }
  201. static void ser_puts(char *str)
  202. {
  203. char *ptr;
  204. ser_init();
  205. for (ptr=str;*ptr;++ptr)
  206. ser_putc(*ptr);
  207. }
  208. static void ser_putc(char c)
  209. {
  210. unsigned port=COM_BASE;
  211. while ((inb(port+5) & 0x20)==0);
  212. outb(c,port);
  213. if (c==0x0a)
  214. {
  215. while ((inb(port+5) & 0x20)==0);
  216. outb(0x0d,port);
  217. }
  218. }
  219. static int ser_printk(const char *fmt, ...)
  220. {
  221. va_list args;
  222. int i;
  223. va_start(args,fmt);
  224. i = vsprintf(strbuf,fmt,args);
  225. ser_puts(strbuf);
  226. va_end(args);
  227. return i;
  228. }
  229. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  230. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  231. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  232. #else /* !__SERIAL__ */
  233. #define TRACE(a) {if (DebugState==1) {printk a;}}
  234. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  235. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  236. #endif
  237. #else /* !DEBUG */
  238. #define TRACE(a)
  239. #define TRACE2(a)
  240. #define TRACE3(a)
  241. #endif
  242. #ifdef GDTH_STATISTICS
  243. static ulong32 max_rq=0, max_index=0, max_sg=0;
  244. #ifdef INT_COAL
  245. static ulong32 max_int_coal=0;
  246. #endif
  247. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  248. static struct timer_list gdth_timer;
  249. #endif
  250. #define PTR2USHORT(a) (ushort)(ulong)(a)
  251. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  252. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  253. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  254. #ifdef CONFIG_ISA
  255. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  256. #endif
  257. #ifdef CONFIG_EISA
  258. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  259. #endif
  260. static unchar gdth_polling; /* polling if TRUE */
  261. static int gdth_ctr_count = 0; /* controller count */
  262. static LIST_HEAD(gdth_instances); /* controller list */
  263. static unchar gdth_write_through = FALSE; /* write through */
  264. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  265. static int elastidx;
  266. static int eoldidx;
  267. static int major;
  268. #define DIN 1 /* IN data direction */
  269. #define DOU 2 /* OUT data direction */
  270. #define DNO DIN /* no data transfer */
  271. #define DUN DIN /* unknown data direction */
  272. static unchar gdth_direction_tab[0x100] = {
  273. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  274. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  275. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  276. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  277. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  278. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  284. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  285. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  289. };
  290. /* LILO and modprobe/insmod parameters */
  291. /* IRQ list for GDT3000/3020 EISA controllers */
  292. static int irq[MAXHA] __initdata =
  293. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  294. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  295. /* disable driver flag */
  296. static int disable __initdata = 0;
  297. /* reserve flag */
  298. static int reserve_mode = 1;
  299. /* reserve list */
  300. static int reserve_list[MAX_RES_ARGS] =
  301. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  302. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  303. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  304. /* scan order for PCI controllers */
  305. static int reverse_scan = 0;
  306. /* virtual channel for the host drives */
  307. static int hdr_channel = 0;
  308. /* max. IDs per channel */
  309. static int max_ids = MAXID;
  310. /* rescan all IDs */
  311. static int rescan = 0;
  312. /* shared access */
  313. static int shared_access = 1;
  314. /* enable support for EISA and ISA controllers */
  315. static int probe_eisa_isa = 0;
  316. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  317. static int force_dma32 = 0;
  318. /* parameters for modprobe/insmod */
  319. module_param_array(irq, int, NULL, 0);
  320. module_param(disable, int, 0);
  321. module_param(reserve_mode, int, 0);
  322. module_param_array(reserve_list, int, NULL, 0);
  323. module_param(reverse_scan, int, 0);
  324. module_param(hdr_channel, int, 0);
  325. module_param(max_ids, int, 0);
  326. module_param(rescan, int, 0);
  327. module_param(shared_access, int, 0);
  328. module_param(probe_eisa_isa, int, 0);
  329. module_param(force_dma32, int, 0);
  330. MODULE_AUTHOR("Achim Leubner");
  331. MODULE_LICENSE("GPL");
  332. /* ioctl interface */
  333. static const struct file_operations gdth_fops = {
  334. .ioctl = gdth_ioctl,
  335. .open = gdth_open,
  336. .release = gdth_close,
  337. };
  338. #include "gdth_proc.h"
  339. #include "gdth_proc.c"
  340. /* notifier block to get a notify on system shutdown/halt/reboot */
  341. static struct notifier_block gdth_notifier = {
  342. gdth_halt, NULL, 0
  343. };
  344. static int notifier_disabled = 0;
  345. static gdth_ha_str *gdth_find_ha(int hanum)
  346. {
  347. gdth_ha_str *ha;
  348. list_for_each_entry(ha, &gdth_instances, list)
  349. if (hanum == ha->hanum)
  350. return ha;
  351. return NULL;
  352. }
  353. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  354. {
  355. struct gdth_cmndinfo *priv = NULL;
  356. ulong flags;
  357. int i;
  358. spin_lock_irqsave(&ha->smp_lock, flags);
  359. for (i=0; i<GDTH_MAXCMDS; ++i) {
  360. if (ha->cmndinfo[i].index == 0) {
  361. priv = &ha->cmndinfo[i];
  362. priv->index = i+1;
  363. memset(priv, 0, sizeof(*priv));
  364. break;
  365. }
  366. }
  367. spin_unlock_irqrestore(&ha->smp_lock, flags);
  368. return priv;
  369. }
  370. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  371. {
  372. BUG_ON(!priv);
  373. priv->index = 0;
  374. }
  375. static void gdth_delay(int milliseconds)
  376. {
  377. if (milliseconds == 0) {
  378. udelay(1);
  379. } else {
  380. mdelay(milliseconds);
  381. }
  382. }
  383. static void gdth_scsi_done(struct scsi_cmnd *scp)
  384. {
  385. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  386. int internal_command = cmndinfo->internal_command;
  387. TRACE2(("gdth_scsi_done()\n"));
  388. gdth_put_cmndinfo(cmndinfo);
  389. scp->host_scribble = NULL;
  390. if (internal_command)
  391. complete((struct completion *)scp->request);
  392. else
  393. scp->scsi_done(scp);
  394. }
  395. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  396. int timeout, u32 *info)
  397. {
  398. gdth_ha_str *ha = shost_priv(sdev->host);
  399. Scsi_Cmnd *scp;
  400. struct gdth_cmndinfo cmndinfo;
  401. DECLARE_COMPLETION_ONSTACK(wait);
  402. int rval;
  403. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  404. if (!scp)
  405. return -ENOMEM;
  406. scp->device = sdev;
  407. memset(&cmndinfo, 0, sizeof(cmndinfo));
  408. /* use request field to save the ptr. to completion struct. */
  409. scp->request = (struct request *)&wait;
  410. scp->timeout_per_command = timeout*HZ;
  411. scp->request_buffer = gdtcmd;
  412. scp->cmd_len = 12;
  413. memcpy(scp->cmnd, cmnd, 12);
  414. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  415. cmndinfo.internal_command = 1;
  416. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  417. __gdth_queuecommand(ha, scp, &cmndinfo);
  418. wait_for_completion(&wait);
  419. rval = scp->SCp.Status;
  420. if (info)
  421. *info = scp->SCp.Message;
  422. kfree(scp);
  423. return rval;
  424. }
  425. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  426. int timeout, u32 *info)
  427. {
  428. struct scsi_device *sdev = scsi_get_host_dev(shost);
  429. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  430. scsi_free_host_dev(sdev);
  431. return rval;
  432. }
  433. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  434. {
  435. *cyls = size /HEADS/SECS;
  436. if (*cyls <= MAXCYLS) {
  437. *heads = HEADS;
  438. *secs = SECS;
  439. } else { /* too high for 64*32 */
  440. *cyls = size /MEDHEADS/MEDSECS;
  441. if (*cyls <= MAXCYLS) {
  442. *heads = MEDHEADS;
  443. *secs = MEDSECS;
  444. } else { /* too high for 127*63 */
  445. *cyls = size /BIGHEADS/BIGSECS;
  446. *heads = BIGHEADS;
  447. *secs = BIGSECS;
  448. }
  449. }
  450. }
  451. /* controller search and initialization functions */
  452. #ifdef CONFIG_EISA
  453. static int __init gdth_search_eisa(ushort eisa_adr)
  454. {
  455. ulong32 id;
  456. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  457. id = inl(eisa_adr+ID0REG);
  458. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  459. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  460. return 0; /* not EISA configured */
  461. return 1;
  462. }
  463. if (id == GDT3_ID) /* GDT3000 */
  464. return 1;
  465. return 0;
  466. }
  467. #endif /* CONFIG_EISA */
  468. #ifdef CONFIG_ISA
  469. static int __init gdth_search_isa(ulong32 bios_adr)
  470. {
  471. void __iomem *addr;
  472. ulong32 id;
  473. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  474. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  475. id = readl(addr);
  476. iounmap(addr);
  477. if (id == GDT2_ID) /* GDT2000 */
  478. return 1;
  479. }
  480. return 0;
  481. }
  482. #endif /* CONFIG_ISA */
  483. #ifdef CONFIG_PCI
  484. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  485. ushort vendor, ushort dev);
  486. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  487. {
  488. ushort device, cnt;
  489. TRACE(("gdth_search_pci()\n"));
  490. cnt = 0;
  491. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  492. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  493. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  494. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  495. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  496. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  497. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  498. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  499. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  500. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  501. PCI_DEVICE_ID_INTEL_SRC);
  502. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  503. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  504. return cnt;
  505. }
  506. /* Vortex only makes RAID controllers.
  507. * We do not really want to specify all 550 ids here, so wildcard match.
  508. */
  509. static struct pci_device_id gdthtable[] __maybe_unused = {
  510. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  511. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  512. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  513. {0}
  514. };
  515. MODULE_DEVICE_TABLE(pci,gdthtable);
  516. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  517. ushort vendor, ushort device)
  518. {
  519. ulong base0, base1, base2;
  520. struct pci_dev *pdev;
  521. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  522. *cnt, vendor, device));
  523. pdev = NULL;
  524. while ((pdev = pci_find_device(vendor, device, pdev))
  525. != NULL) {
  526. if (pci_enable_device(pdev))
  527. continue;
  528. if (*cnt >= MAXHA)
  529. return;
  530. /* GDT PCI controller found, resources are already in pdev */
  531. pcistr[*cnt].pdev = pdev;
  532. pcistr[*cnt].irq = pdev->irq;
  533. base0 = pci_resource_flags(pdev, 0);
  534. base1 = pci_resource_flags(pdev, 1);
  535. base2 = pci_resource_flags(pdev, 2);
  536. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  537. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  538. if (!(base0 & IORESOURCE_MEM))
  539. continue;
  540. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  541. } else { /* GDT6110, GDT6120, .. */
  542. if (!(base0 & IORESOURCE_MEM) ||
  543. !(base2 & IORESOURCE_MEM) ||
  544. !(base1 & IORESOURCE_IO))
  545. continue;
  546. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  547. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  548. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  549. }
  550. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  551. pcistr[*cnt].pdev->bus->number,
  552. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  553. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  554. (*cnt)++;
  555. }
  556. }
  557. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  558. {
  559. gdth_pci_str temp;
  560. int i, changed;
  561. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  562. if (cnt == 0)
  563. return;
  564. do {
  565. changed = FALSE;
  566. for (i = 0; i < cnt-1; ++i) {
  567. if (!reverse_scan) {
  568. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  569. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  570. PCI_SLOT(pcistr[i].pdev->devfn) >
  571. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  572. temp = pcistr[i];
  573. pcistr[i] = pcistr[i+1];
  574. pcistr[i+1] = temp;
  575. changed = TRUE;
  576. }
  577. } else {
  578. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  579. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  580. PCI_SLOT(pcistr[i].pdev->devfn) <
  581. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  582. temp = pcistr[i];
  583. pcistr[i] = pcistr[i+1];
  584. pcistr[i+1] = temp;
  585. changed = TRUE;
  586. }
  587. }
  588. }
  589. } while (changed);
  590. }
  591. #endif /* CONFIG_PCI */
  592. #ifdef CONFIG_EISA
  593. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  594. {
  595. ulong32 retries,id;
  596. unchar prot_ver,eisacf,i,irq_found;
  597. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  598. /* disable board interrupts, deinitialize services */
  599. outb(0xff,eisa_adr+EDOORREG);
  600. outb(0x00,eisa_adr+EDENABREG);
  601. outb(0x00,eisa_adr+EINTENABREG);
  602. outb(0xff,eisa_adr+LDOORREG);
  603. retries = INIT_RETRIES;
  604. gdth_delay(20);
  605. while (inb(eisa_adr+EDOORREG) != 0xff) {
  606. if (--retries == 0) {
  607. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  608. return 0;
  609. }
  610. gdth_delay(1);
  611. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  612. }
  613. prot_ver = inb(eisa_adr+MAILBOXREG);
  614. outb(0xff,eisa_adr+EDOORREG);
  615. if (prot_ver != PROTOCOL_VERSION) {
  616. printk("GDT-EISA: Illegal protocol version\n");
  617. return 0;
  618. }
  619. ha->bmic = eisa_adr;
  620. ha->brd_phys = (ulong32)eisa_adr >> 12;
  621. outl(0,eisa_adr+MAILBOXREG);
  622. outl(0,eisa_adr+MAILBOXREG+4);
  623. outl(0,eisa_adr+MAILBOXREG+8);
  624. outl(0,eisa_adr+MAILBOXREG+12);
  625. /* detect IRQ */
  626. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  627. ha->oem_id = OEM_ID_ICP;
  628. ha->type = GDT_EISA;
  629. ha->stype = id;
  630. outl(1,eisa_adr+MAILBOXREG+8);
  631. outb(0xfe,eisa_adr+LDOORREG);
  632. retries = INIT_RETRIES;
  633. gdth_delay(20);
  634. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  635. if (--retries == 0) {
  636. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  637. return 0;
  638. }
  639. gdth_delay(1);
  640. }
  641. ha->irq = inb(eisa_adr+MAILBOXREG);
  642. outb(0xff,eisa_adr+EDOORREG);
  643. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  644. /* check the result */
  645. if (ha->irq == 0) {
  646. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  647. for (i = 0, irq_found = FALSE;
  648. i < MAXHA && irq[i] != 0xff; ++i) {
  649. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  650. irq_found = TRUE;
  651. break;
  652. }
  653. }
  654. if (irq_found) {
  655. ha->irq = irq[i];
  656. irq[i] = 0;
  657. printk("GDT-EISA: Can not detect controller IRQ,\n");
  658. printk("Use IRQ setting from command line (IRQ = %d)\n",
  659. ha->irq);
  660. } else {
  661. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  662. printk("the controller BIOS or use command line parameters\n");
  663. return 0;
  664. }
  665. }
  666. } else {
  667. eisacf = inb(eisa_adr+EISAREG) & 7;
  668. if (eisacf > 4) /* level triggered */
  669. eisacf -= 4;
  670. ha->irq = gdth_irq_tab[eisacf];
  671. ha->oem_id = OEM_ID_ICP;
  672. ha->type = GDT_EISA;
  673. ha->stype = id;
  674. }
  675. ha->dma64_support = 0;
  676. return 1;
  677. }
  678. #endif /* CONFIG_EISA */
  679. #ifdef CONFIG_ISA
  680. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  681. {
  682. register gdt2_dpram_str __iomem *dp2_ptr;
  683. int i;
  684. unchar irq_drq,prot_ver;
  685. ulong32 retries;
  686. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  687. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  688. if (ha->brd == NULL) {
  689. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  690. return 0;
  691. }
  692. dp2_ptr = ha->brd;
  693. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  694. /* reset interface area */
  695. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  696. if (readl(&dp2_ptr->u) != 0) {
  697. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  698. iounmap(ha->brd);
  699. return 0;
  700. }
  701. /* disable board interrupts, read DRQ and IRQ */
  702. writeb(0xff, &dp2_ptr->io.irqdel);
  703. writeb(0x00, &dp2_ptr->io.irqen);
  704. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  705. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  706. irq_drq = readb(&dp2_ptr->io.rq);
  707. for (i=0; i<3; ++i) {
  708. if ((irq_drq & 1)==0)
  709. break;
  710. irq_drq >>= 1;
  711. }
  712. ha->drq = gdth_drq_tab[i];
  713. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  714. for (i=1; i<5; ++i) {
  715. if ((irq_drq & 1)==0)
  716. break;
  717. irq_drq >>= 1;
  718. }
  719. ha->irq = gdth_irq_tab[i];
  720. /* deinitialize services */
  721. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  722. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  723. writeb(0, &dp2_ptr->io.event);
  724. retries = INIT_RETRIES;
  725. gdth_delay(20);
  726. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  727. if (--retries == 0) {
  728. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  729. iounmap(ha->brd);
  730. return 0;
  731. }
  732. gdth_delay(1);
  733. }
  734. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  735. writeb(0, &dp2_ptr->u.ic.Status);
  736. writeb(0xff, &dp2_ptr->io.irqdel);
  737. if (prot_ver != PROTOCOL_VERSION) {
  738. printk("GDT-ISA: Illegal protocol version\n");
  739. iounmap(ha->brd);
  740. return 0;
  741. }
  742. ha->oem_id = OEM_ID_ICP;
  743. ha->type = GDT_ISA;
  744. ha->ic_all_size = sizeof(dp2_ptr->u);
  745. ha->stype= GDT2_ID;
  746. ha->brd_phys = bios_adr >> 4;
  747. /* special request to controller BIOS */
  748. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  749. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  750. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  751. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  752. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  753. writeb(0, &dp2_ptr->io.event);
  754. retries = INIT_RETRIES;
  755. gdth_delay(20);
  756. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  757. if (--retries == 0) {
  758. printk("GDT-ISA: Initialization error\n");
  759. iounmap(ha->brd);
  760. return 0;
  761. }
  762. gdth_delay(1);
  763. }
  764. writeb(0, &dp2_ptr->u.ic.Status);
  765. writeb(0xff, &dp2_ptr->io.irqdel);
  766. ha->dma64_support = 0;
  767. return 1;
  768. }
  769. #endif /* CONFIG_ISA */
  770. #ifdef CONFIG_PCI
  771. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  772. {
  773. register gdt6_dpram_str __iomem *dp6_ptr;
  774. register gdt6c_dpram_str __iomem *dp6c_ptr;
  775. register gdt6m_dpram_str __iomem *dp6m_ptr;
  776. ulong32 retries;
  777. unchar prot_ver;
  778. ushort command;
  779. int i, found = FALSE;
  780. TRACE(("gdth_init_pci()\n"));
  781. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  782. ha->oem_id = OEM_ID_INTEL;
  783. else
  784. ha->oem_id = OEM_ID_ICP;
  785. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  786. ha->stype = (ulong32)pcistr->pdev->device;
  787. ha->irq = pcistr->irq;
  788. ha->pdev = pcistr->pdev;
  789. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  790. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  791. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  792. if (ha->brd == NULL) {
  793. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  794. return 0;
  795. }
  796. /* check and reset interface area */
  797. dp6_ptr = ha->brd;
  798. writel(DPMEM_MAGIC, &dp6_ptr->u);
  799. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  800. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  801. pcistr->dpmem);
  802. found = FALSE;
  803. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  804. iounmap(ha->brd);
  805. ha->brd = ioremap(i, sizeof(ushort));
  806. if (ha->brd == NULL) {
  807. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  808. return 0;
  809. }
  810. if (readw(ha->brd) != 0xffff) {
  811. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  812. continue;
  813. }
  814. iounmap(ha->brd);
  815. pci_write_config_dword(pcistr->pdev,
  816. PCI_BASE_ADDRESS_0, i);
  817. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  818. if (ha->brd == NULL) {
  819. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  820. return 0;
  821. }
  822. dp6_ptr = ha->brd;
  823. writel(DPMEM_MAGIC, &dp6_ptr->u);
  824. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  825. printk("GDT-PCI: Use free address at 0x%x\n", i);
  826. found = TRUE;
  827. break;
  828. }
  829. }
  830. if (!found) {
  831. printk("GDT-PCI: No free address found!\n");
  832. iounmap(ha->brd);
  833. return 0;
  834. }
  835. }
  836. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  837. if (readl(&dp6_ptr->u) != 0) {
  838. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  839. iounmap(ha->brd);
  840. return 0;
  841. }
  842. /* disable board interrupts, deinit services */
  843. writeb(0xff, &dp6_ptr->io.irqdel);
  844. writeb(0x00, &dp6_ptr->io.irqen);
  845. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  846. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  847. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  848. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  849. writeb(0, &dp6_ptr->io.event);
  850. retries = INIT_RETRIES;
  851. gdth_delay(20);
  852. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  853. if (--retries == 0) {
  854. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  855. iounmap(ha->brd);
  856. return 0;
  857. }
  858. gdth_delay(1);
  859. }
  860. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  861. writeb(0, &dp6_ptr->u.ic.S_Status);
  862. writeb(0xff, &dp6_ptr->io.irqdel);
  863. if (prot_ver != PROTOCOL_VERSION) {
  864. printk("GDT-PCI: Illegal protocol version\n");
  865. iounmap(ha->brd);
  866. return 0;
  867. }
  868. ha->type = GDT_PCI;
  869. ha->ic_all_size = sizeof(dp6_ptr->u);
  870. /* special command to controller BIOS */
  871. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  872. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  873. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  874. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  875. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  876. writeb(0, &dp6_ptr->io.event);
  877. retries = INIT_RETRIES;
  878. gdth_delay(20);
  879. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  880. if (--retries == 0) {
  881. printk("GDT-PCI: Initialization error\n");
  882. iounmap(ha->brd);
  883. return 0;
  884. }
  885. gdth_delay(1);
  886. }
  887. writeb(0, &dp6_ptr->u.ic.S_Status);
  888. writeb(0xff, &dp6_ptr->io.irqdel);
  889. ha->dma64_support = 0;
  890. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  891. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  892. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  893. pcistr->dpmem,ha->irq));
  894. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  895. if (ha->brd == NULL) {
  896. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  897. iounmap(ha->brd);
  898. return 0;
  899. }
  900. /* check and reset interface area */
  901. dp6c_ptr = ha->brd;
  902. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  903. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  904. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  905. pcistr->dpmem);
  906. found = FALSE;
  907. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  908. iounmap(ha->brd);
  909. ha->brd = ioremap(i, sizeof(ushort));
  910. if (ha->brd == NULL) {
  911. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  912. return 0;
  913. }
  914. if (readw(ha->brd) != 0xffff) {
  915. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  916. continue;
  917. }
  918. iounmap(ha->brd);
  919. pci_write_config_dword(pcistr->pdev,
  920. PCI_BASE_ADDRESS_2, i);
  921. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  922. if (ha->brd == NULL) {
  923. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  924. return 0;
  925. }
  926. dp6c_ptr = ha->brd;
  927. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  928. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  929. printk("GDT-PCI: Use free address at 0x%x\n", i);
  930. found = TRUE;
  931. break;
  932. }
  933. }
  934. if (!found) {
  935. printk("GDT-PCI: No free address found!\n");
  936. iounmap(ha->brd);
  937. return 0;
  938. }
  939. }
  940. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  941. if (readl(&dp6c_ptr->u) != 0) {
  942. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  943. iounmap(ha->brd);
  944. return 0;
  945. }
  946. /* disable board interrupts, deinit services */
  947. outb(0x00,PTR2USHORT(&ha->plx->control1));
  948. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  949. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  950. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  951. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  952. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  953. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  954. retries = INIT_RETRIES;
  955. gdth_delay(20);
  956. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  957. if (--retries == 0) {
  958. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  959. iounmap(ha->brd);
  960. return 0;
  961. }
  962. gdth_delay(1);
  963. }
  964. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  965. writeb(0, &dp6c_ptr->u.ic.Status);
  966. if (prot_ver != PROTOCOL_VERSION) {
  967. printk("GDT-PCI: Illegal protocol version\n");
  968. iounmap(ha->brd);
  969. return 0;
  970. }
  971. ha->type = GDT_PCINEW;
  972. ha->ic_all_size = sizeof(dp6c_ptr->u);
  973. /* special command to controller BIOS */
  974. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  975. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  976. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  977. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  978. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  979. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  980. retries = INIT_RETRIES;
  981. gdth_delay(20);
  982. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  983. if (--retries == 0) {
  984. printk("GDT-PCI: Initialization error\n");
  985. iounmap(ha->brd);
  986. return 0;
  987. }
  988. gdth_delay(1);
  989. }
  990. writeb(0, &dp6c_ptr->u.ic.S_Status);
  991. ha->dma64_support = 0;
  992. } else { /* MPR */
  993. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  994. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  995. if (ha->brd == NULL) {
  996. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  997. return 0;
  998. }
  999. /* manipulate config. space to enable DPMEM, start RP controller */
  1000. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1001. command |= 6;
  1002. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1003. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1004. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1005. i = 0xFEFF0001UL;
  1006. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1007. gdth_delay(1);
  1008. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1009. pci_resource_start(pcistr->pdev, 8));
  1010. dp6m_ptr = ha->brd;
  1011. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1012. * Aditional check needed for Xscale based RAID controllers */
  1013. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1014. gdth_delay(1);
  1015. /* check and reset interface area */
  1016. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1017. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1018. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1019. pcistr->dpmem);
  1020. found = FALSE;
  1021. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1022. iounmap(ha->brd);
  1023. ha->brd = ioremap(i, sizeof(ushort));
  1024. if (ha->brd == NULL) {
  1025. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1026. return 0;
  1027. }
  1028. if (readw(ha->brd) != 0xffff) {
  1029. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1030. continue;
  1031. }
  1032. iounmap(ha->brd);
  1033. pci_write_config_dword(pcistr->pdev,
  1034. PCI_BASE_ADDRESS_0, i);
  1035. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1036. if (ha->brd == NULL) {
  1037. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1038. return 0;
  1039. }
  1040. dp6m_ptr = ha->brd;
  1041. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1042. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1043. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1044. found = TRUE;
  1045. break;
  1046. }
  1047. }
  1048. if (!found) {
  1049. printk("GDT-PCI: No free address found!\n");
  1050. iounmap(ha->brd);
  1051. return 0;
  1052. }
  1053. }
  1054. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1055. /* disable board interrupts, deinit services */
  1056. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1057. &dp6m_ptr->i960r.edoor_en_reg);
  1058. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1059. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1060. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1061. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1062. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1063. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1064. retries = INIT_RETRIES;
  1065. gdth_delay(20);
  1066. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1067. if (--retries == 0) {
  1068. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1069. iounmap(ha->brd);
  1070. return 0;
  1071. }
  1072. gdth_delay(1);
  1073. }
  1074. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1075. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1076. if (prot_ver != PROTOCOL_VERSION) {
  1077. printk("GDT-PCI: Illegal protocol version\n");
  1078. iounmap(ha->brd);
  1079. return 0;
  1080. }
  1081. ha->type = GDT_PCIMPR;
  1082. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1083. /* special command to controller BIOS */
  1084. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1085. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1086. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1087. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1088. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1089. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1090. retries = INIT_RETRIES;
  1091. gdth_delay(20);
  1092. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1093. if (--retries == 0) {
  1094. printk("GDT-PCI: Initialization error\n");
  1095. iounmap(ha->brd);
  1096. return 0;
  1097. }
  1098. gdth_delay(1);
  1099. }
  1100. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1101. /* read FW version to detect 64-bit DMA support */
  1102. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1103. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1104. retries = INIT_RETRIES;
  1105. gdth_delay(20);
  1106. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1107. if (--retries == 0) {
  1108. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1109. iounmap(ha->brd);
  1110. return 0;
  1111. }
  1112. gdth_delay(1);
  1113. }
  1114. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1115. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1116. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1117. ha->dma64_support = 0;
  1118. else
  1119. ha->dma64_support = 1;
  1120. }
  1121. return 1;
  1122. }
  1123. #endif /* CONFIG_PCI */
  1124. /* controller protocol functions */
  1125. static void __init gdth_enable_int(gdth_ha_str *ha)
  1126. {
  1127. ulong flags;
  1128. gdt2_dpram_str __iomem *dp2_ptr;
  1129. gdt6_dpram_str __iomem *dp6_ptr;
  1130. gdt6m_dpram_str __iomem *dp6m_ptr;
  1131. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1132. spin_lock_irqsave(&ha->smp_lock, flags);
  1133. if (ha->type == GDT_EISA) {
  1134. outb(0xff, ha->bmic + EDOORREG);
  1135. outb(0xff, ha->bmic + EDENABREG);
  1136. outb(0x01, ha->bmic + EINTENABREG);
  1137. } else if (ha->type == GDT_ISA) {
  1138. dp2_ptr = ha->brd;
  1139. writeb(1, &dp2_ptr->io.irqdel);
  1140. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1141. writeb(1, &dp2_ptr->io.irqen);
  1142. } else if (ha->type == GDT_PCI) {
  1143. dp6_ptr = ha->brd;
  1144. writeb(1, &dp6_ptr->io.irqdel);
  1145. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1146. writeb(1, &dp6_ptr->io.irqen);
  1147. } else if (ha->type == GDT_PCINEW) {
  1148. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1149. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1150. } else if (ha->type == GDT_PCIMPR) {
  1151. dp6m_ptr = ha->brd;
  1152. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1153. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1154. &dp6m_ptr->i960r.edoor_en_reg);
  1155. }
  1156. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1157. }
  1158. /* return IStatus if interrupt was from this card else 0 */
  1159. static unchar gdth_get_status(gdth_ha_str *ha, int irq)
  1160. {
  1161. unchar IStatus = 0;
  1162. TRACE(("gdth_get_status() irq %d ctr_count %d\n", irq, gdth_ctr_count));
  1163. if (ha->irq != (unchar)irq) /* check IRQ */
  1164. return false;
  1165. if (ha->type == GDT_EISA)
  1166. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1167. else if (ha->type == GDT_ISA)
  1168. IStatus =
  1169. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1170. else if (ha->type == GDT_PCI)
  1171. IStatus =
  1172. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1173. else if (ha->type == GDT_PCINEW)
  1174. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1175. else if (ha->type == GDT_PCIMPR)
  1176. IStatus =
  1177. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1178. return IStatus;
  1179. }
  1180. static int gdth_test_busy(gdth_ha_str *ha)
  1181. {
  1182. register int gdtsema0 = 0;
  1183. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1184. if (ha->type == GDT_EISA)
  1185. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1186. else if (ha->type == GDT_ISA)
  1187. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1188. else if (ha->type == GDT_PCI)
  1189. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1190. else if (ha->type == GDT_PCINEW)
  1191. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1192. else if (ha->type == GDT_PCIMPR)
  1193. gdtsema0 =
  1194. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1195. return (gdtsema0 & 1);
  1196. }
  1197. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1198. {
  1199. int i;
  1200. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1201. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1202. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1203. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1204. ha->cmd_tab[i].service = ha->pccb->Service;
  1205. ha->pccb->CommandIndex = (ulong32)i+2;
  1206. return (i+2);
  1207. }
  1208. }
  1209. return 0;
  1210. }
  1211. static void gdth_set_sema0(gdth_ha_str *ha)
  1212. {
  1213. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1214. if (ha->type == GDT_EISA) {
  1215. outb(1, ha->bmic + SEMA0REG);
  1216. } else if (ha->type == GDT_ISA) {
  1217. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1218. } else if (ha->type == GDT_PCI) {
  1219. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1220. } else if (ha->type == GDT_PCINEW) {
  1221. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1222. } else if (ha->type == GDT_PCIMPR) {
  1223. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1224. }
  1225. }
  1226. static void gdth_copy_command(gdth_ha_str *ha)
  1227. {
  1228. register gdth_cmd_str *cmd_ptr;
  1229. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1230. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1231. gdt6_dpram_str __iomem *dp6_ptr;
  1232. gdt2_dpram_str __iomem *dp2_ptr;
  1233. ushort cp_count,dp_offset,cmd_no;
  1234. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1235. cp_count = ha->cmd_len;
  1236. dp_offset= ha->cmd_offs_dpmem;
  1237. cmd_no = ha->cmd_cnt;
  1238. cmd_ptr = ha->pccb;
  1239. ++ha->cmd_cnt;
  1240. if (ha->type == GDT_EISA)
  1241. return; /* no DPMEM, no copy */
  1242. /* set cpcount dword aligned */
  1243. if (cp_count & 3)
  1244. cp_count += (4 - (cp_count & 3));
  1245. ha->cmd_offs_dpmem += cp_count;
  1246. /* set offset and service, copy command to DPMEM */
  1247. if (ha->type == GDT_ISA) {
  1248. dp2_ptr = ha->brd;
  1249. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1250. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1251. writew((ushort)cmd_ptr->Service,
  1252. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1253. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1254. } else if (ha->type == GDT_PCI) {
  1255. dp6_ptr = ha->brd;
  1256. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1257. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1258. writew((ushort)cmd_ptr->Service,
  1259. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1260. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1261. } else if (ha->type == GDT_PCINEW) {
  1262. dp6c_ptr = ha->brd;
  1263. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1264. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1265. writew((ushort)cmd_ptr->Service,
  1266. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1267. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1268. } else if (ha->type == GDT_PCIMPR) {
  1269. dp6m_ptr = ha->brd;
  1270. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1271. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1272. writew((ushort)cmd_ptr->Service,
  1273. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1274. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1275. }
  1276. }
  1277. static void gdth_release_event(gdth_ha_str *ha)
  1278. {
  1279. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1280. #ifdef GDTH_STATISTICS
  1281. {
  1282. ulong32 i,j;
  1283. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1284. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1285. ++i;
  1286. }
  1287. if (max_index < i) {
  1288. max_index = i;
  1289. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1290. }
  1291. }
  1292. #endif
  1293. if (ha->pccb->OpCode == GDT_INIT)
  1294. ha->pccb->Service |= 0x80;
  1295. if (ha->type == GDT_EISA) {
  1296. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1297. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1298. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1299. } else if (ha->type == GDT_ISA) {
  1300. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1301. } else if (ha->type == GDT_PCI) {
  1302. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1303. } else if (ha->type == GDT_PCINEW) {
  1304. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1305. } else if (ha->type == GDT_PCIMPR) {
  1306. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1307. }
  1308. }
  1309. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1310. {
  1311. int answer_found = FALSE;
  1312. int wait_index = 0;
  1313. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1314. if (index == 0)
  1315. return 1; /* no wait required */
  1316. do {
  1317. __gdth_interrupt(ha, (int)ha->irq, true, &wait_index);
  1318. if (wait_index == index) {
  1319. answer_found = TRUE;
  1320. break;
  1321. }
  1322. gdth_delay(1);
  1323. } while (--time);
  1324. while (gdth_test_busy(ha))
  1325. gdth_delay(0);
  1326. return (answer_found);
  1327. }
  1328. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1329. ulong32 p1, ulong64 p2, ulong64 p3)
  1330. {
  1331. register gdth_cmd_str *cmd_ptr;
  1332. int retries,index;
  1333. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1334. cmd_ptr = ha->pccb;
  1335. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1336. /* make command */
  1337. for (retries = INIT_RETRIES;;) {
  1338. cmd_ptr->Service = service;
  1339. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1340. if (!(index=gdth_get_cmd_index(ha))) {
  1341. TRACE(("GDT: No free command index found\n"));
  1342. return 0;
  1343. }
  1344. gdth_set_sema0(ha);
  1345. cmd_ptr->OpCode = opcode;
  1346. cmd_ptr->BoardNode = LOCALBOARD;
  1347. if (service == CACHESERVICE) {
  1348. if (opcode == GDT_IOCTL) {
  1349. cmd_ptr->u.ioctl.subfunc = p1;
  1350. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1351. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1352. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1353. } else {
  1354. if (ha->cache_feat & GDT_64BIT) {
  1355. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1356. cmd_ptr->u.cache64.BlockNo = p2;
  1357. } else {
  1358. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1359. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1360. }
  1361. }
  1362. } else if (service == SCSIRAWSERVICE) {
  1363. if (ha->raw_feat & GDT_64BIT) {
  1364. cmd_ptr->u.raw64.direction = p1;
  1365. cmd_ptr->u.raw64.bus = (unchar)p2;
  1366. cmd_ptr->u.raw64.target = (unchar)p3;
  1367. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1368. } else {
  1369. cmd_ptr->u.raw.direction = p1;
  1370. cmd_ptr->u.raw.bus = (unchar)p2;
  1371. cmd_ptr->u.raw.target = (unchar)p3;
  1372. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1373. }
  1374. } else if (service == SCREENSERVICE) {
  1375. if (opcode == GDT_REALTIME) {
  1376. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1377. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1378. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1379. }
  1380. }
  1381. ha->cmd_len = sizeof(gdth_cmd_str);
  1382. ha->cmd_offs_dpmem = 0;
  1383. ha->cmd_cnt = 0;
  1384. gdth_copy_command(ha);
  1385. gdth_release_event(ha);
  1386. gdth_delay(20);
  1387. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1388. printk("GDT: Initialization error (timeout service %d)\n",service);
  1389. return 0;
  1390. }
  1391. if (ha->status != S_BSY || --retries == 0)
  1392. break;
  1393. gdth_delay(1);
  1394. }
  1395. return (ha->status != S_OK ? 0:1);
  1396. }
  1397. /* search for devices */
  1398. static int __init gdth_search_drives(gdth_ha_str *ha)
  1399. {
  1400. ushort cdev_cnt, i;
  1401. int ok;
  1402. ulong32 bus_no, drv_cnt, drv_no, j;
  1403. gdth_getch_str *chn;
  1404. gdth_drlist_str *drl;
  1405. gdth_iochan_str *ioc;
  1406. gdth_raw_iochan_str *iocr;
  1407. gdth_arcdl_str *alst;
  1408. gdth_alist_str *alst2;
  1409. gdth_oem_str_ioctl *oemstr;
  1410. #ifdef INT_COAL
  1411. gdth_perf_modes *pmod;
  1412. #endif
  1413. #ifdef GDTH_RTC
  1414. unchar rtc[12];
  1415. ulong flags;
  1416. #endif
  1417. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1418. ok = 0;
  1419. /* initialize controller services, at first: screen service */
  1420. ha->screen_feat = 0;
  1421. if (!force_dma32) {
  1422. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1423. if (ok)
  1424. ha->screen_feat = GDT_64BIT;
  1425. }
  1426. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1427. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1428. if (!ok) {
  1429. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1430. ha->hanum, ha->status);
  1431. return 0;
  1432. }
  1433. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1434. #ifdef GDTH_RTC
  1435. /* read realtime clock info, send to controller */
  1436. /* 1. wait for the falling edge of update flag */
  1437. spin_lock_irqsave(&rtc_lock, flags);
  1438. for (j = 0; j < 1000000; ++j)
  1439. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1440. break;
  1441. for (j = 0; j < 1000000; ++j)
  1442. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1443. break;
  1444. /* 2. read info */
  1445. do {
  1446. for (j = 0; j < 12; ++j)
  1447. rtc[j] = CMOS_READ(j);
  1448. } while (rtc[0] != CMOS_READ(0));
  1449. spin_unlock_irqrestore(&rtc_lock, flags);
  1450. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1451. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1452. /* 3. send to controller firmware */
  1453. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1454. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1455. #endif
  1456. /* unfreeze all IOs */
  1457. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1458. /* initialize cache service */
  1459. ha->cache_feat = 0;
  1460. if (!force_dma32) {
  1461. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1462. 0, 0);
  1463. if (ok)
  1464. ha->cache_feat = GDT_64BIT;
  1465. }
  1466. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1467. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1468. if (!ok) {
  1469. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1470. ha->hanum, ha->status);
  1471. return 0;
  1472. }
  1473. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1474. cdev_cnt = (ushort)ha->info;
  1475. ha->fw_vers = ha->service;
  1476. #ifdef INT_COAL
  1477. if (ha->type == GDT_PCIMPR) {
  1478. /* set perf. modes */
  1479. pmod = (gdth_perf_modes *)ha->pscratch;
  1480. pmod->version = 1;
  1481. pmod->st_mode = 1; /* enable one status buffer */
  1482. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1483. pmod->st_buff_indx1 = COALINDEX;
  1484. pmod->st_buff_addr2 = 0;
  1485. pmod->st_buff_u_addr2 = 0;
  1486. pmod->st_buff_indx2 = 0;
  1487. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1488. pmod->cmd_mode = 0; // disable all cmd buffers
  1489. pmod->cmd_buff_addr1 = 0;
  1490. pmod->cmd_buff_u_addr1 = 0;
  1491. pmod->cmd_buff_indx1 = 0;
  1492. pmod->cmd_buff_addr2 = 0;
  1493. pmod->cmd_buff_u_addr2 = 0;
  1494. pmod->cmd_buff_indx2 = 0;
  1495. pmod->cmd_buff_size = 0;
  1496. pmod->reserved1 = 0;
  1497. pmod->reserved2 = 0;
  1498. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1499. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1500. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1501. }
  1502. }
  1503. #endif
  1504. /* detect number of buses - try new IOCTL */
  1505. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1506. iocr->hdr.version = 0xffffffff;
  1507. iocr->hdr.list_entries = MAXBUS;
  1508. iocr->hdr.first_chan = 0;
  1509. iocr->hdr.last_chan = MAXBUS-1;
  1510. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1511. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1512. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1513. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1514. ha->bus_cnt = iocr->hdr.chan_count;
  1515. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1516. if (iocr->list[bus_no].proc_id < MAXID)
  1517. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1518. else
  1519. ha->bus_id[bus_no] = 0xff;
  1520. }
  1521. } else {
  1522. /* old method */
  1523. chn = (gdth_getch_str *)ha->pscratch;
  1524. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1525. chn->channel_no = bus_no;
  1526. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1527. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1528. IO_CHANNEL | INVALID_CHANNEL,
  1529. sizeof(gdth_getch_str))) {
  1530. if (bus_no == 0) {
  1531. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1532. ha->hanum, ha->status);
  1533. return 0;
  1534. }
  1535. break;
  1536. }
  1537. if (chn->siop_id < MAXID)
  1538. ha->bus_id[bus_no] = chn->siop_id;
  1539. else
  1540. ha->bus_id[bus_no] = 0xff;
  1541. }
  1542. ha->bus_cnt = (unchar)bus_no;
  1543. }
  1544. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1545. /* read cache configuration */
  1546. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1547. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1548. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1549. ha->hanum, ha->status);
  1550. return 0;
  1551. }
  1552. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1553. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1554. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1555. ha->cpar.write_back,ha->cpar.block_size));
  1556. /* read board info and features */
  1557. ha->more_proc = FALSE;
  1558. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1559. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1560. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1561. sizeof(gdth_binfo_str));
  1562. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1563. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1564. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1565. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1566. ha->more_proc = TRUE;
  1567. }
  1568. } else {
  1569. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1570. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1571. }
  1572. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1573. /* read more informations */
  1574. if (ha->more_proc) {
  1575. /* physical drives, channel addresses */
  1576. ioc = (gdth_iochan_str *)ha->pscratch;
  1577. ioc->hdr.version = 0xffffffff;
  1578. ioc->hdr.list_entries = MAXBUS;
  1579. ioc->hdr.first_chan = 0;
  1580. ioc->hdr.last_chan = MAXBUS-1;
  1581. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1582. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1583. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1584. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1585. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1586. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1587. }
  1588. } else {
  1589. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1590. ha->raw[bus_no].address = IO_CHANNEL;
  1591. ha->raw[bus_no].local_no = bus_no;
  1592. }
  1593. }
  1594. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1595. chn = (gdth_getch_str *)ha->pscratch;
  1596. chn->channel_no = ha->raw[bus_no].local_no;
  1597. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1598. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1599. ha->raw[bus_no].address | INVALID_CHANNEL,
  1600. sizeof(gdth_getch_str))) {
  1601. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1602. TRACE2(("Channel %d: %d phys. drives\n",
  1603. bus_no,chn->drive_cnt));
  1604. }
  1605. if (ha->raw[bus_no].pdev_cnt > 0) {
  1606. drl = (gdth_drlist_str *)ha->pscratch;
  1607. drl->sc_no = ha->raw[bus_no].local_no;
  1608. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1609. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1610. SCSI_DR_LIST | L_CTRL_PATTERN,
  1611. ha->raw[bus_no].address | INVALID_CHANNEL,
  1612. sizeof(gdth_drlist_str))) {
  1613. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1614. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1615. } else {
  1616. ha->raw[bus_no].pdev_cnt = 0;
  1617. }
  1618. }
  1619. }
  1620. /* logical drives */
  1621. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1622. INVALID_CHANNEL,sizeof(ulong32))) {
  1623. drv_cnt = *(ulong32 *)ha->pscratch;
  1624. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1625. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1626. for (j = 0; j < drv_cnt; ++j) {
  1627. drv_no = ((ulong32 *)ha->pscratch)[j];
  1628. if (drv_no < MAX_LDRIVES) {
  1629. ha->hdr[drv_no].is_logdrv = TRUE;
  1630. TRACE2(("Drive %d is log. drive\n",drv_no));
  1631. }
  1632. }
  1633. }
  1634. alst = (gdth_arcdl_str *)ha->pscratch;
  1635. alst->entries_avail = MAX_LDRIVES;
  1636. alst->first_entry = 0;
  1637. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1638. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1639. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1640. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1641. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1642. for (j = 0; j < alst->entries_init; ++j) {
  1643. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1644. ha->hdr[j].is_master = alst->list[j].is_master;
  1645. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1646. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1647. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1648. }
  1649. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1650. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1651. 0, 35 * sizeof(gdth_alist_str))) {
  1652. for (j = 0; j < 35; ++j) {
  1653. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1654. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1655. ha->hdr[j].is_master = alst2->is_master;
  1656. ha->hdr[j].is_parity = alst2->is_parity;
  1657. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1658. ha->hdr[j].master_no = alst2->cd_handle;
  1659. }
  1660. }
  1661. }
  1662. }
  1663. /* initialize raw service */
  1664. ha->raw_feat = 0;
  1665. if (!force_dma32) {
  1666. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1667. if (ok)
  1668. ha->raw_feat = GDT_64BIT;
  1669. }
  1670. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1671. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1672. if (!ok) {
  1673. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1674. ha->hanum, ha->status);
  1675. return 0;
  1676. }
  1677. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1678. /* set/get features raw service (scatter/gather) */
  1679. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1680. 0, 0)) {
  1681. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1682. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1683. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1684. ha->info));
  1685. ha->raw_feat |= (ushort)ha->info;
  1686. }
  1687. }
  1688. /* set/get features cache service (equal to raw service) */
  1689. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1690. SCATTER_GATHER,0)) {
  1691. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1692. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1693. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1694. ha->info));
  1695. ha->cache_feat |= (ushort)ha->info;
  1696. }
  1697. }
  1698. /* reserve drives for raw service */
  1699. if (reserve_mode != 0) {
  1700. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1701. reserve_mode == 1 ? 1 : 3, 0, 0);
  1702. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1703. ha->status));
  1704. }
  1705. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1706. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1707. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1708. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1709. reserve_list[i], reserve_list[i+1],
  1710. reserve_list[i+2], reserve_list[i+3]));
  1711. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1712. reserve_list[i+1], reserve_list[i+2] |
  1713. (reserve_list[i+3] << 8))) {
  1714. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1715. ha->hanum, ha->status);
  1716. }
  1717. }
  1718. }
  1719. /* Determine OEM string using IOCTL */
  1720. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1721. oemstr->params.ctl_version = 0x01;
  1722. oemstr->params.buffer_size = sizeof(oemstr->text);
  1723. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1724. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1725. sizeof(gdth_oem_str_ioctl))) {
  1726. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1727. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1728. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1729. /* Save the Host Drive inquiry data */
  1730. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1731. sizeof(ha->oem_name));
  1732. } else {
  1733. /* Old method, based on PCI ID */
  1734. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1735. printk("GDT-HA %d: Name: %s\n",
  1736. ha->hanum, ha->binfo.type_string);
  1737. if (ha->oem_id == OEM_ID_INTEL)
  1738. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1739. else
  1740. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1741. }
  1742. /* scanning for host drives */
  1743. for (i = 0; i < cdev_cnt; ++i)
  1744. gdth_analyse_hdrive(ha, i);
  1745. TRACE(("gdth_search_drives() OK\n"));
  1746. return 1;
  1747. }
  1748. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1749. {
  1750. ulong32 drv_cyls;
  1751. int drv_hds, drv_secs;
  1752. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1753. if (hdrive >= MAX_HDRIVES)
  1754. return 0;
  1755. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1756. return 0;
  1757. ha->hdr[hdrive].present = TRUE;
  1758. ha->hdr[hdrive].size = ha->info;
  1759. /* evaluate mapping (sectors per head, heads per cylinder) */
  1760. ha->hdr[hdrive].size &= ~SECS32;
  1761. if (ha->info2 == 0) {
  1762. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1763. } else {
  1764. drv_hds = ha->info2 & 0xff;
  1765. drv_secs = (ha->info2 >> 8) & 0xff;
  1766. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1767. }
  1768. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1769. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1770. /* round size */
  1771. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1772. if (ha->cache_feat & GDT_64BIT) {
  1773. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1774. && ha->info2 != 0) {
  1775. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1776. }
  1777. }
  1778. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1779. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1780. /* get informations about device */
  1781. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1782. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1783. hdrive,ha->info));
  1784. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1785. }
  1786. /* cluster info */
  1787. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1788. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1789. hdrive,ha->info));
  1790. if (!shared_access)
  1791. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1792. }
  1793. /* R/W attributes */
  1794. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1795. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1796. hdrive,ha->info));
  1797. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1798. }
  1799. return 1;
  1800. }
  1801. /* command queueing/sending functions */
  1802. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1803. {
  1804. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1805. register Scsi_Cmnd *pscp;
  1806. register Scsi_Cmnd *nscp;
  1807. ulong flags;
  1808. unchar b, t;
  1809. TRACE(("gdth_putq() priority %d\n",priority));
  1810. spin_lock_irqsave(&ha->smp_lock, flags);
  1811. if (!cmndinfo->internal_command) {
  1812. scp->SCp.this_residual = (int)priority;
  1813. b = scp->device->channel;
  1814. t = scp->device->id;
  1815. if (priority >= DEFAULT_PRI) {
  1816. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1817. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1818. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1819. scp->SCp.buffers_residual = gdth_update_timeout(scp, 0);
  1820. }
  1821. }
  1822. }
  1823. if (ha->req_first==NULL) {
  1824. ha->req_first = scp; /* queue was empty */
  1825. scp->SCp.ptr = NULL;
  1826. } else { /* queue not empty */
  1827. pscp = ha->req_first;
  1828. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1829. /* priority: 0-highest,..,0xff-lowest */
  1830. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  1831. pscp = nscp;
  1832. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1833. }
  1834. pscp->SCp.ptr = (char *)scp;
  1835. scp->SCp.ptr = (char *)nscp;
  1836. }
  1837. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1838. #ifdef GDTH_STATISTICS
  1839. flags = 0;
  1840. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1841. ++flags;
  1842. if (max_rq < flags) {
  1843. max_rq = flags;
  1844. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1845. }
  1846. #endif
  1847. }
  1848. static void gdth_next(gdth_ha_str *ha)
  1849. {
  1850. register Scsi_Cmnd *pscp;
  1851. register Scsi_Cmnd *nscp;
  1852. unchar b, t, l, firsttime;
  1853. unchar this_cmd, next_cmd;
  1854. ulong flags = 0;
  1855. int cmd_index;
  1856. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1857. if (!gdth_polling)
  1858. spin_lock_irqsave(&ha->smp_lock, flags);
  1859. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1860. this_cmd = firsttime = TRUE;
  1861. next_cmd = gdth_polling ? FALSE:TRUE;
  1862. cmd_index = 0;
  1863. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1864. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1865. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1866. if (!gdth_cmnd_priv(nscp)->internal_command) {
  1867. b = nscp->device->channel;
  1868. t = nscp->device->id;
  1869. l = nscp->device->lun;
  1870. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  1871. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1872. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1873. continue;
  1874. }
  1875. } else
  1876. b = t = l = 0;
  1877. if (firsttime) {
  1878. if (gdth_test_busy(ha)) { /* controller busy ? */
  1879. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1880. if (!gdth_polling) {
  1881. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1882. return;
  1883. }
  1884. while (gdth_test_busy(ha))
  1885. gdth_delay(1);
  1886. }
  1887. firsttime = FALSE;
  1888. }
  1889. if (!gdth_cmnd_priv(nscp)->internal_command) {
  1890. if (nscp->SCp.phase == -1) {
  1891. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  1892. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1893. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1894. b, t, l));
  1895. /* TEST_UNIT_READY -> set scan mode */
  1896. if ((ha->scan_mode & 0x0f) == 0) {
  1897. if (b == 0 && t == 0 && l == 0) {
  1898. ha->scan_mode |= 1;
  1899. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1900. }
  1901. } else if ((ha->scan_mode & 0x0f) == 1) {
  1902. if (b == 0 && ((t == 0 && l == 1) ||
  1903. (t == 1 && l == 0))) {
  1904. nscp->SCp.sent_command = GDT_SCAN_START;
  1905. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1906. | SCSIRAWSERVICE;
  1907. ha->scan_mode = 0x12;
  1908. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1909. ha->scan_mode));
  1910. } else {
  1911. ha->scan_mode &= 0x10;
  1912. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1913. }
  1914. } else if (ha->scan_mode == 0x12) {
  1915. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1916. nscp->SCp.phase = SCSIRAWSERVICE;
  1917. nscp->SCp.sent_command = GDT_SCAN_END;
  1918. ha->scan_mode &= 0x10;
  1919. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1920. ha->scan_mode));
  1921. }
  1922. }
  1923. }
  1924. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1925. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1926. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1927. /* always GDT_CLUST_INFO! */
  1928. nscp->SCp.sent_command = GDT_CLUST_INFO;
  1929. }
  1930. }
  1931. }
  1932. if (nscp->SCp.sent_command != -1) {
  1933. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  1934. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1935. this_cmd = FALSE;
  1936. next_cmd = FALSE;
  1937. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  1938. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1939. this_cmd = FALSE;
  1940. next_cmd = FALSE;
  1941. } else {
  1942. memset((char*)nscp->sense_buffer,0,16);
  1943. nscp->sense_buffer[0] = 0x70;
  1944. nscp->sense_buffer[2] = NOT_READY;
  1945. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1946. if (!nscp->SCp.have_data_in)
  1947. nscp->SCp.have_data_in++;
  1948. else
  1949. gdth_scsi_done(nscp);
  1950. }
  1951. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1952. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1953. this_cmd = FALSE;
  1954. next_cmd = FALSE;
  1955. } else if (b != ha->virt_bus) {
  1956. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1957. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1958. this_cmd = FALSE;
  1959. else
  1960. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1961. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1962. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1963. nscp->cmnd[0], b, t, l));
  1964. nscp->result = DID_BAD_TARGET << 16;
  1965. if (!nscp->SCp.have_data_in)
  1966. nscp->SCp.have_data_in++;
  1967. else
  1968. gdth_scsi_done(nscp);
  1969. } else {
  1970. switch (nscp->cmnd[0]) {
  1971. case TEST_UNIT_READY:
  1972. case INQUIRY:
  1973. case REQUEST_SENSE:
  1974. case READ_CAPACITY:
  1975. case VERIFY:
  1976. case START_STOP:
  1977. case MODE_SENSE:
  1978. case SERVICE_ACTION_IN:
  1979. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1980. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1981. nscp->cmnd[4],nscp->cmnd[5]));
  1982. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1983. /* return UNIT_ATTENTION */
  1984. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1985. nscp->cmnd[0], t));
  1986. ha->hdr[t].media_changed = FALSE;
  1987. memset((char*)nscp->sense_buffer,0,16);
  1988. nscp->sense_buffer[0] = 0x70;
  1989. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1990. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1991. if (!nscp->SCp.have_data_in)
  1992. nscp->SCp.have_data_in++;
  1993. else
  1994. gdth_scsi_done(nscp);
  1995. } else if (gdth_internal_cache_cmd(ha, nscp))
  1996. gdth_scsi_done(nscp);
  1997. break;
  1998. case ALLOW_MEDIUM_REMOVAL:
  1999. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2000. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2001. nscp->cmnd[4],nscp->cmnd[5]));
  2002. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2003. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2004. nscp->result = DID_OK << 16;
  2005. nscp->sense_buffer[0] = 0;
  2006. if (!nscp->SCp.have_data_in)
  2007. nscp->SCp.have_data_in++;
  2008. else
  2009. gdth_scsi_done(nscp);
  2010. } else {
  2011. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2012. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2013. nscp->cmnd[4],nscp->cmnd[3]));
  2014. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2015. this_cmd = FALSE;
  2016. }
  2017. break;
  2018. case RESERVE:
  2019. case RELEASE:
  2020. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2021. "RESERVE" : "RELEASE"));
  2022. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2023. this_cmd = FALSE;
  2024. break;
  2025. case READ_6:
  2026. case WRITE_6:
  2027. case READ_10:
  2028. case WRITE_10:
  2029. case READ_16:
  2030. case WRITE_16:
  2031. if (ha->hdr[t].media_changed) {
  2032. /* return UNIT_ATTENTION */
  2033. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2034. nscp->cmnd[0], t));
  2035. ha->hdr[t].media_changed = FALSE;
  2036. memset((char*)nscp->sense_buffer,0,16);
  2037. nscp->sense_buffer[0] = 0x70;
  2038. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2039. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2040. if (!nscp->SCp.have_data_in)
  2041. nscp->SCp.have_data_in++;
  2042. else
  2043. gdth_scsi_done(nscp);
  2044. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2045. this_cmd = FALSE;
  2046. break;
  2047. default:
  2048. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2049. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2050. nscp->cmnd[4],nscp->cmnd[5]));
  2051. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2052. ha->hanum, nscp->cmnd[0]);
  2053. nscp->result = DID_ABORT << 16;
  2054. if (!nscp->SCp.have_data_in)
  2055. nscp->SCp.have_data_in++;
  2056. else
  2057. gdth_scsi_done(nscp);
  2058. break;
  2059. }
  2060. }
  2061. if (!this_cmd)
  2062. break;
  2063. if (nscp == ha->req_first)
  2064. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2065. else
  2066. pscp->SCp.ptr = nscp->SCp.ptr;
  2067. if (!next_cmd)
  2068. break;
  2069. }
  2070. if (ha->cmd_cnt > 0) {
  2071. gdth_release_event(ha);
  2072. }
  2073. if (!gdth_polling)
  2074. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2075. if (gdth_polling && ha->cmd_cnt > 0) {
  2076. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2077. printk("GDT-HA %d: Command %d timed out !\n",
  2078. ha->hanum, cmd_index);
  2079. }
  2080. }
  2081. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2082. char *buffer,ushort count)
  2083. {
  2084. ushort cpcount,i;
  2085. ushort cpsum,cpnow;
  2086. struct scatterlist *sl;
  2087. char *address;
  2088. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2089. if (scp->use_sg) {
  2090. sl = (struct scatterlist *)scp->request_buffer;
  2091. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2092. unsigned long flags;
  2093. cpnow = (ushort)sl->length;
  2094. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2095. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2096. if (cpsum+cpnow > cpcount)
  2097. cpnow = cpcount - cpsum;
  2098. cpsum += cpnow;
  2099. if (!sl->page) {
  2100. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2101. ha->hanum);
  2102. return;
  2103. }
  2104. local_irq_save(flags);
  2105. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2106. memcpy(address,buffer,cpnow);
  2107. flush_dcache_page(sl->page);
  2108. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2109. local_irq_restore(flags);
  2110. if (cpsum == cpcount)
  2111. break;
  2112. buffer += cpnow;
  2113. }
  2114. } else {
  2115. TRACE(("copy_internal() count %d\n",cpcount));
  2116. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2117. }
  2118. }
  2119. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2120. {
  2121. unchar t;
  2122. gdth_inq_data inq;
  2123. gdth_rdcap_data rdc;
  2124. gdth_sense_data sd;
  2125. gdth_modep_data mpd;
  2126. t = scp->device->id;
  2127. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2128. scp->cmnd[0],t));
  2129. scp->result = DID_OK << 16;
  2130. scp->sense_buffer[0] = 0;
  2131. switch (scp->cmnd[0]) {
  2132. case TEST_UNIT_READY:
  2133. case VERIFY:
  2134. case START_STOP:
  2135. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2136. break;
  2137. case INQUIRY:
  2138. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2139. t,ha->hdr[t].devtype));
  2140. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2141. /* you can here set all disks to removable, if you want to do
  2142. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2143. inq.modif_rmb = 0x00;
  2144. if ((ha->hdr[t].devtype & 1) ||
  2145. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2146. inq.modif_rmb = 0x80;
  2147. inq.version = 2;
  2148. inq.resp_aenc = 2;
  2149. inq.add_length= 32;
  2150. strcpy(inq.vendor,ha->oem_name);
  2151. sprintf(inq.product,"Host Drive #%02d",t);
  2152. strcpy(inq.revision," ");
  2153. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2154. break;
  2155. case REQUEST_SENSE:
  2156. TRACE2(("Request sense hdrive %d\n",t));
  2157. sd.errorcode = 0x70;
  2158. sd.segno = 0x00;
  2159. sd.key = NO_SENSE;
  2160. sd.info = 0;
  2161. sd.add_length= 0;
  2162. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2163. break;
  2164. case MODE_SENSE:
  2165. TRACE2(("Mode sense hdrive %d\n",t));
  2166. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2167. mpd.hd.data_length = sizeof(gdth_modep_data);
  2168. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2169. mpd.hd.bd_length = sizeof(mpd.bd);
  2170. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2171. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2172. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2173. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2174. break;
  2175. case READ_CAPACITY:
  2176. TRACE2(("Read capacity hdrive %d\n",t));
  2177. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2178. rdc.last_block_no = 0xffffffff;
  2179. else
  2180. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2181. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2182. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2183. break;
  2184. case SERVICE_ACTION_IN:
  2185. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2186. (ha->cache_feat & GDT_64BIT)) {
  2187. gdth_rdcap16_data rdc16;
  2188. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2189. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2190. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2191. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2192. sizeof(gdth_rdcap16_data));
  2193. } else {
  2194. scp->result = DID_ABORT << 16;
  2195. }
  2196. break;
  2197. default:
  2198. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2199. break;
  2200. }
  2201. if (!scp->SCp.have_data_in)
  2202. scp->SCp.have_data_in++;
  2203. else
  2204. return 1;
  2205. return 0;
  2206. }
  2207. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2208. {
  2209. register gdth_cmd_str *cmdp;
  2210. struct scatterlist *sl;
  2211. ulong32 cnt, blockcnt;
  2212. ulong64 no, blockno;
  2213. dma_addr_t phys_addr;
  2214. int i, cmd_index, read_write, sgcnt, mode64;
  2215. struct page *page;
  2216. ulong offset;
  2217. cmdp = ha->pccb;
  2218. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2219. scp->cmnd[0],scp->cmd_len,hdrive));
  2220. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2221. return 0;
  2222. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2223. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2224. not required, should not occur due to error return on
  2225. READ_CAPACITY_16 */
  2226. cmdp->Service = CACHESERVICE;
  2227. cmdp->RequestBuffer = scp;
  2228. /* search free command index */
  2229. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2230. TRACE(("GDT: No free command index found\n"));
  2231. return 0;
  2232. }
  2233. /* if it's the first command, set command semaphore */
  2234. if (ha->cmd_cnt == 0)
  2235. gdth_set_sema0(ha);
  2236. /* fill command */
  2237. read_write = 0;
  2238. if (scp->SCp.sent_command != -1)
  2239. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2240. else if (scp->cmnd[0] == RESERVE)
  2241. cmdp->OpCode = GDT_RESERVE_DRV;
  2242. else if (scp->cmnd[0] == RELEASE)
  2243. cmdp->OpCode = GDT_RELEASE_DRV;
  2244. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2245. if (scp->cmnd[4] & 1) /* prevent ? */
  2246. cmdp->OpCode = GDT_MOUNT;
  2247. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2248. cmdp->OpCode = GDT_UNMOUNT;
  2249. else
  2250. cmdp->OpCode = GDT_FLUSH;
  2251. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2252. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2253. ) {
  2254. read_write = 1;
  2255. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2256. (ha->cache_feat & GDT_WR_THROUGH)))
  2257. cmdp->OpCode = GDT_WRITE_THR;
  2258. else
  2259. cmdp->OpCode = GDT_WRITE;
  2260. } else {
  2261. read_write = 2;
  2262. cmdp->OpCode = GDT_READ;
  2263. }
  2264. cmdp->BoardNode = LOCALBOARD;
  2265. if (mode64) {
  2266. cmdp->u.cache64.DeviceNo = hdrive;
  2267. cmdp->u.cache64.BlockNo = 1;
  2268. cmdp->u.cache64.sg_canz = 0;
  2269. } else {
  2270. cmdp->u.cache.DeviceNo = hdrive;
  2271. cmdp->u.cache.BlockNo = 1;
  2272. cmdp->u.cache.sg_canz = 0;
  2273. }
  2274. if (read_write) {
  2275. if (scp->cmd_len == 16) {
  2276. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2277. blockno = be64_to_cpu(no);
  2278. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2279. blockcnt = be32_to_cpu(cnt);
  2280. } else if (scp->cmd_len == 10) {
  2281. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2282. blockno = be32_to_cpu(no);
  2283. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2284. blockcnt = be16_to_cpu(cnt);
  2285. } else {
  2286. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2287. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2288. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2289. }
  2290. if (mode64) {
  2291. cmdp->u.cache64.BlockNo = blockno;
  2292. cmdp->u.cache64.BlockCnt = blockcnt;
  2293. } else {
  2294. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2295. cmdp->u.cache.BlockCnt = blockcnt;
  2296. }
  2297. if (scp->use_sg) {
  2298. sl = (struct scatterlist *)scp->request_buffer;
  2299. sgcnt = scp->use_sg;
  2300. scp->SCp.Status = GDTH_MAP_SG;
  2301. scp->SCp.Message = (read_write == 1 ?
  2302. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2303. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2304. if (mode64) {
  2305. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2306. cmdp->u.cache64.sg_canz = sgcnt;
  2307. for (i=0; i<sgcnt; ++i,++sl) {
  2308. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2309. #ifdef GDTH_DMA_STATISTICS
  2310. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2311. ha->dma64_cnt++;
  2312. else
  2313. ha->dma32_cnt++;
  2314. #endif
  2315. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2316. }
  2317. } else {
  2318. cmdp->u.cache.DestAddr= 0xffffffff;
  2319. cmdp->u.cache.sg_canz = sgcnt;
  2320. for (i=0; i<sgcnt; ++i,++sl) {
  2321. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2322. #ifdef GDTH_DMA_STATISTICS
  2323. ha->dma32_cnt++;
  2324. #endif
  2325. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2326. }
  2327. }
  2328. #ifdef GDTH_STATISTICS
  2329. if (max_sg < (ulong32)sgcnt) {
  2330. max_sg = (ulong32)sgcnt;
  2331. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2332. }
  2333. #endif
  2334. } else if (scp->request_bufflen) {
  2335. scp->SCp.Status = GDTH_MAP_SINGLE;
  2336. scp->SCp.Message = (read_write == 1 ?
  2337. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2338. page = virt_to_page(scp->request_buffer);
  2339. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2340. phys_addr = pci_map_page(ha->pdev,page,offset,
  2341. scp->request_bufflen,scp->SCp.Message);
  2342. scp->SCp.dma_handle = phys_addr;
  2343. if (mode64) {
  2344. if (ha->cache_feat & SCATTER_GATHER) {
  2345. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2346. cmdp->u.cache64.sg_canz = 1;
  2347. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2348. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2349. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2350. } else {
  2351. cmdp->u.cache64.DestAddr = phys_addr;
  2352. cmdp->u.cache64.sg_canz= 0;
  2353. }
  2354. } else {
  2355. if (ha->cache_feat & SCATTER_GATHER) {
  2356. cmdp->u.cache.DestAddr = 0xffffffff;
  2357. cmdp->u.cache.sg_canz = 1;
  2358. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2359. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2360. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2361. } else {
  2362. cmdp->u.cache.DestAddr = phys_addr;
  2363. cmdp->u.cache.sg_canz= 0;
  2364. }
  2365. }
  2366. }
  2367. }
  2368. /* evaluate command size, check space */
  2369. if (mode64) {
  2370. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2371. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2372. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2373. cmdp->u.cache64.sg_lst[0].sg_len));
  2374. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2375. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2376. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2377. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2378. } else {
  2379. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2380. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2381. cmdp->u.cache.sg_lst[0].sg_ptr,
  2382. cmdp->u.cache.sg_lst[0].sg_len));
  2383. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2384. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2385. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2386. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2387. }
  2388. if (ha->cmd_len & 3)
  2389. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2390. if (ha->cmd_cnt > 0) {
  2391. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2392. ha->ic_all_size) {
  2393. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2394. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2395. return 0;
  2396. }
  2397. }
  2398. /* copy command */
  2399. gdth_copy_command(ha);
  2400. return cmd_index;
  2401. }
  2402. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2403. {
  2404. register gdth_cmd_str *cmdp;
  2405. struct scatterlist *sl;
  2406. ushort i;
  2407. dma_addr_t phys_addr, sense_paddr;
  2408. int cmd_index, sgcnt, mode64;
  2409. unchar t,l;
  2410. struct page *page;
  2411. ulong offset;
  2412. struct gdth_cmndinfo *cmndinfo;
  2413. t = scp->device->id;
  2414. l = scp->device->lun;
  2415. cmdp = ha->pccb;
  2416. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2417. scp->cmnd[0],b,t,l));
  2418. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2419. return 0;
  2420. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2421. cmdp->Service = SCSIRAWSERVICE;
  2422. cmdp->RequestBuffer = scp;
  2423. /* search free command index */
  2424. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2425. TRACE(("GDT: No free command index found\n"));
  2426. return 0;
  2427. }
  2428. /* if it's the first command, set command semaphore */
  2429. if (ha->cmd_cnt == 0)
  2430. gdth_set_sema0(ha);
  2431. cmndinfo = gdth_cmnd_priv(scp);
  2432. /* fill command */
  2433. if (scp->SCp.sent_command != -1) {
  2434. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2435. cmdp->BoardNode = LOCALBOARD;
  2436. if (mode64) {
  2437. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2438. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2439. cmdp->OpCode, cmdp->u.raw64.direction));
  2440. /* evaluate command size */
  2441. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2442. } else {
  2443. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2444. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2445. cmdp->OpCode, cmdp->u.raw.direction));
  2446. /* evaluate command size */
  2447. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2448. }
  2449. } else {
  2450. page = virt_to_page(scp->sense_buffer);
  2451. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2452. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2453. 16,PCI_DMA_FROMDEVICE);
  2454. cmndinfo->sense_paddr = sense_paddr;
  2455. cmdp->OpCode = GDT_WRITE; /* always */
  2456. cmdp->BoardNode = LOCALBOARD;
  2457. if (mode64) {
  2458. cmdp->u.raw64.reserved = 0;
  2459. cmdp->u.raw64.mdisc_time = 0;
  2460. cmdp->u.raw64.mcon_time = 0;
  2461. cmdp->u.raw64.clen = scp->cmd_len;
  2462. cmdp->u.raw64.target = t;
  2463. cmdp->u.raw64.lun = l;
  2464. cmdp->u.raw64.bus = b;
  2465. cmdp->u.raw64.priority = 0;
  2466. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2467. cmdp->u.raw64.sense_len = 16;
  2468. cmdp->u.raw64.sense_data = sense_paddr;
  2469. cmdp->u.raw64.direction =
  2470. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2471. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2472. cmdp->u.raw64.sg_ranz = 0;
  2473. } else {
  2474. cmdp->u.raw.reserved = 0;
  2475. cmdp->u.raw.mdisc_time = 0;
  2476. cmdp->u.raw.mcon_time = 0;
  2477. cmdp->u.raw.clen = scp->cmd_len;
  2478. cmdp->u.raw.target = t;
  2479. cmdp->u.raw.lun = l;
  2480. cmdp->u.raw.bus = b;
  2481. cmdp->u.raw.priority = 0;
  2482. cmdp->u.raw.link_p = 0;
  2483. cmdp->u.raw.sdlen = scp->request_bufflen;
  2484. cmdp->u.raw.sense_len = 16;
  2485. cmdp->u.raw.sense_data = sense_paddr;
  2486. cmdp->u.raw.direction =
  2487. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2488. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2489. cmdp->u.raw.sg_ranz = 0;
  2490. }
  2491. if (scp->use_sg) {
  2492. sl = (struct scatterlist *)scp->request_buffer;
  2493. sgcnt = scp->use_sg;
  2494. scp->SCp.Status = GDTH_MAP_SG;
  2495. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2496. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2497. if (mode64) {
  2498. cmdp->u.raw64.sdata = (ulong64)-1;
  2499. cmdp->u.raw64.sg_ranz = sgcnt;
  2500. for (i=0; i<sgcnt; ++i,++sl) {
  2501. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2502. #ifdef GDTH_DMA_STATISTICS
  2503. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2504. ha->dma64_cnt++;
  2505. else
  2506. ha->dma32_cnt++;
  2507. #endif
  2508. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2509. }
  2510. } else {
  2511. cmdp->u.raw.sdata = 0xffffffff;
  2512. cmdp->u.raw.sg_ranz = sgcnt;
  2513. for (i=0; i<sgcnt; ++i,++sl) {
  2514. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2515. #ifdef GDTH_DMA_STATISTICS
  2516. ha->dma32_cnt++;
  2517. #endif
  2518. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2519. }
  2520. }
  2521. #ifdef GDTH_STATISTICS
  2522. if (max_sg < sgcnt) {
  2523. max_sg = sgcnt;
  2524. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2525. }
  2526. #endif
  2527. } else if (scp->request_bufflen) {
  2528. scp->SCp.Status = GDTH_MAP_SINGLE;
  2529. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2530. page = virt_to_page(scp->request_buffer);
  2531. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2532. phys_addr = pci_map_page(ha->pdev,page,offset,
  2533. scp->request_bufflen,scp->SCp.Message);
  2534. scp->SCp.dma_handle = phys_addr;
  2535. if (mode64) {
  2536. if (ha->raw_feat & SCATTER_GATHER) {
  2537. cmdp->u.raw64.sdata = (ulong64)-1;
  2538. cmdp->u.raw64.sg_ranz= 1;
  2539. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2540. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2541. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2542. } else {
  2543. cmdp->u.raw64.sdata = phys_addr;
  2544. cmdp->u.raw64.sg_ranz= 0;
  2545. }
  2546. } else {
  2547. if (ha->raw_feat & SCATTER_GATHER) {
  2548. cmdp->u.raw.sdata = 0xffffffff;
  2549. cmdp->u.raw.sg_ranz= 1;
  2550. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2551. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2552. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2553. } else {
  2554. cmdp->u.raw.sdata = phys_addr;
  2555. cmdp->u.raw.sg_ranz= 0;
  2556. }
  2557. }
  2558. }
  2559. if (mode64) {
  2560. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2561. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2562. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2563. cmdp->u.raw64.sg_lst[0].sg_len));
  2564. /* evaluate command size */
  2565. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2566. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2567. } else {
  2568. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2569. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2570. cmdp->u.raw.sg_lst[0].sg_ptr,
  2571. cmdp->u.raw.sg_lst[0].sg_len));
  2572. /* evaluate command size */
  2573. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2574. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2575. }
  2576. }
  2577. /* check space */
  2578. if (ha->cmd_len & 3)
  2579. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2580. if (ha->cmd_cnt > 0) {
  2581. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2582. ha->ic_all_size) {
  2583. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2584. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2585. return 0;
  2586. }
  2587. }
  2588. /* copy command */
  2589. gdth_copy_command(ha);
  2590. return cmd_index;
  2591. }
  2592. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2593. {
  2594. register gdth_cmd_str *cmdp;
  2595. int cmd_index;
  2596. cmdp= ha->pccb;
  2597. TRACE2(("gdth_special_cmd(): "));
  2598. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2599. return 0;
  2600. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2601. cmdp->RequestBuffer = scp;
  2602. /* search free command index */
  2603. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2604. TRACE(("GDT: No free command index found\n"));
  2605. return 0;
  2606. }
  2607. /* if it's the first command, set command semaphore */
  2608. if (ha->cmd_cnt == 0)
  2609. gdth_set_sema0(ha);
  2610. /* evaluate command size, check space */
  2611. if (cmdp->OpCode == GDT_IOCTL) {
  2612. TRACE2(("IOCTL\n"));
  2613. ha->cmd_len =
  2614. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2615. } else if (cmdp->Service == CACHESERVICE) {
  2616. TRACE2(("cache command %d\n",cmdp->OpCode));
  2617. if (ha->cache_feat & GDT_64BIT)
  2618. ha->cmd_len =
  2619. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2620. else
  2621. ha->cmd_len =
  2622. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2623. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2624. TRACE2(("raw command %d\n",cmdp->OpCode));
  2625. if (ha->raw_feat & GDT_64BIT)
  2626. ha->cmd_len =
  2627. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2628. else
  2629. ha->cmd_len =
  2630. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2631. }
  2632. if (ha->cmd_len & 3)
  2633. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2634. if (ha->cmd_cnt > 0) {
  2635. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2636. ha->ic_all_size) {
  2637. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2638. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2639. return 0;
  2640. }
  2641. }
  2642. /* copy command */
  2643. gdth_copy_command(ha);
  2644. return cmd_index;
  2645. }
  2646. /* Controller event handling functions */
  2647. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2648. ushort idx, gdth_evt_data *evt)
  2649. {
  2650. gdth_evt_str *e;
  2651. struct timeval tv;
  2652. /* no GDTH_LOCK_HA() ! */
  2653. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2654. if (source == 0) /* no source -> no event */
  2655. return NULL;
  2656. if (ebuffer[elastidx].event_source == source &&
  2657. ebuffer[elastidx].event_idx == idx &&
  2658. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2659. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2660. (char *)&evt->eu, evt->size)) ||
  2661. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2662. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2663. (char *)&evt->event_string)))) {
  2664. e = &ebuffer[elastidx];
  2665. do_gettimeofday(&tv);
  2666. e->last_stamp = tv.tv_sec;
  2667. ++e->same_count;
  2668. } else {
  2669. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2670. ++elastidx;
  2671. if (elastidx == MAX_EVENTS)
  2672. elastidx = 0;
  2673. if (elastidx == eoldidx) { /* reached mark ? */
  2674. ++eoldidx;
  2675. if (eoldidx == MAX_EVENTS)
  2676. eoldidx = 0;
  2677. }
  2678. }
  2679. e = &ebuffer[elastidx];
  2680. e->event_source = source;
  2681. e->event_idx = idx;
  2682. do_gettimeofday(&tv);
  2683. e->first_stamp = e->last_stamp = tv.tv_sec;
  2684. e->same_count = 1;
  2685. e->event_data = *evt;
  2686. e->application = 0;
  2687. }
  2688. return e;
  2689. }
  2690. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2691. {
  2692. gdth_evt_str *e;
  2693. int eindex;
  2694. ulong flags;
  2695. TRACE2(("gdth_read_event() handle %d\n", handle));
  2696. spin_lock_irqsave(&ha->smp_lock, flags);
  2697. if (handle == -1)
  2698. eindex = eoldidx;
  2699. else
  2700. eindex = handle;
  2701. estr->event_source = 0;
  2702. if (eindex >= MAX_EVENTS) {
  2703. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2704. return eindex;
  2705. }
  2706. e = &ebuffer[eindex];
  2707. if (e->event_source != 0) {
  2708. if (eindex != elastidx) {
  2709. if (++eindex == MAX_EVENTS)
  2710. eindex = 0;
  2711. } else {
  2712. eindex = -1;
  2713. }
  2714. memcpy(estr, e, sizeof(gdth_evt_str));
  2715. }
  2716. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2717. return eindex;
  2718. }
  2719. static void gdth_readapp_event(gdth_ha_str *ha,
  2720. unchar application, gdth_evt_str *estr)
  2721. {
  2722. gdth_evt_str *e;
  2723. int eindex;
  2724. ulong flags;
  2725. unchar found = FALSE;
  2726. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2727. spin_lock_irqsave(&ha->smp_lock, flags);
  2728. eindex = eoldidx;
  2729. for (;;) {
  2730. e = &ebuffer[eindex];
  2731. if (e->event_source == 0)
  2732. break;
  2733. if ((e->application & application) == 0) {
  2734. e->application |= application;
  2735. found = TRUE;
  2736. break;
  2737. }
  2738. if (eindex == elastidx)
  2739. break;
  2740. if (++eindex == MAX_EVENTS)
  2741. eindex = 0;
  2742. }
  2743. if (found)
  2744. memcpy(estr, e, sizeof(gdth_evt_str));
  2745. else
  2746. estr->event_source = 0;
  2747. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2748. }
  2749. static void gdth_clear_events(void)
  2750. {
  2751. TRACE(("gdth_clear_events()"));
  2752. eoldidx = elastidx = 0;
  2753. ebuffer[0].event_source = 0;
  2754. }
  2755. /* SCSI interface functions */
  2756. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha, int irq,
  2757. int gdth_from_wait, int* pIndex)
  2758. {
  2759. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2760. gdt6_dpram_str __iomem *dp6_ptr;
  2761. gdt2_dpram_str __iomem *dp2_ptr;
  2762. Scsi_Cmnd *scp;
  2763. int rval, i;
  2764. unchar IStatus;
  2765. ushort Service;
  2766. ulong flags = 0;
  2767. #ifdef INT_COAL
  2768. int coalesced = FALSE;
  2769. int next = FALSE;
  2770. gdth_coal_status *pcs = NULL;
  2771. int act_int_coal = 0;
  2772. #endif
  2773. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  2774. /* if polling and not from gdth_wait() -> return */
  2775. if (gdth_polling) {
  2776. if (!gdth_from_wait) {
  2777. return IRQ_HANDLED;
  2778. }
  2779. }
  2780. if (!gdth_polling)
  2781. spin_lock_irqsave(&ha->smp_lock, flags);
  2782. /* search controller */
  2783. if (0 == (IStatus = gdth_get_status(ha, irq))) {
  2784. /* spurious interrupt */
  2785. if (!gdth_polling)
  2786. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2787. return IRQ_HANDLED;
  2788. }
  2789. #ifdef GDTH_STATISTICS
  2790. ++act_ints;
  2791. #endif
  2792. #ifdef INT_COAL
  2793. /* See if the fw is returning coalesced status */
  2794. if (IStatus == COALINDEX) {
  2795. /* Coalesced status. Setup the initial status
  2796. buffer pointer and flags */
  2797. pcs = ha->coal_stat;
  2798. coalesced = TRUE;
  2799. next = TRUE;
  2800. }
  2801. do {
  2802. if (coalesced) {
  2803. /* For coalesced requests all status
  2804. information is found in the status buffer */
  2805. IStatus = (unchar)(pcs->status & 0xff);
  2806. }
  2807. #endif
  2808. if (ha->type == GDT_EISA) {
  2809. if (IStatus & 0x80) { /* error flag */
  2810. IStatus &= ~0x80;
  2811. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2812. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2813. } else /* no error */
  2814. ha->status = S_OK;
  2815. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2816. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2817. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2818. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2819. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2820. } else if (ha->type == GDT_ISA) {
  2821. dp2_ptr = ha->brd;
  2822. if (IStatus & 0x80) { /* error flag */
  2823. IStatus &= ~0x80;
  2824. ha->status = readw(&dp2_ptr->u.ic.Status);
  2825. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2826. } else /* no error */
  2827. ha->status = S_OK;
  2828. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2829. ha->service = readw(&dp2_ptr->u.ic.Service);
  2830. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2831. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2832. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2833. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2834. } else if (ha->type == GDT_PCI) {
  2835. dp6_ptr = ha->brd;
  2836. if (IStatus & 0x80) { /* error flag */
  2837. IStatus &= ~0x80;
  2838. ha->status = readw(&dp6_ptr->u.ic.Status);
  2839. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2840. } else /* no error */
  2841. ha->status = S_OK;
  2842. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2843. ha->service = readw(&dp6_ptr->u.ic.Service);
  2844. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2845. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2846. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2847. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2848. } else if (ha->type == GDT_PCINEW) {
  2849. if (IStatus & 0x80) { /* error flag */
  2850. IStatus &= ~0x80;
  2851. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2852. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2853. } else
  2854. ha->status = S_OK;
  2855. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2856. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2857. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2858. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2859. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2860. } else if (ha->type == GDT_PCIMPR) {
  2861. dp6m_ptr = ha->brd;
  2862. if (IStatus & 0x80) { /* error flag */
  2863. IStatus &= ~0x80;
  2864. #ifdef INT_COAL
  2865. if (coalesced)
  2866. ha->status = pcs->ext_status & 0xffff;
  2867. else
  2868. #endif
  2869. ha->status = readw(&dp6m_ptr->i960r.status);
  2870. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2871. } else /* no error */
  2872. ha->status = S_OK;
  2873. #ifdef INT_COAL
  2874. /* get information */
  2875. if (coalesced) {
  2876. ha->info = pcs->info0;
  2877. ha->info2 = pcs->info1;
  2878. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2879. } else
  2880. #endif
  2881. {
  2882. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2883. ha->service = readw(&dp6m_ptr->i960r.service);
  2884. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2885. }
  2886. /* event string */
  2887. if (IStatus == ASYNCINDEX) {
  2888. if (ha->service != SCREENSERVICE &&
  2889. (ha->fw_vers & 0xff) >= 0x1a) {
  2890. ha->dvr.severity = readb
  2891. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2892. for (i = 0; i < 256; ++i) {
  2893. ha->dvr.event_string[i] = readb
  2894. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2895. if (ha->dvr.event_string[i] == 0)
  2896. break;
  2897. }
  2898. }
  2899. }
  2900. #ifdef INT_COAL
  2901. /* Make sure that non coalesced interrupts get cleared
  2902. before being handled by gdth_async_event/gdth_sync_event */
  2903. if (!coalesced)
  2904. #endif
  2905. {
  2906. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2907. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2908. }
  2909. } else {
  2910. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2911. if (!gdth_polling)
  2912. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2913. return IRQ_HANDLED;
  2914. }
  2915. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2916. IStatus,ha->status,ha->info));
  2917. if (gdth_from_wait) {
  2918. *pIndex = (int)IStatus;
  2919. }
  2920. if (IStatus == ASYNCINDEX) {
  2921. TRACE2(("gdth_interrupt() async. event\n"));
  2922. gdth_async_event(ha);
  2923. if (!gdth_polling)
  2924. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2925. gdth_next(ha);
  2926. return IRQ_HANDLED;
  2927. }
  2928. if (IStatus == SPEZINDEX) {
  2929. TRACE2(("Service unknown or not initialized !\n"));
  2930. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2931. ha->dvr.eu.driver.ionode = ha->hanum;
  2932. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2933. if (!gdth_polling)
  2934. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2935. return IRQ_HANDLED;
  2936. }
  2937. scp = ha->cmd_tab[IStatus-2].cmnd;
  2938. Service = ha->cmd_tab[IStatus-2].service;
  2939. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2940. if (scp == UNUSED_CMND) {
  2941. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2942. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2943. ha->dvr.eu.driver.ionode = ha->hanum;
  2944. ha->dvr.eu.driver.index = IStatus;
  2945. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2946. if (!gdth_polling)
  2947. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2948. return IRQ_HANDLED;
  2949. }
  2950. if (scp == INTERNAL_CMND) {
  2951. TRACE(("gdth_interrupt() answer to internal command\n"));
  2952. if (!gdth_polling)
  2953. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2954. return IRQ_HANDLED;
  2955. }
  2956. TRACE(("gdth_interrupt() sync. status\n"));
  2957. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2958. if (!gdth_polling)
  2959. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2960. if (rval == 2) {
  2961. gdth_putq(ha, scp,scp->SCp.this_residual);
  2962. } else if (rval == 1) {
  2963. gdth_scsi_done(scp);
  2964. }
  2965. #ifdef INT_COAL
  2966. if (coalesced) {
  2967. /* go to the next status in the status buffer */
  2968. ++pcs;
  2969. #ifdef GDTH_STATISTICS
  2970. ++act_int_coal;
  2971. if (act_int_coal > max_int_coal) {
  2972. max_int_coal = act_int_coal;
  2973. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2974. }
  2975. #endif
  2976. /* see if there is another status */
  2977. if (pcs->status == 0)
  2978. /* Stop the coalesce loop */
  2979. next = FALSE;
  2980. }
  2981. } while (next);
  2982. /* coalescing only for new GDT_PCIMPR controllers available */
  2983. if (ha->type == GDT_PCIMPR && coalesced) {
  2984. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2985. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2986. }
  2987. #endif
  2988. gdth_next(ha);
  2989. return IRQ_HANDLED;
  2990. }
  2991. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2992. {
  2993. gdth_ha_str *ha = (gdth_ha_str *)dev_id;
  2994. return __gdth_interrupt(ha, irq, false, NULL);
  2995. }
  2996. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2997. Scsi_Cmnd *scp)
  2998. {
  2999. gdth_msg_str *msg;
  3000. gdth_cmd_str *cmdp;
  3001. unchar b, t;
  3002. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  3003. cmdp = ha->pccb;
  3004. TRACE(("gdth_sync_event() serv %d status %d\n",
  3005. service,ha->status));
  3006. if (service == SCREENSERVICE) {
  3007. msg = ha->pmsg;
  3008. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3009. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3010. if (msg->msg_len > MSGLEN+1)
  3011. msg->msg_len = MSGLEN+1;
  3012. if (msg->msg_len)
  3013. if (!(msg->msg_answer && msg->msg_ext)) {
  3014. msg->msg_text[msg->msg_len] = '\0';
  3015. printk("%s",msg->msg_text);
  3016. }
  3017. if (msg->msg_ext && !msg->msg_answer) {
  3018. while (gdth_test_busy(ha))
  3019. gdth_delay(0);
  3020. cmdp->Service = SCREENSERVICE;
  3021. cmdp->RequestBuffer = SCREEN_CMND;
  3022. gdth_get_cmd_index(ha);
  3023. gdth_set_sema0(ha);
  3024. cmdp->OpCode = GDT_READ;
  3025. cmdp->BoardNode = LOCALBOARD;
  3026. cmdp->u.screen.reserved = 0;
  3027. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3028. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3029. ha->cmd_offs_dpmem = 0;
  3030. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3031. + sizeof(ulong64);
  3032. ha->cmd_cnt = 0;
  3033. gdth_copy_command(ha);
  3034. gdth_release_event(ha);
  3035. return 0;
  3036. }
  3037. if (msg->msg_answer && msg->msg_alen) {
  3038. /* default answers (getchar() not possible) */
  3039. if (msg->msg_alen == 1) {
  3040. msg->msg_alen = 0;
  3041. msg->msg_len = 1;
  3042. msg->msg_text[0] = 0;
  3043. } else {
  3044. msg->msg_alen -= 2;
  3045. msg->msg_len = 2;
  3046. msg->msg_text[0] = 1;
  3047. msg->msg_text[1] = 0;
  3048. }
  3049. msg->msg_ext = 0;
  3050. msg->msg_answer = 0;
  3051. while (gdth_test_busy(ha))
  3052. gdth_delay(0);
  3053. cmdp->Service = SCREENSERVICE;
  3054. cmdp->RequestBuffer = SCREEN_CMND;
  3055. gdth_get_cmd_index(ha);
  3056. gdth_set_sema0(ha);
  3057. cmdp->OpCode = GDT_WRITE;
  3058. cmdp->BoardNode = LOCALBOARD;
  3059. cmdp->u.screen.reserved = 0;
  3060. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3061. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3062. ha->cmd_offs_dpmem = 0;
  3063. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3064. + sizeof(ulong64);
  3065. ha->cmd_cnt = 0;
  3066. gdth_copy_command(ha);
  3067. gdth_release_event(ha);
  3068. return 0;
  3069. }
  3070. printk("\n");
  3071. } else {
  3072. b = scp->device->channel;
  3073. t = scp->device->id;
  3074. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3075. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3076. }
  3077. /* cache or raw service */
  3078. if (ha->status == S_BSY) {
  3079. TRACE2(("Controller busy -> retry !\n"));
  3080. if (scp->SCp.sent_command == GDT_MOUNT)
  3081. scp->SCp.sent_command = GDT_CLUST_INFO;
  3082. /* retry */
  3083. return 2;
  3084. }
  3085. if (scp->SCp.Status == GDTH_MAP_SG)
  3086. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3087. scp->use_sg,scp->SCp.Message);
  3088. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3089. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3090. scp->request_bufflen,scp->SCp.Message);
  3091. if (cmndinfo->sense_paddr)
  3092. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  3093. PCI_DMA_FROMDEVICE);
  3094. if (ha->status == S_OK) {
  3095. scp->SCp.Status = S_OK;
  3096. scp->SCp.Message = ha->info;
  3097. if (scp->SCp.sent_command != -1) {
  3098. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3099. scp->SCp.sent_command));
  3100. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3101. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3102. ha->hdr[t].cluster_type = (unchar)ha->info;
  3103. if (!(ha->hdr[t].cluster_type &
  3104. CLUSTER_MOUNTED)) {
  3105. /* NOT MOUNTED -> MOUNT */
  3106. scp->SCp.sent_command = GDT_MOUNT;
  3107. if (ha->hdr[t].cluster_type &
  3108. CLUSTER_RESERVED) {
  3109. /* cluster drive RESERVED (on the other node) */
  3110. scp->SCp.phase = -2; /* reservation conflict */
  3111. }
  3112. } else {
  3113. scp->SCp.sent_command = -1;
  3114. }
  3115. } else {
  3116. if (scp->SCp.sent_command == GDT_MOUNT) {
  3117. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3118. ha->hdr[t].media_changed = TRUE;
  3119. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3120. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3121. ha->hdr[t].media_changed = TRUE;
  3122. }
  3123. scp->SCp.sent_command = -1;
  3124. }
  3125. /* retry */
  3126. scp->SCp.this_residual = HIGH_PRI;
  3127. return 2;
  3128. } else {
  3129. /* RESERVE/RELEASE ? */
  3130. if (scp->cmnd[0] == RESERVE) {
  3131. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3132. } else if (scp->cmnd[0] == RELEASE) {
  3133. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3134. }
  3135. scp->result = DID_OK << 16;
  3136. scp->sense_buffer[0] = 0;
  3137. }
  3138. } else {
  3139. scp->SCp.Status = ha->status;
  3140. scp->SCp.Message = ha->info;
  3141. if (scp->SCp.sent_command != -1) {
  3142. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3143. scp->SCp.sent_command, ha->status));
  3144. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3145. scp->SCp.sent_command == GDT_SCAN_END) {
  3146. scp->SCp.sent_command = -1;
  3147. /* retry */
  3148. scp->SCp.this_residual = HIGH_PRI;
  3149. return 2;
  3150. }
  3151. memset((char*)scp->sense_buffer,0,16);
  3152. scp->sense_buffer[0] = 0x70;
  3153. scp->sense_buffer[2] = NOT_READY;
  3154. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3155. } else if (service == CACHESERVICE) {
  3156. if (ha->status == S_CACHE_UNKNOWN &&
  3157. (ha->hdr[t].cluster_type &
  3158. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3159. /* bus reset -> force GDT_CLUST_INFO */
  3160. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3161. }
  3162. memset((char*)scp->sense_buffer,0,16);
  3163. if (ha->status == (ushort)S_CACHE_RESERV) {
  3164. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3165. } else {
  3166. scp->sense_buffer[0] = 0x70;
  3167. scp->sense_buffer[2] = NOT_READY;
  3168. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3169. }
  3170. if (!cmndinfo->internal_command) {
  3171. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3172. ha->dvr.eu.sync.ionode = ha->hanum;
  3173. ha->dvr.eu.sync.service = service;
  3174. ha->dvr.eu.sync.status = ha->status;
  3175. ha->dvr.eu.sync.info = ha->info;
  3176. ha->dvr.eu.sync.hostdrive = t;
  3177. if (ha->status >= 0x8000)
  3178. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3179. else
  3180. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3181. }
  3182. } else {
  3183. /* sense buffer filled from controller firmware (DMA) */
  3184. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3185. scp->result = DID_BAD_TARGET << 16;
  3186. } else {
  3187. scp->result = (DID_OK << 16) | ha->info;
  3188. }
  3189. }
  3190. }
  3191. if (!scp->SCp.have_data_in)
  3192. scp->SCp.have_data_in++;
  3193. else
  3194. return 1;
  3195. }
  3196. return 0;
  3197. }
  3198. static char *async_cache_tab[] = {
  3199. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3200. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3201. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3202. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3203. /* 2*/ "\005\000\002\006\004"
  3204. "GDT HA %u, Host Drive %lu not ready",
  3205. /* 3*/ "\005\000\002\006\004"
  3206. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3207. /* 4*/ "\005\000\002\006\004"
  3208. "GDT HA %u, mirror update on Host Drive %lu failed",
  3209. /* 5*/ "\005\000\002\006\004"
  3210. "GDT HA %u, Mirror Drive %lu failed",
  3211. /* 6*/ "\005\000\002\006\004"
  3212. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3213. /* 7*/ "\005\000\002\006\004"
  3214. "GDT HA %u, Host Drive %lu write protected",
  3215. /* 8*/ "\005\000\002\006\004"
  3216. "GDT HA %u, media changed in Host Drive %lu",
  3217. /* 9*/ "\005\000\002\006\004"
  3218. "GDT HA %u, Host Drive %lu is offline",
  3219. /*10*/ "\005\000\002\006\004"
  3220. "GDT HA %u, media change of Mirror Drive %lu",
  3221. /*11*/ "\005\000\002\006\004"
  3222. "GDT HA %u, Mirror Drive %lu is write protected",
  3223. /*12*/ "\005\000\002\006\004"
  3224. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3225. /*13*/ "\007\000\002\006\002\010\002"
  3226. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3227. /*14*/ "\005\000\002\006\002"
  3228. "GDT HA %u, Array Drive %u: FAIL state entered",
  3229. /*15*/ "\005\000\002\006\002"
  3230. "GDT HA %u, Array Drive %u: error",
  3231. /*16*/ "\007\000\002\006\002\010\002"
  3232. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3233. /*17*/ "\005\000\002\006\002"
  3234. "GDT HA %u, Array Drive %u: parity build failed",
  3235. /*18*/ "\005\000\002\006\002"
  3236. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3237. /*19*/ "\005\000\002\010\002"
  3238. "GDT HA %u, Test of Hot Fix %u failed",
  3239. /*20*/ "\005\000\002\006\002"
  3240. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3241. /*21*/ "\005\000\002\006\002"
  3242. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3243. /*22*/ "\007\000\002\006\002\010\002"
  3244. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3245. /*23*/ "\005\000\002\006\002"
  3246. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3247. /*24*/ "\005\000\002\010\002"
  3248. "GDT HA %u, mirror update on Cache Drive %u completed",
  3249. /*25*/ "\005\000\002\010\002"
  3250. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3251. /*26*/ "\005\000\002\006\002"
  3252. "GDT HA %u, Array Drive %u: drive rebuild started",
  3253. /*27*/ "\005\000\002\012\001"
  3254. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3255. /*28*/ "\005\000\002\012\001"
  3256. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3257. /*29*/ "\007\000\002\012\001\013\001"
  3258. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3259. /*30*/ "\007\000\002\012\001\013\001"
  3260. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3261. /*31*/ "\007\000\002\012\001\013\001"
  3262. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3263. /*32*/ "\007\000\002\012\001\013\001"
  3264. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3265. /*33*/ "\007\000\002\012\001\013\001"
  3266. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3267. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3268. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3269. /*35*/ "\007\000\002\012\001\013\001"
  3270. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3271. /*36*/ "\007\000\002\012\001\013\001"
  3272. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3273. /*37*/ "\007\000\002\012\001\006\004"
  3274. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3275. /*38*/ "\007\000\002\012\001\013\001"
  3276. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3277. /*39*/ "\007\000\002\012\001\013\001"
  3278. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3279. /*40*/ "\007\000\002\012\001\013\001"
  3280. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3281. /*41*/ "\007\000\002\012\001\013\001"
  3282. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3283. /*42*/ "\005\000\002\006\002"
  3284. "GDT HA %u, Array Drive %u: drive build started",
  3285. /*43*/ "\003\000\002"
  3286. "GDT HA %u, DRAM parity error detected",
  3287. /*44*/ "\005\000\002\006\002"
  3288. "GDT HA %u, Mirror Drive %u: update started",
  3289. /*45*/ "\007\000\002\006\002\010\002"
  3290. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3291. /*46*/ "\005\000\002\006\002"
  3292. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3293. /*47*/ "\005\000\002\006\002"
  3294. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3295. /*48*/ "\005\000\002\006\002"
  3296. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3297. /*49*/ "\005\000\002\006\002"
  3298. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3299. /*50*/ "\007\000\002\012\001\013\001"
  3300. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3301. /*51*/ "\005\000\002\006\002"
  3302. "GDT HA %u, Array Drive %u: expand started",
  3303. /*52*/ "\005\000\002\006\002"
  3304. "GDT HA %u, Array Drive %u: expand finished successfully",
  3305. /*53*/ "\005\000\002\006\002"
  3306. "GDT HA %u, Array Drive %u: expand failed",
  3307. /*54*/ "\003\000\002"
  3308. "GDT HA %u, CPU temperature critical",
  3309. /*55*/ "\003\000\002"
  3310. "GDT HA %u, CPU temperature OK",
  3311. /*56*/ "\005\000\002\006\004"
  3312. "GDT HA %u, Host drive %lu created",
  3313. /*57*/ "\005\000\002\006\002"
  3314. "GDT HA %u, Array Drive %u: expand restarted",
  3315. /*58*/ "\005\000\002\006\002"
  3316. "GDT HA %u, Array Drive %u: expand stopped",
  3317. /*59*/ "\005\000\002\010\002"
  3318. "GDT HA %u, Mirror Drive %u: drive build quited",
  3319. /*60*/ "\005\000\002\006\002"
  3320. "GDT HA %u, Array Drive %u: parity build quited",
  3321. /*61*/ "\005\000\002\006\002"
  3322. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3323. /*62*/ "\005\000\002\006\002"
  3324. "GDT HA %u, Array Drive %u: parity verify started",
  3325. /*63*/ "\005\000\002\006\002"
  3326. "GDT HA %u, Array Drive %u: parity verify done",
  3327. /*64*/ "\005\000\002\006\002"
  3328. "GDT HA %u, Array Drive %u: parity verify failed",
  3329. /*65*/ "\005\000\002\006\002"
  3330. "GDT HA %u, Array Drive %u: parity error detected",
  3331. /*66*/ "\005\000\002\006\002"
  3332. "GDT HA %u, Array Drive %u: parity verify quited",
  3333. /*67*/ "\005\000\002\006\002"
  3334. "GDT HA %u, Host Drive %u reserved",
  3335. /*68*/ "\005\000\002\006\002"
  3336. "GDT HA %u, Host Drive %u mounted and released",
  3337. /*69*/ "\005\000\002\006\002"
  3338. "GDT HA %u, Host Drive %u released",
  3339. /*70*/ "\003\000\002"
  3340. "GDT HA %u, DRAM error detected and corrected with ECC",
  3341. /*71*/ "\003\000\002"
  3342. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3343. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3344. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3345. /*73*/ "\005\000\002\006\002"
  3346. "GDT HA %u, Host drive %u resetted locally",
  3347. /*74*/ "\005\000\002\006\002"
  3348. "GDT HA %u, Host drive %u resetted remotely",
  3349. /*75*/ "\003\000\002"
  3350. "GDT HA %u, async. status 75 unknown",
  3351. };
  3352. static int gdth_async_event(gdth_ha_str *ha)
  3353. {
  3354. gdth_cmd_str *cmdp;
  3355. int cmd_index;
  3356. cmdp= ha->pccb;
  3357. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3358. ha->hanum, ha->service));
  3359. if (ha->service == SCREENSERVICE) {
  3360. if (ha->status == MSG_REQUEST) {
  3361. while (gdth_test_busy(ha))
  3362. gdth_delay(0);
  3363. cmdp->Service = SCREENSERVICE;
  3364. cmdp->RequestBuffer = SCREEN_CMND;
  3365. cmd_index = gdth_get_cmd_index(ha);
  3366. gdth_set_sema0(ha);
  3367. cmdp->OpCode = GDT_READ;
  3368. cmdp->BoardNode = LOCALBOARD;
  3369. cmdp->u.screen.reserved = 0;
  3370. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3371. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3372. ha->cmd_offs_dpmem = 0;
  3373. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3374. + sizeof(ulong64);
  3375. ha->cmd_cnt = 0;
  3376. gdth_copy_command(ha);
  3377. if (ha->type == GDT_EISA)
  3378. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3379. else if (ha->type == GDT_ISA)
  3380. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3381. else
  3382. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3383. (ushort)((ha->brd_phys>>3)&0x1f));
  3384. gdth_release_event(ha);
  3385. }
  3386. } else {
  3387. if (ha->type == GDT_PCIMPR &&
  3388. (ha->fw_vers & 0xff) >= 0x1a) {
  3389. ha->dvr.size = 0;
  3390. ha->dvr.eu.async.ionode = ha->hanum;
  3391. ha->dvr.eu.async.status = ha->status;
  3392. /* severity and event_string already set! */
  3393. } else {
  3394. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3395. ha->dvr.eu.async.ionode = ha->hanum;
  3396. ha->dvr.eu.async.service = ha->service;
  3397. ha->dvr.eu.async.status = ha->status;
  3398. ha->dvr.eu.async.info = ha->info;
  3399. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3400. }
  3401. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3402. gdth_log_event( &ha->dvr, NULL );
  3403. /* new host drive from expand? */
  3404. if (ha->service == CACHESERVICE && ha->status == 56) {
  3405. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3406. (ushort)ha->info));
  3407. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3408. }
  3409. }
  3410. return 1;
  3411. }
  3412. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3413. {
  3414. gdth_stackframe stack;
  3415. char *f = NULL;
  3416. int i,j;
  3417. TRACE2(("gdth_log_event()\n"));
  3418. if (dvr->size == 0) {
  3419. if (buffer == NULL) {
  3420. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3421. } else {
  3422. sprintf(buffer,"Adapter %d: %s\n",
  3423. dvr->eu.async.ionode,dvr->event_string);
  3424. }
  3425. } else if (dvr->eu.async.service == CACHESERVICE &&
  3426. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3427. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3428. dvr->eu.async.status));
  3429. f = async_cache_tab[dvr->eu.async.status];
  3430. /* i: parameter to push, j: stack element to fill */
  3431. for (j=0,i=1; i < f[0]; i+=2) {
  3432. switch (f[i+1]) {
  3433. case 4:
  3434. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3435. break;
  3436. case 2:
  3437. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3438. break;
  3439. case 1:
  3440. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3441. break;
  3442. default:
  3443. break;
  3444. }
  3445. }
  3446. if (buffer == NULL) {
  3447. printk(&f[(int)f[0]],stack);
  3448. printk("\n");
  3449. } else {
  3450. sprintf(buffer,&f[(int)f[0]],stack);
  3451. }
  3452. } else {
  3453. if (buffer == NULL) {
  3454. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3455. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3456. } else {
  3457. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3458. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3459. }
  3460. }
  3461. }
  3462. #ifdef GDTH_STATISTICS
  3463. static void gdth_timeout(ulong data)
  3464. {
  3465. ulong32 i;
  3466. Scsi_Cmnd *nscp;
  3467. gdth_ha_str *ha;
  3468. ulong flags;
  3469. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3470. spin_lock_irqsave(&ha->smp_lock, flags);
  3471. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3472. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3473. ++act_stats;
  3474. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3475. ++act_rq;
  3476. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3477. act_ints, act_ios, act_stats, act_rq));
  3478. act_ints = act_ios = 0;
  3479. gdth_timer.expires = jiffies + 30 * HZ;
  3480. add_timer(&gdth_timer);
  3481. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3482. }
  3483. #endif
  3484. static void __init internal_setup(char *str,int *ints)
  3485. {
  3486. int i, argc;
  3487. char *cur_str, *argv;
  3488. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3489. str ? str:"NULL", ints ? ints[0]:0));
  3490. /* read irq[] from ints[] */
  3491. if (ints) {
  3492. argc = ints[0];
  3493. if (argc > 0) {
  3494. if (argc > MAXHA)
  3495. argc = MAXHA;
  3496. for (i = 0; i < argc; ++i)
  3497. irq[i] = ints[i+1];
  3498. }
  3499. }
  3500. /* analyse string */
  3501. argv = str;
  3502. while (argv && (cur_str = strchr(argv, ':'))) {
  3503. int val = 0, c = *++cur_str;
  3504. if (c == 'n' || c == 'N')
  3505. val = 0;
  3506. else if (c == 'y' || c == 'Y')
  3507. val = 1;
  3508. else
  3509. val = (int)simple_strtoul(cur_str, NULL, 0);
  3510. if (!strncmp(argv, "disable:", 8))
  3511. disable = val;
  3512. else if (!strncmp(argv, "reserve_mode:", 13))
  3513. reserve_mode = val;
  3514. else if (!strncmp(argv, "reverse_scan:", 13))
  3515. reverse_scan = val;
  3516. else if (!strncmp(argv, "hdr_channel:", 12))
  3517. hdr_channel = val;
  3518. else if (!strncmp(argv, "max_ids:", 8))
  3519. max_ids = val;
  3520. else if (!strncmp(argv, "rescan:", 7))
  3521. rescan = val;
  3522. else if (!strncmp(argv, "shared_access:", 14))
  3523. shared_access = val;
  3524. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3525. probe_eisa_isa = val;
  3526. else if (!strncmp(argv, "reserve_list:", 13)) {
  3527. reserve_list[0] = val;
  3528. for (i = 1; i < MAX_RES_ARGS; i++) {
  3529. cur_str = strchr(cur_str, ',');
  3530. if (!cur_str)
  3531. break;
  3532. if (!isdigit((int)*++cur_str)) {
  3533. --cur_str;
  3534. break;
  3535. }
  3536. reserve_list[i] =
  3537. (int)simple_strtoul(cur_str, NULL, 0);
  3538. }
  3539. if (!cur_str)
  3540. break;
  3541. argv = ++cur_str;
  3542. continue;
  3543. }
  3544. if ((argv = strchr(argv, ',')))
  3545. ++argv;
  3546. }
  3547. }
  3548. int __init option_setup(char *str)
  3549. {
  3550. int ints[MAXHA];
  3551. char *cur = str;
  3552. int i = 1;
  3553. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3554. while (cur && isdigit(*cur) && i <= MAXHA) {
  3555. ints[i++] = simple_strtoul(cur, NULL, 0);
  3556. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3557. }
  3558. ints[0] = i - 1;
  3559. internal_setup(cur, ints);
  3560. return 1;
  3561. }
  3562. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3563. {
  3564. TRACE2(("gdth_ctr_name()\n"));
  3565. if (ha->type == GDT_EISA) {
  3566. switch (ha->stype) {
  3567. case GDT3_ID:
  3568. return("GDT3000/3020");
  3569. case GDT3A_ID:
  3570. return("GDT3000A/3020A/3050A");
  3571. case GDT3B_ID:
  3572. return("GDT3000B/3010A");
  3573. }
  3574. } else if (ha->type == GDT_ISA) {
  3575. return("GDT2000/2020");
  3576. } else if (ha->type == GDT_PCI) {
  3577. switch (ha->pdev->device) {
  3578. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3579. return("GDT6000/6020/6050");
  3580. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3581. return("GDT6000B/6010");
  3582. }
  3583. }
  3584. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3585. return("");
  3586. }
  3587. static const char *gdth_info(struct Scsi_Host *shp)
  3588. {
  3589. gdth_ha_str *ha = shost_priv(shp);
  3590. TRACE2(("gdth_info()\n"));
  3591. return ((const char *)ha->binfo.type_string);
  3592. }
  3593. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3594. {
  3595. gdth_ha_str *ha = shost_priv(scp->device->host);
  3596. int i;
  3597. ulong flags;
  3598. Scsi_Cmnd *cmnd;
  3599. unchar b;
  3600. TRACE2(("gdth_eh_bus_reset()\n"));
  3601. b = scp->device->channel;
  3602. /* clear command tab */
  3603. spin_lock_irqsave(&ha->smp_lock, flags);
  3604. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3605. cmnd = ha->cmd_tab[i].cmnd;
  3606. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3607. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3608. }
  3609. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3610. if (b == ha->virt_bus) {
  3611. /* host drives */
  3612. for (i = 0; i < MAX_HDRIVES; ++i) {
  3613. if (ha->hdr[i].present) {
  3614. spin_lock_irqsave(&ha->smp_lock, flags);
  3615. gdth_polling = TRUE;
  3616. while (gdth_test_busy(ha))
  3617. gdth_delay(0);
  3618. if (gdth_internal_cmd(ha, CACHESERVICE,
  3619. GDT_CLUST_RESET, i, 0, 0))
  3620. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3621. gdth_polling = FALSE;
  3622. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3623. }
  3624. }
  3625. } else {
  3626. /* raw devices */
  3627. spin_lock_irqsave(&ha->smp_lock, flags);
  3628. for (i = 0; i < MAXID; ++i)
  3629. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3630. gdth_polling = TRUE;
  3631. while (gdth_test_busy(ha))
  3632. gdth_delay(0);
  3633. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3634. BUS_L2P(ha,b), 0, 0);
  3635. gdth_polling = FALSE;
  3636. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3637. }
  3638. return SUCCESS;
  3639. }
  3640. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3641. {
  3642. unchar b, t;
  3643. gdth_ha_str *ha = shost_priv(sdev->host);
  3644. struct scsi_device *sd;
  3645. unsigned capacity;
  3646. sd = sdev;
  3647. capacity = cap;
  3648. b = sd->channel;
  3649. t = sd->id;
  3650. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3651. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3652. /* raw device or host drive without mapping information */
  3653. TRACE2(("Evaluate mapping\n"));
  3654. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3655. } else {
  3656. ip[0] = ha->hdr[t].heads;
  3657. ip[1] = ha->hdr[t].secs;
  3658. ip[2] = capacity / ip[0] / ip[1];
  3659. }
  3660. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3661. ip[0],ip[1],ip[2]));
  3662. return 0;
  3663. }
  3664. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3665. void (*done)(struct scsi_cmnd *))
  3666. {
  3667. gdth_ha_str *ha = shost_priv(scp->device->host);
  3668. struct gdth_cmndinfo *cmndinfo;
  3669. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3670. cmndinfo = gdth_get_cmndinfo(ha);
  3671. BUG_ON(!cmndinfo);
  3672. scp->scsi_done = done;
  3673. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3674. scp->SCp.this_residual = DEFAULT_PRI;
  3675. return __gdth_queuecommand(ha, scp, cmndinfo);
  3676. }
  3677. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3678. struct gdth_cmndinfo *cmndinfo)
  3679. {
  3680. scp->host_scribble = (unsigned char *)cmndinfo;
  3681. scp->SCp.have_data_in = 1;
  3682. scp->SCp.phase = -1;
  3683. scp->SCp.sent_command = -1;
  3684. scp->SCp.Status = GDTH_MAP_NONE;
  3685. #ifdef GDTH_STATISTICS
  3686. ++act_ios;
  3687. #endif
  3688. gdth_putq(ha, scp, scp->SCp.this_residual);
  3689. gdth_next(ha);
  3690. return 0;
  3691. }
  3692. static int gdth_open(struct inode *inode, struct file *filep)
  3693. {
  3694. gdth_ha_str *ha;
  3695. list_for_each_entry(ha, &gdth_instances, list) {
  3696. if (!ha->sdev)
  3697. ha->sdev = scsi_get_host_dev(ha->shost);
  3698. }
  3699. TRACE(("gdth_open()\n"));
  3700. return 0;
  3701. }
  3702. static int gdth_close(struct inode *inode, struct file *filep)
  3703. {
  3704. TRACE(("gdth_close()\n"));
  3705. return 0;
  3706. }
  3707. static int ioc_event(void __user *arg)
  3708. {
  3709. gdth_ioctl_event evt;
  3710. gdth_ha_str *ha;
  3711. ulong flags;
  3712. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3713. return -EFAULT;
  3714. ha = gdth_find_ha(evt.ionode);
  3715. if (!ha)
  3716. return -EFAULT;
  3717. if (evt.erase == 0xff) {
  3718. if (evt.event.event_source == ES_TEST)
  3719. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3720. else if (evt.event.event_source == ES_DRIVER)
  3721. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3722. else if (evt.event.event_source == ES_SYNC)
  3723. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3724. else
  3725. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3726. spin_lock_irqsave(&ha->smp_lock, flags);
  3727. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3728. &evt.event.event_data);
  3729. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3730. } else if (evt.erase == 0xfe) {
  3731. gdth_clear_events();
  3732. } else if (evt.erase == 0) {
  3733. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3734. } else {
  3735. gdth_readapp_event(ha, evt.erase, &evt.event);
  3736. }
  3737. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3738. return -EFAULT;
  3739. return 0;
  3740. }
  3741. static int ioc_lockdrv(void __user *arg)
  3742. {
  3743. gdth_ioctl_lockdrv ldrv;
  3744. unchar i, j;
  3745. ulong flags;
  3746. gdth_ha_str *ha;
  3747. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3748. return -EFAULT;
  3749. ha = gdth_find_ha(ldrv.ionode);
  3750. if (!ha)
  3751. return -EFAULT;
  3752. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3753. j = ldrv.drives[i];
  3754. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3755. continue;
  3756. if (ldrv.lock) {
  3757. spin_lock_irqsave(&ha->smp_lock, flags);
  3758. ha->hdr[j].lock = 1;
  3759. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3760. gdth_wait_completion(ha, ha->bus_cnt, j);
  3761. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3762. } else {
  3763. spin_lock_irqsave(&ha->smp_lock, flags);
  3764. ha->hdr[j].lock = 0;
  3765. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3766. gdth_start_timeout(ha, ha->bus_cnt, j);
  3767. gdth_next(ha);
  3768. }
  3769. }
  3770. return 0;
  3771. }
  3772. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3773. {
  3774. gdth_ioctl_reset res;
  3775. gdth_cmd_str cmd;
  3776. gdth_ha_str *ha;
  3777. int rval;
  3778. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3779. res.number >= MAX_HDRIVES)
  3780. return -EFAULT;
  3781. ha = gdth_find_ha(res.ionode);
  3782. if (!ha)
  3783. return -EFAULT;
  3784. if (!ha->hdr[res.number].present)
  3785. return 0;
  3786. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3787. cmd.Service = CACHESERVICE;
  3788. cmd.OpCode = GDT_CLUST_RESET;
  3789. if (ha->cache_feat & GDT_64BIT)
  3790. cmd.u.cache64.DeviceNo = res.number;
  3791. else
  3792. cmd.u.cache.DeviceNo = res.number;
  3793. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3794. if (rval < 0)
  3795. return rval;
  3796. res.status = rval;
  3797. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3798. return -EFAULT;
  3799. return 0;
  3800. }
  3801. static int ioc_general(void __user *arg, char *cmnd)
  3802. {
  3803. gdth_ioctl_general gen;
  3804. char *buf = NULL;
  3805. ulong64 paddr;
  3806. gdth_ha_str *ha;
  3807. int rval;
  3808. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3809. return -EFAULT;
  3810. ha = gdth_find_ha(gen.ionode);
  3811. if (!ha)
  3812. return -EFAULT;
  3813. if (gen.data_len + gen.sense_len != 0) {
  3814. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3815. FALSE, &paddr)))
  3816. return -EFAULT;
  3817. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3818. gen.data_len + gen.sense_len)) {
  3819. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3820. return -EFAULT;
  3821. }
  3822. if (gen.command.OpCode == GDT_IOCTL) {
  3823. gen.command.u.ioctl.p_param = paddr;
  3824. } else if (gen.command.Service == CACHESERVICE) {
  3825. if (ha->cache_feat & GDT_64BIT) {
  3826. /* copy elements from 32-bit IOCTL structure */
  3827. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3828. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3829. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3830. /* addresses */
  3831. if (ha->cache_feat & SCATTER_GATHER) {
  3832. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3833. gen.command.u.cache64.sg_canz = 1;
  3834. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3835. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3836. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3837. } else {
  3838. gen.command.u.cache64.DestAddr = paddr;
  3839. gen.command.u.cache64.sg_canz = 0;
  3840. }
  3841. } else {
  3842. if (ha->cache_feat & SCATTER_GATHER) {
  3843. gen.command.u.cache.DestAddr = 0xffffffff;
  3844. gen.command.u.cache.sg_canz = 1;
  3845. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3846. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3847. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3848. } else {
  3849. gen.command.u.cache.DestAddr = paddr;
  3850. gen.command.u.cache.sg_canz = 0;
  3851. }
  3852. }
  3853. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3854. if (ha->raw_feat & GDT_64BIT) {
  3855. /* copy elements from 32-bit IOCTL structure */
  3856. char cmd[16];
  3857. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3858. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3859. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3860. gen.command.u.raw64.target = gen.command.u.raw.target;
  3861. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3862. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3863. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3864. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3865. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3866. /* addresses */
  3867. if (ha->raw_feat & SCATTER_GATHER) {
  3868. gen.command.u.raw64.sdata = (ulong64)-1;
  3869. gen.command.u.raw64.sg_ranz = 1;
  3870. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3871. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3872. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3873. } else {
  3874. gen.command.u.raw64.sdata = paddr;
  3875. gen.command.u.raw64.sg_ranz = 0;
  3876. }
  3877. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3878. } else {
  3879. if (ha->raw_feat & SCATTER_GATHER) {
  3880. gen.command.u.raw.sdata = 0xffffffff;
  3881. gen.command.u.raw.sg_ranz = 1;
  3882. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3883. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3884. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3885. } else {
  3886. gen.command.u.raw.sdata = paddr;
  3887. gen.command.u.raw.sg_ranz = 0;
  3888. }
  3889. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3890. }
  3891. } else {
  3892. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3893. return -EFAULT;
  3894. }
  3895. }
  3896. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3897. if (rval < 0)
  3898. return rval;
  3899. gen.status = rval;
  3900. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3901. gen.data_len + gen.sense_len)) {
  3902. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3903. return -EFAULT;
  3904. }
  3905. if (copy_to_user(arg, &gen,
  3906. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3907. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3908. return -EFAULT;
  3909. }
  3910. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3911. return 0;
  3912. }
  3913. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3914. {
  3915. gdth_ioctl_rescan *rsc;
  3916. gdth_cmd_str *cmd;
  3917. gdth_ha_str *ha;
  3918. unchar i;
  3919. int rc = -ENOMEM;
  3920. u32 cluster_type = 0;
  3921. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3922. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3923. if (!rsc || !cmd)
  3924. goto free_fail;
  3925. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3926. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3927. rc = -EFAULT;
  3928. goto free_fail;
  3929. }
  3930. memset(cmd, 0, sizeof(gdth_cmd_str));
  3931. for (i = 0; i < MAX_HDRIVES; ++i) {
  3932. if (!ha->hdr[i].present) {
  3933. rsc->hdr_list[i].bus = 0xff;
  3934. continue;
  3935. }
  3936. rsc->hdr_list[i].bus = ha->virt_bus;
  3937. rsc->hdr_list[i].target = i;
  3938. rsc->hdr_list[i].lun = 0;
  3939. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3940. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3941. cmd->Service = CACHESERVICE;
  3942. cmd->OpCode = GDT_CLUST_INFO;
  3943. if (ha->cache_feat & GDT_64BIT)
  3944. cmd->u.cache64.DeviceNo = i;
  3945. else
  3946. cmd->u.cache.DeviceNo = i;
  3947. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3948. rsc->hdr_list[i].cluster_type = cluster_type;
  3949. }
  3950. }
  3951. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3952. rc = -EFAULT;
  3953. else
  3954. rc = 0;
  3955. free_fail:
  3956. kfree(rsc);
  3957. kfree(cmd);
  3958. return rc;
  3959. }
  3960. static int ioc_rescan(void __user *arg, char *cmnd)
  3961. {
  3962. gdth_ioctl_rescan *rsc;
  3963. gdth_cmd_str *cmd;
  3964. ushort i, status, hdr_cnt;
  3965. ulong32 info;
  3966. int cyls, hds, secs;
  3967. int rc = -ENOMEM;
  3968. ulong flags;
  3969. gdth_ha_str *ha;
  3970. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3971. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3972. if (!cmd || !rsc)
  3973. goto free_fail;
  3974. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3975. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3976. rc = -EFAULT;
  3977. goto free_fail;
  3978. }
  3979. memset(cmd, 0, sizeof(gdth_cmd_str));
  3980. if (rsc->flag == 0) {
  3981. /* old method: re-init. cache service */
  3982. cmd->Service = CACHESERVICE;
  3983. if (ha->cache_feat & GDT_64BIT) {
  3984. cmd->OpCode = GDT_X_INIT_HOST;
  3985. cmd->u.cache64.DeviceNo = LINUX_OS;
  3986. } else {
  3987. cmd->OpCode = GDT_INIT;
  3988. cmd->u.cache.DeviceNo = LINUX_OS;
  3989. }
  3990. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3991. i = 0;
  3992. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  3993. } else {
  3994. i = rsc->hdr_no;
  3995. hdr_cnt = i + 1;
  3996. }
  3997. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3998. cmd->Service = CACHESERVICE;
  3999. cmd->OpCode = GDT_INFO;
  4000. if (ha->cache_feat & GDT_64BIT)
  4001. cmd->u.cache64.DeviceNo = i;
  4002. else
  4003. cmd->u.cache.DeviceNo = i;
  4004. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4005. spin_lock_irqsave(&ha->smp_lock, flags);
  4006. rsc->hdr_list[i].bus = ha->virt_bus;
  4007. rsc->hdr_list[i].target = i;
  4008. rsc->hdr_list[i].lun = 0;
  4009. if (status != S_OK) {
  4010. ha->hdr[i].present = FALSE;
  4011. } else {
  4012. ha->hdr[i].present = TRUE;
  4013. ha->hdr[i].size = info;
  4014. /* evaluate mapping */
  4015. ha->hdr[i].size &= ~SECS32;
  4016. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4017. ha->hdr[i].heads = hds;
  4018. ha->hdr[i].secs = secs;
  4019. /* round size */
  4020. ha->hdr[i].size = cyls * hds * secs;
  4021. }
  4022. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4023. if (status != S_OK)
  4024. continue;
  4025. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4026. /* but we need ha->info2, not yet stored in scp->SCp */
  4027. /* devtype, cluster info, R/W attribs */
  4028. cmd->Service = CACHESERVICE;
  4029. cmd->OpCode = GDT_DEVTYPE;
  4030. if (ha->cache_feat & GDT_64BIT)
  4031. cmd->u.cache64.DeviceNo = i;
  4032. else
  4033. cmd->u.cache.DeviceNo = i;
  4034. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4035. spin_lock_irqsave(&ha->smp_lock, flags);
  4036. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4037. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4038. cmd->Service = CACHESERVICE;
  4039. cmd->OpCode = GDT_CLUST_INFO;
  4040. if (ha->cache_feat & GDT_64BIT)
  4041. cmd->u.cache64.DeviceNo = i;
  4042. else
  4043. cmd->u.cache.DeviceNo = i;
  4044. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4045. spin_lock_irqsave(&ha->smp_lock, flags);
  4046. ha->hdr[i].cluster_type =
  4047. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4048. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4049. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4050. cmd->Service = CACHESERVICE;
  4051. cmd->OpCode = GDT_RW_ATTRIBS;
  4052. if (ha->cache_feat & GDT_64BIT)
  4053. cmd->u.cache64.DeviceNo = i;
  4054. else
  4055. cmd->u.cache.DeviceNo = i;
  4056. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4057. spin_lock_irqsave(&ha->smp_lock, flags);
  4058. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4059. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4060. }
  4061. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4062. rc = -EFAULT;
  4063. else
  4064. rc = 0;
  4065. free_fail:
  4066. kfree(rsc);
  4067. kfree(cmd);
  4068. return rc;
  4069. }
  4070. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4071. unsigned int cmd, unsigned long arg)
  4072. {
  4073. gdth_ha_str *ha;
  4074. Scsi_Cmnd *scp;
  4075. ulong flags;
  4076. char cmnd[MAX_COMMAND_SIZE];
  4077. void __user *argp = (void __user *)arg;
  4078. memset(cmnd, 0xff, 12);
  4079. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4080. switch (cmd) {
  4081. case GDTIOCTL_CTRCNT:
  4082. {
  4083. int cnt = gdth_ctr_count;
  4084. if (put_user(cnt, (int __user *)argp))
  4085. return -EFAULT;
  4086. break;
  4087. }
  4088. case GDTIOCTL_DRVERS:
  4089. {
  4090. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4091. if (put_user(ver, (int __user *)argp))
  4092. return -EFAULT;
  4093. break;
  4094. }
  4095. case GDTIOCTL_OSVERS:
  4096. {
  4097. gdth_ioctl_osvers osv;
  4098. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4099. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4100. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4101. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4102. return -EFAULT;
  4103. break;
  4104. }
  4105. case GDTIOCTL_CTRTYPE:
  4106. {
  4107. gdth_ioctl_ctrtype ctrt;
  4108. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4109. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4110. return -EFAULT;
  4111. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4112. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4113. } else {
  4114. if (ha->type != GDT_PCIMPR) {
  4115. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4116. } else {
  4117. ctrt.type =
  4118. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4119. if (ha->stype >= 0x300)
  4120. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4121. else
  4122. ctrt.ext_type = 0x6000 | ha->stype;
  4123. }
  4124. ctrt.device_id = ha->pdev->device;
  4125. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4126. }
  4127. ctrt.info = ha->brd_phys;
  4128. ctrt.oem_id = ha->oem_id;
  4129. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4130. return -EFAULT;
  4131. break;
  4132. }
  4133. case GDTIOCTL_GENERAL:
  4134. return ioc_general(argp, cmnd);
  4135. case GDTIOCTL_EVENT:
  4136. return ioc_event(argp);
  4137. case GDTIOCTL_LOCKDRV:
  4138. return ioc_lockdrv(argp);
  4139. case GDTIOCTL_LOCKCHN:
  4140. {
  4141. gdth_ioctl_lockchn lchn;
  4142. unchar i, j;
  4143. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4144. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4145. return -EFAULT;
  4146. i = lchn.channel;
  4147. if (i < ha->bus_cnt) {
  4148. if (lchn.lock) {
  4149. spin_lock_irqsave(&ha->smp_lock, flags);
  4150. ha->raw[i].lock = 1;
  4151. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4152. for (j = 0; j < ha->tid_cnt; ++j) {
  4153. gdth_wait_completion(ha, i, j);
  4154. gdth_stop_timeout(ha, i, j);
  4155. }
  4156. } else {
  4157. spin_lock_irqsave(&ha->smp_lock, flags);
  4158. ha->raw[i].lock = 0;
  4159. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4160. for (j = 0; j < ha->tid_cnt; ++j) {
  4161. gdth_start_timeout(ha, i, j);
  4162. gdth_next(ha);
  4163. }
  4164. }
  4165. }
  4166. break;
  4167. }
  4168. case GDTIOCTL_RESCAN:
  4169. return ioc_rescan(argp, cmnd);
  4170. case GDTIOCTL_HDRLIST:
  4171. return ioc_hdrlist(argp, cmnd);
  4172. case GDTIOCTL_RESET_BUS:
  4173. {
  4174. gdth_ioctl_reset res;
  4175. int rval;
  4176. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4177. (NULL == (ha = gdth_find_ha(res.ionode))))
  4178. return -EFAULT;
  4179. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4180. if (!scp)
  4181. return -ENOMEM;
  4182. scp->device = ha->sdev;
  4183. scp->cmd_len = 12;
  4184. scp->use_sg = 0;
  4185. scp->device->channel = res.number;
  4186. rval = gdth_eh_bus_reset(scp);
  4187. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4188. kfree(scp);
  4189. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4190. return -EFAULT;
  4191. break;
  4192. }
  4193. case GDTIOCTL_RESET_DRV:
  4194. return ioc_resetdrv(argp, cmnd);
  4195. default:
  4196. break;
  4197. }
  4198. return 0;
  4199. }
  4200. /* flush routine */
  4201. static void gdth_flush(gdth_ha_str *ha)
  4202. {
  4203. int i;
  4204. gdth_cmd_str gdtcmd;
  4205. char cmnd[MAX_COMMAND_SIZE];
  4206. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4207. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4208. for (i = 0; i < MAX_HDRIVES; ++i) {
  4209. if (ha->hdr[i].present) {
  4210. gdtcmd.BoardNode = LOCALBOARD;
  4211. gdtcmd.Service = CACHESERVICE;
  4212. gdtcmd.OpCode = GDT_FLUSH;
  4213. if (ha->cache_feat & GDT_64BIT) {
  4214. gdtcmd.u.cache64.DeviceNo = i;
  4215. gdtcmd.u.cache64.BlockNo = 1;
  4216. gdtcmd.u.cache64.sg_canz = 0;
  4217. } else {
  4218. gdtcmd.u.cache.DeviceNo = i;
  4219. gdtcmd.u.cache.BlockNo = 1;
  4220. gdtcmd.u.cache.sg_canz = 0;
  4221. }
  4222. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4223. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4224. }
  4225. }
  4226. }
  4227. /* shutdown routine */
  4228. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4229. {
  4230. gdth_ha_str *ha;
  4231. #ifndef __alpha__
  4232. gdth_cmd_str gdtcmd;
  4233. char cmnd[MAX_COMMAND_SIZE];
  4234. #endif
  4235. if (notifier_disabled)
  4236. return NOTIFY_OK;
  4237. TRACE2(("gdth_halt() event %d\n",(int)event));
  4238. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4239. return NOTIFY_DONE;
  4240. notifier_disabled = 1;
  4241. printk("GDT-HA: Flushing all host drives .. ");
  4242. list_for_each_entry(ha, &gdth_instances, list) {
  4243. gdth_flush(ha);
  4244. #ifndef __alpha__
  4245. /* controller reset */
  4246. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4247. gdtcmd.BoardNode = LOCALBOARD;
  4248. gdtcmd.Service = CACHESERVICE;
  4249. gdtcmd.OpCode = GDT_RESET;
  4250. TRACE2(("gdth_halt(): reset controller %d\n", ha->hanum));
  4251. gdth_execute(ha->shost, &gdtcmd, cmnd, 10, NULL);
  4252. #endif
  4253. }
  4254. printk("Done.\n");
  4255. #ifdef GDTH_STATISTICS
  4256. del_timer(&gdth_timer);
  4257. #endif
  4258. return NOTIFY_OK;
  4259. }
  4260. /* configure lun */
  4261. static int gdth_slave_configure(struct scsi_device *sdev)
  4262. {
  4263. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4264. sdev->skip_ms_page_3f = 1;
  4265. sdev->skip_ms_page_8 = 1;
  4266. return 0;
  4267. }
  4268. static struct scsi_host_template gdth_template = {
  4269. .name = "GDT SCSI Disk Array Controller",
  4270. .info = gdth_info,
  4271. .queuecommand = gdth_queuecommand,
  4272. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4273. .slave_configure = gdth_slave_configure,
  4274. .bios_param = gdth_bios_param,
  4275. .proc_info = gdth_proc_info,
  4276. .proc_name = "gdth",
  4277. .can_queue = GDTH_MAXCMDS,
  4278. .this_id = -1,
  4279. .sg_tablesize = GDTH_MAXSG,
  4280. .cmd_per_lun = GDTH_MAXC_P_L,
  4281. .unchecked_isa_dma = 1,
  4282. .use_clustering = ENABLE_CLUSTERING,
  4283. };
  4284. #ifdef CONFIG_ISA
  4285. static int gdth_isa_probe_one(ulong32 isa_bios)
  4286. {
  4287. struct Scsi_Host *shp;
  4288. gdth_ha_str *ha;
  4289. dma_addr_t scratch_dma_handle = 0;
  4290. int error, i;
  4291. if (!gdth_search_isa(isa_bios))
  4292. return -ENXIO;
  4293. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4294. if (!shp)
  4295. return -ENOMEM;
  4296. ha = shost_priv(shp);
  4297. error = -ENODEV;
  4298. if (!gdth_init_isa(isa_bios,ha))
  4299. goto out_host_put;
  4300. /* controller found and initialized */
  4301. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4302. isa_bios, ha->irq, ha->drq);
  4303. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4304. if (error) {
  4305. printk("GDT-ISA: Unable to allocate IRQ\n");
  4306. goto out_host_put;
  4307. }
  4308. error = request_dma(ha->drq, "gdth");
  4309. if (error) {
  4310. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4311. goto out_free_irq;
  4312. }
  4313. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4314. enable_dma(ha->drq);
  4315. shp->unchecked_isa_dma = 1;
  4316. shp->irq = ha->irq;
  4317. shp->dma_channel = ha->drq;
  4318. ha->hanum = gdth_ctr_count++;
  4319. ha->shost = shp;
  4320. ha->pccb = &ha->cmdext;
  4321. ha->ccb_phys = 0L;
  4322. ha->pdev = NULL;
  4323. error = -ENOMEM;
  4324. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4325. &scratch_dma_handle);
  4326. if (!ha->pscratch)
  4327. goto out_dec_counters;
  4328. ha->scratch_phys = scratch_dma_handle;
  4329. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4330. &scratch_dma_handle);
  4331. if (!ha->pmsg)
  4332. goto out_free_pscratch;
  4333. ha->msg_phys = scratch_dma_handle;
  4334. #ifdef INT_COAL
  4335. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4336. sizeof(gdth_coal_status) * MAXOFFSETS,
  4337. &scratch_dma_handle);
  4338. if (!ha->coal_stat)
  4339. goto out_free_pmsg;
  4340. ha->coal_stat_phys = scratch_dma_handle;
  4341. #endif
  4342. ha->scratch_busy = FALSE;
  4343. ha->req_first = NULL;
  4344. ha->tid_cnt = MAX_HDRIVES;
  4345. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4346. ha->tid_cnt = max_ids;
  4347. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4348. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4349. ha->scan_mode = rescan ? 0x10 : 0;
  4350. error = -ENODEV;
  4351. if (!gdth_search_drives(ha)) {
  4352. printk("GDT-ISA: Error during device scan\n");
  4353. goto out_free_coal_stat;
  4354. }
  4355. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4356. hdr_channel = ha->bus_cnt;
  4357. ha->virt_bus = hdr_channel;
  4358. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4359. shp->max_cmd_len = 16;
  4360. shp->max_id = ha->tid_cnt;
  4361. shp->max_lun = MAXLUN;
  4362. shp->max_channel = ha->bus_cnt;
  4363. spin_lock_init(&ha->smp_lock);
  4364. gdth_enable_int(ha);
  4365. error = scsi_add_host(shp, NULL);
  4366. if (error)
  4367. goto out_free_coal_stat;
  4368. list_add_tail(&ha->list, &gdth_instances);
  4369. return 0;
  4370. out_free_coal_stat:
  4371. #ifdef INT_COAL
  4372. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4373. ha->coal_stat, ha->coal_stat_phys);
  4374. out_free_pmsg:
  4375. #endif
  4376. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4377. ha->pmsg, ha->msg_phys);
  4378. out_free_pscratch:
  4379. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4380. ha->pscratch, ha->scratch_phys);
  4381. out_dec_counters:
  4382. gdth_ctr_count--;
  4383. out_free_irq:
  4384. free_irq(ha->irq, ha);
  4385. out_host_put:
  4386. scsi_host_put(shp);
  4387. return error;
  4388. }
  4389. #endif /* CONFIG_ISA */
  4390. #ifdef CONFIG_EISA
  4391. static int gdth_eisa_probe_one(ushort eisa_slot)
  4392. {
  4393. struct Scsi_Host *shp;
  4394. gdth_ha_str *ha;
  4395. dma_addr_t scratch_dma_handle = 0;
  4396. int error, i;
  4397. if (!gdth_search_eisa(eisa_slot))
  4398. return -ENXIO;
  4399. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4400. if (!shp)
  4401. return -ENOMEM;
  4402. ha = shost_priv(shp);
  4403. error = -ENODEV;
  4404. if (!gdth_init_eisa(eisa_slot,ha))
  4405. goto out_host_put;
  4406. /* controller found and initialized */
  4407. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4408. eisa_slot >> 12, ha->irq);
  4409. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4410. if (error) {
  4411. printk("GDT-EISA: Unable to allocate IRQ\n");
  4412. goto out_host_put;
  4413. }
  4414. shp->unchecked_isa_dma = 0;
  4415. shp->irq = ha->irq;
  4416. shp->dma_channel = 0xff;
  4417. ha->hanum = gdth_ctr_count++;
  4418. ha->shost = shp;
  4419. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4420. ha->pccb = &ha->cmdext;
  4421. ha->ccb_phys = 0L;
  4422. error = -ENOMEM;
  4423. ha->pdev = NULL;
  4424. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4425. &scratch_dma_handle);
  4426. if (!ha->pscratch)
  4427. goto out_free_irq;
  4428. ha->scratch_phys = scratch_dma_handle;
  4429. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4430. &scratch_dma_handle);
  4431. if (!ha->pmsg)
  4432. goto out_free_pscratch;
  4433. ha->msg_phys = scratch_dma_handle;
  4434. #ifdef INT_COAL
  4435. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4436. sizeof(gdth_coal_status) * MAXOFFSETS,
  4437. &scratch_dma_handle);
  4438. if (!ha->coal_stat)
  4439. goto out_free_pmsg;
  4440. ha->coal_stat_phys = scratch_dma_handle;
  4441. #endif
  4442. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4443. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4444. if (!ha->ccb_phys)
  4445. goto out_free_coal_stat;
  4446. ha->scratch_busy = FALSE;
  4447. ha->req_first = NULL;
  4448. ha->tid_cnt = MAX_HDRIVES;
  4449. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4450. ha->tid_cnt = max_ids;
  4451. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4452. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4453. ha->scan_mode = rescan ? 0x10 : 0;
  4454. if (!gdth_search_drives(ha)) {
  4455. printk("GDT-EISA: Error during device scan\n");
  4456. error = -ENODEV;
  4457. goto out_free_ccb_phys;
  4458. }
  4459. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4460. hdr_channel = ha->bus_cnt;
  4461. ha->virt_bus = hdr_channel;
  4462. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4463. shp->max_cmd_len = 16;
  4464. shp->max_id = ha->tid_cnt;
  4465. shp->max_lun = MAXLUN;
  4466. shp->max_channel = ha->bus_cnt;
  4467. spin_lock_init(&ha->smp_lock);
  4468. gdth_enable_int(ha);
  4469. error = scsi_add_host(shp, NULL);
  4470. if (error)
  4471. goto out_free_coal_stat;
  4472. list_add_tail(&ha->list, &gdth_instances);
  4473. return 0;
  4474. out_free_ccb_phys:
  4475. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4476. PCI_DMA_BIDIRECTIONAL);
  4477. out_free_coal_stat:
  4478. #ifdef INT_COAL
  4479. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4480. ha->coal_stat, ha->coal_stat_phys);
  4481. out_free_pmsg:
  4482. #endif
  4483. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4484. ha->pmsg, ha->msg_phys);
  4485. out_free_pscratch:
  4486. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4487. ha->pscratch, ha->scratch_phys);
  4488. out_free_irq:
  4489. free_irq(ha->irq, ha);
  4490. gdth_ctr_count--;
  4491. out_host_put:
  4492. scsi_host_put(shp);
  4493. return error;
  4494. }
  4495. #endif /* CONFIG_EISA */
  4496. #ifdef CONFIG_PCI
  4497. static int gdth_pci_probe_one(gdth_pci_str *pcistr, int ctr)
  4498. {
  4499. struct Scsi_Host *shp;
  4500. gdth_ha_str *ha;
  4501. dma_addr_t scratch_dma_handle = 0;
  4502. int error, i;
  4503. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4504. if (!shp)
  4505. return -ENOMEM;
  4506. ha = shost_priv(shp);
  4507. error = -ENODEV;
  4508. if (!gdth_init_pci(&pcistr[ctr],ha))
  4509. goto out_host_put;
  4510. /* controller found and initialized */
  4511. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4512. pcistr[ctr].pdev->bus->number,
  4513. PCI_SLOT(pcistr[ctr].pdev->devfn),
  4514. ha->irq);
  4515. error = request_irq(ha->irq, gdth_interrupt,
  4516. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4517. if (error) {
  4518. printk("GDT-PCI: Unable to allocate IRQ\n");
  4519. goto out_host_put;
  4520. }
  4521. shp->unchecked_isa_dma = 0;
  4522. shp->irq = ha->irq;
  4523. shp->dma_channel = 0xff;
  4524. ha->hanum = gdth_ctr_count++;
  4525. ha->shost = shp;
  4526. ha->pccb = &ha->cmdext;
  4527. ha->ccb_phys = 0L;
  4528. error = -ENOMEM;
  4529. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4530. &scratch_dma_handle);
  4531. if (!ha->pscratch)
  4532. goto out_free_irq;
  4533. ha->scratch_phys = scratch_dma_handle;
  4534. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4535. &scratch_dma_handle);
  4536. if (!ha->pmsg)
  4537. goto out_free_pscratch;
  4538. ha->msg_phys = scratch_dma_handle;
  4539. #ifdef INT_COAL
  4540. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4541. sizeof(gdth_coal_status) * MAXOFFSETS,
  4542. &scratch_dma_handle);
  4543. if (!ha->coal_stat)
  4544. goto out_free_pmsg;
  4545. ha->coal_stat_phys = scratch_dma_handle;
  4546. #endif
  4547. ha->scratch_busy = FALSE;
  4548. ha->req_first = NULL;
  4549. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4550. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4551. ha->tid_cnt = max_ids;
  4552. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4553. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4554. ha->scan_mode = rescan ? 0x10 : 0;
  4555. error = -ENODEV;
  4556. if (!gdth_search_drives(ha)) {
  4557. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4558. goto out_free_coal_stat;
  4559. }
  4560. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4561. hdr_channel = ha->bus_cnt;
  4562. ha->virt_bus = hdr_channel;
  4563. /* 64-bit DMA only supported from FW >= x.43 */
  4564. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4565. !ha->dma64_support) {
  4566. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4567. printk(KERN_WARNING "GDT-PCI %d: "
  4568. "Unable to set 32-bit DMA\n", ha->hanum);
  4569. goto out_free_coal_stat;
  4570. }
  4571. } else {
  4572. shp->max_cmd_len = 16;
  4573. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4574. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4575. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4576. printk(KERN_WARNING "GDT-PCI %d: "
  4577. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4578. goto out_free_coal_stat;
  4579. }
  4580. }
  4581. shp->max_id = ha->tid_cnt;
  4582. shp->max_lun = MAXLUN;
  4583. shp->max_channel = ha->bus_cnt;
  4584. spin_lock_init(&ha->smp_lock);
  4585. gdth_enable_int(ha);
  4586. error = scsi_add_host(shp, &pcistr[ctr].pdev->dev);
  4587. if (error)
  4588. goto out_free_coal_stat;
  4589. list_add_tail(&ha->list, &gdth_instances);
  4590. return 0;
  4591. out_free_coal_stat:
  4592. #ifdef INT_COAL
  4593. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4594. ha->coal_stat, ha->coal_stat_phys);
  4595. out_free_pmsg:
  4596. #endif
  4597. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4598. ha->pmsg, ha->msg_phys);
  4599. out_free_pscratch:
  4600. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4601. ha->pscratch, ha->scratch_phys);
  4602. out_free_irq:
  4603. free_irq(ha->irq, ha);
  4604. gdth_ctr_count--;
  4605. out_host_put:
  4606. scsi_host_put(shp);
  4607. return error;
  4608. }
  4609. #endif /* CONFIG_PCI */
  4610. static void gdth_remove_one(gdth_ha_str *ha)
  4611. {
  4612. struct Scsi_Host *shp = ha->shost;
  4613. TRACE2(("gdth_remove_one()\n"));
  4614. scsi_remove_host(shp);
  4615. if (ha->sdev) {
  4616. scsi_free_host_dev(ha->sdev);
  4617. ha->sdev = NULL;
  4618. }
  4619. gdth_flush(ha);
  4620. if (shp->irq)
  4621. free_irq(shp->irq,ha);
  4622. #ifdef CONFIG_ISA
  4623. if (shp->dma_channel != 0xff)
  4624. free_dma(shp->dma_channel);
  4625. #endif
  4626. #ifdef INT_COAL
  4627. if (ha->coal_stat)
  4628. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4629. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4630. #endif
  4631. if (ha->pscratch)
  4632. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4633. ha->pscratch, ha->scratch_phys);
  4634. if (ha->pmsg)
  4635. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4636. ha->pmsg, ha->msg_phys);
  4637. if (ha->ccb_phys)
  4638. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4639. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4640. scsi_host_put(shp);
  4641. }
  4642. static int __init gdth_init(void)
  4643. {
  4644. if (disable) {
  4645. printk("GDT-HA: Controller driver disabled from"
  4646. " command line !\n");
  4647. return 0;
  4648. }
  4649. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4650. GDTH_VERSION_STR);
  4651. /* initializations */
  4652. gdth_polling = TRUE;
  4653. gdth_clear_events();
  4654. /* As default we do not probe for EISA or ISA controllers */
  4655. if (probe_eisa_isa) {
  4656. /* scanning for controllers, at first: ISA controller */
  4657. #ifdef CONFIG_ISA
  4658. ulong32 isa_bios;
  4659. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4660. isa_bios += 0x8000UL)
  4661. gdth_isa_probe_one(isa_bios);
  4662. #endif
  4663. #ifdef CONFIG_EISA
  4664. {
  4665. ushort eisa_slot;
  4666. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4667. eisa_slot += 0x1000)
  4668. gdth_eisa_probe_one(eisa_slot);
  4669. }
  4670. #endif
  4671. }
  4672. #ifdef CONFIG_PCI
  4673. /* scanning for PCI controllers */
  4674. {
  4675. gdth_pci_str pcistr[MAXHA];
  4676. int cnt,ctr;
  4677. cnt = gdth_search_pci(pcistr);
  4678. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n", cnt);
  4679. gdth_sort_pci(pcistr,cnt);
  4680. for (ctr = 0; ctr < cnt; ++ctr)
  4681. gdth_pci_probe_one(pcistr, ctr);
  4682. }
  4683. #endif /* CONFIG_PCI */
  4684. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4685. #ifdef GDTH_STATISTICS
  4686. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4687. init_timer(&gdth_timer);
  4688. gdth_timer.expires = jiffies + HZ;
  4689. gdth_timer.data = 0L;
  4690. gdth_timer.function = gdth_timeout;
  4691. add_timer(&gdth_timer);
  4692. #endif
  4693. major = register_chrdev(0,"gdth", &gdth_fops);
  4694. notifier_disabled = 0;
  4695. register_reboot_notifier(&gdth_notifier);
  4696. gdth_polling = FALSE;
  4697. return 0;
  4698. }
  4699. static void __exit gdth_exit(void)
  4700. {
  4701. gdth_ha_str *ha;
  4702. list_for_each_entry(ha, &gdth_instances, list)
  4703. gdth_remove_one(ha);
  4704. #ifdef GDTH_STATISTICS
  4705. del_timer(&gdth_timer);
  4706. #endif
  4707. unregister_chrdev(major,"gdth");
  4708. unregister_reboot_notifier(&gdth_notifier);
  4709. }
  4710. module_init(gdth_init);
  4711. module_exit(gdth_exit);
  4712. #ifndef MODULE
  4713. __setup("gdth=", option_setup);
  4714. #endif