xhci-mem.c 70 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/usb.h>
  23. #include <linux/pci.h>
  24. #include <linux/slab.h>
  25. #include <linux/dmapool.h>
  26. #include "xhci.h"
  27. /*
  28. * Allocates a generic ring segment from the ring pool, sets the dma address,
  29. * initializes the segment to zero, and sets the private next pointer to NULL.
  30. *
  31. * Section 4.11.1.1:
  32. * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  33. */
  34. static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
  35. {
  36. struct xhci_segment *seg;
  37. dma_addr_t dma;
  38. seg = kzalloc(sizeof *seg, flags);
  39. if (!seg)
  40. return NULL;
  41. xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
  42. seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  43. if (!seg->trbs) {
  44. kfree(seg);
  45. return NULL;
  46. }
  47. xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
  48. seg->trbs, (unsigned long long)dma);
  49. memset(seg->trbs, 0, SEGMENT_SIZE);
  50. seg->dma = dma;
  51. seg->next = NULL;
  52. return seg;
  53. }
  54. static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  55. {
  56. if (!seg)
  57. return;
  58. if (seg->trbs) {
  59. xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
  60. seg->trbs, (unsigned long long)seg->dma);
  61. dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  62. seg->trbs = NULL;
  63. }
  64. xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
  65. kfree(seg);
  66. }
  67. /*
  68. * Make the prev segment point to the next segment.
  69. *
  70. * Change the last TRB in the prev segment to be a Link TRB which points to the
  71. * DMA address of the next segment. The caller needs to set any Link TRB
  72. * related flags, such as End TRB, Toggle Cycle, and no snoop.
  73. */
  74. static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  75. struct xhci_segment *next, bool link_trbs)
  76. {
  77. u32 val;
  78. if (!prev || !next)
  79. return;
  80. prev->next = next;
  81. if (link_trbs) {
  82. prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
  83. cpu_to_le64(next->dma);
  84. /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
  85. val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  86. val &= ~TRB_TYPE_BITMASK;
  87. val |= TRB_TYPE(TRB_LINK);
  88. /* Always set the chain bit with 0.95 hardware */
  89. if (xhci_link_trb_quirk(xhci))
  90. val |= TRB_CHAIN;
  91. prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
  92. }
  93. xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
  94. (unsigned long long)prev->dma,
  95. (unsigned long long)next->dma);
  96. }
  97. /* XXX: Do we need the hcd structure in all these functions? */
  98. void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
  99. {
  100. struct xhci_segment *seg;
  101. struct xhci_segment *first_seg;
  102. if (!ring || !ring->first_seg)
  103. return;
  104. first_seg = ring->first_seg;
  105. seg = first_seg->next;
  106. xhci_dbg(xhci, "Freeing ring at %p\n", ring);
  107. while (seg != first_seg) {
  108. struct xhci_segment *next = seg->next;
  109. xhci_segment_free(xhci, seg);
  110. seg = next;
  111. }
  112. xhci_segment_free(xhci, first_seg);
  113. ring->first_seg = NULL;
  114. kfree(ring);
  115. }
  116. static void xhci_initialize_ring_info(struct xhci_ring *ring)
  117. {
  118. /* The ring is empty, so the enqueue pointer == dequeue pointer */
  119. ring->enqueue = ring->first_seg->trbs;
  120. ring->enq_seg = ring->first_seg;
  121. ring->dequeue = ring->enqueue;
  122. ring->deq_seg = ring->first_seg;
  123. /* The ring is initialized to 0. The producer must write 1 to the cycle
  124. * bit to handover ownership of the TRB, so PCS = 1. The consumer must
  125. * compare CCS to the cycle bit to check ownership, so CCS = 1.
  126. */
  127. ring->cycle_state = 1;
  128. /* Not necessary for new rings, but needed for re-initialized rings */
  129. ring->enq_updates = 0;
  130. ring->deq_updates = 0;
  131. }
  132. /**
  133. * Create a new ring with zero or more segments.
  134. *
  135. * Link each segment together into a ring.
  136. * Set the end flag and the cycle toggle bit on the last segment.
  137. * See section 4.9.1 and figures 15 and 16.
  138. */
  139. static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
  140. unsigned int num_segs, bool link_trbs, gfp_t flags)
  141. {
  142. struct xhci_ring *ring;
  143. struct xhci_segment *prev;
  144. ring = kzalloc(sizeof *(ring), flags);
  145. xhci_dbg(xhci, "Allocating ring at %p\n", ring);
  146. if (!ring)
  147. return NULL;
  148. INIT_LIST_HEAD(&ring->td_list);
  149. if (num_segs == 0)
  150. return ring;
  151. ring->first_seg = xhci_segment_alloc(xhci, flags);
  152. if (!ring->first_seg)
  153. goto fail;
  154. num_segs--;
  155. prev = ring->first_seg;
  156. while (num_segs > 0) {
  157. struct xhci_segment *next;
  158. next = xhci_segment_alloc(xhci, flags);
  159. if (!next)
  160. goto fail;
  161. xhci_link_segments(xhci, prev, next, link_trbs);
  162. prev = next;
  163. num_segs--;
  164. }
  165. xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
  166. if (link_trbs) {
  167. /* See section 4.9.2.1 and 6.4.4.1 */
  168. prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
  169. cpu_to_le32(LINK_TOGGLE);
  170. xhci_dbg(xhci, "Wrote link toggle flag to"
  171. " segment %p (virtual), 0x%llx (DMA)\n",
  172. prev, (unsigned long long)prev->dma);
  173. }
  174. xhci_initialize_ring_info(ring);
  175. return ring;
  176. fail:
  177. xhci_ring_free(xhci, ring);
  178. return NULL;
  179. }
  180. void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
  181. struct xhci_virt_device *virt_dev,
  182. unsigned int ep_index)
  183. {
  184. int rings_cached;
  185. rings_cached = virt_dev->num_rings_cached;
  186. if (rings_cached < XHCI_MAX_RINGS_CACHED) {
  187. virt_dev->ring_cache[rings_cached] =
  188. virt_dev->eps[ep_index].ring;
  189. virt_dev->num_rings_cached++;
  190. xhci_dbg(xhci, "Cached old ring, "
  191. "%d ring%s cached\n",
  192. virt_dev->num_rings_cached,
  193. (virt_dev->num_rings_cached > 1) ? "s" : "");
  194. } else {
  195. xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
  196. xhci_dbg(xhci, "Ring cache full (%d rings), "
  197. "freeing ring\n",
  198. virt_dev->num_rings_cached);
  199. }
  200. virt_dev->eps[ep_index].ring = NULL;
  201. }
  202. /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
  203. * pointers to the beginning of the ring.
  204. */
  205. static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
  206. struct xhci_ring *ring)
  207. {
  208. struct xhci_segment *seg = ring->first_seg;
  209. do {
  210. memset(seg->trbs, 0,
  211. sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
  212. /* All endpoint rings have link TRBs */
  213. xhci_link_segments(xhci, seg, seg->next, 1);
  214. seg = seg->next;
  215. } while (seg != ring->first_seg);
  216. xhci_initialize_ring_info(ring);
  217. /* td list should be empty since all URBs have been cancelled,
  218. * but just in case...
  219. */
  220. INIT_LIST_HEAD(&ring->td_list);
  221. }
  222. #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
  223. static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
  224. int type, gfp_t flags)
  225. {
  226. struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
  227. if (!ctx)
  228. return NULL;
  229. BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
  230. ctx->type = type;
  231. ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
  232. if (type == XHCI_CTX_TYPE_INPUT)
  233. ctx->size += CTX_SIZE(xhci->hcc_params);
  234. ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
  235. memset(ctx->bytes, 0, ctx->size);
  236. return ctx;
  237. }
  238. static void xhci_free_container_ctx(struct xhci_hcd *xhci,
  239. struct xhci_container_ctx *ctx)
  240. {
  241. if (!ctx)
  242. return;
  243. dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
  244. kfree(ctx);
  245. }
  246. struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
  247. struct xhci_container_ctx *ctx)
  248. {
  249. BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
  250. return (struct xhci_input_control_ctx *)ctx->bytes;
  251. }
  252. struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
  253. struct xhci_container_ctx *ctx)
  254. {
  255. if (ctx->type == XHCI_CTX_TYPE_DEVICE)
  256. return (struct xhci_slot_ctx *)ctx->bytes;
  257. return (struct xhci_slot_ctx *)
  258. (ctx->bytes + CTX_SIZE(xhci->hcc_params));
  259. }
  260. struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
  261. struct xhci_container_ctx *ctx,
  262. unsigned int ep_index)
  263. {
  264. /* increment ep index by offset of start of ep ctx array */
  265. ep_index++;
  266. if (ctx->type == XHCI_CTX_TYPE_INPUT)
  267. ep_index++;
  268. return (struct xhci_ep_ctx *)
  269. (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
  270. }
  271. /***************** Streams structures manipulation *************************/
  272. static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
  273. unsigned int num_stream_ctxs,
  274. struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
  275. {
  276. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  277. if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
  278. pci_free_consistent(pdev,
  279. sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
  280. stream_ctx, dma);
  281. else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
  282. return dma_pool_free(xhci->small_streams_pool,
  283. stream_ctx, dma);
  284. else
  285. return dma_pool_free(xhci->medium_streams_pool,
  286. stream_ctx, dma);
  287. }
  288. /*
  289. * The stream context array for each endpoint with bulk streams enabled can
  290. * vary in size, based on:
  291. * - how many streams the endpoint supports,
  292. * - the maximum primary stream array size the host controller supports,
  293. * - and how many streams the device driver asks for.
  294. *
  295. * The stream context array must be a power of 2, and can be as small as
  296. * 64 bytes or as large as 1MB.
  297. */
  298. static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
  299. unsigned int num_stream_ctxs, dma_addr_t *dma,
  300. gfp_t mem_flags)
  301. {
  302. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  303. if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
  304. return pci_alloc_consistent(pdev,
  305. sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
  306. dma);
  307. else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
  308. return dma_pool_alloc(xhci->small_streams_pool,
  309. mem_flags, dma);
  310. else
  311. return dma_pool_alloc(xhci->medium_streams_pool,
  312. mem_flags, dma);
  313. }
  314. struct xhci_ring *xhci_dma_to_transfer_ring(
  315. struct xhci_virt_ep *ep,
  316. u64 address)
  317. {
  318. if (ep->ep_state & EP_HAS_STREAMS)
  319. return radix_tree_lookup(&ep->stream_info->trb_address_map,
  320. address >> SEGMENT_SHIFT);
  321. return ep->ring;
  322. }
  323. /* Only use this when you know stream_info is valid */
  324. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  325. static struct xhci_ring *dma_to_stream_ring(
  326. struct xhci_stream_info *stream_info,
  327. u64 address)
  328. {
  329. return radix_tree_lookup(&stream_info->trb_address_map,
  330. address >> SEGMENT_SHIFT);
  331. }
  332. #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
  333. struct xhci_ring *xhci_stream_id_to_ring(
  334. struct xhci_virt_device *dev,
  335. unsigned int ep_index,
  336. unsigned int stream_id)
  337. {
  338. struct xhci_virt_ep *ep = &dev->eps[ep_index];
  339. if (stream_id == 0)
  340. return ep->ring;
  341. if (!ep->stream_info)
  342. return NULL;
  343. if (stream_id > ep->stream_info->num_streams)
  344. return NULL;
  345. return ep->stream_info->stream_rings[stream_id];
  346. }
  347. #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
  348. static int xhci_test_radix_tree(struct xhci_hcd *xhci,
  349. unsigned int num_streams,
  350. struct xhci_stream_info *stream_info)
  351. {
  352. u32 cur_stream;
  353. struct xhci_ring *cur_ring;
  354. u64 addr;
  355. for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
  356. struct xhci_ring *mapped_ring;
  357. int trb_size = sizeof(union xhci_trb);
  358. cur_ring = stream_info->stream_rings[cur_stream];
  359. for (addr = cur_ring->first_seg->dma;
  360. addr < cur_ring->first_seg->dma + SEGMENT_SIZE;
  361. addr += trb_size) {
  362. mapped_ring = dma_to_stream_ring(stream_info, addr);
  363. if (cur_ring != mapped_ring) {
  364. xhci_warn(xhci, "WARN: DMA address 0x%08llx "
  365. "didn't map to stream ID %u; "
  366. "mapped to ring %p\n",
  367. (unsigned long long) addr,
  368. cur_stream,
  369. mapped_ring);
  370. return -EINVAL;
  371. }
  372. }
  373. /* One TRB after the end of the ring segment shouldn't return a
  374. * pointer to the current ring (although it may be a part of a
  375. * different ring).
  376. */
  377. mapped_ring = dma_to_stream_ring(stream_info, addr);
  378. if (mapped_ring != cur_ring) {
  379. /* One TRB before should also fail */
  380. addr = cur_ring->first_seg->dma - trb_size;
  381. mapped_ring = dma_to_stream_ring(stream_info, addr);
  382. }
  383. if (mapped_ring == cur_ring) {
  384. xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
  385. "mapped to valid stream ID %u; "
  386. "mapped ring = %p\n",
  387. (unsigned long long) addr,
  388. cur_stream,
  389. mapped_ring);
  390. return -EINVAL;
  391. }
  392. }
  393. return 0;
  394. }
  395. #endif /* CONFIG_USB_XHCI_HCD_DEBUGGING */
  396. /*
  397. * Change an endpoint's internal structure so it supports stream IDs. The
  398. * number of requested streams includes stream 0, which cannot be used by device
  399. * drivers.
  400. *
  401. * The number of stream contexts in the stream context array may be bigger than
  402. * the number of streams the driver wants to use. This is because the number of
  403. * stream context array entries must be a power of two.
  404. *
  405. * We need a radix tree for mapping physical addresses of TRBs to which stream
  406. * ID they belong to. We need to do this because the host controller won't tell
  407. * us which stream ring the TRB came from. We could store the stream ID in an
  408. * event data TRB, but that doesn't help us for the cancellation case, since the
  409. * endpoint may stop before it reaches that event data TRB.
  410. *
  411. * The radix tree maps the upper portion of the TRB DMA address to a ring
  412. * segment that has the same upper portion of DMA addresses. For example, say I
  413. * have segments of size 1KB, that are always 64-byte aligned. A segment may
  414. * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
  415. * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
  416. * pass the radix tree a key to get the right stream ID:
  417. *
  418. * 0x10c90fff >> 10 = 0x43243
  419. * 0x10c912c0 >> 10 = 0x43244
  420. * 0x10c91400 >> 10 = 0x43245
  421. *
  422. * Obviously, only those TRBs with DMA addresses that are within the segment
  423. * will make the radix tree return the stream ID for that ring.
  424. *
  425. * Caveats for the radix tree:
  426. *
  427. * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
  428. * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
  429. * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
  430. * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
  431. * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
  432. * extended systems (where the DMA address can be bigger than 32-bits),
  433. * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
  434. */
  435. struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
  436. unsigned int num_stream_ctxs,
  437. unsigned int num_streams, gfp_t mem_flags)
  438. {
  439. struct xhci_stream_info *stream_info;
  440. u32 cur_stream;
  441. struct xhci_ring *cur_ring;
  442. unsigned long key;
  443. u64 addr;
  444. int ret;
  445. xhci_dbg(xhci, "Allocating %u streams and %u "
  446. "stream context array entries.\n",
  447. num_streams, num_stream_ctxs);
  448. if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
  449. xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
  450. return NULL;
  451. }
  452. xhci->cmd_ring_reserved_trbs++;
  453. stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
  454. if (!stream_info)
  455. goto cleanup_trbs;
  456. stream_info->num_streams = num_streams;
  457. stream_info->num_stream_ctxs = num_stream_ctxs;
  458. /* Initialize the array of virtual pointers to stream rings. */
  459. stream_info->stream_rings = kzalloc(
  460. sizeof(struct xhci_ring *)*num_streams,
  461. mem_flags);
  462. if (!stream_info->stream_rings)
  463. goto cleanup_info;
  464. /* Initialize the array of DMA addresses for stream rings for the HW. */
  465. stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
  466. num_stream_ctxs, &stream_info->ctx_array_dma,
  467. mem_flags);
  468. if (!stream_info->stream_ctx_array)
  469. goto cleanup_ctx;
  470. memset(stream_info->stream_ctx_array, 0,
  471. sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
  472. /* Allocate everything needed to free the stream rings later */
  473. stream_info->free_streams_command =
  474. xhci_alloc_command(xhci, true, true, mem_flags);
  475. if (!stream_info->free_streams_command)
  476. goto cleanup_ctx;
  477. INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
  478. /* Allocate rings for all the streams that the driver will use,
  479. * and add their segment DMA addresses to the radix tree.
  480. * Stream 0 is reserved.
  481. */
  482. for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
  483. stream_info->stream_rings[cur_stream] =
  484. xhci_ring_alloc(xhci, 1, true, mem_flags);
  485. cur_ring = stream_info->stream_rings[cur_stream];
  486. if (!cur_ring)
  487. goto cleanup_rings;
  488. cur_ring->stream_id = cur_stream;
  489. /* Set deq ptr, cycle bit, and stream context type */
  490. addr = cur_ring->first_seg->dma |
  491. SCT_FOR_CTX(SCT_PRI_TR) |
  492. cur_ring->cycle_state;
  493. stream_info->stream_ctx_array[cur_stream].stream_ring =
  494. cpu_to_le64(addr);
  495. xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
  496. cur_stream, (unsigned long long) addr);
  497. key = (unsigned long)
  498. (cur_ring->first_seg->dma >> SEGMENT_SHIFT);
  499. ret = radix_tree_insert(&stream_info->trb_address_map,
  500. key, cur_ring);
  501. if (ret) {
  502. xhci_ring_free(xhci, cur_ring);
  503. stream_info->stream_rings[cur_stream] = NULL;
  504. goto cleanup_rings;
  505. }
  506. }
  507. /* Leave the other unused stream ring pointers in the stream context
  508. * array initialized to zero. This will cause the xHC to give us an
  509. * error if the device asks for a stream ID we don't have setup (if it
  510. * was any other way, the host controller would assume the ring is
  511. * "empty" and wait forever for data to be queued to that stream ID).
  512. */
  513. #if XHCI_DEBUG
  514. /* Do a little test on the radix tree to make sure it returns the
  515. * correct values.
  516. */
  517. if (xhci_test_radix_tree(xhci, num_streams, stream_info))
  518. goto cleanup_rings;
  519. #endif
  520. return stream_info;
  521. cleanup_rings:
  522. for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
  523. cur_ring = stream_info->stream_rings[cur_stream];
  524. if (cur_ring) {
  525. addr = cur_ring->first_seg->dma;
  526. radix_tree_delete(&stream_info->trb_address_map,
  527. addr >> SEGMENT_SHIFT);
  528. xhci_ring_free(xhci, cur_ring);
  529. stream_info->stream_rings[cur_stream] = NULL;
  530. }
  531. }
  532. xhci_free_command(xhci, stream_info->free_streams_command);
  533. cleanup_ctx:
  534. kfree(stream_info->stream_rings);
  535. cleanup_info:
  536. kfree(stream_info);
  537. cleanup_trbs:
  538. xhci->cmd_ring_reserved_trbs--;
  539. return NULL;
  540. }
  541. /*
  542. * Sets the MaxPStreams field and the Linear Stream Array field.
  543. * Sets the dequeue pointer to the stream context array.
  544. */
  545. void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
  546. struct xhci_ep_ctx *ep_ctx,
  547. struct xhci_stream_info *stream_info)
  548. {
  549. u32 max_primary_streams;
  550. /* MaxPStreams is the number of stream context array entries, not the
  551. * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
  552. * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
  553. */
  554. max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
  555. xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
  556. 1 << (max_primary_streams + 1));
  557. ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
  558. ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
  559. | EP_HAS_LSA);
  560. ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
  561. }
  562. /*
  563. * Sets the MaxPStreams field and the Linear Stream Array field to 0.
  564. * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
  565. * not at the beginning of the ring).
  566. */
  567. void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
  568. struct xhci_ep_ctx *ep_ctx,
  569. struct xhci_virt_ep *ep)
  570. {
  571. dma_addr_t addr;
  572. ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
  573. addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
  574. ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
  575. }
  576. /* Frees all stream contexts associated with the endpoint,
  577. *
  578. * Caller should fix the endpoint context streams fields.
  579. */
  580. void xhci_free_stream_info(struct xhci_hcd *xhci,
  581. struct xhci_stream_info *stream_info)
  582. {
  583. int cur_stream;
  584. struct xhci_ring *cur_ring;
  585. dma_addr_t addr;
  586. if (!stream_info)
  587. return;
  588. for (cur_stream = 1; cur_stream < stream_info->num_streams;
  589. cur_stream++) {
  590. cur_ring = stream_info->stream_rings[cur_stream];
  591. if (cur_ring) {
  592. addr = cur_ring->first_seg->dma;
  593. radix_tree_delete(&stream_info->trb_address_map,
  594. addr >> SEGMENT_SHIFT);
  595. xhci_ring_free(xhci, cur_ring);
  596. stream_info->stream_rings[cur_stream] = NULL;
  597. }
  598. }
  599. xhci_free_command(xhci, stream_info->free_streams_command);
  600. xhci->cmd_ring_reserved_trbs--;
  601. if (stream_info->stream_ctx_array)
  602. xhci_free_stream_ctx(xhci,
  603. stream_info->num_stream_ctxs,
  604. stream_info->stream_ctx_array,
  605. stream_info->ctx_array_dma);
  606. if (stream_info)
  607. kfree(stream_info->stream_rings);
  608. kfree(stream_info);
  609. }
  610. /***************** Device context manipulation *************************/
  611. static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
  612. struct xhci_virt_ep *ep)
  613. {
  614. init_timer(&ep->stop_cmd_timer);
  615. ep->stop_cmd_timer.data = (unsigned long) ep;
  616. ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
  617. ep->xhci = xhci;
  618. }
  619. static void xhci_free_tt_info(struct xhci_hcd *xhci,
  620. struct xhci_virt_device *virt_dev,
  621. int slot_id)
  622. {
  623. struct list_head *tt;
  624. struct list_head *tt_list_head;
  625. struct list_head *tt_next;
  626. struct xhci_tt_bw_info *tt_info;
  627. /* If the device never made it past the Set Address stage,
  628. * it may not have the real_port set correctly.
  629. */
  630. if (virt_dev->real_port == 0 ||
  631. virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
  632. xhci_dbg(xhci, "Bad real port.\n");
  633. return;
  634. }
  635. tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
  636. if (list_empty(tt_list_head))
  637. return;
  638. list_for_each(tt, tt_list_head) {
  639. tt_info = list_entry(tt, struct xhci_tt_bw_info, tt_list);
  640. if (tt_info->slot_id == slot_id)
  641. break;
  642. }
  643. /* Cautionary measure in case the hub was disconnected before we
  644. * stored the TT information.
  645. */
  646. if (tt_info->slot_id != slot_id)
  647. return;
  648. tt_next = tt->next;
  649. tt_info = list_entry(tt, struct xhci_tt_bw_info,
  650. tt_list);
  651. /* Multi-TT hubs will have more than one entry */
  652. do {
  653. list_del(tt);
  654. kfree(tt_info);
  655. tt = tt_next;
  656. if (list_empty(tt_list_head))
  657. break;
  658. tt_next = tt->next;
  659. tt_info = list_entry(tt, struct xhci_tt_bw_info,
  660. tt_list);
  661. } while (tt_info->slot_id == slot_id);
  662. }
  663. int xhci_alloc_tt_info(struct xhci_hcd *xhci,
  664. struct xhci_virt_device *virt_dev,
  665. struct usb_device *hdev,
  666. struct usb_tt *tt, gfp_t mem_flags)
  667. {
  668. struct xhci_tt_bw_info *tt_info;
  669. unsigned int num_ports;
  670. int i, j;
  671. if (!tt->multi)
  672. num_ports = 1;
  673. else
  674. num_ports = hdev->maxchild;
  675. for (i = 0; i < num_ports; i++, tt_info++) {
  676. struct xhci_interval_bw_table *bw_table;
  677. tt_info = kzalloc(sizeof(*tt_info), mem_flags);
  678. if (!tt_info)
  679. goto free_tts;
  680. INIT_LIST_HEAD(&tt_info->tt_list);
  681. list_add(&tt_info->tt_list,
  682. &xhci->rh_bw[virt_dev->real_port - 1].tts);
  683. tt_info->slot_id = virt_dev->udev->slot_id;
  684. if (tt->multi)
  685. tt_info->ttport = i+1;
  686. bw_table = &tt_info->bw_table;
  687. for (j = 0; j < XHCI_MAX_INTERVAL; j++)
  688. INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
  689. }
  690. return 0;
  691. free_tts:
  692. xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
  693. return -ENOMEM;
  694. }
  695. /* All the xhci_tds in the ring's TD list should be freed at this point.
  696. * Should be called with xhci->lock held if there is any chance the TT lists
  697. * will be manipulated by the configure endpoint, allocate device, or update
  698. * hub functions while this function is removing the TT entries from the list.
  699. */
  700. void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
  701. {
  702. struct xhci_virt_device *dev;
  703. int i;
  704. int old_active_eps = 0;
  705. /* Slot ID 0 is reserved */
  706. if (slot_id == 0 || !xhci->devs[slot_id])
  707. return;
  708. dev = xhci->devs[slot_id];
  709. xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
  710. if (!dev)
  711. return;
  712. if (dev->tt_info)
  713. old_active_eps = dev->tt_info->active_eps;
  714. for (i = 0; i < 31; ++i) {
  715. if (dev->eps[i].ring)
  716. xhci_ring_free(xhci, dev->eps[i].ring);
  717. if (dev->eps[i].stream_info)
  718. xhci_free_stream_info(xhci,
  719. dev->eps[i].stream_info);
  720. /* Endpoints on the TT/root port lists should have been removed
  721. * when usb_disable_device() was called for the device.
  722. * We can't drop them anyway, because the udev might have gone
  723. * away by this point, and we can't tell what speed it was.
  724. */
  725. if (!list_empty(&dev->eps[i].bw_endpoint_list))
  726. xhci_warn(xhci, "Slot %u endpoint %u "
  727. "not removed from BW list!\n",
  728. slot_id, i);
  729. }
  730. /* If this is a hub, free the TT(s) from the TT list */
  731. xhci_free_tt_info(xhci, dev, slot_id);
  732. /* If necessary, update the number of active TTs on this root port */
  733. xhci_update_tt_active_eps(xhci, dev, old_active_eps);
  734. if (dev->ring_cache) {
  735. for (i = 0; i < dev->num_rings_cached; i++)
  736. xhci_ring_free(xhci, dev->ring_cache[i]);
  737. kfree(dev->ring_cache);
  738. }
  739. if (dev->in_ctx)
  740. xhci_free_container_ctx(xhci, dev->in_ctx);
  741. if (dev->out_ctx)
  742. xhci_free_container_ctx(xhci, dev->out_ctx);
  743. kfree(xhci->devs[slot_id]);
  744. xhci->devs[slot_id] = NULL;
  745. }
  746. int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
  747. struct usb_device *udev, gfp_t flags)
  748. {
  749. struct xhci_virt_device *dev;
  750. int i;
  751. /* Slot ID 0 is reserved */
  752. if (slot_id == 0 || xhci->devs[slot_id]) {
  753. xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
  754. return 0;
  755. }
  756. xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
  757. if (!xhci->devs[slot_id])
  758. return 0;
  759. dev = xhci->devs[slot_id];
  760. /* Allocate the (output) device context that will be used in the HC. */
  761. dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
  762. if (!dev->out_ctx)
  763. goto fail;
  764. xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
  765. (unsigned long long)dev->out_ctx->dma);
  766. /* Allocate the (input) device context for address device command */
  767. dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
  768. if (!dev->in_ctx)
  769. goto fail;
  770. xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
  771. (unsigned long long)dev->in_ctx->dma);
  772. /* Initialize the cancellation list and watchdog timers for each ep */
  773. for (i = 0; i < 31; i++) {
  774. xhci_init_endpoint_timer(xhci, &dev->eps[i]);
  775. INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
  776. INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
  777. }
  778. /* Allocate endpoint 0 ring */
  779. dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
  780. if (!dev->eps[0].ring)
  781. goto fail;
  782. /* Allocate pointers to the ring cache */
  783. dev->ring_cache = kzalloc(
  784. sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
  785. flags);
  786. if (!dev->ring_cache)
  787. goto fail;
  788. dev->num_rings_cached = 0;
  789. init_completion(&dev->cmd_completion);
  790. INIT_LIST_HEAD(&dev->cmd_list);
  791. dev->udev = udev;
  792. /* Point to output device context in dcbaa. */
  793. xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
  794. xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
  795. slot_id,
  796. &xhci->dcbaa->dev_context_ptrs[slot_id],
  797. le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
  798. return 1;
  799. fail:
  800. xhci_free_virt_device(xhci, slot_id);
  801. return 0;
  802. }
  803. void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
  804. struct usb_device *udev)
  805. {
  806. struct xhci_virt_device *virt_dev;
  807. struct xhci_ep_ctx *ep0_ctx;
  808. struct xhci_ring *ep_ring;
  809. virt_dev = xhci->devs[udev->slot_id];
  810. ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
  811. ep_ring = virt_dev->eps[0].ring;
  812. /*
  813. * FIXME we don't keep track of the dequeue pointer very well after a
  814. * Set TR dequeue pointer, so we're setting the dequeue pointer of the
  815. * host to our enqueue pointer. This should only be called after a
  816. * configured device has reset, so all control transfers should have
  817. * been completed or cancelled before the reset.
  818. */
  819. ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
  820. ep_ring->enqueue)
  821. | ep_ring->cycle_state);
  822. }
  823. /*
  824. * The xHCI roothub may have ports of differing speeds in any order in the port
  825. * status registers. xhci->port_array provides an array of the port speed for
  826. * each offset into the port status registers.
  827. *
  828. * The xHCI hardware wants to know the roothub port number that the USB device
  829. * is attached to (or the roothub port its ancestor hub is attached to). All we
  830. * know is the index of that port under either the USB 2.0 or the USB 3.0
  831. * roothub, but that doesn't give us the real index into the HW port status
  832. * registers. Scan through the xHCI roothub port array, looking for the Nth
  833. * entry of the correct port speed. Return the port number of that entry.
  834. */
  835. static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
  836. struct usb_device *udev)
  837. {
  838. struct usb_device *top_dev;
  839. unsigned int num_similar_speed_ports;
  840. unsigned int faked_port_num;
  841. int i;
  842. for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
  843. top_dev = top_dev->parent)
  844. /* Found device below root hub */;
  845. faked_port_num = top_dev->portnum;
  846. for (i = 0, num_similar_speed_ports = 0;
  847. i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
  848. u8 port_speed = xhci->port_array[i];
  849. /*
  850. * Skip ports that don't have known speeds, or have duplicate
  851. * Extended Capabilities port speed entries.
  852. */
  853. if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
  854. continue;
  855. /*
  856. * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
  857. * 1.1 ports are under the USB 2.0 hub. If the port speed
  858. * matches the device speed, it's a similar speed port.
  859. */
  860. if ((port_speed == 0x03) == (udev->speed == USB_SPEED_SUPER))
  861. num_similar_speed_ports++;
  862. if (num_similar_speed_ports == faked_port_num)
  863. /* Roothub ports are numbered from 1 to N */
  864. return i+1;
  865. }
  866. return 0;
  867. }
  868. /* Setup an xHCI virtual device for a Set Address command */
  869. int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
  870. {
  871. struct xhci_virt_device *dev;
  872. struct xhci_ep_ctx *ep0_ctx;
  873. struct xhci_slot_ctx *slot_ctx;
  874. struct xhci_input_control_ctx *ctrl_ctx;
  875. u32 port_num;
  876. struct usb_device *top_dev;
  877. dev = xhci->devs[udev->slot_id];
  878. /* Slot ID 0 is reserved */
  879. if (udev->slot_id == 0 || !dev) {
  880. xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
  881. udev->slot_id);
  882. return -EINVAL;
  883. }
  884. ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
  885. ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
  886. slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
  887. /* 2) New slot context and endpoint 0 context are valid*/
  888. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
  889. /* 3) Only the control endpoint is valid - one endpoint context */
  890. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
  891. switch (udev->speed) {
  892. case USB_SPEED_SUPER:
  893. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
  894. break;
  895. case USB_SPEED_HIGH:
  896. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
  897. break;
  898. case USB_SPEED_FULL:
  899. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
  900. break;
  901. case USB_SPEED_LOW:
  902. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
  903. break;
  904. case USB_SPEED_WIRELESS:
  905. xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
  906. return -EINVAL;
  907. break;
  908. default:
  909. /* Speed was set earlier, this shouldn't happen. */
  910. BUG();
  911. }
  912. /* Find the root hub port this device is under */
  913. port_num = xhci_find_real_port_number(xhci, udev);
  914. if (!port_num)
  915. return -EINVAL;
  916. slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
  917. /* Set the port number in the virtual_device to the faked port number */
  918. for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
  919. top_dev = top_dev->parent)
  920. /* Found device below root hub */;
  921. dev->fake_port = top_dev->portnum;
  922. dev->real_port = port_num;
  923. xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
  924. xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
  925. /* Find the right bandwidth table that this device will be a part of.
  926. * If this is a full speed device attached directly to a root port (or a
  927. * decendent of one), it counts as a primary bandwidth domain, not a
  928. * secondary bandwidth domain under a TT. An xhci_tt_info structure
  929. * will never be created for the HS root hub.
  930. */
  931. if (!udev->tt || !udev->tt->hub->parent) {
  932. dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
  933. } else {
  934. struct xhci_root_port_bw_info *rh_bw;
  935. struct xhci_tt_bw_info *tt_bw;
  936. rh_bw = &xhci->rh_bw[port_num - 1];
  937. /* Find the right TT. */
  938. list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
  939. if (tt_bw->slot_id != udev->tt->hub->slot_id)
  940. continue;
  941. if (!dev->udev->tt->multi ||
  942. (udev->tt->multi &&
  943. tt_bw->ttport == dev->udev->ttport)) {
  944. dev->bw_table = &tt_bw->bw_table;
  945. dev->tt_info = tt_bw;
  946. break;
  947. }
  948. }
  949. if (!dev->tt_info)
  950. xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
  951. }
  952. /* Is this a LS/FS device under an external HS hub? */
  953. if (udev->tt && udev->tt->hub->parent) {
  954. slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
  955. (udev->ttport << 8));
  956. if (udev->tt->multi)
  957. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  958. }
  959. xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
  960. xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
  961. /* Step 4 - ring already allocated */
  962. /* Step 5 */
  963. ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
  964. /*
  965. * XXX: Not sure about wireless USB devices.
  966. */
  967. switch (udev->speed) {
  968. case USB_SPEED_SUPER:
  969. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
  970. break;
  971. case USB_SPEED_HIGH:
  972. /* USB core guesses at a 64-byte max packet first for FS devices */
  973. case USB_SPEED_FULL:
  974. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
  975. break;
  976. case USB_SPEED_LOW:
  977. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
  978. break;
  979. case USB_SPEED_WIRELESS:
  980. xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
  981. return -EINVAL;
  982. break;
  983. default:
  984. /* New speed? */
  985. BUG();
  986. }
  987. /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
  988. ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
  989. ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
  990. dev->eps[0].ring->cycle_state);
  991. /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
  992. return 0;
  993. }
  994. /*
  995. * Convert interval expressed as 2^(bInterval - 1) == interval into
  996. * straight exponent value 2^n == interval.
  997. *
  998. */
  999. static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
  1000. struct usb_host_endpoint *ep)
  1001. {
  1002. unsigned int interval;
  1003. interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
  1004. if (interval != ep->desc.bInterval - 1)
  1005. dev_warn(&udev->dev,
  1006. "ep %#x - rounding interval to %d %sframes\n",
  1007. ep->desc.bEndpointAddress,
  1008. 1 << interval,
  1009. udev->speed == USB_SPEED_FULL ? "" : "micro");
  1010. if (udev->speed == USB_SPEED_FULL) {
  1011. /*
  1012. * Full speed isoc endpoints specify interval in frames,
  1013. * not microframes. We are using microframes everywhere,
  1014. * so adjust accordingly.
  1015. */
  1016. interval += 3; /* 1 frame = 2^3 uframes */
  1017. }
  1018. return interval;
  1019. }
  1020. /*
  1021. * Convert bInterval expressed in frames (in 1-255 range) to exponent of
  1022. * microframes, rounded down to nearest power of 2.
  1023. */
  1024. static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
  1025. struct usb_host_endpoint *ep)
  1026. {
  1027. unsigned int interval;
  1028. interval = fls(8 * ep->desc.bInterval) - 1;
  1029. interval = clamp_val(interval, 3, 10);
  1030. if ((1 << interval) != 8 * ep->desc.bInterval)
  1031. dev_warn(&udev->dev,
  1032. "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
  1033. ep->desc.bEndpointAddress,
  1034. 1 << interval,
  1035. 8 * ep->desc.bInterval);
  1036. return interval;
  1037. }
  1038. /* Return the polling or NAK interval.
  1039. *
  1040. * The polling interval is expressed in "microframes". If xHCI's Interval field
  1041. * is set to N, it will service the endpoint every 2^(Interval)*125us.
  1042. *
  1043. * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
  1044. * is set to 0.
  1045. */
  1046. static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
  1047. struct usb_host_endpoint *ep)
  1048. {
  1049. unsigned int interval = 0;
  1050. switch (udev->speed) {
  1051. case USB_SPEED_HIGH:
  1052. /* Max NAK rate */
  1053. if (usb_endpoint_xfer_control(&ep->desc) ||
  1054. usb_endpoint_xfer_bulk(&ep->desc)) {
  1055. interval = ep->desc.bInterval;
  1056. break;
  1057. }
  1058. /* Fall through - SS and HS isoc/int have same decoding */
  1059. case USB_SPEED_SUPER:
  1060. if (usb_endpoint_xfer_int(&ep->desc) ||
  1061. usb_endpoint_xfer_isoc(&ep->desc)) {
  1062. interval = xhci_parse_exponent_interval(udev, ep);
  1063. }
  1064. break;
  1065. case USB_SPEED_FULL:
  1066. if (usb_endpoint_xfer_isoc(&ep->desc)) {
  1067. interval = xhci_parse_exponent_interval(udev, ep);
  1068. break;
  1069. }
  1070. /*
  1071. * Fall through for interrupt endpoint interval decoding
  1072. * since it uses the same rules as low speed interrupt
  1073. * endpoints.
  1074. */
  1075. case USB_SPEED_LOW:
  1076. if (usb_endpoint_xfer_int(&ep->desc) ||
  1077. usb_endpoint_xfer_isoc(&ep->desc)) {
  1078. interval = xhci_parse_frame_interval(udev, ep);
  1079. }
  1080. break;
  1081. default:
  1082. BUG();
  1083. }
  1084. return EP_INTERVAL(interval);
  1085. }
  1086. /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
  1087. * High speed endpoint descriptors can define "the number of additional
  1088. * transaction opportunities per microframe", but that goes in the Max Burst
  1089. * endpoint context field.
  1090. */
  1091. static u32 xhci_get_endpoint_mult(struct usb_device *udev,
  1092. struct usb_host_endpoint *ep)
  1093. {
  1094. if (udev->speed != USB_SPEED_SUPER ||
  1095. !usb_endpoint_xfer_isoc(&ep->desc))
  1096. return 0;
  1097. return ep->ss_ep_comp.bmAttributes;
  1098. }
  1099. static u32 xhci_get_endpoint_type(struct usb_device *udev,
  1100. struct usb_host_endpoint *ep)
  1101. {
  1102. int in;
  1103. u32 type;
  1104. in = usb_endpoint_dir_in(&ep->desc);
  1105. if (usb_endpoint_xfer_control(&ep->desc)) {
  1106. type = EP_TYPE(CTRL_EP);
  1107. } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
  1108. if (in)
  1109. type = EP_TYPE(BULK_IN_EP);
  1110. else
  1111. type = EP_TYPE(BULK_OUT_EP);
  1112. } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
  1113. if (in)
  1114. type = EP_TYPE(ISOC_IN_EP);
  1115. else
  1116. type = EP_TYPE(ISOC_OUT_EP);
  1117. } else if (usb_endpoint_xfer_int(&ep->desc)) {
  1118. if (in)
  1119. type = EP_TYPE(INT_IN_EP);
  1120. else
  1121. type = EP_TYPE(INT_OUT_EP);
  1122. } else {
  1123. BUG();
  1124. }
  1125. return type;
  1126. }
  1127. /* Return the maximum endpoint service interval time (ESIT) payload.
  1128. * Basically, this is the maxpacket size, multiplied by the burst size
  1129. * and mult size.
  1130. */
  1131. static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
  1132. struct usb_device *udev,
  1133. struct usb_host_endpoint *ep)
  1134. {
  1135. int max_burst;
  1136. int max_packet;
  1137. /* Only applies for interrupt or isochronous endpoints */
  1138. if (usb_endpoint_xfer_control(&ep->desc) ||
  1139. usb_endpoint_xfer_bulk(&ep->desc))
  1140. return 0;
  1141. if (udev->speed == USB_SPEED_SUPER)
  1142. return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
  1143. max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
  1144. max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
  1145. /* A 0 in max burst means 1 transfer per ESIT */
  1146. return max_packet * (max_burst + 1);
  1147. }
  1148. /* Set up an endpoint with one ring segment. Do not allocate stream rings.
  1149. * Drivers will have to call usb_alloc_streams() to do that.
  1150. */
  1151. int xhci_endpoint_init(struct xhci_hcd *xhci,
  1152. struct xhci_virt_device *virt_dev,
  1153. struct usb_device *udev,
  1154. struct usb_host_endpoint *ep,
  1155. gfp_t mem_flags)
  1156. {
  1157. unsigned int ep_index;
  1158. struct xhci_ep_ctx *ep_ctx;
  1159. struct xhci_ring *ep_ring;
  1160. unsigned int max_packet;
  1161. unsigned int max_burst;
  1162. u32 max_esit_payload;
  1163. ep_index = xhci_get_endpoint_index(&ep->desc);
  1164. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
  1165. /* Set up the endpoint ring */
  1166. /*
  1167. * Isochronous endpoint ring needs bigger size because one isoc URB
  1168. * carries multiple packets and it will insert multiple tds to the
  1169. * ring.
  1170. * This should be replaced with dynamic ring resizing in the future.
  1171. */
  1172. if (usb_endpoint_xfer_isoc(&ep->desc))
  1173. virt_dev->eps[ep_index].new_ring =
  1174. xhci_ring_alloc(xhci, 8, true, mem_flags);
  1175. else
  1176. virt_dev->eps[ep_index].new_ring =
  1177. xhci_ring_alloc(xhci, 1, true, mem_flags);
  1178. if (!virt_dev->eps[ep_index].new_ring) {
  1179. /* Attempt to use the ring cache */
  1180. if (virt_dev->num_rings_cached == 0)
  1181. return -ENOMEM;
  1182. virt_dev->eps[ep_index].new_ring =
  1183. virt_dev->ring_cache[virt_dev->num_rings_cached];
  1184. virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
  1185. virt_dev->num_rings_cached--;
  1186. xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring);
  1187. }
  1188. virt_dev->eps[ep_index].skip = false;
  1189. ep_ring = virt_dev->eps[ep_index].new_ring;
  1190. ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
  1191. ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
  1192. | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
  1193. /* FIXME dig Mult and streams info out of ep companion desc */
  1194. /* Allow 3 retries for everything but isoc;
  1195. * CErr shall be set to 0 for Isoch endpoints.
  1196. */
  1197. if (!usb_endpoint_xfer_isoc(&ep->desc))
  1198. ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
  1199. else
  1200. ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
  1201. ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
  1202. /* Set the max packet size and max burst */
  1203. switch (udev->speed) {
  1204. case USB_SPEED_SUPER:
  1205. max_packet = usb_endpoint_maxp(&ep->desc);
  1206. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
  1207. /* dig out max burst from ep companion desc */
  1208. max_packet = ep->ss_ep_comp.bMaxBurst;
  1209. ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
  1210. break;
  1211. case USB_SPEED_HIGH:
  1212. /* bits 11:12 specify the number of additional transaction
  1213. * opportunities per microframe (USB 2.0, section 9.6.6)
  1214. */
  1215. if (usb_endpoint_xfer_isoc(&ep->desc) ||
  1216. usb_endpoint_xfer_int(&ep->desc)) {
  1217. max_burst = (usb_endpoint_maxp(&ep->desc)
  1218. & 0x1800) >> 11;
  1219. ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
  1220. }
  1221. /* Fall through */
  1222. case USB_SPEED_FULL:
  1223. case USB_SPEED_LOW:
  1224. max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
  1225. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
  1226. break;
  1227. default:
  1228. BUG();
  1229. }
  1230. max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
  1231. ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
  1232. /*
  1233. * XXX no idea how to calculate the average TRB buffer length for bulk
  1234. * endpoints, as the driver gives us no clue how big each scatter gather
  1235. * list entry (or buffer) is going to be.
  1236. *
  1237. * For isochronous and interrupt endpoints, we set it to the max
  1238. * available, until we have new API in the USB core to allow drivers to
  1239. * declare how much bandwidth they actually need.
  1240. *
  1241. * Normally, it would be calculated by taking the total of the buffer
  1242. * lengths in the TD and then dividing by the number of TRBs in a TD,
  1243. * including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
  1244. * use Event Data TRBs, and we don't chain in a link TRB on short
  1245. * transfers, we're basically dividing by 1.
  1246. *
  1247. * xHCI 1.0 specification indicates that the Average TRB Length should
  1248. * be set to 8 for control endpoints.
  1249. */
  1250. if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
  1251. ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
  1252. else
  1253. ep_ctx->tx_info |=
  1254. cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
  1255. /* FIXME Debug endpoint context */
  1256. return 0;
  1257. }
  1258. void xhci_endpoint_zero(struct xhci_hcd *xhci,
  1259. struct xhci_virt_device *virt_dev,
  1260. struct usb_host_endpoint *ep)
  1261. {
  1262. unsigned int ep_index;
  1263. struct xhci_ep_ctx *ep_ctx;
  1264. ep_index = xhci_get_endpoint_index(&ep->desc);
  1265. ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
  1266. ep_ctx->ep_info = 0;
  1267. ep_ctx->ep_info2 = 0;
  1268. ep_ctx->deq = 0;
  1269. ep_ctx->tx_info = 0;
  1270. /* Don't free the endpoint ring until the set interface or configuration
  1271. * request succeeds.
  1272. */
  1273. }
  1274. void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
  1275. {
  1276. bw_info->ep_interval = 0;
  1277. bw_info->mult = 0;
  1278. bw_info->num_packets = 0;
  1279. bw_info->max_packet_size = 0;
  1280. bw_info->type = 0;
  1281. bw_info->max_esit_payload = 0;
  1282. }
  1283. void xhci_update_bw_info(struct xhci_hcd *xhci,
  1284. struct xhci_container_ctx *in_ctx,
  1285. struct xhci_input_control_ctx *ctrl_ctx,
  1286. struct xhci_virt_device *virt_dev)
  1287. {
  1288. struct xhci_bw_info *bw_info;
  1289. struct xhci_ep_ctx *ep_ctx;
  1290. unsigned int ep_type;
  1291. int i;
  1292. for (i = 1; i < 31; ++i) {
  1293. bw_info = &virt_dev->eps[i].bw_info;
  1294. /* We can't tell what endpoint type is being dropped, but
  1295. * unconditionally clearing the bandwidth info for non-periodic
  1296. * endpoints should be harmless because the info will never be
  1297. * set in the first place.
  1298. */
  1299. if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
  1300. /* Dropped endpoint */
  1301. xhci_clear_endpoint_bw_info(bw_info);
  1302. continue;
  1303. }
  1304. if (EP_IS_ADDED(ctrl_ctx, i)) {
  1305. ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
  1306. ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
  1307. /* Ignore non-periodic endpoints */
  1308. if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
  1309. ep_type != ISOC_IN_EP &&
  1310. ep_type != INT_IN_EP)
  1311. continue;
  1312. /* Added or changed endpoint */
  1313. bw_info->ep_interval = CTX_TO_EP_INTERVAL(
  1314. le32_to_cpu(ep_ctx->ep_info));
  1315. bw_info->mult = CTX_TO_EP_MULT(
  1316. le32_to_cpu(ep_ctx->ep_info));
  1317. /* Number of packets is zero-based in the input context,
  1318. * but we want one-based for the interval table.
  1319. */
  1320. bw_info->num_packets = CTX_TO_MAX_BURST(
  1321. le32_to_cpu(ep_ctx->ep_info2)) + 1;
  1322. bw_info->max_packet_size = MAX_PACKET_DECODED(
  1323. le32_to_cpu(ep_ctx->ep_info2));
  1324. bw_info->type = ep_type;
  1325. bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
  1326. le32_to_cpu(ep_ctx->tx_info));
  1327. }
  1328. }
  1329. }
  1330. /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
  1331. * Useful when you want to change one particular aspect of the endpoint and then
  1332. * issue a configure endpoint command.
  1333. */
  1334. void xhci_endpoint_copy(struct xhci_hcd *xhci,
  1335. struct xhci_container_ctx *in_ctx,
  1336. struct xhci_container_ctx *out_ctx,
  1337. unsigned int ep_index)
  1338. {
  1339. struct xhci_ep_ctx *out_ep_ctx;
  1340. struct xhci_ep_ctx *in_ep_ctx;
  1341. out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
  1342. in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
  1343. in_ep_ctx->ep_info = out_ep_ctx->ep_info;
  1344. in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
  1345. in_ep_ctx->deq = out_ep_ctx->deq;
  1346. in_ep_ctx->tx_info = out_ep_ctx->tx_info;
  1347. }
  1348. /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
  1349. * Useful when you want to change one particular aspect of the endpoint and then
  1350. * issue a configure endpoint command. Only the context entries field matters,
  1351. * but we'll copy the whole thing anyway.
  1352. */
  1353. void xhci_slot_copy(struct xhci_hcd *xhci,
  1354. struct xhci_container_ctx *in_ctx,
  1355. struct xhci_container_ctx *out_ctx)
  1356. {
  1357. struct xhci_slot_ctx *in_slot_ctx;
  1358. struct xhci_slot_ctx *out_slot_ctx;
  1359. in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
  1360. out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
  1361. in_slot_ctx->dev_info = out_slot_ctx->dev_info;
  1362. in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
  1363. in_slot_ctx->tt_info = out_slot_ctx->tt_info;
  1364. in_slot_ctx->dev_state = out_slot_ctx->dev_state;
  1365. }
  1366. /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
  1367. static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
  1368. {
  1369. int i;
  1370. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  1371. int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
  1372. xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
  1373. if (!num_sp)
  1374. return 0;
  1375. xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
  1376. if (!xhci->scratchpad)
  1377. goto fail_sp;
  1378. xhci->scratchpad->sp_array =
  1379. pci_alloc_consistent(to_pci_dev(dev),
  1380. num_sp * sizeof(u64),
  1381. &xhci->scratchpad->sp_dma);
  1382. if (!xhci->scratchpad->sp_array)
  1383. goto fail_sp2;
  1384. xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
  1385. if (!xhci->scratchpad->sp_buffers)
  1386. goto fail_sp3;
  1387. xhci->scratchpad->sp_dma_buffers =
  1388. kzalloc(sizeof(dma_addr_t) * num_sp, flags);
  1389. if (!xhci->scratchpad->sp_dma_buffers)
  1390. goto fail_sp4;
  1391. xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
  1392. for (i = 0; i < num_sp; i++) {
  1393. dma_addr_t dma;
  1394. void *buf = pci_alloc_consistent(to_pci_dev(dev),
  1395. xhci->page_size, &dma);
  1396. if (!buf)
  1397. goto fail_sp5;
  1398. xhci->scratchpad->sp_array[i] = dma;
  1399. xhci->scratchpad->sp_buffers[i] = buf;
  1400. xhci->scratchpad->sp_dma_buffers[i] = dma;
  1401. }
  1402. return 0;
  1403. fail_sp5:
  1404. for (i = i - 1; i >= 0; i--) {
  1405. pci_free_consistent(to_pci_dev(dev), xhci->page_size,
  1406. xhci->scratchpad->sp_buffers[i],
  1407. xhci->scratchpad->sp_dma_buffers[i]);
  1408. }
  1409. kfree(xhci->scratchpad->sp_dma_buffers);
  1410. fail_sp4:
  1411. kfree(xhci->scratchpad->sp_buffers);
  1412. fail_sp3:
  1413. pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
  1414. xhci->scratchpad->sp_array,
  1415. xhci->scratchpad->sp_dma);
  1416. fail_sp2:
  1417. kfree(xhci->scratchpad);
  1418. xhci->scratchpad = NULL;
  1419. fail_sp:
  1420. return -ENOMEM;
  1421. }
  1422. static void scratchpad_free(struct xhci_hcd *xhci)
  1423. {
  1424. int num_sp;
  1425. int i;
  1426. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  1427. if (!xhci->scratchpad)
  1428. return;
  1429. num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
  1430. for (i = 0; i < num_sp; i++) {
  1431. pci_free_consistent(pdev, xhci->page_size,
  1432. xhci->scratchpad->sp_buffers[i],
  1433. xhci->scratchpad->sp_dma_buffers[i]);
  1434. }
  1435. kfree(xhci->scratchpad->sp_dma_buffers);
  1436. kfree(xhci->scratchpad->sp_buffers);
  1437. pci_free_consistent(pdev, num_sp * sizeof(u64),
  1438. xhci->scratchpad->sp_array,
  1439. xhci->scratchpad->sp_dma);
  1440. kfree(xhci->scratchpad);
  1441. xhci->scratchpad = NULL;
  1442. }
  1443. struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
  1444. bool allocate_in_ctx, bool allocate_completion,
  1445. gfp_t mem_flags)
  1446. {
  1447. struct xhci_command *command;
  1448. command = kzalloc(sizeof(*command), mem_flags);
  1449. if (!command)
  1450. return NULL;
  1451. if (allocate_in_ctx) {
  1452. command->in_ctx =
  1453. xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
  1454. mem_flags);
  1455. if (!command->in_ctx) {
  1456. kfree(command);
  1457. return NULL;
  1458. }
  1459. }
  1460. if (allocate_completion) {
  1461. command->completion =
  1462. kzalloc(sizeof(struct completion), mem_flags);
  1463. if (!command->completion) {
  1464. xhci_free_container_ctx(xhci, command->in_ctx);
  1465. kfree(command);
  1466. return NULL;
  1467. }
  1468. init_completion(command->completion);
  1469. }
  1470. command->status = 0;
  1471. INIT_LIST_HEAD(&command->cmd_list);
  1472. return command;
  1473. }
  1474. void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
  1475. {
  1476. if (urb_priv) {
  1477. kfree(urb_priv->td[0]);
  1478. kfree(urb_priv);
  1479. }
  1480. }
  1481. void xhci_free_command(struct xhci_hcd *xhci,
  1482. struct xhci_command *command)
  1483. {
  1484. xhci_free_container_ctx(xhci,
  1485. command->in_ctx);
  1486. kfree(command->completion);
  1487. kfree(command);
  1488. }
  1489. void xhci_mem_cleanup(struct xhci_hcd *xhci)
  1490. {
  1491. struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
  1492. int size;
  1493. int i;
  1494. /* Free the Event Ring Segment Table and the actual Event Ring */
  1495. if (xhci->ir_set) {
  1496. xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
  1497. xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
  1498. xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
  1499. }
  1500. size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
  1501. if (xhci->erst.entries)
  1502. pci_free_consistent(pdev, size,
  1503. xhci->erst.entries, xhci->erst.erst_dma_addr);
  1504. xhci->erst.entries = NULL;
  1505. xhci_dbg(xhci, "Freed ERST\n");
  1506. if (xhci->event_ring)
  1507. xhci_ring_free(xhci, xhci->event_ring);
  1508. xhci->event_ring = NULL;
  1509. xhci_dbg(xhci, "Freed event ring\n");
  1510. xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
  1511. if (xhci->cmd_ring)
  1512. xhci_ring_free(xhci, xhci->cmd_ring);
  1513. xhci->cmd_ring = NULL;
  1514. xhci_dbg(xhci, "Freed command ring\n");
  1515. for (i = 1; i < MAX_HC_SLOTS; ++i)
  1516. xhci_free_virt_device(xhci, i);
  1517. if (xhci->segment_pool)
  1518. dma_pool_destroy(xhci->segment_pool);
  1519. xhci->segment_pool = NULL;
  1520. xhci_dbg(xhci, "Freed segment pool\n");
  1521. if (xhci->device_pool)
  1522. dma_pool_destroy(xhci->device_pool);
  1523. xhci->device_pool = NULL;
  1524. xhci_dbg(xhci, "Freed device context pool\n");
  1525. if (xhci->small_streams_pool)
  1526. dma_pool_destroy(xhci->small_streams_pool);
  1527. xhci->small_streams_pool = NULL;
  1528. xhci_dbg(xhci, "Freed small stream array pool\n");
  1529. if (xhci->medium_streams_pool)
  1530. dma_pool_destroy(xhci->medium_streams_pool);
  1531. xhci->medium_streams_pool = NULL;
  1532. xhci_dbg(xhci, "Freed medium stream array pool\n");
  1533. xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
  1534. if (xhci->dcbaa)
  1535. pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
  1536. xhci->dcbaa, xhci->dcbaa->dma);
  1537. xhci->dcbaa = NULL;
  1538. scratchpad_free(xhci);
  1539. xhci->num_usb2_ports = 0;
  1540. xhci->num_usb3_ports = 0;
  1541. kfree(xhci->usb2_ports);
  1542. kfree(xhci->usb3_ports);
  1543. kfree(xhci->port_array);
  1544. kfree(xhci->rh_bw);
  1545. xhci->page_size = 0;
  1546. xhci->page_shift = 0;
  1547. xhci->bus_state[0].bus_suspended = 0;
  1548. xhci->bus_state[1].bus_suspended = 0;
  1549. }
  1550. static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
  1551. struct xhci_segment *input_seg,
  1552. union xhci_trb *start_trb,
  1553. union xhci_trb *end_trb,
  1554. dma_addr_t input_dma,
  1555. struct xhci_segment *result_seg,
  1556. char *test_name, int test_number)
  1557. {
  1558. unsigned long long start_dma;
  1559. unsigned long long end_dma;
  1560. struct xhci_segment *seg;
  1561. start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
  1562. end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
  1563. seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
  1564. if (seg != result_seg) {
  1565. xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
  1566. test_name, test_number);
  1567. xhci_warn(xhci, "Tested TRB math w/ seg %p and "
  1568. "input DMA 0x%llx\n",
  1569. input_seg,
  1570. (unsigned long long) input_dma);
  1571. xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
  1572. "ending TRB %p (0x%llx DMA)\n",
  1573. start_trb, start_dma,
  1574. end_trb, end_dma);
  1575. xhci_warn(xhci, "Expected seg %p, got seg %p\n",
  1576. result_seg, seg);
  1577. return -1;
  1578. }
  1579. return 0;
  1580. }
  1581. /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
  1582. static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
  1583. {
  1584. struct {
  1585. dma_addr_t input_dma;
  1586. struct xhci_segment *result_seg;
  1587. } simple_test_vector [] = {
  1588. /* A zeroed DMA field should fail */
  1589. { 0, NULL },
  1590. /* One TRB before the ring start should fail */
  1591. { xhci->event_ring->first_seg->dma - 16, NULL },
  1592. /* One byte before the ring start should fail */
  1593. { xhci->event_ring->first_seg->dma - 1, NULL },
  1594. /* Starting TRB should succeed */
  1595. { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
  1596. /* Ending TRB should succeed */
  1597. { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
  1598. xhci->event_ring->first_seg },
  1599. /* One byte after the ring end should fail */
  1600. { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
  1601. /* One TRB after the ring end should fail */
  1602. { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
  1603. /* An address of all ones should fail */
  1604. { (dma_addr_t) (~0), NULL },
  1605. };
  1606. struct {
  1607. struct xhci_segment *input_seg;
  1608. union xhci_trb *start_trb;
  1609. union xhci_trb *end_trb;
  1610. dma_addr_t input_dma;
  1611. struct xhci_segment *result_seg;
  1612. } complex_test_vector [] = {
  1613. /* Test feeding a valid DMA address from a different ring */
  1614. { .input_seg = xhci->event_ring->first_seg,
  1615. .start_trb = xhci->event_ring->first_seg->trbs,
  1616. .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
  1617. .input_dma = xhci->cmd_ring->first_seg->dma,
  1618. .result_seg = NULL,
  1619. },
  1620. /* Test feeding a valid end TRB from a different ring */
  1621. { .input_seg = xhci->event_ring->first_seg,
  1622. .start_trb = xhci->event_ring->first_seg->trbs,
  1623. .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
  1624. .input_dma = xhci->cmd_ring->first_seg->dma,
  1625. .result_seg = NULL,
  1626. },
  1627. /* Test feeding a valid start and end TRB from a different ring */
  1628. { .input_seg = xhci->event_ring->first_seg,
  1629. .start_trb = xhci->cmd_ring->first_seg->trbs,
  1630. .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
  1631. .input_dma = xhci->cmd_ring->first_seg->dma,
  1632. .result_seg = NULL,
  1633. },
  1634. /* TRB in this ring, but after this TD */
  1635. { .input_seg = xhci->event_ring->first_seg,
  1636. .start_trb = &xhci->event_ring->first_seg->trbs[0],
  1637. .end_trb = &xhci->event_ring->first_seg->trbs[3],
  1638. .input_dma = xhci->event_ring->first_seg->dma + 4*16,
  1639. .result_seg = NULL,
  1640. },
  1641. /* TRB in this ring, but before this TD */
  1642. { .input_seg = xhci->event_ring->first_seg,
  1643. .start_trb = &xhci->event_ring->first_seg->trbs[3],
  1644. .end_trb = &xhci->event_ring->first_seg->trbs[6],
  1645. .input_dma = xhci->event_ring->first_seg->dma + 2*16,
  1646. .result_seg = NULL,
  1647. },
  1648. /* TRB in this ring, but after this wrapped TD */
  1649. { .input_seg = xhci->event_ring->first_seg,
  1650. .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
  1651. .end_trb = &xhci->event_ring->first_seg->trbs[1],
  1652. .input_dma = xhci->event_ring->first_seg->dma + 2*16,
  1653. .result_seg = NULL,
  1654. },
  1655. /* TRB in this ring, but before this wrapped TD */
  1656. { .input_seg = xhci->event_ring->first_seg,
  1657. .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
  1658. .end_trb = &xhci->event_ring->first_seg->trbs[1],
  1659. .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
  1660. .result_seg = NULL,
  1661. },
  1662. /* TRB not in this ring, and we have a wrapped TD */
  1663. { .input_seg = xhci->event_ring->first_seg,
  1664. .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
  1665. .end_trb = &xhci->event_ring->first_seg->trbs[1],
  1666. .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
  1667. .result_seg = NULL,
  1668. },
  1669. };
  1670. unsigned int num_tests;
  1671. int i, ret;
  1672. num_tests = ARRAY_SIZE(simple_test_vector);
  1673. for (i = 0; i < num_tests; i++) {
  1674. ret = xhci_test_trb_in_td(xhci,
  1675. xhci->event_ring->first_seg,
  1676. xhci->event_ring->first_seg->trbs,
  1677. &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
  1678. simple_test_vector[i].input_dma,
  1679. simple_test_vector[i].result_seg,
  1680. "Simple", i);
  1681. if (ret < 0)
  1682. return ret;
  1683. }
  1684. num_tests = ARRAY_SIZE(complex_test_vector);
  1685. for (i = 0; i < num_tests; i++) {
  1686. ret = xhci_test_trb_in_td(xhci,
  1687. complex_test_vector[i].input_seg,
  1688. complex_test_vector[i].start_trb,
  1689. complex_test_vector[i].end_trb,
  1690. complex_test_vector[i].input_dma,
  1691. complex_test_vector[i].result_seg,
  1692. "Complex", i);
  1693. if (ret < 0)
  1694. return ret;
  1695. }
  1696. xhci_dbg(xhci, "TRB math tests passed.\n");
  1697. return 0;
  1698. }
  1699. static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
  1700. {
  1701. u64 temp;
  1702. dma_addr_t deq;
  1703. deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
  1704. xhci->event_ring->dequeue);
  1705. if (deq == 0 && !in_interrupt())
  1706. xhci_warn(xhci, "WARN something wrong with SW event ring "
  1707. "dequeue ptr.\n");
  1708. /* Update HC event ring dequeue pointer */
  1709. temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
  1710. temp &= ERST_PTR_MASK;
  1711. /* Don't clear the EHB bit (which is RW1C) because
  1712. * there might be more events to service.
  1713. */
  1714. temp &= ~ERST_EHB;
  1715. xhci_dbg(xhci, "// Write event ring dequeue pointer, "
  1716. "preserving EHB bit\n");
  1717. xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
  1718. &xhci->ir_set->erst_dequeue);
  1719. }
  1720. static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
  1721. __le32 __iomem *addr, u8 major_revision)
  1722. {
  1723. u32 temp, port_offset, port_count;
  1724. int i;
  1725. if (major_revision > 0x03) {
  1726. xhci_warn(xhci, "Ignoring unknown port speed, "
  1727. "Ext Cap %p, revision = 0x%x\n",
  1728. addr, major_revision);
  1729. /* Ignoring port protocol we can't understand. FIXME */
  1730. return;
  1731. }
  1732. /* Port offset and count in the third dword, see section 7.2 */
  1733. temp = xhci_readl(xhci, addr + 2);
  1734. port_offset = XHCI_EXT_PORT_OFF(temp);
  1735. port_count = XHCI_EXT_PORT_COUNT(temp);
  1736. xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
  1737. "count = %u, revision = 0x%x\n",
  1738. addr, port_offset, port_count, major_revision);
  1739. /* Port count includes the current port offset */
  1740. if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
  1741. /* WTF? "Valid values are ‘1’ to MaxPorts" */
  1742. return;
  1743. port_offset--;
  1744. for (i = port_offset; i < (port_offset + port_count); i++) {
  1745. /* Duplicate entry. Ignore the port if the revisions differ. */
  1746. if (xhci->port_array[i] != 0) {
  1747. xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
  1748. " port %u\n", addr, i);
  1749. xhci_warn(xhci, "Port was marked as USB %u, "
  1750. "duplicated as USB %u\n",
  1751. xhci->port_array[i], major_revision);
  1752. /* Only adjust the roothub port counts if we haven't
  1753. * found a similar duplicate.
  1754. */
  1755. if (xhci->port_array[i] != major_revision &&
  1756. xhci->port_array[i] != DUPLICATE_ENTRY) {
  1757. if (xhci->port_array[i] == 0x03)
  1758. xhci->num_usb3_ports--;
  1759. else
  1760. xhci->num_usb2_ports--;
  1761. xhci->port_array[i] = DUPLICATE_ENTRY;
  1762. }
  1763. /* FIXME: Should we disable the port? */
  1764. continue;
  1765. }
  1766. xhci->port_array[i] = major_revision;
  1767. if (major_revision == 0x03)
  1768. xhci->num_usb3_ports++;
  1769. else
  1770. xhci->num_usb2_ports++;
  1771. }
  1772. /* FIXME: Should we disable ports not in the Extended Capabilities? */
  1773. }
  1774. /*
  1775. * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
  1776. * specify what speeds each port is supposed to be. We can't count on the port
  1777. * speed bits in the PORTSC register being correct until a device is connected,
  1778. * but we need to set up the two fake roothubs with the correct number of USB
  1779. * 3.0 and USB 2.0 ports at host controller initialization time.
  1780. */
  1781. static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
  1782. {
  1783. __le32 __iomem *addr;
  1784. u32 offset;
  1785. unsigned int num_ports;
  1786. int i, j, port_index;
  1787. addr = &xhci->cap_regs->hcc_params;
  1788. offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
  1789. if (offset == 0) {
  1790. xhci_err(xhci, "No Extended Capability registers, "
  1791. "unable to set up roothub.\n");
  1792. return -ENODEV;
  1793. }
  1794. num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
  1795. xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
  1796. if (!xhci->port_array)
  1797. return -ENOMEM;
  1798. xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
  1799. if (!xhci->rh_bw)
  1800. return -ENOMEM;
  1801. for (i = 0; i < num_ports; i++) {
  1802. struct xhci_interval_bw_table *bw_table;
  1803. INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
  1804. bw_table = &xhci->rh_bw[i].bw_table;
  1805. for (j = 0; j < XHCI_MAX_INTERVAL; j++)
  1806. INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
  1807. }
  1808. /*
  1809. * For whatever reason, the first capability offset is from the
  1810. * capability register base, not from the HCCPARAMS register.
  1811. * See section 5.3.6 for offset calculation.
  1812. */
  1813. addr = &xhci->cap_regs->hc_capbase + offset;
  1814. while (1) {
  1815. u32 cap_id;
  1816. cap_id = xhci_readl(xhci, addr);
  1817. if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
  1818. xhci_add_in_port(xhci, num_ports, addr,
  1819. (u8) XHCI_EXT_PORT_MAJOR(cap_id));
  1820. offset = XHCI_EXT_CAPS_NEXT(cap_id);
  1821. if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
  1822. == num_ports)
  1823. break;
  1824. /*
  1825. * Once you're into the Extended Capabilities, the offset is
  1826. * always relative to the register holding the offset.
  1827. */
  1828. addr += offset;
  1829. }
  1830. if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
  1831. xhci_warn(xhci, "No ports on the roothubs?\n");
  1832. return -ENODEV;
  1833. }
  1834. xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
  1835. xhci->num_usb2_ports, xhci->num_usb3_ports);
  1836. /* Place limits on the number of roothub ports so that the hub
  1837. * descriptors aren't longer than the USB core will allocate.
  1838. */
  1839. if (xhci->num_usb3_ports > 15) {
  1840. xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
  1841. xhci->num_usb3_ports = 15;
  1842. }
  1843. if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
  1844. xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
  1845. USB_MAXCHILDREN);
  1846. xhci->num_usb2_ports = USB_MAXCHILDREN;
  1847. }
  1848. /*
  1849. * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
  1850. * Not sure how the USB core will handle a hub with no ports...
  1851. */
  1852. if (xhci->num_usb2_ports) {
  1853. xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
  1854. xhci->num_usb2_ports, flags);
  1855. if (!xhci->usb2_ports)
  1856. return -ENOMEM;
  1857. port_index = 0;
  1858. for (i = 0; i < num_ports; i++) {
  1859. if (xhci->port_array[i] == 0x03 ||
  1860. xhci->port_array[i] == 0 ||
  1861. xhci->port_array[i] == DUPLICATE_ENTRY)
  1862. continue;
  1863. xhci->usb2_ports[port_index] =
  1864. &xhci->op_regs->port_status_base +
  1865. NUM_PORT_REGS*i;
  1866. xhci_dbg(xhci, "USB 2.0 port at index %u, "
  1867. "addr = %p\n", i,
  1868. xhci->usb2_ports[port_index]);
  1869. port_index++;
  1870. if (port_index == xhci->num_usb2_ports)
  1871. break;
  1872. }
  1873. }
  1874. if (xhci->num_usb3_ports) {
  1875. xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
  1876. xhci->num_usb3_ports, flags);
  1877. if (!xhci->usb3_ports)
  1878. return -ENOMEM;
  1879. port_index = 0;
  1880. for (i = 0; i < num_ports; i++)
  1881. if (xhci->port_array[i] == 0x03) {
  1882. xhci->usb3_ports[port_index] =
  1883. &xhci->op_regs->port_status_base +
  1884. NUM_PORT_REGS*i;
  1885. xhci_dbg(xhci, "USB 3.0 port at index %u, "
  1886. "addr = %p\n", i,
  1887. xhci->usb3_ports[port_index]);
  1888. port_index++;
  1889. if (port_index == xhci->num_usb3_ports)
  1890. break;
  1891. }
  1892. }
  1893. return 0;
  1894. }
  1895. int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
  1896. {
  1897. dma_addr_t dma;
  1898. struct device *dev = xhci_to_hcd(xhci)->self.controller;
  1899. unsigned int val, val2;
  1900. u64 val_64;
  1901. struct xhci_segment *seg;
  1902. u32 page_size;
  1903. int i;
  1904. page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
  1905. xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
  1906. for (i = 0; i < 16; i++) {
  1907. if ((0x1 & page_size) != 0)
  1908. break;
  1909. page_size = page_size >> 1;
  1910. }
  1911. if (i < 16)
  1912. xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
  1913. else
  1914. xhci_warn(xhci, "WARN: no supported page size\n");
  1915. /* Use 4K pages, since that's common and the minimum the HC supports */
  1916. xhci->page_shift = 12;
  1917. xhci->page_size = 1 << xhci->page_shift;
  1918. xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
  1919. /*
  1920. * Program the Number of Device Slots Enabled field in the CONFIG
  1921. * register with the max value of slots the HC can handle.
  1922. */
  1923. val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
  1924. xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
  1925. (unsigned int) val);
  1926. val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
  1927. val |= (val2 & ~HCS_SLOTS_MASK);
  1928. xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
  1929. (unsigned int) val);
  1930. xhci_writel(xhci, val, &xhci->op_regs->config_reg);
  1931. /*
  1932. * Section 5.4.8 - doorbell array must be
  1933. * "physically contiguous and 64-byte (cache line) aligned".
  1934. */
  1935. xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
  1936. sizeof(*xhci->dcbaa), &dma);
  1937. if (!xhci->dcbaa)
  1938. goto fail;
  1939. memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
  1940. xhci->dcbaa->dma = dma;
  1941. xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
  1942. (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
  1943. xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
  1944. /*
  1945. * Initialize the ring segment pool. The ring must be a contiguous
  1946. * structure comprised of TRBs. The TRBs must be 16 byte aligned,
  1947. * however, the command ring segment needs 64-byte aligned segments,
  1948. * so we pick the greater alignment need.
  1949. */
  1950. xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
  1951. SEGMENT_SIZE, 64, xhci->page_size);
  1952. /* See Table 46 and Note on Figure 55 */
  1953. xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
  1954. 2112, 64, xhci->page_size);
  1955. if (!xhci->segment_pool || !xhci->device_pool)
  1956. goto fail;
  1957. /* Linear stream context arrays don't have any boundary restrictions,
  1958. * and only need to be 16-byte aligned.
  1959. */
  1960. xhci->small_streams_pool =
  1961. dma_pool_create("xHCI 256 byte stream ctx arrays",
  1962. dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
  1963. xhci->medium_streams_pool =
  1964. dma_pool_create("xHCI 1KB stream ctx arrays",
  1965. dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
  1966. /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
  1967. * will be allocated with pci_alloc_consistent()
  1968. */
  1969. if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
  1970. goto fail;
  1971. /* Set up the command ring to have one segments for now. */
  1972. xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
  1973. if (!xhci->cmd_ring)
  1974. goto fail;
  1975. xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
  1976. xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
  1977. (unsigned long long)xhci->cmd_ring->first_seg->dma);
  1978. /* Set the address in the Command Ring Control register */
  1979. val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
  1980. val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
  1981. (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
  1982. xhci->cmd_ring->cycle_state;
  1983. xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
  1984. xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
  1985. xhci_dbg_cmd_ptrs(xhci);
  1986. val = xhci_readl(xhci, &xhci->cap_regs->db_off);
  1987. val &= DBOFF_MASK;
  1988. xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
  1989. " from cap regs base addr\n", val);
  1990. xhci->dba = (void __iomem *) xhci->cap_regs + val;
  1991. xhci_dbg_regs(xhci);
  1992. xhci_print_run_regs(xhci);
  1993. /* Set ir_set to interrupt register set 0 */
  1994. xhci->ir_set = &xhci->run_regs->ir_set[0];
  1995. /*
  1996. * Event ring setup: Allocate a normal ring, but also setup
  1997. * the event ring segment table (ERST). Section 4.9.3.
  1998. */
  1999. xhci_dbg(xhci, "// Allocating event ring\n");
  2000. xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
  2001. if (!xhci->event_ring)
  2002. goto fail;
  2003. if (xhci_check_trb_in_td_math(xhci, flags) < 0)
  2004. goto fail;
  2005. xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
  2006. sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
  2007. if (!xhci->erst.entries)
  2008. goto fail;
  2009. xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
  2010. (unsigned long long)dma);
  2011. memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
  2012. xhci->erst.num_entries = ERST_NUM_SEGS;
  2013. xhci->erst.erst_dma_addr = dma;
  2014. xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
  2015. xhci->erst.num_entries,
  2016. xhci->erst.entries,
  2017. (unsigned long long)xhci->erst.erst_dma_addr);
  2018. /* set ring base address and size for each segment table entry */
  2019. for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
  2020. struct xhci_erst_entry *entry = &xhci->erst.entries[val];
  2021. entry->seg_addr = cpu_to_le64(seg->dma);
  2022. entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
  2023. entry->rsvd = 0;
  2024. seg = seg->next;
  2025. }
  2026. /* set ERST count with the number of entries in the segment table */
  2027. val = xhci_readl(xhci, &xhci->ir_set->erst_size);
  2028. val &= ERST_SIZE_MASK;
  2029. val |= ERST_NUM_SEGS;
  2030. xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
  2031. val);
  2032. xhci_writel(xhci, val, &xhci->ir_set->erst_size);
  2033. xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
  2034. /* set the segment table base address */
  2035. xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
  2036. (unsigned long long)xhci->erst.erst_dma_addr);
  2037. val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
  2038. val_64 &= ERST_PTR_MASK;
  2039. val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
  2040. xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
  2041. /* Set the event ring dequeue address */
  2042. xhci_set_hc_event_deq(xhci);
  2043. xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
  2044. xhci_print_ir_set(xhci, 0);
  2045. /*
  2046. * XXX: Might need to set the Interrupter Moderation Register to
  2047. * something other than the default (~1ms minimum between interrupts).
  2048. * See section 5.5.1.2.
  2049. */
  2050. init_completion(&xhci->addr_dev);
  2051. for (i = 0; i < MAX_HC_SLOTS; ++i)
  2052. xhci->devs[i] = NULL;
  2053. for (i = 0; i < USB_MAXCHILDREN; ++i) {
  2054. xhci->bus_state[0].resume_done[i] = 0;
  2055. xhci->bus_state[1].resume_done[i] = 0;
  2056. }
  2057. if (scratchpad_alloc(xhci, flags))
  2058. goto fail;
  2059. if (xhci_setup_port_arrays(xhci, flags))
  2060. goto fail;
  2061. return 0;
  2062. fail:
  2063. xhci_warn(xhci, "Couldn't initialize memory\n");
  2064. xhci_mem_cleanup(xhci);
  2065. return -ENOMEM;
  2066. }