eeprom.c 14 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
  18. {
  19. REG_WRITE(ah, reg, val);
  20. if (ah->config.analog_shiftreg)
  21. udelay(100);
  22. }
  23. void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
  24. u32 shift, u32 val)
  25. {
  26. u32 regVal;
  27. regVal = REG_READ(ah, reg) & ~mask;
  28. regVal |= (val << shift) & mask;
  29. REG_WRITE(ah, reg, regVal);
  30. if (ah->config.analog_shiftreg)
  31. udelay(100);
  32. }
  33. int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
  34. int16_t targetLeft, int16_t targetRight)
  35. {
  36. int16_t rv;
  37. if (srcRight == srcLeft) {
  38. rv = targetLeft;
  39. } else {
  40. rv = (int16_t) (((target - srcLeft) * targetRight +
  41. (srcRight - target) * targetLeft) /
  42. (srcRight - srcLeft));
  43. }
  44. return rv;
  45. }
  46. bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
  47. u16 *indexL, u16 *indexR)
  48. {
  49. u16 i;
  50. if (target <= pList[0]) {
  51. *indexL = *indexR = 0;
  52. return true;
  53. }
  54. if (target >= pList[listSize - 1]) {
  55. *indexL = *indexR = (u16) (listSize - 1);
  56. return true;
  57. }
  58. for (i = 0; i < listSize - 1; i++) {
  59. if (pList[i] == target) {
  60. *indexL = *indexR = i;
  61. return true;
  62. }
  63. if (target < pList[i + 1]) {
  64. *indexL = i;
  65. *indexR = (u16) (i + 1);
  66. return false;
  67. }
  68. }
  69. return false;
  70. }
  71. void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
  72. int eep_start_loc, int size)
  73. {
  74. int i = 0, j, addr;
  75. u32 addrdata[8];
  76. u32 data[8];
  77. for (addr = 0; addr < size; addr++) {
  78. addrdata[i] = AR5416_EEPROM_OFFSET +
  79. ((addr + eep_start_loc) << AR5416_EEPROM_S);
  80. i++;
  81. if (i == 8) {
  82. REG_READ_MULTI(ah, addrdata, data, i);
  83. for (j = 0; j < i; j++) {
  84. *eep_data = data[j];
  85. eep_data++;
  86. }
  87. i = 0;
  88. }
  89. }
  90. if (i != 0) {
  91. REG_READ_MULTI(ah, addrdata, data, i);
  92. for (j = 0; j < i; j++) {
  93. *eep_data = data[j];
  94. eep_data++;
  95. }
  96. }
  97. }
  98. bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
  99. {
  100. bool ret;
  101. ret = common->bus_ops->eeprom_read(common, off, data);
  102. if (!ret)
  103. ath_dbg(common, EEPROM, "Unable to read eeprom region\n");
  104. return ret;
  105. }
  106. void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
  107. u8 *pVpdList, u16 numIntercepts,
  108. u8 *pRetVpdList)
  109. {
  110. u16 i, k;
  111. u8 currPwr = pwrMin;
  112. u16 idxL = 0, idxR = 0;
  113. for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
  114. ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
  115. numIntercepts, &(idxL),
  116. &(idxR));
  117. if (idxR < 1)
  118. idxR = 1;
  119. if (idxL == numIntercepts - 1)
  120. idxL = (u16) (numIntercepts - 2);
  121. if (pPwrList[idxL] == pPwrList[idxR])
  122. k = pVpdList[idxL];
  123. else
  124. k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
  125. (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
  126. (pPwrList[idxR] - pPwrList[idxL]));
  127. pRetVpdList[i] = (u8) k;
  128. currPwr += 2;
  129. }
  130. }
  131. void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
  132. struct ath9k_channel *chan,
  133. struct cal_target_power_leg *powInfo,
  134. u16 numChannels,
  135. struct cal_target_power_leg *pNewPower,
  136. u16 numRates, bool isExtTarget)
  137. {
  138. struct chan_centers centers;
  139. u16 clo, chi;
  140. int i;
  141. int matchIndex = -1, lowIndex = -1;
  142. u16 freq;
  143. ath9k_hw_get_channel_centers(ah, chan, &centers);
  144. freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
  145. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
  146. IS_CHAN_2GHZ(chan))) {
  147. matchIndex = 0;
  148. } else {
  149. for (i = 0; (i < numChannels) &&
  150. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  151. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  152. IS_CHAN_2GHZ(chan))) {
  153. matchIndex = i;
  154. break;
  155. } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  156. IS_CHAN_2GHZ(chan)) && i > 0 &&
  157. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  158. IS_CHAN_2GHZ(chan))) {
  159. lowIndex = i - 1;
  160. break;
  161. }
  162. }
  163. if ((matchIndex == -1) && (lowIndex == -1))
  164. matchIndex = i - 1;
  165. }
  166. if (matchIndex != -1) {
  167. *pNewPower = powInfo[matchIndex];
  168. } else {
  169. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  170. IS_CHAN_2GHZ(chan));
  171. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  172. IS_CHAN_2GHZ(chan));
  173. for (i = 0; i < numRates; i++) {
  174. pNewPower->tPow2x[i] =
  175. (u8)ath9k_hw_interpolate(freq, clo, chi,
  176. powInfo[lowIndex].tPow2x[i],
  177. powInfo[lowIndex + 1].tPow2x[i]);
  178. }
  179. }
  180. }
  181. void ath9k_hw_get_target_powers(struct ath_hw *ah,
  182. struct ath9k_channel *chan,
  183. struct cal_target_power_ht *powInfo,
  184. u16 numChannels,
  185. struct cal_target_power_ht *pNewPower,
  186. u16 numRates, bool isHt40Target)
  187. {
  188. struct chan_centers centers;
  189. u16 clo, chi;
  190. int i;
  191. int matchIndex = -1, lowIndex = -1;
  192. u16 freq;
  193. ath9k_hw_get_channel_centers(ah, chan, &centers);
  194. freq = isHt40Target ? centers.synth_center : centers.ctl_center;
  195. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
  196. matchIndex = 0;
  197. } else {
  198. for (i = 0; (i < numChannels) &&
  199. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  200. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  201. IS_CHAN_2GHZ(chan))) {
  202. matchIndex = i;
  203. break;
  204. } else
  205. if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  206. IS_CHAN_2GHZ(chan)) && i > 0 &&
  207. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  208. IS_CHAN_2GHZ(chan))) {
  209. lowIndex = i - 1;
  210. break;
  211. }
  212. }
  213. if ((matchIndex == -1) && (lowIndex == -1))
  214. matchIndex = i - 1;
  215. }
  216. if (matchIndex != -1) {
  217. *pNewPower = powInfo[matchIndex];
  218. } else {
  219. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  220. IS_CHAN_2GHZ(chan));
  221. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  222. IS_CHAN_2GHZ(chan));
  223. for (i = 0; i < numRates; i++) {
  224. pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
  225. clo, chi,
  226. powInfo[lowIndex].tPow2x[i],
  227. powInfo[lowIndex + 1].tPow2x[i]);
  228. }
  229. }
  230. }
  231. u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
  232. bool is2GHz, int num_band_edges)
  233. {
  234. u16 twiceMaxEdgePower = MAX_RATE_POWER;
  235. int i;
  236. for (i = 0; (i < num_band_edges) &&
  237. (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  238. if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
  239. twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
  240. break;
  241. } else if ((i > 0) &&
  242. (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
  243. is2GHz))) {
  244. if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
  245. is2GHz) < freq &&
  246. CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
  247. twiceMaxEdgePower =
  248. CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
  249. }
  250. break;
  251. }
  252. }
  253. return twiceMaxEdgePower;
  254. }
  255. u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
  256. u8 antenna_reduction)
  257. {
  258. u16 reduction = antenna_reduction;
  259. /*
  260. * Reduce scaled Power by number of chains active
  261. * to get the per chain tx power level.
  262. */
  263. switch (ar5416_get_ntxchains(ah->txchainmask)) {
  264. case 1:
  265. break;
  266. case 2:
  267. reduction += POWER_CORRECTION_FOR_TWO_CHAIN;
  268. break;
  269. case 3:
  270. reduction += POWER_CORRECTION_FOR_THREE_CHAIN;
  271. break;
  272. }
  273. if (power_limit > reduction)
  274. power_limit -= reduction;
  275. else
  276. power_limit = 0;
  277. return power_limit;
  278. }
  279. void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
  280. {
  281. struct ath_common *common = ath9k_hw_common(ah);
  282. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  283. switch (ar5416_get_ntxchains(ah->txchainmask)) {
  284. case 1:
  285. break;
  286. case 2:
  287. regulatory->max_power_level += POWER_CORRECTION_FOR_TWO_CHAIN;
  288. break;
  289. case 3:
  290. regulatory->max_power_level += POWER_CORRECTION_FOR_THREE_CHAIN;
  291. break;
  292. default:
  293. ath_dbg(common, EEPROM, "Invalid chainmask configuration\n");
  294. break;
  295. }
  296. }
  297. void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
  298. struct ath9k_channel *chan,
  299. void *pRawDataSet,
  300. u8 *bChans, u16 availPiers,
  301. u16 tPdGainOverlap,
  302. u16 *pPdGainBoundaries, u8 *pPDADCValues,
  303. u16 numXpdGains)
  304. {
  305. int i, j, k;
  306. int16_t ss;
  307. u16 idxL = 0, idxR = 0, numPiers;
  308. static u8 vpdTableL[AR5416_NUM_PD_GAINS]
  309. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  310. static u8 vpdTableR[AR5416_NUM_PD_GAINS]
  311. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  312. static u8 vpdTableI[AR5416_NUM_PD_GAINS]
  313. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  314. u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
  315. u8 minPwrT4[AR5416_NUM_PD_GAINS];
  316. u8 maxPwrT4[AR5416_NUM_PD_GAINS];
  317. int16_t vpdStep;
  318. int16_t tmpVal;
  319. u16 sizeCurrVpdTable, maxIndex, tgtIndex;
  320. bool match;
  321. int16_t minDelta = 0;
  322. struct chan_centers centers;
  323. int pdgain_boundary_default;
  324. struct cal_data_per_freq *data_def = pRawDataSet;
  325. struct cal_data_per_freq_4k *data_4k = pRawDataSet;
  326. struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
  327. bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
  328. int intercepts;
  329. if (AR_SREV_9287(ah))
  330. intercepts = AR9287_PD_GAIN_ICEPTS;
  331. else
  332. intercepts = AR5416_PD_GAIN_ICEPTS;
  333. memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
  334. ath9k_hw_get_channel_centers(ah, chan, &centers);
  335. for (numPiers = 0; numPiers < availPiers; numPiers++) {
  336. if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
  337. break;
  338. }
  339. match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
  340. IS_CHAN_2GHZ(chan)),
  341. bChans, numPiers, &idxL, &idxR);
  342. if (match) {
  343. if (AR_SREV_9287(ah)) {
  344. /* FIXME: array overrun? */
  345. for (i = 0; i < numXpdGains; i++) {
  346. minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
  347. maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
  348. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  349. data_9287[idxL].pwrPdg[i],
  350. data_9287[idxL].vpdPdg[i],
  351. intercepts,
  352. vpdTableI[i]);
  353. }
  354. } else if (eeprom_4k) {
  355. for (i = 0; i < numXpdGains; i++) {
  356. minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
  357. maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
  358. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  359. data_4k[idxL].pwrPdg[i],
  360. data_4k[idxL].vpdPdg[i],
  361. intercepts,
  362. vpdTableI[i]);
  363. }
  364. } else {
  365. for (i = 0; i < numXpdGains; i++) {
  366. minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
  367. maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
  368. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  369. data_def[idxL].pwrPdg[i],
  370. data_def[idxL].vpdPdg[i],
  371. intercepts,
  372. vpdTableI[i]);
  373. }
  374. }
  375. } else {
  376. for (i = 0; i < numXpdGains; i++) {
  377. if (AR_SREV_9287(ah)) {
  378. pVpdL = data_9287[idxL].vpdPdg[i];
  379. pPwrL = data_9287[idxL].pwrPdg[i];
  380. pVpdR = data_9287[idxR].vpdPdg[i];
  381. pPwrR = data_9287[idxR].pwrPdg[i];
  382. } else if (eeprom_4k) {
  383. pVpdL = data_4k[idxL].vpdPdg[i];
  384. pPwrL = data_4k[idxL].pwrPdg[i];
  385. pVpdR = data_4k[idxR].vpdPdg[i];
  386. pPwrR = data_4k[idxR].pwrPdg[i];
  387. } else {
  388. pVpdL = data_def[idxL].vpdPdg[i];
  389. pPwrL = data_def[idxL].pwrPdg[i];
  390. pVpdR = data_def[idxR].vpdPdg[i];
  391. pPwrR = data_def[idxR].pwrPdg[i];
  392. }
  393. minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
  394. maxPwrT4[i] =
  395. min(pPwrL[intercepts - 1],
  396. pPwrR[intercepts - 1]);
  397. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  398. pPwrL, pVpdL,
  399. intercepts,
  400. vpdTableL[i]);
  401. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  402. pPwrR, pVpdR,
  403. intercepts,
  404. vpdTableR[i]);
  405. for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
  406. vpdTableI[i][j] =
  407. (u8)(ath9k_hw_interpolate((u16)
  408. FREQ2FBIN(centers.
  409. synth_center,
  410. IS_CHAN_2GHZ
  411. (chan)),
  412. bChans[idxL], bChans[idxR],
  413. vpdTableL[i][j], vpdTableR[i][j]));
  414. }
  415. }
  416. }
  417. k = 0;
  418. for (i = 0; i < numXpdGains; i++) {
  419. if (i == (numXpdGains - 1))
  420. pPdGainBoundaries[i] =
  421. (u16)(maxPwrT4[i] / 2);
  422. else
  423. pPdGainBoundaries[i] =
  424. (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
  425. pPdGainBoundaries[i] =
  426. min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
  427. minDelta = 0;
  428. if (i == 0) {
  429. if (AR_SREV_9280_20_OR_LATER(ah))
  430. ss = (int16_t)(0 - (minPwrT4[i] / 2));
  431. else
  432. ss = 0;
  433. } else {
  434. ss = (int16_t)((pPdGainBoundaries[i - 1] -
  435. (minPwrT4[i] / 2)) -
  436. tPdGainOverlap + 1 + minDelta);
  437. }
  438. vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
  439. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  440. while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  441. tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
  442. pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
  443. ss++;
  444. }
  445. sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
  446. tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
  447. (minPwrT4[i] / 2));
  448. maxIndex = (tgtIndex < sizeCurrVpdTable) ?
  449. tgtIndex : sizeCurrVpdTable;
  450. while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  451. pPDADCValues[k++] = vpdTableI[i][ss++];
  452. }
  453. vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
  454. vpdTableI[i][sizeCurrVpdTable - 2]);
  455. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  456. if (tgtIndex >= maxIndex) {
  457. while ((ss <= tgtIndex) &&
  458. (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  459. tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
  460. (ss - maxIndex + 1) * vpdStep));
  461. pPDADCValues[k++] = (u8)((tmpVal > 255) ?
  462. 255 : tmpVal);
  463. ss++;
  464. }
  465. }
  466. }
  467. if (eeprom_4k)
  468. pdgain_boundary_default = 58;
  469. else
  470. pdgain_boundary_default = pPdGainBoundaries[i - 1];
  471. while (i < AR5416_PD_GAINS_IN_MASK) {
  472. pPdGainBoundaries[i] = pdgain_boundary_default;
  473. i++;
  474. }
  475. while (k < AR5416_NUM_PDADC_VALUES) {
  476. pPDADCValues[k] = pPDADCValues[k - 1];
  477. k++;
  478. }
  479. }
  480. int ath9k_hw_eeprom_init(struct ath_hw *ah)
  481. {
  482. int status;
  483. if (AR_SREV_9300_20_OR_LATER(ah))
  484. ah->eep_ops = &eep_ar9300_ops;
  485. else if (AR_SREV_9287(ah)) {
  486. ah->eep_ops = &eep_ar9287_ops;
  487. } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
  488. ah->eep_ops = &eep_4k_ops;
  489. } else {
  490. ah->eep_ops = &eep_def_ops;
  491. }
  492. if (!ah->eep_ops->fill_eeprom(ah))
  493. return -EIO;
  494. status = ah->eep_ops->check_eeprom(ah);
  495. return status;
  496. }