hdmi_drv.c 26 KB

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  1. /*
  2. * Samsung HDMI interface driver
  3. *
  4. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  5. *
  6. * Tomasz Stanislawski, <t.stanislaws@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published
  10. * by the Free Software Foundiation. either version 2 of the License,
  11. * or (at your option) any later version
  12. */
  13. #ifdef CONFIG_VIDEO_SAMSUNG_S5P_HDMI_DEBUG
  14. #define DEBUG
  15. #endif
  16. #include <linux/kernel.h>
  17. #include <linux/slab.h>
  18. #include <linux/io.h>
  19. #include <linux/i2c.h>
  20. #include <linux/platform_device.h>
  21. #include <media/v4l2-subdev.h>
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irq.h>
  25. #include <linux/delay.h>
  26. #include <linux/bug.h>
  27. #include <linux/pm_runtime.h>
  28. #include <linux/clk.h>
  29. #include <linux/regulator/consumer.h>
  30. #include <media/s5p_hdmi.h>
  31. #include <media/v4l2-common.h>
  32. #include <media/v4l2-dev.h>
  33. #include <media/v4l2-device.h>
  34. #include "regs-hdmi.h"
  35. MODULE_AUTHOR("Tomasz Stanislawski, <t.stanislaws@samsung.com>");
  36. MODULE_DESCRIPTION("Samsung HDMI");
  37. MODULE_LICENSE("GPL");
  38. /* default preset configured on probe */
  39. #define HDMI_DEFAULT_PRESET V4L2_DV_480P59_94
  40. struct hdmi_pulse {
  41. u32 beg;
  42. u32 end;
  43. };
  44. struct hdmi_timings {
  45. struct hdmi_pulse hact;
  46. u32 hsyn_pol; /* 0 - high, 1 - low */
  47. struct hdmi_pulse hsyn;
  48. u32 interlaced;
  49. struct hdmi_pulse vact[2];
  50. u32 vsyn_pol; /* 0 - high, 1 - low */
  51. u32 vsyn_off;
  52. struct hdmi_pulse vsyn[2];
  53. };
  54. struct hdmi_resources {
  55. struct clk *hdmi;
  56. struct clk *sclk_hdmi;
  57. struct clk *sclk_pixel;
  58. struct clk *sclk_hdmiphy;
  59. struct clk *hdmiphy;
  60. struct regulator_bulk_data *regul_bulk;
  61. int regul_count;
  62. };
  63. struct hdmi_device {
  64. /** base address of HDMI registers */
  65. void __iomem *regs;
  66. /** HDMI interrupt */
  67. unsigned int irq;
  68. /** pointer to device parent */
  69. struct device *dev;
  70. /** subdev generated by HDMI device */
  71. struct v4l2_subdev sd;
  72. /** V4L2 device structure */
  73. struct v4l2_device v4l2_dev;
  74. /** subdev of HDMIPHY interface */
  75. struct v4l2_subdev *phy_sd;
  76. /** subdev of MHL interface */
  77. struct v4l2_subdev *mhl_sd;
  78. /** configuration of current graphic mode */
  79. const struct hdmi_timings *cur_conf;
  80. /** flag indicating that timings are dirty */
  81. int cur_conf_dirty;
  82. /** current preset */
  83. u32 cur_preset;
  84. /** other resources */
  85. struct hdmi_resources res;
  86. };
  87. static struct platform_device_id hdmi_driver_types[] = {
  88. {
  89. .name = "s5pv210-hdmi",
  90. }, {
  91. .name = "exynos4-hdmi",
  92. }, {
  93. /* end node */
  94. }
  95. };
  96. static const struct v4l2_subdev_ops hdmi_sd_ops;
  97. static struct hdmi_device *sd_to_hdmi_dev(struct v4l2_subdev *sd)
  98. {
  99. return container_of(sd, struct hdmi_device, sd);
  100. }
  101. static inline
  102. void hdmi_write(struct hdmi_device *hdev, u32 reg_id, u32 value)
  103. {
  104. writel(value, hdev->regs + reg_id);
  105. }
  106. static inline
  107. void hdmi_write_mask(struct hdmi_device *hdev, u32 reg_id, u32 value, u32 mask)
  108. {
  109. u32 old = readl(hdev->regs + reg_id);
  110. value = (value & mask) | (old & ~mask);
  111. writel(value, hdev->regs + reg_id);
  112. }
  113. static inline
  114. void hdmi_writeb(struct hdmi_device *hdev, u32 reg_id, u8 value)
  115. {
  116. writeb(value, hdev->regs + reg_id);
  117. }
  118. static inline
  119. void hdmi_writebn(struct hdmi_device *hdev, u32 reg_id, int n, u32 value)
  120. {
  121. switch (n) {
  122. default:
  123. writeb(value >> 24, hdev->regs + reg_id + 12);
  124. case 3:
  125. writeb(value >> 16, hdev->regs + reg_id + 8);
  126. case 2:
  127. writeb(value >> 8, hdev->regs + reg_id + 4);
  128. case 1:
  129. writeb(value >> 0, hdev->regs + reg_id + 0);
  130. }
  131. }
  132. static inline u32 hdmi_read(struct hdmi_device *hdev, u32 reg_id)
  133. {
  134. return readl(hdev->regs + reg_id);
  135. }
  136. static irqreturn_t hdmi_irq_handler(int irq, void *dev_data)
  137. {
  138. struct hdmi_device *hdev = dev_data;
  139. u32 intc_flag;
  140. (void)irq;
  141. intc_flag = hdmi_read(hdev, HDMI_INTC_FLAG);
  142. /* clearing flags for HPD plug/unplug */
  143. if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
  144. printk(KERN_INFO "unplugged\n");
  145. hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0,
  146. HDMI_INTC_FLAG_HPD_UNPLUG);
  147. }
  148. if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
  149. printk(KERN_INFO "plugged\n");
  150. hdmi_write_mask(hdev, HDMI_INTC_FLAG, ~0,
  151. HDMI_INTC_FLAG_HPD_PLUG);
  152. }
  153. return IRQ_HANDLED;
  154. }
  155. static void hdmi_reg_init(struct hdmi_device *hdev)
  156. {
  157. /* enable HPD interrupts */
  158. hdmi_write_mask(hdev, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
  159. HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
  160. /* choose DVI mode */
  161. hdmi_write_mask(hdev, HDMI_MODE_SEL,
  162. HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
  163. hdmi_write_mask(hdev, HDMI_CON_2, ~0,
  164. HDMI_DVI_PERAMBLE_EN | HDMI_DVI_BAND_EN);
  165. /* disable bluescreen */
  166. hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
  167. /* choose bluescreen (fecal) color */
  168. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_0, 0x12);
  169. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_1, 0x34);
  170. hdmi_writeb(hdev, HDMI_BLUE_SCREEN_2, 0x56);
  171. }
  172. static void hdmi_timing_apply(struct hdmi_device *hdev,
  173. const struct hdmi_timings *t)
  174. {
  175. /* setting core registers */
  176. hdmi_writebn(hdev, HDMI_H_BLANK_0, 2, t->hact.beg);
  177. hdmi_writebn(hdev, HDMI_H_SYNC_GEN_0, 3,
  178. (t->hsyn_pol << 20) | (t->hsyn.end << 10) | t->hsyn.beg);
  179. hdmi_writeb(hdev, HDMI_VSYNC_POL, t->vsyn_pol);
  180. hdmi_writebn(hdev, HDMI_V_BLANK_0, 3,
  181. (t->vact[0].beg << 11) | t->vact[0].end);
  182. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_1_0, 3,
  183. (t->vsyn[0].beg << 12) | t->vsyn[0].end);
  184. if (t->interlaced) {
  185. u32 vsyn_trans = t->hsyn.beg + t->vsyn_off;
  186. hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 1);
  187. hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3,
  188. (t->hact.end << 12) | t->vact[1].end);
  189. hdmi_writebn(hdev, HDMI_V_BLANK_F_0, 3,
  190. (t->vact[1].end << 11) | t->vact[1].beg);
  191. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_2_0, 3,
  192. (t->vsyn[1].beg << 12) | t->vsyn[1].end);
  193. hdmi_writebn(hdev, HDMI_V_SYNC_GEN_3_0, 3,
  194. (vsyn_trans << 12) | vsyn_trans);
  195. } else {
  196. hdmi_writeb(hdev, HDMI_INT_PRO_MODE, 0);
  197. hdmi_writebn(hdev, HDMI_H_V_LINE_0, 3,
  198. (t->hact.end << 12) | t->vact[0].end);
  199. }
  200. /* Timing generator registers */
  201. hdmi_writebn(hdev, HDMI_TG_H_FSZ_L, 2, t->hact.end);
  202. hdmi_writebn(hdev, HDMI_TG_HACT_ST_L, 2, t->hact.beg);
  203. hdmi_writebn(hdev, HDMI_TG_HACT_SZ_L, 2, t->hact.end - t->hact.beg);
  204. hdmi_writebn(hdev, HDMI_TG_VSYNC_L, 2, t->vsyn[0].beg);
  205. hdmi_writebn(hdev, HDMI_TG_VACT_ST_L, 2, t->vact[0].beg);
  206. hdmi_writebn(hdev, HDMI_TG_VACT_SZ_L, 2,
  207. t->vact[0].end - t->vact[0].beg);
  208. hdmi_writebn(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, 2, t->vsyn[0].beg);
  209. hdmi_writebn(hdev, HDMI_TG_FIELD_TOP_HDMI_L, 2, t->vsyn[0].beg);
  210. if (t->interlaced) {
  211. hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_FIELD_EN);
  212. hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[1].end);
  213. hdmi_writebn(hdev, HDMI_TG_VSYNC2_L, 2, t->vsyn[1].beg);
  214. hdmi_writebn(hdev, HDMI_TG_FIELD_CHG_L, 2, t->vact[0].end);
  215. hdmi_writebn(hdev, HDMI_TG_VACT_ST2_L, 2, t->vact[1].beg);
  216. hdmi_writebn(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, 2, t->vsyn[1].beg);
  217. hdmi_writebn(hdev, HDMI_TG_FIELD_BOT_HDMI_L, 2, t->vsyn[1].beg);
  218. } else {
  219. hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_FIELD_EN);
  220. hdmi_writebn(hdev, HDMI_TG_V_FSZ_L, 2, t->vact[0].end);
  221. }
  222. }
  223. static int hdmi_conf_apply(struct hdmi_device *hdmi_dev)
  224. {
  225. struct device *dev = hdmi_dev->dev;
  226. const struct hdmi_timings *conf = hdmi_dev->cur_conf;
  227. struct v4l2_dv_preset preset;
  228. int ret;
  229. dev_dbg(dev, "%s\n", __func__);
  230. /* skip if conf is already synchronized with HW */
  231. if (!hdmi_dev->cur_conf_dirty)
  232. return 0;
  233. /* reset hdmiphy */
  234. hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
  235. mdelay(10);
  236. hdmi_write_mask(hdmi_dev, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
  237. mdelay(10);
  238. /* configure presets */
  239. preset.preset = hdmi_dev->cur_preset;
  240. ret = v4l2_subdev_call(hdmi_dev->phy_sd, video, s_dv_preset, &preset);
  241. if (ret) {
  242. dev_err(dev, "failed to set preset (%u)\n", preset.preset);
  243. return ret;
  244. }
  245. /* resetting HDMI core */
  246. hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, 0, HDMI_CORE_SW_RSTOUT);
  247. mdelay(10);
  248. hdmi_write_mask(hdmi_dev, HDMI_CORE_RSTOUT, ~0, HDMI_CORE_SW_RSTOUT);
  249. mdelay(10);
  250. hdmi_reg_init(hdmi_dev);
  251. /* setting core registers */
  252. hdmi_timing_apply(hdmi_dev, conf);
  253. hdmi_dev->cur_conf_dirty = 0;
  254. return 0;
  255. }
  256. static void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix)
  257. {
  258. #define DUMPREG(reg_id) \
  259. dev_dbg(hdev->dev, "%s:" #reg_id " = %08x\n", prefix, \
  260. readl(hdev->regs + reg_id))
  261. dev_dbg(hdev->dev, "%s: ---- CONTROL REGISTERS ----\n", prefix);
  262. DUMPREG(HDMI_INTC_FLAG);
  263. DUMPREG(HDMI_INTC_CON);
  264. DUMPREG(HDMI_HPD_STATUS);
  265. DUMPREG(HDMI_PHY_RSTOUT);
  266. DUMPREG(HDMI_PHY_VPLL);
  267. DUMPREG(HDMI_PHY_CMU);
  268. DUMPREG(HDMI_CORE_RSTOUT);
  269. dev_dbg(hdev->dev, "%s: ---- CORE REGISTERS ----\n", prefix);
  270. DUMPREG(HDMI_CON_0);
  271. DUMPREG(HDMI_CON_1);
  272. DUMPREG(HDMI_CON_2);
  273. DUMPREG(HDMI_SYS_STATUS);
  274. DUMPREG(HDMI_PHY_STATUS);
  275. DUMPREG(HDMI_STATUS_EN);
  276. DUMPREG(HDMI_HPD);
  277. DUMPREG(HDMI_MODE_SEL);
  278. DUMPREG(HDMI_HPD_GEN);
  279. DUMPREG(HDMI_DC_CONTROL);
  280. DUMPREG(HDMI_VIDEO_PATTERN_GEN);
  281. dev_dbg(hdev->dev, "%s: ---- CORE SYNC REGISTERS ----\n", prefix);
  282. DUMPREG(HDMI_H_BLANK_0);
  283. DUMPREG(HDMI_H_BLANK_1);
  284. DUMPREG(HDMI_V_BLANK_0);
  285. DUMPREG(HDMI_V_BLANK_1);
  286. DUMPREG(HDMI_V_BLANK_2);
  287. DUMPREG(HDMI_H_V_LINE_0);
  288. DUMPREG(HDMI_H_V_LINE_1);
  289. DUMPREG(HDMI_H_V_LINE_2);
  290. DUMPREG(HDMI_VSYNC_POL);
  291. DUMPREG(HDMI_INT_PRO_MODE);
  292. DUMPREG(HDMI_V_BLANK_F_0);
  293. DUMPREG(HDMI_V_BLANK_F_1);
  294. DUMPREG(HDMI_V_BLANK_F_2);
  295. DUMPREG(HDMI_H_SYNC_GEN_0);
  296. DUMPREG(HDMI_H_SYNC_GEN_1);
  297. DUMPREG(HDMI_H_SYNC_GEN_2);
  298. DUMPREG(HDMI_V_SYNC_GEN_1_0);
  299. DUMPREG(HDMI_V_SYNC_GEN_1_1);
  300. DUMPREG(HDMI_V_SYNC_GEN_1_2);
  301. DUMPREG(HDMI_V_SYNC_GEN_2_0);
  302. DUMPREG(HDMI_V_SYNC_GEN_2_1);
  303. DUMPREG(HDMI_V_SYNC_GEN_2_2);
  304. DUMPREG(HDMI_V_SYNC_GEN_3_0);
  305. DUMPREG(HDMI_V_SYNC_GEN_3_1);
  306. DUMPREG(HDMI_V_SYNC_GEN_3_2);
  307. dev_dbg(hdev->dev, "%s: ---- TG REGISTERS ----\n", prefix);
  308. DUMPREG(HDMI_TG_CMD);
  309. DUMPREG(HDMI_TG_H_FSZ_L);
  310. DUMPREG(HDMI_TG_H_FSZ_H);
  311. DUMPREG(HDMI_TG_HACT_ST_L);
  312. DUMPREG(HDMI_TG_HACT_ST_H);
  313. DUMPREG(HDMI_TG_HACT_SZ_L);
  314. DUMPREG(HDMI_TG_HACT_SZ_H);
  315. DUMPREG(HDMI_TG_V_FSZ_L);
  316. DUMPREG(HDMI_TG_V_FSZ_H);
  317. DUMPREG(HDMI_TG_VSYNC_L);
  318. DUMPREG(HDMI_TG_VSYNC_H);
  319. DUMPREG(HDMI_TG_VSYNC2_L);
  320. DUMPREG(HDMI_TG_VSYNC2_H);
  321. DUMPREG(HDMI_TG_VACT_ST_L);
  322. DUMPREG(HDMI_TG_VACT_ST_H);
  323. DUMPREG(HDMI_TG_VACT_SZ_L);
  324. DUMPREG(HDMI_TG_VACT_SZ_H);
  325. DUMPREG(HDMI_TG_FIELD_CHG_L);
  326. DUMPREG(HDMI_TG_FIELD_CHG_H);
  327. DUMPREG(HDMI_TG_VACT_ST2_L);
  328. DUMPREG(HDMI_TG_VACT_ST2_H);
  329. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
  330. DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
  331. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
  332. DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
  333. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
  334. DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
  335. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
  336. DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
  337. #undef DUMPREG
  338. }
  339. static const struct hdmi_timings hdmi_timings_480p = {
  340. .hact = { .beg = 138, .end = 858 },
  341. .hsyn_pol = 1,
  342. .hsyn = { .beg = 16, .end = 16 + 62 },
  343. .interlaced = 0,
  344. .vact[0] = { .beg = 42 + 3, .end = 522 + 3 },
  345. .vsyn_pol = 1,
  346. .vsyn[0] = { .beg = 6 + 3, .end = 12 + 3},
  347. };
  348. static const struct hdmi_timings hdmi_timings_576p50 = {
  349. .hact = { .beg = 144, .end = 864 },
  350. .hsyn_pol = 1,
  351. .hsyn = { .beg = 12, .end = 12 + 64 },
  352. .interlaced = 0,
  353. .vact[0] = { .beg = 44 + 5, .end = 620 + 5 },
  354. .vsyn_pol = 1,
  355. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  356. };
  357. static const struct hdmi_timings hdmi_timings_720p60 = {
  358. .hact = { .beg = 370, .end = 1650 },
  359. .hsyn_pol = 0,
  360. .hsyn = { .beg = 110, .end = 110 + 40 },
  361. .interlaced = 0,
  362. .vact[0] = { .beg = 25 + 5, .end = 745 + 5 },
  363. .vsyn_pol = 0,
  364. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  365. };
  366. static const struct hdmi_timings hdmi_timings_720p50 = {
  367. .hact = { .beg = 700, .end = 1980 },
  368. .hsyn_pol = 0,
  369. .hsyn = { .beg = 440, .end = 440 + 40 },
  370. .interlaced = 0,
  371. .vact[0] = { .beg = 25 + 5, .end = 745 + 5 },
  372. .vsyn_pol = 0,
  373. .vsyn[0] = { .beg = 0 + 5, .end = 5 + 5},
  374. };
  375. static const struct hdmi_timings hdmi_timings_1080p24 = {
  376. .hact = { .beg = 830, .end = 2750 },
  377. .hsyn_pol = 0,
  378. .hsyn = { .beg = 638, .end = 638 + 44 },
  379. .interlaced = 0,
  380. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  381. .vsyn_pol = 0,
  382. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  383. };
  384. static const struct hdmi_timings hdmi_timings_1080p60 = {
  385. .hact = { .beg = 280, .end = 2200 },
  386. .hsyn_pol = 0,
  387. .hsyn = { .beg = 88, .end = 88 + 44 },
  388. .interlaced = 0,
  389. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  390. .vsyn_pol = 0,
  391. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  392. };
  393. static const struct hdmi_timings hdmi_timings_1080i60 = {
  394. .hact = { .beg = 280, .end = 2200 },
  395. .hsyn_pol = 0,
  396. .hsyn = { .beg = 88, .end = 88 + 44 },
  397. .interlaced = 1,
  398. .vact[0] = { .beg = 20 + 2, .end = 560 + 2 },
  399. .vact[1] = { .beg = 583 + 2, .end = 1123 + 2 },
  400. .vsyn_pol = 0,
  401. .vsyn_off = 1100,
  402. .vsyn[0] = { .beg = 0 + 2, .end = 5 + 2},
  403. .vsyn[1] = { .beg = 562 + 2, .end = 567 + 2},
  404. };
  405. static const struct hdmi_timings hdmi_timings_1080i50 = {
  406. .hact = { .beg = 720, .end = 2640 },
  407. .hsyn_pol = 0,
  408. .hsyn = { .beg = 528, .end = 528 + 44 },
  409. .interlaced = 1,
  410. .vact[0] = { .beg = 20 + 2, .end = 560 + 2 },
  411. .vact[1] = { .beg = 583 + 2, .end = 1123 + 2 },
  412. .vsyn_pol = 0,
  413. .vsyn_off = 1320,
  414. .vsyn[0] = { .beg = 0 + 2, .end = 5 + 2},
  415. .vsyn[1] = { .beg = 562 + 2, .end = 567 + 2},
  416. };
  417. static const struct hdmi_timings hdmi_timings_1080p50 = {
  418. .hact = { .beg = 720, .end = 2640 },
  419. .hsyn_pol = 0,
  420. .hsyn = { .beg = 528, .end = 528 + 44 },
  421. .interlaced = 0,
  422. .vact[0] = { .beg = 41 + 4, .end = 1121 + 4 },
  423. .vsyn_pol = 0,
  424. .vsyn[0] = { .beg = 0 + 4, .end = 5 + 4},
  425. };
  426. static const struct {
  427. u32 preset;
  428. const struct hdmi_timings *timings;
  429. } hdmi_timings[] = {
  430. { V4L2_DV_480P59_94, &hdmi_timings_480p },
  431. { V4L2_DV_576P50, &hdmi_timings_576p50 },
  432. { V4L2_DV_720P50, &hdmi_timings_720p50 },
  433. { V4L2_DV_720P59_94, &hdmi_timings_720p60 },
  434. { V4L2_DV_720P60, &hdmi_timings_720p60 },
  435. { V4L2_DV_1080P24, &hdmi_timings_1080p24 },
  436. { V4L2_DV_1080P30, &hdmi_timings_1080p60 },
  437. { V4L2_DV_1080P50, &hdmi_timings_1080p50 },
  438. { V4L2_DV_1080I50, &hdmi_timings_1080i50 },
  439. { V4L2_DV_1080I60, &hdmi_timings_1080i60 },
  440. { V4L2_DV_1080P60, &hdmi_timings_1080p60 },
  441. };
  442. static const struct hdmi_timings *hdmi_preset2timings(u32 preset)
  443. {
  444. int i;
  445. for (i = 0; i < ARRAY_SIZE(hdmi_timings); ++i)
  446. if (hdmi_timings[i].preset == preset)
  447. return hdmi_timings[i].timings;
  448. return NULL;
  449. }
  450. static int hdmi_streamon(struct hdmi_device *hdev)
  451. {
  452. struct device *dev = hdev->dev;
  453. struct hdmi_resources *res = &hdev->res;
  454. int ret, tries;
  455. dev_dbg(dev, "%s\n", __func__);
  456. ret = hdmi_conf_apply(hdev);
  457. if (ret)
  458. return ret;
  459. ret = v4l2_subdev_call(hdev->phy_sd, video, s_stream, 1);
  460. if (ret)
  461. return ret;
  462. /* waiting for HDMIPHY's PLL to get to steady state */
  463. for (tries = 100; tries; --tries) {
  464. u32 val = hdmi_read(hdev, HDMI_PHY_STATUS);
  465. if (val & HDMI_PHY_STATUS_READY)
  466. break;
  467. mdelay(1);
  468. }
  469. /* steady state not achieved */
  470. if (tries == 0) {
  471. dev_err(dev, "hdmiphy's pll could not reach steady state.\n");
  472. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  473. hdmi_dumpregs(hdev, "hdmiphy - s_stream");
  474. return -EIO;
  475. }
  476. /* starting MHL */
  477. ret = v4l2_subdev_call(hdev->mhl_sd, video, s_stream, 1);
  478. if (hdev->mhl_sd && ret) {
  479. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  480. hdmi_dumpregs(hdev, "mhl - s_stream");
  481. return -EIO;
  482. }
  483. /* hdmiphy clock is used for HDMI in streaming mode */
  484. clk_disable(res->sclk_hdmi);
  485. clk_set_parent(res->sclk_hdmi, res->sclk_hdmiphy);
  486. clk_enable(res->sclk_hdmi);
  487. /* enable HDMI and timing generator */
  488. hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_EN);
  489. hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, HDMI_TG_EN);
  490. hdmi_dumpregs(hdev, "streamon");
  491. return 0;
  492. }
  493. static int hdmi_streamoff(struct hdmi_device *hdev)
  494. {
  495. struct device *dev = hdev->dev;
  496. struct hdmi_resources *res = &hdev->res;
  497. dev_dbg(dev, "%s\n", __func__);
  498. hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_EN);
  499. hdmi_write_mask(hdev, HDMI_TG_CMD, 0, HDMI_TG_EN);
  500. /* pixel(vpll) clock is used for HDMI in config mode */
  501. clk_disable(res->sclk_hdmi);
  502. clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
  503. clk_enable(res->sclk_hdmi);
  504. v4l2_subdev_call(hdev->mhl_sd, video, s_stream, 0);
  505. v4l2_subdev_call(hdev->phy_sd, video, s_stream, 0);
  506. hdmi_dumpregs(hdev, "streamoff");
  507. return 0;
  508. }
  509. static int hdmi_s_stream(struct v4l2_subdev *sd, int enable)
  510. {
  511. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  512. struct device *dev = hdev->dev;
  513. dev_dbg(dev, "%s(%d)\n", __func__, enable);
  514. if (enable)
  515. return hdmi_streamon(hdev);
  516. return hdmi_streamoff(hdev);
  517. }
  518. static void hdmi_resource_poweron(struct hdmi_resources *res)
  519. {
  520. /* turn HDMI power on */
  521. regulator_bulk_enable(res->regul_count, res->regul_bulk);
  522. /* power-on hdmi physical interface */
  523. clk_enable(res->hdmiphy);
  524. /* use VPP as parent clock; HDMIPHY is not working yet */
  525. clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
  526. /* turn clocks on */
  527. clk_enable(res->sclk_hdmi);
  528. }
  529. static void hdmi_resource_poweroff(struct hdmi_resources *res)
  530. {
  531. /* turn clocks off */
  532. clk_disable(res->sclk_hdmi);
  533. /* power-off hdmiphy */
  534. clk_disable(res->hdmiphy);
  535. /* turn HDMI power off */
  536. regulator_bulk_disable(res->regul_count, res->regul_bulk);
  537. }
  538. static int hdmi_s_power(struct v4l2_subdev *sd, int on)
  539. {
  540. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  541. int ret;
  542. if (on)
  543. ret = pm_runtime_get_sync(hdev->dev);
  544. else
  545. ret = pm_runtime_put_sync(hdev->dev);
  546. /* only values < 0 indicate errors */
  547. return IS_ERR_VALUE(ret) ? ret : 0;
  548. }
  549. static int hdmi_s_dv_preset(struct v4l2_subdev *sd,
  550. struct v4l2_dv_preset *preset)
  551. {
  552. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  553. struct device *dev = hdev->dev;
  554. const struct hdmi_timings *conf;
  555. conf = hdmi_preset2timings(preset->preset);
  556. if (conf == NULL) {
  557. dev_err(dev, "preset (%u) not supported\n", preset->preset);
  558. return -EINVAL;
  559. }
  560. hdev->cur_conf = conf;
  561. hdev->cur_conf_dirty = 1;
  562. hdev->cur_preset = preset->preset;
  563. return 0;
  564. }
  565. static int hdmi_g_dv_preset(struct v4l2_subdev *sd,
  566. struct v4l2_dv_preset *preset)
  567. {
  568. memset(preset, 0, sizeof(*preset));
  569. preset->preset = sd_to_hdmi_dev(sd)->cur_preset;
  570. return 0;
  571. }
  572. static int hdmi_g_mbus_fmt(struct v4l2_subdev *sd,
  573. struct v4l2_mbus_framefmt *fmt)
  574. {
  575. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  576. const struct hdmi_timings *t = hdev->cur_conf;
  577. dev_dbg(hdev->dev, "%s\n", __func__);
  578. if (!hdev->cur_conf)
  579. return -EINVAL;
  580. memset(fmt, 0, sizeof *fmt);
  581. fmt->width = t->hact.end - t->hact.beg;
  582. fmt->height = t->vact[0].end - t->vact[0].beg;
  583. fmt->code = V4L2_MBUS_FMT_FIXED; /* means RGB888 */
  584. fmt->colorspace = V4L2_COLORSPACE_SRGB;
  585. if (t->interlaced) {
  586. fmt->field = V4L2_FIELD_INTERLACED;
  587. fmt->height *= 2;
  588. } else {
  589. fmt->field = V4L2_FIELD_NONE;
  590. }
  591. return 0;
  592. }
  593. static int hdmi_enum_dv_presets(struct v4l2_subdev *sd,
  594. struct v4l2_dv_enum_preset *preset)
  595. {
  596. if (preset->index >= ARRAY_SIZE(hdmi_timings))
  597. return -EINVAL;
  598. return v4l_fill_dv_preset_info(hdmi_timings[preset->index].preset,
  599. preset);
  600. }
  601. static const struct v4l2_subdev_core_ops hdmi_sd_core_ops = {
  602. .s_power = hdmi_s_power,
  603. };
  604. static const struct v4l2_subdev_video_ops hdmi_sd_video_ops = {
  605. .s_dv_preset = hdmi_s_dv_preset,
  606. .g_dv_preset = hdmi_g_dv_preset,
  607. .enum_dv_presets = hdmi_enum_dv_presets,
  608. .g_mbus_fmt = hdmi_g_mbus_fmt,
  609. .s_stream = hdmi_s_stream,
  610. };
  611. static const struct v4l2_subdev_ops hdmi_sd_ops = {
  612. .core = &hdmi_sd_core_ops,
  613. .video = &hdmi_sd_video_ops,
  614. };
  615. static int hdmi_runtime_suspend(struct device *dev)
  616. {
  617. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  618. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  619. dev_dbg(dev, "%s\n", __func__);
  620. v4l2_subdev_call(hdev->mhl_sd, core, s_power, 0);
  621. hdmi_resource_poweroff(&hdev->res);
  622. /* flag that device context is lost */
  623. hdev->cur_conf_dirty = 1;
  624. return 0;
  625. }
  626. static int hdmi_runtime_resume(struct device *dev)
  627. {
  628. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  629. struct hdmi_device *hdev = sd_to_hdmi_dev(sd);
  630. int ret = 0;
  631. dev_dbg(dev, "%s\n", __func__);
  632. hdmi_resource_poweron(&hdev->res);
  633. /* starting MHL */
  634. ret = v4l2_subdev_call(hdev->mhl_sd, core, s_power, 1);
  635. if (hdev->mhl_sd && ret)
  636. goto fail;
  637. dev_dbg(dev, "poweron succeed\n");
  638. return 0;
  639. fail:
  640. hdmi_resource_poweroff(&hdev->res);
  641. dev_err(dev, "poweron failed\n");
  642. return ret;
  643. }
  644. static const struct dev_pm_ops hdmi_pm_ops = {
  645. .runtime_suspend = hdmi_runtime_suspend,
  646. .runtime_resume = hdmi_runtime_resume,
  647. };
  648. static void hdmi_resources_cleanup(struct hdmi_device *hdev)
  649. {
  650. struct hdmi_resources *res = &hdev->res;
  651. dev_dbg(hdev->dev, "HDMI resource cleanup\n");
  652. /* put clocks, power */
  653. if (res->regul_count)
  654. regulator_bulk_free(res->regul_count, res->regul_bulk);
  655. /* kfree is NULL-safe */
  656. kfree(res->regul_bulk);
  657. if (!IS_ERR_OR_NULL(res->hdmiphy))
  658. clk_put(res->hdmiphy);
  659. if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
  660. clk_put(res->sclk_hdmiphy);
  661. if (!IS_ERR_OR_NULL(res->sclk_pixel))
  662. clk_put(res->sclk_pixel);
  663. if (!IS_ERR_OR_NULL(res->sclk_hdmi))
  664. clk_put(res->sclk_hdmi);
  665. if (!IS_ERR_OR_NULL(res->hdmi))
  666. clk_put(res->hdmi);
  667. memset(res, 0, sizeof *res);
  668. }
  669. static int hdmi_resources_init(struct hdmi_device *hdev)
  670. {
  671. struct device *dev = hdev->dev;
  672. struct hdmi_resources *res = &hdev->res;
  673. static char *supply[] = {
  674. "hdmi-en",
  675. "vdd",
  676. "vdd_osc",
  677. "vdd_pll",
  678. };
  679. int i, ret;
  680. dev_dbg(dev, "HDMI resource init\n");
  681. memset(res, 0, sizeof *res);
  682. /* get clocks, power */
  683. res->hdmi = clk_get(dev, "hdmi");
  684. if (IS_ERR_OR_NULL(res->hdmi)) {
  685. dev_err(dev, "failed to get clock 'hdmi'\n");
  686. goto fail;
  687. }
  688. res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
  689. if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
  690. dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
  691. goto fail;
  692. }
  693. res->sclk_pixel = clk_get(dev, "sclk_pixel");
  694. if (IS_ERR_OR_NULL(res->sclk_pixel)) {
  695. dev_err(dev, "failed to get clock 'sclk_pixel'\n");
  696. goto fail;
  697. }
  698. res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
  699. if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
  700. dev_err(dev, "failed to get clock 'sclk_hdmiphy'\n");
  701. goto fail;
  702. }
  703. res->hdmiphy = clk_get(dev, "hdmiphy");
  704. if (IS_ERR_OR_NULL(res->hdmiphy)) {
  705. dev_err(dev, "failed to get clock 'hdmiphy'\n");
  706. goto fail;
  707. }
  708. res->regul_bulk = kcalloc(ARRAY_SIZE(supply),
  709. sizeof(res->regul_bulk[0]), GFP_KERNEL);
  710. if (!res->regul_bulk) {
  711. dev_err(dev, "failed to get memory for regulators\n");
  712. goto fail;
  713. }
  714. for (i = 0; i < ARRAY_SIZE(supply); ++i) {
  715. res->regul_bulk[i].supply = supply[i];
  716. res->regul_bulk[i].consumer = NULL;
  717. }
  718. ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
  719. if (ret) {
  720. dev_err(dev, "failed to get regulators\n");
  721. goto fail;
  722. }
  723. res->regul_count = ARRAY_SIZE(supply);
  724. return 0;
  725. fail:
  726. dev_err(dev, "HDMI resource init - failed\n");
  727. hdmi_resources_cleanup(hdev);
  728. return -ENODEV;
  729. }
  730. static int __devinit hdmi_probe(struct platform_device *pdev)
  731. {
  732. struct device *dev = &pdev->dev;
  733. struct resource *res;
  734. struct i2c_adapter *adapter;
  735. struct v4l2_subdev *sd;
  736. struct hdmi_device *hdmi_dev = NULL;
  737. struct s5p_hdmi_platform_data *pdata = dev->platform_data;
  738. int ret;
  739. dev_dbg(dev, "probe start\n");
  740. if (!pdata) {
  741. dev_err(dev, "platform data is missing\n");
  742. ret = -ENODEV;
  743. goto fail;
  744. }
  745. hdmi_dev = devm_kzalloc(&pdev->dev, sizeof(*hdmi_dev), GFP_KERNEL);
  746. if (!hdmi_dev) {
  747. dev_err(dev, "out of memory\n");
  748. ret = -ENOMEM;
  749. goto fail;
  750. }
  751. hdmi_dev->dev = dev;
  752. ret = hdmi_resources_init(hdmi_dev);
  753. if (ret)
  754. goto fail;
  755. /* mapping HDMI registers */
  756. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  757. if (res == NULL) {
  758. dev_err(dev, "get memory resource failed.\n");
  759. ret = -ENXIO;
  760. goto fail_init;
  761. }
  762. hdmi_dev->regs = devm_ioremap(&pdev->dev, res->start,
  763. resource_size(res));
  764. if (hdmi_dev->regs == NULL) {
  765. dev_err(dev, "register mapping failed.\n");
  766. ret = -ENXIO;
  767. goto fail_init;
  768. }
  769. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  770. if (res == NULL) {
  771. dev_err(dev, "get interrupt resource failed.\n");
  772. ret = -ENXIO;
  773. goto fail_init;
  774. }
  775. ret = devm_request_irq(&pdev->dev, res->start, hdmi_irq_handler, 0,
  776. "hdmi", hdmi_dev);
  777. if (ret) {
  778. dev_err(dev, "request interrupt failed.\n");
  779. goto fail_init;
  780. }
  781. hdmi_dev->irq = res->start;
  782. /* setting v4l2 name to prevent WARN_ON in v4l2_device_register */
  783. strlcpy(hdmi_dev->v4l2_dev.name, dev_name(dev),
  784. sizeof(hdmi_dev->v4l2_dev.name));
  785. /* passing NULL owner prevents driver from erasing drvdata */
  786. ret = v4l2_device_register(NULL, &hdmi_dev->v4l2_dev);
  787. if (ret) {
  788. dev_err(dev, "could not register v4l2 device.\n");
  789. goto fail_init;
  790. }
  791. /* testing if hdmiphy info is present */
  792. if (!pdata->hdmiphy_info) {
  793. dev_err(dev, "hdmiphy info is missing in platform data\n");
  794. ret = -ENXIO;
  795. goto fail_vdev;
  796. }
  797. adapter = i2c_get_adapter(pdata->hdmiphy_bus);
  798. if (adapter == NULL) {
  799. dev_err(dev, "hdmiphy adapter request failed\n");
  800. ret = -ENXIO;
  801. goto fail_vdev;
  802. }
  803. hdmi_dev->phy_sd = v4l2_i2c_new_subdev_board(&hdmi_dev->v4l2_dev,
  804. adapter, pdata->hdmiphy_info, NULL);
  805. /* on failure or not adapter is no longer useful */
  806. i2c_put_adapter(adapter);
  807. if (hdmi_dev->phy_sd == NULL) {
  808. dev_err(dev, "missing subdev for hdmiphy\n");
  809. ret = -ENODEV;
  810. goto fail_vdev;
  811. }
  812. /* initialization of MHL interface if present */
  813. if (pdata->mhl_info) {
  814. adapter = i2c_get_adapter(pdata->mhl_bus);
  815. if (adapter == NULL) {
  816. dev_err(dev, "MHL adapter request failed\n");
  817. ret = -ENXIO;
  818. goto fail_vdev;
  819. }
  820. hdmi_dev->mhl_sd = v4l2_i2c_new_subdev_board(
  821. &hdmi_dev->v4l2_dev, adapter,
  822. pdata->mhl_info, NULL);
  823. /* on failure or not adapter is no longer useful */
  824. i2c_put_adapter(adapter);
  825. if (hdmi_dev->mhl_sd == NULL) {
  826. dev_err(dev, "missing subdev for MHL\n");
  827. ret = -ENODEV;
  828. goto fail_vdev;
  829. }
  830. }
  831. clk_enable(hdmi_dev->res.hdmi);
  832. pm_runtime_enable(dev);
  833. sd = &hdmi_dev->sd;
  834. v4l2_subdev_init(sd, &hdmi_sd_ops);
  835. sd->owner = THIS_MODULE;
  836. strlcpy(sd->name, "s5p-hdmi", sizeof sd->name);
  837. hdmi_dev->cur_preset = HDMI_DEFAULT_PRESET;
  838. /* FIXME: missing fail preset is not supported */
  839. hdmi_dev->cur_conf = hdmi_preset2timings(hdmi_dev->cur_preset);
  840. hdmi_dev->cur_conf_dirty = 1;
  841. /* storing subdev for call that have only access to struct device */
  842. dev_set_drvdata(dev, sd);
  843. dev_info(dev, "probe successful\n");
  844. return 0;
  845. fail_vdev:
  846. v4l2_device_unregister(&hdmi_dev->v4l2_dev);
  847. fail_init:
  848. hdmi_resources_cleanup(hdmi_dev);
  849. fail:
  850. dev_err(dev, "probe failed\n");
  851. return ret;
  852. }
  853. static int __devexit hdmi_remove(struct platform_device *pdev)
  854. {
  855. struct device *dev = &pdev->dev;
  856. struct v4l2_subdev *sd = dev_get_drvdata(dev);
  857. struct hdmi_device *hdmi_dev = sd_to_hdmi_dev(sd);
  858. pm_runtime_disable(dev);
  859. clk_disable(hdmi_dev->res.hdmi);
  860. v4l2_device_unregister(&hdmi_dev->v4l2_dev);
  861. disable_irq(hdmi_dev->irq);
  862. hdmi_resources_cleanup(hdmi_dev);
  863. dev_info(dev, "remove successful\n");
  864. return 0;
  865. }
  866. static struct platform_driver hdmi_driver __refdata = {
  867. .probe = hdmi_probe,
  868. .remove = __devexit_p(hdmi_remove),
  869. .id_table = hdmi_driver_types,
  870. .driver = {
  871. .name = "s5p-hdmi",
  872. .owner = THIS_MODULE,
  873. .pm = &hdmi_pm_ops,
  874. }
  875. };
  876. module_platform_driver(hdmi_driver);