dnp5370.c 9.3 KB

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  1. /*
  2. * This is the configuration for SSV Dil/NetPC DNP/5370 board.
  3. *
  4. * DIL module: http://www.dilnetpc.com/dnp0086.htm
  5. * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
  6. *
  7. * Copyright 2010 3ality Digital Systems
  8. * Copyright 2005 National ICT Australia (NICTA)
  9. * Copyright 2004-2006 Analog Devices Inc.
  10. *
  11. * Licensed under the GPL-2 or later.
  12. */
  13. #include <linux/device.h>
  14. #include <linux/kernel.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/io.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/nand.h>
  19. #include <linux/mtd/partitions.h>
  20. #include <linux/mtd/plat-ram.h>
  21. #include <linux/mtd/physmap.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spi/flash.h>
  24. #include <linux/irq.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/i2c.h>
  27. #include <linux/spi/mmc_spi.h>
  28. #include <linux/phy.h>
  29. #include <asm/dma.h>
  30. #include <asm/bfin5xx_spi.h>
  31. #include <asm/reboot.h>
  32. #include <asm/portmux.h>
  33. #include <asm/dpmc.h>
  34. /*
  35. * Name the Board for the /proc/cpuinfo
  36. */
  37. const char bfin_board_name[] = "DNP/5370";
  38. #define FLASH_MAC 0x202f0000
  39. #define CONFIG_MTD_PHYSMAP_LEN 0x300000
  40. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  41. static struct platform_device rtc_device = {
  42. .name = "rtc-bfin",
  43. .id = -1,
  44. };
  45. #endif
  46. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  47. #include <linux/bfin_mac.h>
  48. static const unsigned short bfin_mac_peripherals[] = P_RMII0;
  49. static struct bfin_phydev_platform_data bfin_phydev_data[] = {
  50. {
  51. .addr = 1,
  52. .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
  53. },
  54. };
  55. static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
  56. .phydev_number = 1,
  57. .phydev_data = bfin_phydev_data,
  58. .phy_mode = PHY_INTERFACE_MODE_RMII,
  59. .mac_peripherals = bfin_mac_peripherals,
  60. };
  61. static struct platform_device bfin_mii_bus = {
  62. .name = "bfin_mii_bus",
  63. .dev = {
  64. .platform_data = &bfin_mii_bus_data,
  65. }
  66. };
  67. static struct platform_device bfin_mac_device = {
  68. .name = "bfin_mac",
  69. .dev = {
  70. .platform_data = &bfin_mii_bus,
  71. }
  72. };
  73. #endif
  74. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  75. static struct mtd_partition asmb_flash_partitions[] = {
  76. {
  77. .name = "bootloader(nor)",
  78. .size = 0x30000,
  79. .offset = 0,
  80. }, {
  81. .name = "linux kernel and rootfs(nor)",
  82. .size = 0x300000 - 0x30000 - 0x10000,
  83. .offset = MTDPART_OFS_APPEND,
  84. }, {
  85. .name = "MAC address(nor)",
  86. .size = 0x10000,
  87. .offset = MTDPART_OFS_APPEND,
  88. .mask_flags = MTD_WRITEABLE,
  89. }
  90. };
  91. static struct physmap_flash_data asmb_flash_data = {
  92. .width = 1,
  93. .parts = asmb_flash_partitions,
  94. .nr_parts = ARRAY_SIZE(asmb_flash_partitions),
  95. };
  96. static struct resource asmb_flash_resource = {
  97. .start = 0x20000000,
  98. .end = 0x202fffff,
  99. .flags = IORESOURCE_MEM,
  100. };
  101. /* 4 MB NOR flash attached to async memory banks 0-2,
  102. * therefore only 3 MB visible.
  103. */
  104. static struct platform_device asmb_flash_device = {
  105. .name = "physmap-flash",
  106. .id = 0,
  107. .dev = {
  108. .platform_data = &asmb_flash_data,
  109. },
  110. .num_resources = 1,
  111. .resource = &asmb_flash_resource,
  112. };
  113. #endif
  114. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  115. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  116. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  117. .enable_dma = 0, /* use no dma transfer with this chip*/
  118. };
  119. #endif
  120. #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
  121. /* This mapping is for at45db642 it has 1056 page size,
  122. * partition size and offset should be page aligned
  123. */
  124. static struct mtd_partition bfin_spi_dataflash_partitions[] = {
  125. {
  126. .name = "JFFS2 dataflash(nor)",
  127. #ifdef CONFIG_MTD_PAGESIZE_1024
  128. .offset = 0x40000,
  129. .size = 0x7C0000,
  130. #else
  131. .offset = 0x0,
  132. .size = 0x840000,
  133. #endif
  134. }
  135. };
  136. static struct flash_platform_data bfin_spi_dataflash_data = {
  137. .name = "mtd_dataflash",
  138. .parts = bfin_spi_dataflash_partitions,
  139. .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
  140. .type = "mtd_dataflash",
  141. };
  142. static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
  143. .enable_dma = 0, /* use no dma transfer with this chip*/
  144. };
  145. #endif
  146. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  147. /* SD/MMC card reader at SPI bus */
  148. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  149. {
  150. .modalias = "mmc_spi",
  151. .max_speed_hz = 20000000,
  152. .bus_num = 0,
  153. .chip_select = 1,
  154. .controller_data = &mmc_spi_chip_info,
  155. .mode = SPI_MODE_3,
  156. },
  157. #endif
  158. /* 8 Megabyte Atmel NOR flash chip at SPI bus */
  159. #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
  160. {
  161. .modalias = "mtd_dataflash",
  162. .max_speed_hz = 16700000,
  163. .bus_num = 0,
  164. .chip_select = 2,
  165. .platform_data = &bfin_spi_dataflash_data,
  166. .controller_data = &spi_dataflash_chip_info,
  167. .mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
  168. },
  169. #endif
  170. };
  171. /* SPI controller data */
  172. /* SPI (0) */
  173. static struct resource bfin_spi0_resource[] = {
  174. [0] = {
  175. .start = SPI0_REGBASE,
  176. .end = SPI0_REGBASE + 0xFF,
  177. .flags = IORESOURCE_MEM,
  178. },
  179. [1] = {
  180. .start = CH_SPI,
  181. .end = CH_SPI,
  182. .flags = IORESOURCE_DMA,
  183. },
  184. [2] = {
  185. .start = IRQ_SPI,
  186. .end = IRQ_SPI,
  187. .flags = IORESOURCE_IRQ,
  188. },
  189. };
  190. static struct bfin5xx_spi_master spi_bfin_master_info = {
  191. .num_chipselect = 8,
  192. .enable_dma = 1, /* master has the ability to do dma transfer */
  193. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  194. };
  195. static struct platform_device spi_bfin_master_device = {
  196. .name = "bfin-spi",
  197. .id = 0, /* Bus number */
  198. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  199. .resource = bfin_spi0_resource,
  200. .dev = {
  201. .platform_data = &spi_bfin_master_info, /* Passed to driver */
  202. },
  203. };
  204. #endif
  205. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  206. #ifdef CONFIG_SERIAL_BFIN_UART0
  207. static struct resource bfin_uart0_resources[] = {
  208. {
  209. .start = UART0_THR,
  210. .end = UART0_GCTL+2,
  211. .flags = IORESOURCE_MEM,
  212. },
  213. {
  214. .start = IRQ_UART0_RX,
  215. .end = IRQ_UART0_RX+1,
  216. .flags = IORESOURCE_IRQ,
  217. },
  218. {
  219. .start = IRQ_UART0_ERROR,
  220. .end = IRQ_UART0_ERROR,
  221. .flags = IORESOURCE_IRQ,
  222. },
  223. {
  224. .start = CH_UART0_TX,
  225. .end = CH_UART0_TX,
  226. .flags = IORESOURCE_DMA,
  227. },
  228. {
  229. .start = CH_UART0_RX,
  230. .end = CH_UART0_RX,
  231. .flags = IORESOURCE_DMA,
  232. },
  233. };
  234. static unsigned short bfin_uart0_peripherals[] = {
  235. P_UART0_TX, P_UART0_RX, 0
  236. };
  237. static struct platform_device bfin_uart0_device = {
  238. .name = "bfin-uart",
  239. .id = 0,
  240. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  241. .resource = bfin_uart0_resources,
  242. .dev = {
  243. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  244. },
  245. };
  246. #endif
  247. #ifdef CONFIG_SERIAL_BFIN_UART1
  248. static struct resource bfin_uart1_resources[] = {
  249. {
  250. .start = UART1_THR,
  251. .end = UART1_GCTL+2,
  252. .flags = IORESOURCE_MEM,
  253. },
  254. {
  255. .start = IRQ_UART1_RX,
  256. .end = IRQ_UART1_RX+1,
  257. .flags = IORESOURCE_IRQ,
  258. },
  259. {
  260. .start = IRQ_UART1_ERROR,
  261. .end = IRQ_UART1_ERROR,
  262. .flags = IORESOURCE_IRQ,
  263. },
  264. {
  265. .start = CH_UART1_TX,
  266. .end = CH_UART1_TX,
  267. .flags = IORESOURCE_DMA,
  268. },
  269. {
  270. .start = CH_UART1_RX,
  271. .end = CH_UART1_RX,
  272. .flags = IORESOURCE_DMA,
  273. },
  274. };
  275. static unsigned short bfin_uart1_peripherals[] = {
  276. P_UART1_TX, P_UART1_RX, 0
  277. };
  278. static struct platform_device bfin_uart1_device = {
  279. .name = "bfin-uart",
  280. .id = 1,
  281. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  282. .resource = bfin_uart1_resources,
  283. .dev = {
  284. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  285. },
  286. };
  287. #endif
  288. #endif
  289. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  290. static struct resource bfin_twi0_resource[] = {
  291. [0] = {
  292. .start = TWI0_REGBASE,
  293. .end = TWI0_REGBASE + 0xff,
  294. .flags = IORESOURCE_MEM,
  295. },
  296. [1] = {
  297. .start = IRQ_TWI,
  298. .end = IRQ_TWI,
  299. .flags = IORESOURCE_IRQ,
  300. },
  301. };
  302. static struct platform_device i2c_bfin_twi_device = {
  303. .name = "i2c-bfin-twi",
  304. .id = 0,
  305. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  306. .resource = bfin_twi0_resource,
  307. };
  308. #endif
  309. static struct platform_device *dnp5370_devices[] __initdata = {
  310. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  311. #ifdef CONFIG_SERIAL_BFIN_UART0
  312. &bfin_uart0_device,
  313. #endif
  314. #ifdef CONFIG_SERIAL_BFIN_UART1
  315. &bfin_uart1_device,
  316. #endif
  317. #endif
  318. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  319. &asmb_flash_device,
  320. #endif
  321. #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
  322. &bfin_mii_bus,
  323. &bfin_mac_device,
  324. #endif
  325. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  326. &spi_bfin_master_device,
  327. #endif
  328. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  329. &i2c_bfin_twi_device,
  330. #endif
  331. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  332. &rtc_device,
  333. #endif
  334. };
  335. static int __init dnp5370_init(void)
  336. {
  337. printk(KERN_INFO "DNP/5370: registering device resources\n");
  338. platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
  339. printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
  340. ARRAY_SIZE(bfin_spi_board_info));
  341. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  342. printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
  343. return 0;
  344. }
  345. arch_initcall(dnp5370_init);
  346. /*
  347. * Currently the MAC address is saved in Flash by U-Boot
  348. */
  349. void bfin_get_ether_addr(char *addr)
  350. {
  351. *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
  352. *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
  353. }
  354. EXPORT_SYMBOL(bfin_get_ether_addr);