intel_sdvo.c 78 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "drm_crtc.h"
  34. #include "drm_edid.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. static const char *tv_format_names[] = {
  50. "NTSC_M" , "NTSC_J" , "NTSC_443",
  51. "PAL_B" , "PAL_D" , "PAL_G" ,
  52. "PAL_H" , "PAL_I" , "PAL_M" ,
  53. "PAL_N" , "PAL_NC" , "PAL_60" ,
  54. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  55. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  56. "SECAM_60"
  57. };
  58. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  59. struct intel_sdvo {
  60. struct intel_encoder base;
  61. struct i2c_adapter *i2c;
  62. u8 slave_addr;
  63. struct i2c_adapter ddc;
  64. /* Register for the SDVO device: SDVOB or SDVOC */
  65. int sdvo_reg;
  66. /* Active outputs controlled by this SDVO output */
  67. uint16_t controlled_output;
  68. /*
  69. * Capabilities of the SDVO device returned by
  70. * i830_sdvo_get_capabilities()
  71. */
  72. struct intel_sdvo_caps caps;
  73. /* Pixel clock limitations reported by the SDVO device, in kHz */
  74. int pixel_clock_min, pixel_clock_max;
  75. /*
  76. * For multiple function SDVO device,
  77. * this is for current attached outputs.
  78. */
  79. uint16_t attached_output;
  80. /*
  81. * Hotplug activation bits for this device
  82. */
  83. uint8_t hotplug_active[2];
  84. /**
  85. * This is used to select the color range of RBG outputs in HDMI mode.
  86. * It is only valid when using TMDS encoding and 8 bit per color mode.
  87. */
  88. uint32_t color_range;
  89. /**
  90. * This is set if we're going to treat the device as TV-out.
  91. *
  92. * While we have these nice friendly flags for output types that ought
  93. * to decide this for us, the S-Video output on our HDMI+S-Video card
  94. * shows up as RGB1 (VGA).
  95. */
  96. bool is_tv;
  97. /* This is for current tv format name */
  98. int tv_format_index;
  99. /**
  100. * This is set if we treat the device as HDMI, instead of DVI.
  101. */
  102. bool is_hdmi;
  103. bool has_hdmi_monitor;
  104. bool has_hdmi_audio;
  105. /**
  106. * This is set if we detect output of sdvo device as LVDS and
  107. * have a valid fixed mode to use with the panel.
  108. */
  109. bool is_lvds;
  110. /**
  111. * This is sdvo fixed pannel mode pointer
  112. */
  113. struct drm_display_mode *sdvo_lvds_fixed_mode;
  114. /* DDC bus used by this SDVO encoder */
  115. uint8_t ddc_bus;
  116. /* Input timings for adjusted_mode */
  117. struct intel_sdvo_dtd input_dtd;
  118. };
  119. struct intel_sdvo_connector {
  120. struct intel_connector base;
  121. /* Mark the type of connector */
  122. uint16_t output_flag;
  123. int force_audio;
  124. /* This contains all current supported TV format */
  125. u8 tv_format_supported[TV_FORMAT_NUM];
  126. int format_supported_num;
  127. struct drm_property *tv_format;
  128. /* add the property for the SDVO-TV */
  129. struct drm_property *left;
  130. struct drm_property *right;
  131. struct drm_property *top;
  132. struct drm_property *bottom;
  133. struct drm_property *hpos;
  134. struct drm_property *vpos;
  135. struct drm_property *contrast;
  136. struct drm_property *saturation;
  137. struct drm_property *hue;
  138. struct drm_property *sharpness;
  139. struct drm_property *flicker_filter;
  140. struct drm_property *flicker_filter_adaptive;
  141. struct drm_property *flicker_filter_2d;
  142. struct drm_property *tv_chroma_filter;
  143. struct drm_property *tv_luma_filter;
  144. struct drm_property *dot_crawl;
  145. /* add the property for the SDVO-TV/LVDS */
  146. struct drm_property *brightness;
  147. /* Add variable to record current setting for the above property */
  148. u32 left_margin, right_margin, top_margin, bottom_margin;
  149. /* this is to get the range of margin.*/
  150. u32 max_hscan, max_vscan;
  151. u32 max_hpos, cur_hpos;
  152. u32 max_vpos, cur_vpos;
  153. u32 cur_brightness, max_brightness;
  154. u32 cur_contrast, max_contrast;
  155. u32 cur_saturation, max_saturation;
  156. u32 cur_hue, max_hue;
  157. u32 cur_sharpness, max_sharpness;
  158. u32 cur_flicker_filter, max_flicker_filter;
  159. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  160. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  161. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  162. u32 cur_tv_luma_filter, max_tv_luma_filter;
  163. u32 cur_dot_crawl, max_dot_crawl;
  164. };
  165. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  166. {
  167. return container_of(encoder, struct intel_sdvo, base.base);
  168. }
  169. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  170. {
  171. return container_of(intel_attached_encoder(connector),
  172. struct intel_sdvo, base);
  173. }
  174. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  175. {
  176. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  177. }
  178. static bool
  179. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  180. static bool
  181. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  182. struct intel_sdvo_connector *intel_sdvo_connector,
  183. int type);
  184. static bool
  185. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  186. struct intel_sdvo_connector *intel_sdvo_connector);
  187. /**
  188. * Writes the SDVOB or SDVOC with the given value, but always writes both
  189. * SDVOB and SDVOC to work around apparent hardware issues (according to
  190. * comments in the BIOS).
  191. */
  192. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  193. {
  194. struct drm_device *dev = intel_sdvo->base.base.dev;
  195. struct drm_i915_private *dev_priv = dev->dev_private;
  196. u32 bval = val, cval = val;
  197. int i;
  198. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  199. I915_WRITE(intel_sdvo->sdvo_reg, val);
  200. I915_READ(intel_sdvo->sdvo_reg);
  201. return;
  202. }
  203. if (intel_sdvo->sdvo_reg == SDVOB) {
  204. cval = I915_READ(SDVOC);
  205. } else {
  206. bval = I915_READ(SDVOB);
  207. }
  208. /*
  209. * Write the registers twice for luck. Sometimes,
  210. * writing them only once doesn't appear to 'stick'.
  211. * The BIOS does this too. Yay, magic
  212. */
  213. for (i = 0; i < 2; i++)
  214. {
  215. I915_WRITE(SDVOB, bval);
  216. I915_READ(SDVOB);
  217. I915_WRITE(SDVOC, cval);
  218. I915_READ(SDVOC);
  219. }
  220. }
  221. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  222. {
  223. struct i2c_msg msgs[] = {
  224. {
  225. .addr = intel_sdvo->slave_addr,
  226. .flags = 0,
  227. .len = 1,
  228. .buf = &addr,
  229. },
  230. {
  231. .addr = intel_sdvo->slave_addr,
  232. .flags = I2C_M_RD,
  233. .len = 1,
  234. .buf = ch,
  235. }
  236. };
  237. int ret;
  238. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  239. return true;
  240. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  241. return false;
  242. }
  243. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  244. /** Mapping of command numbers to names, for debug output */
  245. static const struct _sdvo_cmd_name {
  246. u8 cmd;
  247. const char *name;
  248. } sdvo_cmd_names[] = {
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  292. /* Add the op code for SDVO enhancements */
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  337. /* HDMI op code */
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  358. };
  359. #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
  360. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  361. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  362. const void *args, int args_len)
  363. {
  364. int i;
  365. DRM_DEBUG_KMS("%s: W: %02X ",
  366. SDVO_NAME(intel_sdvo), cmd);
  367. for (i = 0; i < args_len; i++)
  368. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  369. for (; i < 8; i++)
  370. DRM_LOG_KMS(" ");
  371. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  372. if (cmd == sdvo_cmd_names[i].cmd) {
  373. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  374. break;
  375. }
  376. }
  377. if (i == ARRAY_SIZE(sdvo_cmd_names))
  378. DRM_LOG_KMS("(%02X)", cmd);
  379. DRM_LOG_KMS("\n");
  380. }
  381. static const char *cmd_status_names[] = {
  382. "Power on",
  383. "Success",
  384. "Not supported",
  385. "Invalid arg",
  386. "Pending",
  387. "Target not specified",
  388. "Scaling not supported"
  389. };
  390. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  391. const void *args, int args_len)
  392. {
  393. u8 buf[args_len*2 + 2], status;
  394. struct i2c_msg msgs[args_len + 3];
  395. int i, ret;
  396. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  397. for (i = 0; i < args_len; i++) {
  398. msgs[i].addr = intel_sdvo->slave_addr;
  399. msgs[i].flags = 0;
  400. msgs[i].len = 2;
  401. msgs[i].buf = buf + 2 *i;
  402. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  403. buf[2*i + 1] = ((u8*)args)[i];
  404. }
  405. msgs[i].addr = intel_sdvo->slave_addr;
  406. msgs[i].flags = 0;
  407. msgs[i].len = 2;
  408. msgs[i].buf = buf + 2*i;
  409. buf[2*i + 0] = SDVO_I2C_OPCODE;
  410. buf[2*i + 1] = cmd;
  411. /* the following two are to read the response */
  412. status = SDVO_I2C_CMD_STATUS;
  413. msgs[i+1].addr = intel_sdvo->slave_addr;
  414. msgs[i+1].flags = 0;
  415. msgs[i+1].len = 1;
  416. msgs[i+1].buf = &status;
  417. msgs[i+2].addr = intel_sdvo->slave_addr;
  418. msgs[i+2].flags = I2C_M_RD;
  419. msgs[i+2].len = 1;
  420. msgs[i+2].buf = &status;
  421. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  422. if (ret < 0) {
  423. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  424. return false;
  425. }
  426. if (ret != i+3) {
  427. /* failure in I2C transfer */
  428. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  429. return false;
  430. }
  431. return true;
  432. }
  433. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  434. void *response, int response_len)
  435. {
  436. u8 retry = 5;
  437. u8 status;
  438. int i;
  439. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  440. /*
  441. * The documentation states that all commands will be
  442. * processed within 15µs, and that we need only poll
  443. * the status byte a maximum of 3 times in order for the
  444. * command to be complete.
  445. *
  446. * Check 5 times in case the hardware failed to read the docs.
  447. */
  448. if (!intel_sdvo_read_byte(intel_sdvo,
  449. SDVO_I2C_CMD_STATUS,
  450. &status))
  451. goto log_fail;
  452. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  453. udelay(15);
  454. if (!intel_sdvo_read_byte(intel_sdvo,
  455. SDVO_I2C_CMD_STATUS,
  456. &status))
  457. goto log_fail;
  458. }
  459. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  460. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  461. else
  462. DRM_LOG_KMS("(??? %d)", status);
  463. if (status != SDVO_CMD_STATUS_SUCCESS)
  464. goto log_fail;
  465. /* Read the command response */
  466. for (i = 0; i < response_len; i++) {
  467. if (!intel_sdvo_read_byte(intel_sdvo,
  468. SDVO_I2C_RETURN_0 + i,
  469. &((u8 *)response)[i]))
  470. goto log_fail;
  471. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  472. }
  473. DRM_LOG_KMS("\n");
  474. return true;
  475. log_fail:
  476. DRM_LOG_KMS("... failed\n");
  477. return false;
  478. }
  479. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  480. {
  481. if (mode->clock >= 100000)
  482. return 1;
  483. else if (mode->clock >= 50000)
  484. return 2;
  485. else
  486. return 4;
  487. }
  488. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  489. u8 ddc_bus)
  490. {
  491. /* This must be the immediately preceding write before the i2c xfer */
  492. return intel_sdvo_write_cmd(intel_sdvo,
  493. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  494. &ddc_bus, 1);
  495. }
  496. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  497. {
  498. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  499. return false;
  500. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  501. }
  502. static bool
  503. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  504. {
  505. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  506. return false;
  507. return intel_sdvo_read_response(intel_sdvo, value, len);
  508. }
  509. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  510. {
  511. struct intel_sdvo_set_target_input_args targets = {0};
  512. return intel_sdvo_set_value(intel_sdvo,
  513. SDVO_CMD_SET_TARGET_INPUT,
  514. &targets, sizeof(targets));
  515. }
  516. /**
  517. * Return whether each input is trained.
  518. *
  519. * This function is making an assumption about the layout of the response,
  520. * which should be checked against the docs.
  521. */
  522. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  523. {
  524. struct intel_sdvo_get_trained_inputs_response response;
  525. BUILD_BUG_ON(sizeof(response) != 1);
  526. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  527. &response, sizeof(response)))
  528. return false;
  529. *input_1 = response.input0_trained;
  530. *input_2 = response.input1_trained;
  531. return true;
  532. }
  533. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  534. u16 outputs)
  535. {
  536. return intel_sdvo_set_value(intel_sdvo,
  537. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  538. &outputs, sizeof(outputs));
  539. }
  540. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  541. int mode)
  542. {
  543. u8 state = SDVO_ENCODER_STATE_ON;
  544. switch (mode) {
  545. case DRM_MODE_DPMS_ON:
  546. state = SDVO_ENCODER_STATE_ON;
  547. break;
  548. case DRM_MODE_DPMS_STANDBY:
  549. state = SDVO_ENCODER_STATE_STANDBY;
  550. break;
  551. case DRM_MODE_DPMS_SUSPEND:
  552. state = SDVO_ENCODER_STATE_SUSPEND;
  553. break;
  554. case DRM_MODE_DPMS_OFF:
  555. state = SDVO_ENCODER_STATE_OFF;
  556. break;
  557. }
  558. return intel_sdvo_set_value(intel_sdvo,
  559. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  560. }
  561. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  562. int *clock_min,
  563. int *clock_max)
  564. {
  565. struct intel_sdvo_pixel_clock_range clocks;
  566. BUILD_BUG_ON(sizeof(clocks) != 4);
  567. if (!intel_sdvo_get_value(intel_sdvo,
  568. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  569. &clocks, sizeof(clocks)))
  570. return false;
  571. /* Convert the values from units of 10 kHz to kHz. */
  572. *clock_min = clocks.min * 10;
  573. *clock_max = clocks.max * 10;
  574. return true;
  575. }
  576. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  577. u16 outputs)
  578. {
  579. return intel_sdvo_set_value(intel_sdvo,
  580. SDVO_CMD_SET_TARGET_OUTPUT,
  581. &outputs, sizeof(outputs));
  582. }
  583. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  584. struct intel_sdvo_dtd *dtd)
  585. {
  586. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  587. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  588. }
  589. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  590. struct intel_sdvo_dtd *dtd)
  591. {
  592. return intel_sdvo_set_timing(intel_sdvo,
  593. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  594. }
  595. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  596. struct intel_sdvo_dtd *dtd)
  597. {
  598. return intel_sdvo_set_timing(intel_sdvo,
  599. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  600. }
  601. static bool
  602. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  603. uint16_t clock,
  604. uint16_t width,
  605. uint16_t height)
  606. {
  607. struct intel_sdvo_preferred_input_timing_args args;
  608. memset(&args, 0, sizeof(args));
  609. args.clock = clock;
  610. args.width = width;
  611. args.height = height;
  612. args.interlace = 0;
  613. if (intel_sdvo->is_lvds &&
  614. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  615. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  616. args.scaled = 1;
  617. return intel_sdvo_set_value(intel_sdvo,
  618. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  619. &args, sizeof(args));
  620. }
  621. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  622. struct intel_sdvo_dtd *dtd)
  623. {
  624. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  625. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  626. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  627. &dtd->part1, sizeof(dtd->part1)) &&
  628. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  629. &dtd->part2, sizeof(dtd->part2));
  630. }
  631. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  632. {
  633. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  634. }
  635. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  636. const struct drm_display_mode *mode)
  637. {
  638. uint16_t width, height;
  639. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  640. uint16_t h_sync_offset, v_sync_offset;
  641. width = mode->crtc_hdisplay;
  642. height = mode->crtc_vdisplay;
  643. /* do some mode translations */
  644. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  645. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  646. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  647. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  648. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  649. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  650. dtd->part1.clock = mode->clock / 10;
  651. dtd->part1.h_active = width & 0xff;
  652. dtd->part1.h_blank = h_blank_len & 0xff;
  653. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  654. ((h_blank_len >> 8) & 0xf);
  655. dtd->part1.v_active = height & 0xff;
  656. dtd->part1.v_blank = v_blank_len & 0xff;
  657. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  658. ((v_blank_len >> 8) & 0xf);
  659. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  660. dtd->part2.h_sync_width = h_sync_len & 0xff;
  661. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  662. (v_sync_len & 0xf);
  663. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  664. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  665. ((v_sync_len & 0x30) >> 4);
  666. dtd->part2.dtd_flags = 0x18;
  667. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  668. dtd->part2.dtd_flags |= 0x2;
  669. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  670. dtd->part2.dtd_flags |= 0x4;
  671. dtd->part2.sdvo_flags = 0;
  672. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  673. dtd->part2.reserved = 0;
  674. }
  675. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  676. const struct intel_sdvo_dtd *dtd)
  677. {
  678. mode->hdisplay = dtd->part1.h_active;
  679. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  680. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  681. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  682. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  683. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  684. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  685. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  686. mode->vdisplay = dtd->part1.v_active;
  687. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  688. mode->vsync_start = mode->vdisplay;
  689. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  690. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  691. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  692. mode->vsync_end = mode->vsync_start +
  693. (dtd->part2.v_sync_off_width & 0xf);
  694. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  695. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  696. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  697. mode->clock = dtd->part1.clock * 10;
  698. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  699. if (dtd->part2.dtd_flags & 0x2)
  700. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  701. if (dtd->part2.dtd_flags & 0x4)
  702. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  703. }
  704. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  705. {
  706. struct intel_sdvo_encode encode;
  707. BUILD_BUG_ON(sizeof(encode) != 2);
  708. return intel_sdvo_get_value(intel_sdvo,
  709. SDVO_CMD_GET_SUPP_ENCODE,
  710. &encode, sizeof(encode));
  711. }
  712. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  713. uint8_t mode)
  714. {
  715. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  716. }
  717. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  718. uint8_t mode)
  719. {
  720. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  721. }
  722. #if 0
  723. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  724. {
  725. int i, j;
  726. uint8_t set_buf_index[2];
  727. uint8_t av_split;
  728. uint8_t buf_size;
  729. uint8_t buf[48];
  730. uint8_t *pos;
  731. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  732. for (i = 0; i <= av_split; i++) {
  733. set_buf_index[0] = i; set_buf_index[1] = 0;
  734. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  735. set_buf_index, 2);
  736. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  737. intel_sdvo_read_response(encoder, &buf_size, 1);
  738. pos = buf;
  739. for (j = 0; j <= buf_size; j += 8) {
  740. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  741. NULL, 0);
  742. intel_sdvo_read_response(encoder, pos, 8);
  743. pos += 8;
  744. }
  745. }
  746. }
  747. #endif
  748. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
  749. {
  750. struct dip_infoframe avi_if = {
  751. .type = DIP_TYPE_AVI,
  752. .ver = DIP_VERSION_AVI,
  753. .len = DIP_LEN_AVI,
  754. };
  755. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  756. uint8_t set_buf_index[2] = { 1, 0 };
  757. uint64_t *data = (uint64_t *)&avi_if;
  758. unsigned i;
  759. intel_dip_infoframe_csum(&avi_if);
  760. if (!intel_sdvo_set_value(intel_sdvo,
  761. SDVO_CMD_SET_HBUF_INDEX,
  762. set_buf_index, 2))
  763. return false;
  764. for (i = 0; i < sizeof(avi_if); i += 8) {
  765. if (!intel_sdvo_set_value(intel_sdvo,
  766. SDVO_CMD_SET_HBUF_DATA,
  767. data, 8))
  768. return false;
  769. data++;
  770. }
  771. return intel_sdvo_set_value(intel_sdvo,
  772. SDVO_CMD_SET_HBUF_TXRATE,
  773. &tx_rate, 1);
  774. }
  775. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  776. {
  777. struct intel_sdvo_tv_format format;
  778. uint32_t format_map;
  779. format_map = 1 << intel_sdvo->tv_format_index;
  780. memset(&format, 0, sizeof(format));
  781. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  782. BUILD_BUG_ON(sizeof(format) != 6);
  783. return intel_sdvo_set_value(intel_sdvo,
  784. SDVO_CMD_SET_TV_FORMAT,
  785. &format, sizeof(format));
  786. }
  787. static bool
  788. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  789. struct drm_display_mode *mode)
  790. {
  791. struct intel_sdvo_dtd output_dtd;
  792. if (!intel_sdvo_set_target_output(intel_sdvo,
  793. intel_sdvo->attached_output))
  794. return false;
  795. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  796. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  797. return false;
  798. return true;
  799. }
  800. static bool
  801. intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
  802. struct drm_display_mode *mode,
  803. struct drm_display_mode *adjusted_mode)
  804. {
  805. /* Reset the input timing to the screen. Assume always input 0. */
  806. if (!intel_sdvo_set_target_input(intel_sdvo))
  807. return false;
  808. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  809. mode->clock / 10,
  810. mode->hdisplay,
  811. mode->vdisplay))
  812. return false;
  813. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  814. &intel_sdvo->input_dtd))
  815. return false;
  816. intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
  817. drm_mode_set_crtcinfo(adjusted_mode, 0);
  818. return true;
  819. }
  820. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  821. struct drm_display_mode *mode,
  822. struct drm_display_mode *adjusted_mode)
  823. {
  824. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  825. int multiplier;
  826. /* We need to construct preferred input timings based on our
  827. * output timings. To do that, we have to set the output
  828. * timings, even though this isn't really the right place in
  829. * the sequence to do it. Oh well.
  830. */
  831. if (intel_sdvo->is_tv) {
  832. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  833. return false;
  834. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  835. mode,
  836. adjusted_mode);
  837. } else if (intel_sdvo->is_lvds) {
  838. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  839. intel_sdvo->sdvo_lvds_fixed_mode))
  840. return false;
  841. (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
  842. mode,
  843. adjusted_mode);
  844. }
  845. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  846. * SDVO device will factor out the multiplier during mode_set.
  847. */
  848. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  849. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  850. return true;
  851. }
  852. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  853. struct drm_display_mode *mode,
  854. struct drm_display_mode *adjusted_mode)
  855. {
  856. struct drm_device *dev = encoder->dev;
  857. struct drm_i915_private *dev_priv = dev->dev_private;
  858. struct drm_crtc *crtc = encoder->crtc;
  859. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  860. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  861. u32 sdvox;
  862. struct intel_sdvo_in_out_map in_out;
  863. struct intel_sdvo_dtd input_dtd;
  864. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  865. int rate;
  866. if (!mode)
  867. return;
  868. /* First, set the input mapping for the first input to our controlled
  869. * output. This is only correct if we're a single-input device, in
  870. * which case the first input is the output from the appropriate SDVO
  871. * channel on the motherboard. In a two-input device, the first input
  872. * will be SDVOB and the second SDVOC.
  873. */
  874. in_out.in0 = intel_sdvo->attached_output;
  875. in_out.in1 = 0;
  876. intel_sdvo_set_value(intel_sdvo,
  877. SDVO_CMD_SET_IN_OUT_MAP,
  878. &in_out, sizeof(in_out));
  879. /* Set the output timings to the screen */
  880. if (!intel_sdvo_set_target_output(intel_sdvo,
  881. intel_sdvo->attached_output))
  882. return;
  883. /* We have tried to get input timing in mode_fixup, and filled into
  884. * adjusted_mode.
  885. */
  886. if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
  887. input_dtd = intel_sdvo->input_dtd;
  888. } else {
  889. /* Set the output timing to the screen */
  890. if (!intel_sdvo_set_target_output(intel_sdvo,
  891. intel_sdvo->attached_output))
  892. return;
  893. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  894. (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
  895. }
  896. /* Set the input timing to the screen. Assume always input 0. */
  897. if (!intel_sdvo_set_target_input(intel_sdvo))
  898. return;
  899. if (intel_sdvo->has_hdmi_monitor) {
  900. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  901. intel_sdvo_set_colorimetry(intel_sdvo,
  902. SDVO_COLORIMETRY_RGB256);
  903. intel_sdvo_set_avi_infoframe(intel_sdvo);
  904. } else
  905. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  906. if (intel_sdvo->is_tv &&
  907. !intel_sdvo_set_tv_format(intel_sdvo))
  908. return;
  909. (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
  910. switch (pixel_multiplier) {
  911. default:
  912. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  913. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  914. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  915. }
  916. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  917. return;
  918. /* Set the SDVO control regs. */
  919. if (INTEL_INFO(dev)->gen >= 4) {
  920. sdvox = 0;
  921. if (intel_sdvo->is_hdmi)
  922. sdvox |= intel_sdvo->color_range;
  923. if (INTEL_INFO(dev)->gen < 5)
  924. sdvox |= SDVO_BORDER_ENABLE;
  925. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  926. sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  927. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  928. sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  929. } else {
  930. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  931. switch (intel_sdvo->sdvo_reg) {
  932. case SDVOB:
  933. sdvox &= SDVOB_PRESERVE_MASK;
  934. break;
  935. case SDVOC:
  936. sdvox &= SDVOC_PRESERVE_MASK;
  937. break;
  938. }
  939. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  940. }
  941. if (intel_crtc->pipe == 1)
  942. sdvox |= SDVO_PIPE_B_SELECT;
  943. if (intel_sdvo->has_hdmi_audio)
  944. sdvox |= SDVO_AUDIO_ENABLE;
  945. if (INTEL_INFO(dev)->gen >= 4) {
  946. /* done in crtc_mode_set as the dpll_md reg must be written early */
  947. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  948. /* done in crtc_mode_set as it lives inside the dpll register */
  949. } else {
  950. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  951. }
  952. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  953. INTEL_INFO(dev)->gen < 5)
  954. sdvox |= SDVO_STALL_SELECT;
  955. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  956. }
  957. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  958. {
  959. struct drm_device *dev = encoder->dev;
  960. struct drm_i915_private *dev_priv = dev->dev_private;
  961. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  962. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  963. u32 temp;
  964. if (mode != DRM_MODE_DPMS_ON) {
  965. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  966. if (0)
  967. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  968. if (mode == DRM_MODE_DPMS_OFF) {
  969. temp = I915_READ(intel_sdvo->sdvo_reg);
  970. if ((temp & SDVO_ENABLE) != 0) {
  971. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  972. }
  973. }
  974. } else {
  975. bool input1, input2;
  976. int i;
  977. u8 status;
  978. temp = I915_READ(intel_sdvo->sdvo_reg);
  979. if ((temp & SDVO_ENABLE) == 0)
  980. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  981. for (i = 0; i < 2; i++)
  982. intel_wait_for_vblank(dev, intel_crtc->pipe);
  983. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  984. /* Warn if the device reported failure to sync.
  985. * A lot of SDVO devices fail to notify of sync, but it's
  986. * a given it the status is a success, we succeeded.
  987. */
  988. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  989. DRM_DEBUG_KMS("First %s output reported failure to "
  990. "sync\n", SDVO_NAME(intel_sdvo));
  991. }
  992. if (0)
  993. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  994. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  995. }
  996. return;
  997. }
  998. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  999. struct drm_display_mode *mode)
  1000. {
  1001. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1002. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1003. return MODE_NO_DBLESCAN;
  1004. if (intel_sdvo->pixel_clock_min > mode->clock)
  1005. return MODE_CLOCK_LOW;
  1006. if (intel_sdvo->pixel_clock_max < mode->clock)
  1007. return MODE_CLOCK_HIGH;
  1008. if (intel_sdvo->is_lvds) {
  1009. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1010. return MODE_PANEL;
  1011. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1012. return MODE_PANEL;
  1013. }
  1014. return MODE_OK;
  1015. }
  1016. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1017. {
  1018. BUILD_BUG_ON(sizeof(*caps) != 8);
  1019. if (!intel_sdvo_get_value(intel_sdvo,
  1020. SDVO_CMD_GET_DEVICE_CAPS,
  1021. caps, sizeof(*caps)))
  1022. return false;
  1023. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1024. " vendor_id: %d\n"
  1025. " device_id: %d\n"
  1026. " device_rev_id: %d\n"
  1027. " sdvo_version_major: %d\n"
  1028. " sdvo_version_minor: %d\n"
  1029. " sdvo_inputs_mask: %d\n"
  1030. " smooth_scaling: %d\n"
  1031. " sharp_scaling: %d\n"
  1032. " up_scaling: %d\n"
  1033. " down_scaling: %d\n"
  1034. " stall_support: %d\n"
  1035. " output_flags: %d\n",
  1036. caps->vendor_id,
  1037. caps->device_id,
  1038. caps->device_rev_id,
  1039. caps->sdvo_version_major,
  1040. caps->sdvo_version_minor,
  1041. caps->sdvo_inputs_mask,
  1042. caps->smooth_scaling,
  1043. caps->sharp_scaling,
  1044. caps->up_scaling,
  1045. caps->down_scaling,
  1046. caps->stall_support,
  1047. caps->output_flags);
  1048. return true;
  1049. }
  1050. static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
  1051. {
  1052. u8 response[2];
  1053. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1054. &response, 2) && response[0];
  1055. }
  1056. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1057. {
  1058. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1059. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
  1060. }
  1061. static bool
  1062. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1063. {
  1064. /* Is there more than one type of output? */
  1065. int caps = intel_sdvo->caps.output_flags & 0xf;
  1066. return caps & -caps;
  1067. }
  1068. static struct edid *
  1069. intel_sdvo_get_edid(struct drm_connector *connector)
  1070. {
  1071. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1072. return drm_get_edid(connector, &sdvo->ddc);
  1073. }
  1074. /* Mac mini hack -- use the same DDC as the analog connector */
  1075. static struct edid *
  1076. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1077. {
  1078. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1079. return drm_get_edid(connector,
  1080. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1081. }
  1082. enum drm_connector_status
  1083. intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1084. {
  1085. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1086. enum drm_connector_status status;
  1087. struct edid *edid;
  1088. edid = intel_sdvo_get_edid(connector);
  1089. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1090. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1091. /*
  1092. * Don't use the 1 as the argument of DDC bus switch to get
  1093. * the EDID. It is used for SDVO SPD ROM.
  1094. */
  1095. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1096. intel_sdvo->ddc_bus = ddc;
  1097. edid = intel_sdvo_get_edid(connector);
  1098. if (edid)
  1099. break;
  1100. }
  1101. /*
  1102. * If we found the EDID on the other bus,
  1103. * assume that is the correct DDC bus.
  1104. */
  1105. if (edid == NULL)
  1106. intel_sdvo->ddc_bus = saved_ddc;
  1107. }
  1108. /*
  1109. * When there is no edid and no monitor is connected with VGA
  1110. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1111. */
  1112. if (edid == NULL)
  1113. edid = intel_sdvo_get_analog_edid(connector);
  1114. status = connector_status_unknown;
  1115. if (edid != NULL) {
  1116. /* DDC bus is shared, match EDID to connector type */
  1117. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1118. status = connector_status_connected;
  1119. if (intel_sdvo->is_hdmi) {
  1120. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1121. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1122. }
  1123. } else
  1124. status = connector_status_disconnected;
  1125. connector->display_info.raw_edid = NULL;
  1126. kfree(edid);
  1127. }
  1128. if (status == connector_status_connected) {
  1129. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1130. if (intel_sdvo_connector->force_audio)
  1131. intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
  1132. }
  1133. return status;
  1134. }
  1135. static enum drm_connector_status
  1136. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1137. {
  1138. uint16_t response;
  1139. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1140. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1141. enum drm_connector_status ret;
  1142. if (!intel_sdvo_write_cmd(intel_sdvo,
  1143. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1144. return connector_status_unknown;
  1145. /* add 30ms delay when the output type might be TV */
  1146. if (intel_sdvo->caps.output_flags &
  1147. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1148. mdelay(30);
  1149. if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
  1150. return connector_status_unknown;
  1151. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1152. response & 0xff, response >> 8,
  1153. intel_sdvo_connector->output_flag);
  1154. if (response == 0)
  1155. return connector_status_disconnected;
  1156. intel_sdvo->attached_output = response;
  1157. intel_sdvo->has_hdmi_monitor = false;
  1158. intel_sdvo->has_hdmi_audio = false;
  1159. if ((intel_sdvo_connector->output_flag & response) == 0)
  1160. ret = connector_status_disconnected;
  1161. else if (IS_TMDS(intel_sdvo_connector))
  1162. ret = intel_sdvo_hdmi_sink_detect(connector);
  1163. else {
  1164. struct edid *edid;
  1165. /* if we have an edid check it matches the connection */
  1166. edid = intel_sdvo_get_edid(connector);
  1167. if (edid == NULL)
  1168. edid = intel_sdvo_get_analog_edid(connector);
  1169. if (edid != NULL) {
  1170. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1171. ret = connector_status_disconnected;
  1172. else
  1173. ret = connector_status_connected;
  1174. connector->display_info.raw_edid = NULL;
  1175. kfree(edid);
  1176. } else
  1177. ret = connector_status_connected;
  1178. }
  1179. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1180. if (ret == connector_status_connected) {
  1181. intel_sdvo->is_tv = false;
  1182. intel_sdvo->is_lvds = false;
  1183. intel_sdvo->base.needs_tv_clock = false;
  1184. if (response & SDVO_TV_MASK) {
  1185. intel_sdvo->is_tv = true;
  1186. intel_sdvo->base.needs_tv_clock = true;
  1187. }
  1188. if (response & SDVO_LVDS_MASK)
  1189. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1190. }
  1191. return ret;
  1192. }
  1193. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1194. {
  1195. struct edid *edid;
  1196. /* set the bus switch and get the modes */
  1197. edid = intel_sdvo_get_edid(connector);
  1198. /*
  1199. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1200. * link between analog and digital outputs. So, if the regular SDVO
  1201. * DDC fails, check to see if the analog output is disconnected, in
  1202. * which case we'll look there for the digital DDC data.
  1203. */
  1204. if (edid == NULL)
  1205. edid = intel_sdvo_get_analog_edid(connector);
  1206. if (edid != NULL) {
  1207. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1208. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1209. bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector);
  1210. if (connector_is_digital == monitor_is_digital) {
  1211. drm_mode_connector_update_edid_property(connector, edid);
  1212. drm_add_edid_modes(connector, edid);
  1213. }
  1214. connector->display_info.raw_edid = NULL;
  1215. kfree(edid);
  1216. }
  1217. }
  1218. /*
  1219. * Set of SDVO TV modes.
  1220. * Note! This is in reply order (see loop in get_tv_modes).
  1221. * XXX: all 60Hz refresh?
  1222. */
  1223. static const struct drm_display_mode sdvo_tv_modes[] = {
  1224. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1225. 416, 0, 200, 201, 232, 233, 0,
  1226. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1227. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1228. 416, 0, 240, 241, 272, 273, 0,
  1229. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1230. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1231. 496, 0, 300, 301, 332, 333, 0,
  1232. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1233. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1234. 736, 0, 350, 351, 382, 383, 0,
  1235. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1236. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1237. 736, 0, 400, 401, 432, 433, 0,
  1238. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1239. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1240. 736, 0, 480, 481, 512, 513, 0,
  1241. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1242. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1243. 800, 0, 480, 481, 512, 513, 0,
  1244. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1245. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1246. 800, 0, 576, 577, 608, 609, 0,
  1247. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1248. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1249. 816, 0, 350, 351, 382, 383, 0,
  1250. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1251. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1252. 816, 0, 400, 401, 432, 433, 0,
  1253. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1254. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1255. 816, 0, 480, 481, 512, 513, 0,
  1256. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1257. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1258. 816, 0, 540, 541, 572, 573, 0,
  1259. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1260. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1261. 816, 0, 576, 577, 608, 609, 0,
  1262. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1263. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1264. 864, 0, 576, 577, 608, 609, 0,
  1265. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1266. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1267. 896, 0, 600, 601, 632, 633, 0,
  1268. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1269. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1270. 928, 0, 624, 625, 656, 657, 0,
  1271. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1272. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1273. 1016, 0, 766, 767, 798, 799, 0,
  1274. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1275. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1276. 1120, 0, 768, 769, 800, 801, 0,
  1277. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1278. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1279. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1280. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1281. };
  1282. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1283. {
  1284. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1285. struct intel_sdvo_sdtv_resolution_request tv_res;
  1286. uint32_t reply = 0, format_map = 0;
  1287. int i;
  1288. /* Read the list of supported input resolutions for the selected TV
  1289. * format.
  1290. */
  1291. format_map = 1 << intel_sdvo->tv_format_index;
  1292. memcpy(&tv_res, &format_map,
  1293. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1294. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1295. return;
  1296. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1297. if (!intel_sdvo_write_cmd(intel_sdvo,
  1298. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1299. &tv_res, sizeof(tv_res)))
  1300. return;
  1301. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1302. return;
  1303. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1304. if (reply & (1 << i)) {
  1305. struct drm_display_mode *nmode;
  1306. nmode = drm_mode_duplicate(connector->dev,
  1307. &sdvo_tv_modes[i]);
  1308. if (nmode)
  1309. drm_mode_probed_add(connector, nmode);
  1310. }
  1311. }
  1312. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1313. {
  1314. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1315. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1316. struct drm_display_mode *newmode;
  1317. /*
  1318. * Attempt to get the mode list from DDC.
  1319. * Assume that the preferred modes are
  1320. * arranged in priority order.
  1321. */
  1322. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1323. if (list_empty(&connector->probed_modes) == false)
  1324. goto end;
  1325. /* Fetch modes from VBT */
  1326. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1327. newmode = drm_mode_duplicate(connector->dev,
  1328. dev_priv->sdvo_lvds_vbt_mode);
  1329. if (newmode != NULL) {
  1330. /* Guarantee the mode is preferred */
  1331. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1332. DRM_MODE_TYPE_DRIVER);
  1333. drm_mode_probed_add(connector, newmode);
  1334. }
  1335. }
  1336. end:
  1337. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1338. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1339. intel_sdvo->sdvo_lvds_fixed_mode =
  1340. drm_mode_duplicate(connector->dev, newmode);
  1341. drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
  1342. 0);
  1343. intel_sdvo->is_lvds = true;
  1344. break;
  1345. }
  1346. }
  1347. }
  1348. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1349. {
  1350. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1351. if (IS_TV(intel_sdvo_connector))
  1352. intel_sdvo_get_tv_modes(connector);
  1353. else if (IS_LVDS(intel_sdvo_connector))
  1354. intel_sdvo_get_lvds_modes(connector);
  1355. else
  1356. intel_sdvo_get_ddc_modes(connector);
  1357. return !list_empty(&connector->probed_modes);
  1358. }
  1359. static void
  1360. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1361. {
  1362. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1363. struct drm_device *dev = connector->dev;
  1364. if (intel_sdvo_connector->left)
  1365. drm_property_destroy(dev, intel_sdvo_connector->left);
  1366. if (intel_sdvo_connector->right)
  1367. drm_property_destroy(dev, intel_sdvo_connector->right);
  1368. if (intel_sdvo_connector->top)
  1369. drm_property_destroy(dev, intel_sdvo_connector->top);
  1370. if (intel_sdvo_connector->bottom)
  1371. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1372. if (intel_sdvo_connector->hpos)
  1373. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1374. if (intel_sdvo_connector->vpos)
  1375. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1376. if (intel_sdvo_connector->saturation)
  1377. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1378. if (intel_sdvo_connector->contrast)
  1379. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1380. if (intel_sdvo_connector->hue)
  1381. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1382. if (intel_sdvo_connector->sharpness)
  1383. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1384. if (intel_sdvo_connector->flicker_filter)
  1385. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1386. if (intel_sdvo_connector->flicker_filter_2d)
  1387. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1388. if (intel_sdvo_connector->flicker_filter_adaptive)
  1389. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1390. if (intel_sdvo_connector->tv_luma_filter)
  1391. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1392. if (intel_sdvo_connector->tv_chroma_filter)
  1393. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1394. if (intel_sdvo_connector->dot_crawl)
  1395. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1396. if (intel_sdvo_connector->brightness)
  1397. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1398. }
  1399. static void intel_sdvo_destroy(struct drm_connector *connector)
  1400. {
  1401. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1402. if (intel_sdvo_connector->tv_format)
  1403. drm_property_destroy(connector->dev,
  1404. intel_sdvo_connector->tv_format);
  1405. intel_sdvo_destroy_enhance_property(connector);
  1406. drm_sysfs_connector_remove(connector);
  1407. drm_connector_cleanup(connector);
  1408. kfree(connector);
  1409. }
  1410. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1411. {
  1412. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1413. struct edid *edid;
  1414. bool has_audio = false;
  1415. if (!intel_sdvo->is_hdmi)
  1416. return false;
  1417. edid = intel_sdvo_get_edid(connector);
  1418. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1419. has_audio = drm_detect_monitor_audio(edid);
  1420. return has_audio;
  1421. }
  1422. static int
  1423. intel_sdvo_set_property(struct drm_connector *connector,
  1424. struct drm_property *property,
  1425. uint64_t val)
  1426. {
  1427. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1428. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1429. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1430. uint16_t temp_value;
  1431. uint8_t cmd;
  1432. int ret;
  1433. ret = drm_connector_property_set_value(connector, property, val);
  1434. if (ret)
  1435. return ret;
  1436. if (property == dev_priv->force_audio_property) {
  1437. int i = val;
  1438. bool has_audio;
  1439. if (i == intel_sdvo_connector->force_audio)
  1440. return 0;
  1441. intel_sdvo_connector->force_audio = i;
  1442. if (i == 0)
  1443. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1444. else
  1445. has_audio = i > 0;
  1446. if (has_audio == intel_sdvo->has_hdmi_audio)
  1447. return 0;
  1448. intel_sdvo->has_hdmi_audio = has_audio;
  1449. goto done;
  1450. }
  1451. if (property == dev_priv->broadcast_rgb_property) {
  1452. if (val == !!intel_sdvo->color_range)
  1453. return 0;
  1454. intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1455. goto done;
  1456. }
  1457. #define CHECK_PROPERTY(name, NAME) \
  1458. if (intel_sdvo_connector->name == property) { \
  1459. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1460. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1461. cmd = SDVO_CMD_SET_##NAME; \
  1462. intel_sdvo_connector->cur_##name = temp_value; \
  1463. goto set_value; \
  1464. }
  1465. if (property == intel_sdvo_connector->tv_format) {
  1466. if (val >= TV_FORMAT_NUM)
  1467. return -EINVAL;
  1468. if (intel_sdvo->tv_format_index ==
  1469. intel_sdvo_connector->tv_format_supported[val])
  1470. return 0;
  1471. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1472. goto done;
  1473. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1474. temp_value = val;
  1475. if (intel_sdvo_connector->left == property) {
  1476. drm_connector_property_set_value(connector,
  1477. intel_sdvo_connector->right, val);
  1478. if (intel_sdvo_connector->left_margin == temp_value)
  1479. return 0;
  1480. intel_sdvo_connector->left_margin = temp_value;
  1481. intel_sdvo_connector->right_margin = temp_value;
  1482. temp_value = intel_sdvo_connector->max_hscan -
  1483. intel_sdvo_connector->left_margin;
  1484. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1485. goto set_value;
  1486. } else if (intel_sdvo_connector->right == property) {
  1487. drm_connector_property_set_value(connector,
  1488. intel_sdvo_connector->left, val);
  1489. if (intel_sdvo_connector->right_margin == temp_value)
  1490. return 0;
  1491. intel_sdvo_connector->left_margin = temp_value;
  1492. intel_sdvo_connector->right_margin = temp_value;
  1493. temp_value = intel_sdvo_connector->max_hscan -
  1494. intel_sdvo_connector->left_margin;
  1495. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1496. goto set_value;
  1497. } else if (intel_sdvo_connector->top == property) {
  1498. drm_connector_property_set_value(connector,
  1499. intel_sdvo_connector->bottom, val);
  1500. if (intel_sdvo_connector->top_margin == temp_value)
  1501. return 0;
  1502. intel_sdvo_connector->top_margin = temp_value;
  1503. intel_sdvo_connector->bottom_margin = temp_value;
  1504. temp_value = intel_sdvo_connector->max_vscan -
  1505. intel_sdvo_connector->top_margin;
  1506. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1507. goto set_value;
  1508. } else if (intel_sdvo_connector->bottom == property) {
  1509. drm_connector_property_set_value(connector,
  1510. intel_sdvo_connector->top, val);
  1511. if (intel_sdvo_connector->bottom_margin == temp_value)
  1512. return 0;
  1513. intel_sdvo_connector->top_margin = temp_value;
  1514. intel_sdvo_connector->bottom_margin = temp_value;
  1515. temp_value = intel_sdvo_connector->max_vscan -
  1516. intel_sdvo_connector->top_margin;
  1517. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1518. goto set_value;
  1519. }
  1520. CHECK_PROPERTY(hpos, HPOS)
  1521. CHECK_PROPERTY(vpos, VPOS)
  1522. CHECK_PROPERTY(saturation, SATURATION)
  1523. CHECK_PROPERTY(contrast, CONTRAST)
  1524. CHECK_PROPERTY(hue, HUE)
  1525. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1526. CHECK_PROPERTY(sharpness, SHARPNESS)
  1527. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1528. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1529. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1530. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1531. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1532. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1533. }
  1534. return -EINVAL; /* unknown property */
  1535. set_value:
  1536. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1537. return -EIO;
  1538. done:
  1539. if (intel_sdvo->base.base.crtc) {
  1540. struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
  1541. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1542. crtc->y, crtc->fb);
  1543. }
  1544. return 0;
  1545. #undef CHECK_PROPERTY
  1546. }
  1547. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1548. .dpms = intel_sdvo_dpms,
  1549. .mode_fixup = intel_sdvo_mode_fixup,
  1550. .prepare = intel_encoder_prepare,
  1551. .mode_set = intel_sdvo_mode_set,
  1552. .commit = intel_encoder_commit,
  1553. };
  1554. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1555. .dpms = drm_helper_connector_dpms,
  1556. .detect = intel_sdvo_detect,
  1557. .fill_modes = drm_helper_probe_single_connector_modes,
  1558. .set_property = intel_sdvo_set_property,
  1559. .destroy = intel_sdvo_destroy,
  1560. };
  1561. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1562. .get_modes = intel_sdvo_get_modes,
  1563. .mode_valid = intel_sdvo_mode_valid,
  1564. .best_encoder = intel_best_encoder,
  1565. };
  1566. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1567. {
  1568. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1569. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1570. drm_mode_destroy(encoder->dev,
  1571. intel_sdvo->sdvo_lvds_fixed_mode);
  1572. i2c_del_adapter(&intel_sdvo->ddc);
  1573. intel_encoder_destroy(encoder);
  1574. }
  1575. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1576. .destroy = intel_sdvo_enc_destroy,
  1577. };
  1578. static void
  1579. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1580. {
  1581. uint16_t mask = 0;
  1582. unsigned int num_bits;
  1583. /* Make a mask of outputs less than or equal to our own priority in the
  1584. * list.
  1585. */
  1586. switch (sdvo->controlled_output) {
  1587. case SDVO_OUTPUT_LVDS1:
  1588. mask |= SDVO_OUTPUT_LVDS1;
  1589. case SDVO_OUTPUT_LVDS0:
  1590. mask |= SDVO_OUTPUT_LVDS0;
  1591. case SDVO_OUTPUT_TMDS1:
  1592. mask |= SDVO_OUTPUT_TMDS1;
  1593. case SDVO_OUTPUT_TMDS0:
  1594. mask |= SDVO_OUTPUT_TMDS0;
  1595. case SDVO_OUTPUT_RGB1:
  1596. mask |= SDVO_OUTPUT_RGB1;
  1597. case SDVO_OUTPUT_RGB0:
  1598. mask |= SDVO_OUTPUT_RGB0;
  1599. break;
  1600. }
  1601. /* Count bits to find what number we are in the priority list. */
  1602. mask &= sdvo->caps.output_flags;
  1603. num_bits = hweight16(mask);
  1604. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1605. if (num_bits > 3)
  1606. num_bits = 3;
  1607. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1608. sdvo->ddc_bus = 1 << num_bits;
  1609. }
  1610. /**
  1611. * Choose the appropriate DDC bus for control bus switch command for this
  1612. * SDVO output based on the controlled output.
  1613. *
  1614. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1615. * outputs, then LVDS outputs.
  1616. */
  1617. static void
  1618. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1619. struct intel_sdvo *sdvo, u32 reg)
  1620. {
  1621. struct sdvo_device_mapping *mapping;
  1622. if (IS_SDVOB(reg))
  1623. mapping = &(dev_priv->sdvo_mappings[0]);
  1624. else
  1625. mapping = &(dev_priv->sdvo_mappings[1]);
  1626. if (mapping->initialized)
  1627. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1628. else
  1629. intel_sdvo_guess_ddc_bus(sdvo);
  1630. }
  1631. static void
  1632. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1633. struct intel_sdvo *sdvo, u32 reg)
  1634. {
  1635. struct sdvo_device_mapping *mapping;
  1636. u8 pin, speed;
  1637. if (IS_SDVOB(reg))
  1638. mapping = &dev_priv->sdvo_mappings[0];
  1639. else
  1640. mapping = &dev_priv->sdvo_mappings[1];
  1641. pin = GMBUS_PORT_DPB;
  1642. speed = GMBUS_RATE_1MHZ >> 8;
  1643. if (mapping->initialized) {
  1644. pin = mapping->i2c_pin;
  1645. speed = mapping->i2c_speed;
  1646. }
  1647. if (pin < GMBUS_NUM_PORTS) {
  1648. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1649. intel_gmbus_set_speed(sdvo->i2c, speed);
  1650. intel_gmbus_force_bit(sdvo->i2c, true);
  1651. } else
  1652. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1653. }
  1654. static bool
  1655. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1656. {
  1657. return intel_sdvo_check_supp_encode(intel_sdvo);
  1658. }
  1659. static u8
  1660. intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1661. {
  1662. struct drm_i915_private *dev_priv = dev->dev_private;
  1663. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1664. if (IS_SDVOB(sdvo_reg)) {
  1665. my_mapping = &dev_priv->sdvo_mappings[0];
  1666. other_mapping = &dev_priv->sdvo_mappings[1];
  1667. } else {
  1668. my_mapping = &dev_priv->sdvo_mappings[1];
  1669. other_mapping = &dev_priv->sdvo_mappings[0];
  1670. }
  1671. /* If the BIOS described our SDVO device, take advantage of it. */
  1672. if (my_mapping->slave_addr)
  1673. return my_mapping->slave_addr;
  1674. /* If the BIOS only described a different SDVO device, use the
  1675. * address that it isn't using.
  1676. */
  1677. if (other_mapping->slave_addr) {
  1678. if (other_mapping->slave_addr == 0x70)
  1679. return 0x72;
  1680. else
  1681. return 0x70;
  1682. }
  1683. /* No SDVO device info is found for another DVO port,
  1684. * so use mapping assumption we had before BIOS parsing.
  1685. */
  1686. if (IS_SDVOB(sdvo_reg))
  1687. return 0x70;
  1688. else
  1689. return 0x72;
  1690. }
  1691. static void
  1692. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1693. struct intel_sdvo *encoder)
  1694. {
  1695. drm_connector_init(encoder->base.base.dev,
  1696. &connector->base.base,
  1697. &intel_sdvo_connector_funcs,
  1698. connector->base.base.connector_type);
  1699. drm_connector_helper_add(&connector->base.base,
  1700. &intel_sdvo_connector_helper_funcs);
  1701. connector->base.base.interlace_allowed = 0;
  1702. connector->base.base.doublescan_allowed = 0;
  1703. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1704. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1705. drm_sysfs_connector_add(&connector->base.base);
  1706. }
  1707. static void
  1708. intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
  1709. {
  1710. struct drm_device *dev = connector->base.base.dev;
  1711. intel_attach_force_audio_property(&connector->base.base);
  1712. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
  1713. intel_attach_broadcast_rgb_property(&connector->base.base);
  1714. }
  1715. static bool
  1716. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1717. {
  1718. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1719. struct drm_connector *connector;
  1720. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1721. struct intel_connector *intel_connector;
  1722. struct intel_sdvo_connector *intel_sdvo_connector;
  1723. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1724. if (!intel_sdvo_connector)
  1725. return false;
  1726. if (device == 0) {
  1727. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1728. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1729. } else if (device == 1) {
  1730. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1731. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1732. }
  1733. intel_connector = &intel_sdvo_connector->base;
  1734. connector = &intel_connector->base;
  1735. if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
  1736. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1737. intel_sdvo->hotplug_active[0] |= 1 << device;
  1738. /* Some SDVO devices have one-shot hotplug interrupts.
  1739. * Ensure that they get re-enabled when an interrupt happens.
  1740. */
  1741. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1742. intel_sdvo_enable_hotplug(intel_encoder);
  1743. }
  1744. else
  1745. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1746. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1747. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1748. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1749. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1750. intel_sdvo->is_hdmi = true;
  1751. }
  1752. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1753. (1 << INTEL_ANALOG_CLONE_BIT));
  1754. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1755. if (intel_sdvo->is_hdmi)
  1756. intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
  1757. return true;
  1758. }
  1759. static bool
  1760. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1761. {
  1762. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1763. struct drm_connector *connector;
  1764. struct intel_connector *intel_connector;
  1765. struct intel_sdvo_connector *intel_sdvo_connector;
  1766. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1767. if (!intel_sdvo_connector)
  1768. return false;
  1769. intel_connector = &intel_sdvo_connector->base;
  1770. connector = &intel_connector->base;
  1771. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1772. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1773. intel_sdvo->controlled_output |= type;
  1774. intel_sdvo_connector->output_flag = type;
  1775. intel_sdvo->is_tv = true;
  1776. intel_sdvo->base.needs_tv_clock = true;
  1777. intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1778. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1779. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1780. goto err;
  1781. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1782. goto err;
  1783. return true;
  1784. err:
  1785. intel_sdvo_destroy(connector);
  1786. return false;
  1787. }
  1788. static bool
  1789. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1790. {
  1791. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1792. struct drm_connector *connector;
  1793. struct intel_connector *intel_connector;
  1794. struct intel_sdvo_connector *intel_sdvo_connector;
  1795. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1796. if (!intel_sdvo_connector)
  1797. return false;
  1798. intel_connector = &intel_sdvo_connector->base;
  1799. connector = &intel_connector->base;
  1800. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1801. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1802. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1803. if (device == 0) {
  1804. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1805. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1806. } else if (device == 1) {
  1807. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1808. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1809. }
  1810. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1811. (1 << INTEL_ANALOG_CLONE_BIT));
  1812. intel_sdvo_connector_init(intel_sdvo_connector,
  1813. intel_sdvo);
  1814. return true;
  1815. }
  1816. static bool
  1817. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  1818. {
  1819. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1820. struct drm_connector *connector;
  1821. struct intel_connector *intel_connector;
  1822. struct intel_sdvo_connector *intel_sdvo_connector;
  1823. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1824. if (!intel_sdvo_connector)
  1825. return false;
  1826. intel_connector = &intel_sdvo_connector->base;
  1827. connector = &intel_connector->base;
  1828. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1829. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1830. if (device == 0) {
  1831. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1832. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1833. } else if (device == 1) {
  1834. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1835. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1836. }
  1837. intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1838. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1839. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1840. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1841. goto err;
  1842. return true;
  1843. err:
  1844. intel_sdvo_destroy(connector);
  1845. return false;
  1846. }
  1847. static bool
  1848. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  1849. {
  1850. intel_sdvo->is_tv = false;
  1851. intel_sdvo->base.needs_tv_clock = false;
  1852. intel_sdvo->is_lvds = false;
  1853. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1854. if (flags & SDVO_OUTPUT_TMDS0)
  1855. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  1856. return false;
  1857. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1858. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  1859. return false;
  1860. /* TV has no XXX1 function block */
  1861. if (flags & SDVO_OUTPUT_SVID0)
  1862. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  1863. return false;
  1864. if (flags & SDVO_OUTPUT_CVBS0)
  1865. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  1866. return false;
  1867. if (flags & SDVO_OUTPUT_RGB0)
  1868. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  1869. return false;
  1870. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1871. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  1872. return false;
  1873. if (flags & SDVO_OUTPUT_LVDS0)
  1874. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  1875. return false;
  1876. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1877. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  1878. return false;
  1879. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1880. unsigned char bytes[2];
  1881. intel_sdvo->controlled_output = 0;
  1882. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  1883. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1884. SDVO_NAME(intel_sdvo),
  1885. bytes[0], bytes[1]);
  1886. return false;
  1887. }
  1888. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
  1889. return true;
  1890. }
  1891. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  1892. struct intel_sdvo_connector *intel_sdvo_connector,
  1893. int type)
  1894. {
  1895. struct drm_device *dev = intel_sdvo->base.base.dev;
  1896. struct intel_sdvo_tv_format format;
  1897. uint32_t format_map, i;
  1898. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  1899. return false;
  1900. BUILD_BUG_ON(sizeof(format) != 6);
  1901. if (!intel_sdvo_get_value(intel_sdvo,
  1902. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1903. &format, sizeof(format)))
  1904. return false;
  1905. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1906. if (format_map == 0)
  1907. return false;
  1908. intel_sdvo_connector->format_supported_num = 0;
  1909. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1910. if (format_map & (1 << i))
  1911. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  1912. intel_sdvo_connector->tv_format =
  1913. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1914. "mode", intel_sdvo_connector->format_supported_num);
  1915. if (!intel_sdvo_connector->tv_format)
  1916. return false;
  1917. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  1918. drm_property_add_enum(
  1919. intel_sdvo_connector->tv_format, i,
  1920. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  1921. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  1922. drm_connector_attach_property(&intel_sdvo_connector->base.base,
  1923. intel_sdvo_connector->tv_format, 0);
  1924. return true;
  1925. }
  1926. #define ENHANCEMENT(name, NAME) do { \
  1927. if (enhancements.name) { \
  1928. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1929. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1930. return false; \
  1931. intel_sdvo_connector->max_##name = data_value[0]; \
  1932. intel_sdvo_connector->cur_##name = response; \
  1933. intel_sdvo_connector->name = \
  1934. drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
  1935. if (!intel_sdvo_connector->name) return false; \
  1936. intel_sdvo_connector->name->values[0] = 0; \
  1937. intel_sdvo_connector->name->values[1] = data_value[0]; \
  1938. drm_connector_attach_property(connector, \
  1939. intel_sdvo_connector->name, \
  1940. intel_sdvo_connector->cur_##name); \
  1941. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1942. data_value[0], data_value[1], response); \
  1943. } \
  1944. } while(0)
  1945. static bool
  1946. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  1947. struct intel_sdvo_connector *intel_sdvo_connector,
  1948. struct intel_sdvo_enhancements_reply enhancements)
  1949. {
  1950. struct drm_device *dev = intel_sdvo->base.base.dev;
  1951. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  1952. uint16_t response, data_value[2];
  1953. /* when horizontal overscan is supported, Add the left/right property */
  1954. if (enhancements.overscan_h) {
  1955. if (!intel_sdvo_get_value(intel_sdvo,
  1956. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1957. &data_value, 4))
  1958. return false;
  1959. if (!intel_sdvo_get_value(intel_sdvo,
  1960. SDVO_CMD_GET_OVERSCAN_H,
  1961. &response, 2))
  1962. return false;
  1963. intel_sdvo_connector->max_hscan = data_value[0];
  1964. intel_sdvo_connector->left_margin = data_value[0] - response;
  1965. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  1966. intel_sdvo_connector->left =
  1967. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  1968. "left_margin", 2);
  1969. if (!intel_sdvo_connector->left)
  1970. return false;
  1971. intel_sdvo_connector->left->values[0] = 0;
  1972. intel_sdvo_connector->left->values[1] = data_value[0];
  1973. drm_connector_attach_property(connector,
  1974. intel_sdvo_connector->left,
  1975. intel_sdvo_connector->left_margin);
  1976. intel_sdvo_connector->right =
  1977. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  1978. "right_margin", 2);
  1979. if (!intel_sdvo_connector->right)
  1980. return false;
  1981. intel_sdvo_connector->right->values[0] = 0;
  1982. intel_sdvo_connector->right->values[1] = data_value[0];
  1983. drm_connector_attach_property(connector,
  1984. intel_sdvo_connector->right,
  1985. intel_sdvo_connector->right_margin);
  1986. DRM_DEBUG_KMS("h_overscan: max %d, "
  1987. "default %d, current %d\n",
  1988. data_value[0], data_value[1], response);
  1989. }
  1990. if (enhancements.overscan_v) {
  1991. if (!intel_sdvo_get_value(intel_sdvo,
  1992. SDVO_CMD_GET_MAX_OVERSCAN_V,
  1993. &data_value, 4))
  1994. return false;
  1995. if (!intel_sdvo_get_value(intel_sdvo,
  1996. SDVO_CMD_GET_OVERSCAN_V,
  1997. &response, 2))
  1998. return false;
  1999. intel_sdvo_connector->max_vscan = data_value[0];
  2000. intel_sdvo_connector->top_margin = data_value[0] - response;
  2001. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2002. intel_sdvo_connector->top =
  2003. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2004. "top_margin", 2);
  2005. if (!intel_sdvo_connector->top)
  2006. return false;
  2007. intel_sdvo_connector->top->values[0] = 0;
  2008. intel_sdvo_connector->top->values[1] = data_value[0];
  2009. drm_connector_attach_property(connector,
  2010. intel_sdvo_connector->top,
  2011. intel_sdvo_connector->top_margin);
  2012. intel_sdvo_connector->bottom =
  2013. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2014. "bottom_margin", 2);
  2015. if (!intel_sdvo_connector->bottom)
  2016. return false;
  2017. intel_sdvo_connector->bottom->values[0] = 0;
  2018. intel_sdvo_connector->bottom->values[1] = data_value[0];
  2019. drm_connector_attach_property(connector,
  2020. intel_sdvo_connector->bottom,
  2021. intel_sdvo_connector->bottom_margin);
  2022. DRM_DEBUG_KMS("v_overscan: max %d, "
  2023. "default %d, current %d\n",
  2024. data_value[0], data_value[1], response);
  2025. }
  2026. ENHANCEMENT(hpos, HPOS);
  2027. ENHANCEMENT(vpos, VPOS);
  2028. ENHANCEMENT(saturation, SATURATION);
  2029. ENHANCEMENT(contrast, CONTRAST);
  2030. ENHANCEMENT(hue, HUE);
  2031. ENHANCEMENT(sharpness, SHARPNESS);
  2032. ENHANCEMENT(brightness, BRIGHTNESS);
  2033. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2034. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2035. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2036. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2037. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2038. if (enhancements.dot_crawl) {
  2039. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2040. return false;
  2041. intel_sdvo_connector->max_dot_crawl = 1;
  2042. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2043. intel_sdvo_connector->dot_crawl =
  2044. drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
  2045. if (!intel_sdvo_connector->dot_crawl)
  2046. return false;
  2047. intel_sdvo_connector->dot_crawl->values[0] = 0;
  2048. intel_sdvo_connector->dot_crawl->values[1] = 1;
  2049. drm_connector_attach_property(connector,
  2050. intel_sdvo_connector->dot_crawl,
  2051. intel_sdvo_connector->cur_dot_crawl);
  2052. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2053. }
  2054. return true;
  2055. }
  2056. static bool
  2057. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2058. struct intel_sdvo_connector *intel_sdvo_connector,
  2059. struct intel_sdvo_enhancements_reply enhancements)
  2060. {
  2061. struct drm_device *dev = intel_sdvo->base.base.dev;
  2062. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2063. uint16_t response, data_value[2];
  2064. ENHANCEMENT(brightness, BRIGHTNESS);
  2065. return true;
  2066. }
  2067. #undef ENHANCEMENT
  2068. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2069. struct intel_sdvo_connector *intel_sdvo_connector)
  2070. {
  2071. union {
  2072. struct intel_sdvo_enhancements_reply reply;
  2073. uint16_t response;
  2074. } enhancements;
  2075. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2076. enhancements.response = 0;
  2077. intel_sdvo_get_value(intel_sdvo,
  2078. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2079. &enhancements, sizeof(enhancements));
  2080. if (enhancements.response == 0) {
  2081. DRM_DEBUG_KMS("No enhancement is supported\n");
  2082. return true;
  2083. }
  2084. if (IS_TV(intel_sdvo_connector))
  2085. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2086. else if(IS_LVDS(intel_sdvo_connector))
  2087. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2088. else
  2089. return true;
  2090. }
  2091. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2092. struct i2c_msg *msgs,
  2093. int num)
  2094. {
  2095. struct intel_sdvo *sdvo = adapter->algo_data;
  2096. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2097. return -EIO;
  2098. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2099. }
  2100. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2101. {
  2102. struct intel_sdvo *sdvo = adapter->algo_data;
  2103. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2104. }
  2105. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2106. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2107. .functionality = intel_sdvo_ddc_proxy_func
  2108. };
  2109. static bool
  2110. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2111. struct drm_device *dev)
  2112. {
  2113. sdvo->ddc.owner = THIS_MODULE;
  2114. sdvo->ddc.class = I2C_CLASS_DDC;
  2115. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2116. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2117. sdvo->ddc.algo_data = sdvo;
  2118. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2119. return i2c_add_adapter(&sdvo->ddc) == 0;
  2120. }
  2121. bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2122. {
  2123. struct drm_i915_private *dev_priv = dev->dev_private;
  2124. struct intel_encoder *intel_encoder;
  2125. struct intel_sdvo *intel_sdvo;
  2126. int i;
  2127. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2128. if (!intel_sdvo)
  2129. return false;
  2130. intel_sdvo->sdvo_reg = sdvo_reg;
  2131. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2132. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2133. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
  2134. kfree(intel_sdvo);
  2135. return false;
  2136. }
  2137. /* encoder type will be decided later */
  2138. intel_encoder = &intel_sdvo->base;
  2139. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2140. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2141. /* Read the regs to test if we can talk to the device */
  2142. for (i = 0; i < 0x40; i++) {
  2143. u8 byte;
  2144. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2145. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2146. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2147. goto err;
  2148. }
  2149. }
  2150. if (IS_SDVOB(sdvo_reg))
  2151. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2152. else
  2153. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2154. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2155. /* In default case sdvo lvds is false */
  2156. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2157. goto err;
  2158. /* Set up hotplug command - note paranoia about contents of reply.
  2159. * We assume that the hardware is in a sane state, and only touch
  2160. * the bits we think we understand.
  2161. */
  2162. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
  2163. &intel_sdvo->hotplug_active, 2);
  2164. intel_sdvo->hotplug_active[0] &= ~0x3;
  2165. if (intel_sdvo_output_setup(intel_sdvo,
  2166. intel_sdvo->caps.output_flags) != true) {
  2167. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2168. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2169. goto err;
  2170. }
  2171. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2172. /* Set the input timing to the screen. Assume always input 0. */
  2173. if (!intel_sdvo_set_target_input(intel_sdvo))
  2174. goto err;
  2175. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2176. &intel_sdvo->pixel_clock_min,
  2177. &intel_sdvo->pixel_clock_max))
  2178. goto err;
  2179. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2180. "clock range %dMHz - %dMHz, "
  2181. "input 1: %c, input 2: %c, "
  2182. "output 1: %c, output 2: %c\n",
  2183. SDVO_NAME(intel_sdvo),
  2184. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2185. intel_sdvo->caps.device_rev_id,
  2186. intel_sdvo->pixel_clock_min / 1000,
  2187. intel_sdvo->pixel_clock_max / 1000,
  2188. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2189. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2190. /* check currently supported outputs */
  2191. intel_sdvo->caps.output_flags &
  2192. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2193. intel_sdvo->caps.output_flags &
  2194. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2195. return true;
  2196. err:
  2197. drm_encoder_cleanup(&intel_encoder->base);
  2198. i2c_del_adapter(&intel_sdvo->ddc);
  2199. kfree(intel_sdvo);
  2200. return false;
  2201. }