iwl-rx.c 36 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <net/mac80211.h>
  31. #include <asm/unaligned.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-sta.h"
  36. #include "iwl-io.h"
  37. #include "iwl-calib.h"
  38. #include "iwl-helpers.h"
  39. /************************** RX-FUNCTIONS ****************************/
  40. /*
  41. * Rx theory of operation
  42. *
  43. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  44. * each of which point to Receive Buffers to be filled by the NIC. These get
  45. * used not only for Rx frames, but for any command response or notification
  46. * from the NIC. The driver and NIC manage the Rx buffers by means
  47. * of indexes into the circular buffer.
  48. *
  49. * Rx Queue Indexes
  50. * The host/firmware share two index registers for managing the Rx buffers.
  51. *
  52. * The READ index maps to the first position that the firmware may be writing
  53. * to -- the driver can read up to (but not including) this position and get
  54. * good data.
  55. * The READ index is managed by the firmware once the card is enabled.
  56. *
  57. * The WRITE index maps to the last position the driver has read from -- the
  58. * position preceding WRITE is the last slot the firmware can place a packet.
  59. *
  60. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  61. * WRITE = READ.
  62. *
  63. * During initialization, the host sets up the READ queue position to the first
  64. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  65. *
  66. * When the firmware places a packet in a buffer, it will advance the READ index
  67. * and fire the RX interrupt. The driver can then query the READ index and
  68. * process as many packets as possible, moving the WRITE index forward as it
  69. * resets the Rx queue buffers with new memory.
  70. *
  71. * The management in the driver is as follows:
  72. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  73. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  74. * to replenish the iwl->rxq->rx_free.
  75. * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  76. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  77. * 'processed' and 'read' driver indexes as well)
  78. * + A received packet is processed and handed to the kernel network stack,
  79. * detached from the iwl->rxq. The driver 'processed' index is updated.
  80. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  81. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  82. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  83. * were enough free buffers and RX_STALLED is set it is cleared.
  84. *
  85. *
  86. * Driver sequence:
  87. *
  88. * iwl_rx_queue_alloc() Allocates rx_free
  89. * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
  90. * iwl_rx_queue_restock
  91. * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  92. * queue, updates firmware pointers, and updates
  93. * the WRITE index. If insufficient rx_free buffers
  94. * are available, schedules iwl_rx_replenish
  95. *
  96. * -- enable interrupts --
  97. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  98. * READ INDEX, detaching the SKB from the pool.
  99. * Moves the packet buffer from queue to rx_used.
  100. * Calls iwl_rx_queue_restock to refill any empty
  101. * slots.
  102. * ...
  103. *
  104. */
  105. /**
  106. * iwl_rx_queue_space - Return number of free slots available in queue.
  107. */
  108. int iwl_rx_queue_space(const struct iwl_rx_queue *q)
  109. {
  110. int s = q->read - q->write;
  111. if (s <= 0)
  112. s += RX_QUEUE_SIZE;
  113. /* keep some buffer to not confuse full and empty queue */
  114. s -= 2;
  115. if (s < 0)
  116. s = 0;
  117. return s;
  118. }
  119. EXPORT_SYMBOL(iwl_rx_queue_space);
  120. /**
  121. * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  122. */
  123. int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  124. {
  125. unsigned long flags;
  126. u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg;
  127. u32 reg;
  128. int ret = 0;
  129. spin_lock_irqsave(&q->lock, flags);
  130. if (q->need_update == 0)
  131. goto exit_unlock;
  132. /* If power-saving is in use, make sure device is awake */
  133. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  134. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  135. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  136. iwl_set_bit(priv, CSR_GP_CNTRL,
  137. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  138. goto exit_unlock;
  139. }
  140. q->write_actual = (q->write & ~0x7);
  141. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  142. /* Else device is assumed to be awake */
  143. } else {
  144. /* Device expects a multiple of 8 */
  145. q->write_actual = (q->write & ~0x7);
  146. iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
  147. }
  148. q->need_update = 0;
  149. exit_unlock:
  150. spin_unlock_irqrestore(&q->lock, flags);
  151. return ret;
  152. }
  153. EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
  154. /**
  155. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  156. */
  157. static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
  158. dma_addr_t dma_addr)
  159. {
  160. return cpu_to_le32((u32)(dma_addr >> 8));
  161. }
  162. /**
  163. * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
  164. *
  165. * If there are slots in the RX queue that need to be restocked,
  166. * and we have free pre-allocated buffers, fill the ranks as much
  167. * as we can, pulling from rx_free.
  168. *
  169. * This moves the 'write' index forward to catch up with 'processed', and
  170. * also updates the memory address in the firmware to reference the new
  171. * target buffer.
  172. */
  173. int iwl_rx_queue_restock(struct iwl_priv *priv)
  174. {
  175. struct iwl_rx_queue *rxq = &priv->rxq;
  176. struct list_head *element;
  177. struct iwl_rx_mem_buffer *rxb;
  178. unsigned long flags;
  179. int write;
  180. int ret = 0;
  181. spin_lock_irqsave(&rxq->lock, flags);
  182. write = rxq->write & ~0x7;
  183. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  184. /* Get next free Rx buffer, remove from free list */
  185. element = rxq->rx_free.next;
  186. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  187. list_del(element);
  188. /* Point to Rx buffer via next RBD in circular buffer */
  189. rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->page_dma);
  190. rxq->queue[rxq->write] = rxb;
  191. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  192. rxq->free_count--;
  193. }
  194. spin_unlock_irqrestore(&rxq->lock, flags);
  195. /* If the pre-allocated buffer pool is dropping low, schedule to
  196. * refill it */
  197. if (rxq->free_count <= RX_LOW_WATERMARK)
  198. queue_work(priv->workqueue, &priv->rx_replenish);
  199. /* If we've added more space for the firmware to place data, tell it.
  200. * Increment device's write pointer in multiples of 8. */
  201. if (rxq->write_actual != (rxq->write & ~0x7)) {
  202. spin_lock_irqsave(&rxq->lock, flags);
  203. rxq->need_update = 1;
  204. spin_unlock_irqrestore(&rxq->lock, flags);
  205. ret = iwl_rx_queue_update_write_ptr(priv, rxq);
  206. }
  207. return ret;
  208. }
  209. EXPORT_SYMBOL(iwl_rx_queue_restock);
  210. /**
  211. * iwl_rx_replenish - Move all used packet from rx_used to rx_free
  212. *
  213. * When moving to rx_free an SKB is allocated for the slot.
  214. *
  215. * Also restock the Rx queue via iwl_rx_queue_restock.
  216. * This is called as a scheduled work item (except for during initialization)
  217. */
  218. void iwl_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  219. {
  220. struct iwl_rx_queue *rxq = &priv->rxq;
  221. struct list_head *element;
  222. struct iwl_rx_mem_buffer *rxb;
  223. struct page *page;
  224. unsigned long flags;
  225. while (1) {
  226. spin_lock_irqsave(&rxq->lock, flags);
  227. if (list_empty(&rxq->rx_used)) {
  228. spin_unlock_irqrestore(&rxq->lock, flags);
  229. return;
  230. }
  231. spin_unlock_irqrestore(&rxq->lock, flags);
  232. if (rxq->free_count > RX_LOW_WATERMARK)
  233. priority |= __GFP_NOWARN;
  234. if (priv->hw_params.rx_page_order > 0)
  235. priority |= __GFP_COMP;
  236. /* Alloc a new receive buffer */
  237. page = alloc_pages(priority, priv->hw_params.rx_page_order);
  238. if (!page) {
  239. if (net_ratelimit())
  240. IWL_DEBUG_INFO(priv, "alloc_pages failed, "
  241. "order: %d\n",
  242. priv->hw_params.rx_page_order);
  243. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  244. net_ratelimit())
  245. IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
  246. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  247. rxq->free_count);
  248. /* We don't reschedule replenish work here -- we will
  249. * call the restock method and if it still needs
  250. * more buffers it will schedule replenish */
  251. return;
  252. }
  253. spin_lock_irqsave(&rxq->lock, flags);
  254. if (list_empty(&rxq->rx_used)) {
  255. spin_unlock_irqrestore(&rxq->lock, flags);
  256. __free_pages(page, priv->hw_params.rx_page_order);
  257. return;
  258. }
  259. element = rxq->rx_used.next;
  260. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  261. list_del(element);
  262. spin_unlock_irqrestore(&rxq->lock, flags);
  263. rxb->page = page;
  264. /* Get physical address of the RB */
  265. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  266. PAGE_SIZE << priv->hw_params.rx_page_order,
  267. PCI_DMA_FROMDEVICE);
  268. /* dma address must be no more than 36 bits */
  269. BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
  270. /* and also 256 byte aligned! */
  271. BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
  272. spin_lock_irqsave(&rxq->lock, flags);
  273. list_add_tail(&rxb->list, &rxq->rx_free);
  274. rxq->free_count++;
  275. priv->alloc_rxb_page++;
  276. spin_unlock_irqrestore(&rxq->lock, flags);
  277. }
  278. }
  279. void iwl_rx_replenish(struct iwl_priv *priv)
  280. {
  281. unsigned long flags;
  282. iwl_rx_allocate(priv, GFP_KERNEL);
  283. spin_lock_irqsave(&priv->lock, flags);
  284. iwl_rx_queue_restock(priv);
  285. spin_unlock_irqrestore(&priv->lock, flags);
  286. }
  287. EXPORT_SYMBOL(iwl_rx_replenish);
  288. void iwl_rx_replenish_now(struct iwl_priv *priv)
  289. {
  290. iwl_rx_allocate(priv, GFP_ATOMIC);
  291. iwl_rx_queue_restock(priv);
  292. }
  293. EXPORT_SYMBOL(iwl_rx_replenish_now);
  294. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  295. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  296. * This free routine walks the list of POOL entries and if SKB is set to
  297. * non NULL it is unmapped and freed
  298. */
  299. void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  300. {
  301. int i;
  302. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  303. if (rxq->pool[i].page != NULL) {
  304. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  305. PAGE_SIZE << priv->hw_params.rx_page_order,
  306. PCI_DMA_FROMDEVICE);
  307. __free_pages(rxq->pool[i].page,
  308. priv->hw_params.rx_page_order);
  309. rxq->pool[i].page = NULL;
  310. priv->alloc_rxb_page--;
  311. }
  312. }
  313. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  314. rxq->dma_addr);
  315. pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
  316. rxq->rb_stts, rxq->rb_stts_dma);
  317. rxq->bd = NULL;
  318. rxq->rb_stts = NULL;
  319. }
  320. EXPORT_SYMBOL(iwl_rx_queue_free);
  321. int iwl_rx_queue_alloc(struct iwl_priv *priv)
  322. {
  323. struct iwl_rx_queue *rxq = &priv->rxq;
  324. struct pci_dev *dev = priv->pci_dev;
  325. int i;
  326. spin_lock_init(&rxq->lock);
  327. INIT_LIST_HEAD(&rxq->rx_free);
  328. INIT_LIST_HEAD(&rxq->rx_used);
  329. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  330. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  331. if (!rxq->bd)
  332. goto err_bd;
  333. rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status),
  334. &rxq->rb_stts_dma);
  335. if (!rxq->rb_stts)
  336. goto err_rb;
  337. /* Fill the rx_used queue with _all_ of the Rx buffers */
  338. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  339. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  340. /* Set us so that we have processed and used all buffers, but have
  341. * not restocked the Rx queue with fresh buffers */
  342. rxq->read = rxq->write = 0;
  343. rxq->write_actual = 0;
  344. rxq->free_count = 0;
  345. rxq->need_update = 0;
  346. return 0;
  347. err_rb:
  348. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  349. rxq->dma_addr);
  350. err_bd:
  351. return -ENOMEM;
  352. }
  353. EXPORT_SYMBOL(iwl_rx_queue_alloc);
  354. void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  355. {
  356. unsigned long flags;
  357. int i;
  358. spin_lock_irqsave(&rxq->lock, flags);
  359. INIT_LIST_HEAD(&rxq->rx_free);
  360. INIT_LIST_HEAD(&rxq->rx_used);
  361. /* Fill the rx_used queue with _all_ of the Rx buffers */
  362. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  363. /* In the reset function, these buffers may have been allocated
  364. * to an SKB, so we need to unmap and free potential storage */
  365. if (rxq->pool[i].page != NULL) {
  366. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  367. PAGE_SIZE << priv->hw_params.rx_page_order,
  368. PCI_DMA_FROMDEVICE);
  369. priv->alloc_rxb_page--;
  370. __free_pages(rxq->pool[i].page,
  371. priv->hw_params.rx_page_order);
  372. rxq->pool[i].page = NULL;
  373. }
  374. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  375. }
  376. /* Set us so that we have processed and used all buffers, but have
  377. * not restocked the Rx queue with fresh buffers */
  378. rxq->read = rxq->write = 0;
  379. rxq->write_actual = 0;
  380. rxq->free_count = 0;
  381. spin_unlock_irqrestore(&rxq->lock, flags);
  382. }
  383. int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  384. {
  385. u32 rb_size;
  386. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  387. u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
  388. if (!priv->cfg->use_isr_legacy)
  389. rb_timeout = RX_RB_TIMEOUT;
  390. if (priv->cfg->mod_params->amsdu_size_8K)
  391. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  392. else
  393. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  394. /* Stop Rx DMA */
  395. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  396. /* Reset driver's Rx queue write index */
  397. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  398. /* Tell device where to find RBD circular buffer in DRAM */
  399. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  400. (u32)(rxq->dma_addr >> 8));
  401. /* Tell device where in DRAM to update its Rx status */
  402. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  403. rxq->rb_stts_dma >> 4);
  404. /* Enable Rx DMA
  405. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  406. * the credit mechanism in 5000 HW RX FIFO
  407. * Direct rx interrupts to hosts
  408. * Rx buffer size 4 or 8k
  409. * RB timeout 0x10
  410. * 256 RBDs
  411. */
  412. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  413. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  414. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  415. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  416. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  417. rb_size|
  418. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  419. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  420. iwl_write32(priv, CSR_INT_COALESCING, 0x40);
  421. return 0;
  422. }
  423. int iwl_rxq_stop(struct iwl_priv *priv)
  424. {
  425. /* stop Rx DMA */
  426. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  427. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  428. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  429. return 0;
  430. }
  431. EXPORT_SYMBOL(iwl_rxq_stop);
  432. void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
  433. struct iwl_rx_mem_buffer *rxb)
  434. {
  435. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  436. struct iwl_missed_beacon_notif *missed_beacon;
  437. missed_beacon = &pkt->u.missed_beacon;
  438. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  439. IWL_DEBUG_CALIB(priv, "missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  440. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  441. le32_to_cpu(missed_beacon->total_missed_becons),
  442. le32_to_cpu(missed_beacon->num_recvd_beacons),
  443. le32_to_cpu(missed_beacon->num_expected_beacons));
  444. if (!test_bit(STATUS_SCANNING, &priv->status))
  445. iwl_init_sensitivity(priv);
  446. }
  447. }
  448. EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
  449. /* Calculate noise level, based on measurements during network silence just
  450. * before arriving beacon. This measurement can be done only if we know
  451. * exactly when to expect beacons, therefore only when we're associated. */
  452. static void iwl_rx_calc_noise(struct iwl_priv *priv)
  453. {
  454. struct statistics_rx_non_phy *rx_info
  455. = &(priv->statistics.rx.general);
  456. int num_active_rx = 0;
  457. int total_silence = 0;
  458. int bcn_silence_a =
  459. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  460. int bcn_silence_b =
  461. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  462. int bcn_silence_c =
  463. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  464. if (bcn_silence_a) {
  465. total_silence += bcn_silence_a;
  466. num_active_rx++;
  467. }
  468. if (bcn_silence_b) {
  469. total_silence += bcn_silence_b;
  470. num_active_rx++;
  471. }
  472. if (bcn_silence_c) {
  473. total_silence += bcn_silence_c;
  474. num_active_rx++;
  475. }
  476. /* Average among active antennas */
  477. if (num_active_rx)
  478. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  479. else
  480. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  481. IWL_DEBUG_CALIB(priv, "inband silence a %u, b %u, c %u, dBm %d\n",
  482. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  483. priv->last_rx_noise);
  484. }
  485. #ifdef CONFIG_IWLWIFI_DEBUG
  486. /*
  487. * based on the assumption of all statistics counter are in DWORD
  488. * FIXME: This function is for debugging, do not deal with
  489. * the case of counters roll-over.
  490. */
  491. static void iwl_accumulative_statistics(struct iwl_priv *priv,
  492. __le32 *stats)
  493. {
  494. int i;
  495. __le32 *prev_stats;
  496. u32 *accum_stats;
  497. prev_stats = (__le32 *)&priv->statistics;
  498. accum_stats = (u32 *)&priv->accum_statistics;
  499. for (i = sizeof(__le32); i < sizeof(struct iwl_notif_statistics);
  500. i += sizeof(__le32), stats++, prev_stats++, accum_stats++)
  501. if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats))
  502. *accum_stats += (le32_to_cpu(*stats) -
  503. le32_to_cpu(*prev_stats));
  504. /* reset accumulative statistics for "no-counter" type statistics */
  505. priv->accum_statistics.general.temperature =
  506. priv->statistics.general.temperature;
  507. priv->accum_statistics.general.temperature_m =
  508. priv->statistics.general.temperature_m;
  509. priv->accum_statistics.general.ttl_timestamp =
  510. priv->statistics.general.ttl_timestamp;
  511. priv->accum_statistics.tx.tx_power.ant_a =
  512. priv->statistics.tx.tx_power.ant_a;
  513. priv->accum_statistics.tx.tx_power.ant_b =
  514. priv->statistics.tx.tx_power.ant_b;
  515. priv->accum_statistics.tx.tx_power.ant_c =
  516. priv->statistics.tx.tx_power.ant_c;
  517. }
  518. #endif
  519. #define REG_RECALIB_PERIOD (60)
  520. void iwl_rx_statistics(struct iwl_priv *priv,
  521. struct iwl_rx_mem_buffer *rxb)
  522. {
  523. int change;
  524. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  525. IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
  526. (int)sizeof(priv->statistics),
  527. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  528. change = ((priv->statistics.general.temperature !=
  529. pkt->u.stats.general.temperature) ||
  530. ((priv->statistics.flag &
  531. STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
  532. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
  533. #ifdef CONFIG_IWLWIFI_DEBUG
  534. iwl_accumulative_statistics(priv, (__le32 *)&pkt->u.stats);
  535. #endif
  536. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  537. set_bit(STATUS_STATISTICS, &priv->status);
  538. /* Reschedule the statistics timer to occur in
  539. * REG_RECALIB_PERIOD seconds to ensure we get a
  540. * thermal update even if the uCode doesn't give
  541. * us one */
  542. mod_timer(&priv->statistics_periodic, jiffies +
  543. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  544. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  545. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  546. iwl_rx_calc_noise(priv);
  547. queue_work(priv->workqueue, &priv->run_time_calib_work);
  548. }
  549. iwl_leds_background(priv);
  550. if (priv->cfg->ops->lib->temp_ops.temperature && change)
  551. priv->cfg->ops->lib->temp_ops.temperature(priv);
  552. }
  553. EXPORT_SYMBOL(iwl_rx_statistics);
  554. #define PERFECT_RSSI (-20) /* dBm */
  555. #define WORST_RSSI (-95) /* dBm */
  556. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  557. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  558. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  559. * about formulas used below. */
  560. static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm)
  561. {
  562. int sig_qual;
  563. int degradation = PERFECT_RSSI - rssi_dbm;
  564. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  565. * as indicator; formula is (signal dbm - noise dbm).
  566. * SNR at or above 40 is a great signal (100%).
  567. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  568. * Weakest usable signal is usually 10 - 15 dB SNR. */
  569. if (noise_dbm) {
  570. if (rssi_dbm - noise_dbm >= 40)
  571. return 100;
  572. else if (rssi_dbm < noise_dbm)
  573. return 0;
  574. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  575. /* Else use just the signal level.
  576. * This formula is a least squares fit of data points collected and
  577. * compared with a reference system that had a percentage (%) display
  578. * for signal quality. */
  579. } else
  580. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  581. (15 * RSSI_RANGE + 62 * degradation)) /
  582. (RSSI_RANGE * RSSI_RANGE);
  583. if (sig_qual > 100)
  584. sig_qual = 100;
  585. else if (sig_qual < 1)
  586. sig_qual = 0;
  587. return sig_qual;
  588. }
  589. /* Calc max signal level (dBm) among 3 possible receivers */
  590. static inline int iwl_calc_rssi(struct iwl_priv *priv,
  591. struct iwl_rx_phy_res *rx_resp)
  592. {
  593. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  594. }
  595. #ifdef CONFIG_IWLWIFI_DEBUG
  596. /**
  597. * iwl_dbg_report_frame - dump frame to syslog during debug sessions
  598. *
  599. * You may hack this function to show different aspects of received frames,
  600. * including selective frame dumps.
  601. * group100 parameter selects whether to show 1 out of 100 good data frames.
  602. * All beacon and probe response frames are printed.
  603. */
  604. static void iwl_dbg_report_frame(struct iwl_priv *priv,
  605. struct iwl_rx_phy_res *phy_res, u16 length,
  606. struct ieee80211_hdr *header, int group100)
  607. {
  608. u32 to_us;
  609. u32 print_summary = 0;
  610. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  611. u32 hundred = 0;
  612. u32 dataframe = 0;
  613. __le16 fc;
  614. u16 seq_ctl;
  615. u16 channel;
  616. u16 phy_flags;
  617. u32 rate_n_flags;
  618. u32 tsf_low;
  619. int rssi;
  620. if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX)))
  621. return;
  622. /* MAC header */
  623. fc = header->frame_control;
  624. seq_ctl = le16_to_cpu(header->seq_ctrl);
  625. /* metadata */
  626. channel = le16_to_cpu(phy_res->channel);
  627. phy_flags = le16_to_cpu(phy_res->phy_flags);
  628. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  629. /* signal statistics */
  630. rssi = iwl_calc_rssi(priv, phy_res);
  631. tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
  632. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  633. /* if data frame is to us and all is good,
  634. * (optionally) print summary for only 1 out of every 100 */
  635. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  636. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  637. dataframe = 1;
  638. if (!group100)
  639. print_summary = 1; /* print each frame */
  640. else if (priv->framecnt_to_us < 100) {
  641. priv->framecnt_to_us++;
  642. print_summary = 0;
  643. } else {
  644. priv->framecnt_to_us = 0;
  645. print_summary = 1;
  646. hundred = 1;
  647. }
  648. } else {
  649. /* print summary for all other frames */
  650. print_summary = 1;
  651. }
  652. if (print_summary) {
  653. char *title;
  654. int rate_idx;
  655. u32 bitrate;
  656. if (hundred)
  657. title = "100Frames";
  658. else if (ieee80211_has_retry(fc))
  659. title = "Retry";
  660. else if (ieee80211_is_assoc_resp(fc))
  661. title = "AscRsp";
  662. else if (ieee80211_is_reassoc_resp(fc))
  663. title = "RasRsp";
  664. else if (ieee80211_is_probe_resp(fc)) {
  665. title = "PrbRsp";
  666. print_dump = 1; /* dump frame contents */
  667. } else if (ieee80211_is_beacon(fc)) {
  668. title = "Beacon";
  669. print_dump = 1; /* dump frame contents */
  670. } else if (ieee80211_is_atim(fc))
  671. title = "ATIM";
  672. else if (ieee80211_is_auth(fc))
  673. title = "Auth";
  674. else if (ieee80211_is_deauth(fc))
  675. title = "DeAuth";
  676. else if (ieee80211_is_disassoc(fc))
  677. title = "DisAssoc";
  678. else
  679. title = "Frame";
  680. rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
  681. if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
  682. bitrate = 0;
  683. WARN_ON_ONCE(1);
  684. } else {
  685. bitrate = iwl_rates[rate_idx].ieee / 2;
  686. }
  687. /* print frame summary.
  688. * MAC addresses show just the last byte (for brevity),
  689. * but you can hack it to show more, if you'd like to. */
  690. if (dataframe)
  691. IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
  692. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  693. title, le16_to_cpu(fc), header->addr1[5],
  694. length, rssi, channel, bitrate);
  695. else {
  696. /* src/dst addresses assume managed mode */
  697. IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, "
  698. "len=%u, rssi=%d, tim=%lu usec, "
  699. "phy=0x%02x, chnl=%d\n",
  700. title, le16_to_cpu(fc), header->addr1[5],
  701. header->addr3[5], length, rssi,
  702. tsf_low - priv->scan_start_tsf,
  703. phy_flags, channel);
  704. }
  705. }
  706. if (print_dump)
  707. iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
  708. }
  709. #endif
  710. /*
  711. * returns non-zero if packet should be dropped
  712. */
  713. int iwl_set_decrypted_flag(struct iwl_priv *priv,
  714. struct ieee80211_hdr *hdr,
  715. u32 decrypt_res,
  716. struct ieee80211_rx_status *stats)
  717. {
  718. u16 fc = le16_to_cpu(hdr->frame_control);
  719. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  720. return 0;
  721. if (!(fc & IEEE80211_FCTL_PROTECTED))
  722. return 0;
  723. IWL_DEBUG_RX(priv, "decrypt_res:0x%x\n", decrypt_res);
  724. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  725. case RX_RES_STATUS_SEC_TYPE_TKIP:
  726. /* The uCode has got a bad phase 1 Key, pushes the packet.
  727. * Decryption will be done in SW. */
  728. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  729. RX_RES_STATUS_BAD_KEY_TTAK)
  730. break;
  731. case RX_RES_STATUS_SEC_TYPE_WEP:
  732. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  733. RX_RES_STATUS_BAD_ICV_MIC) {
  734. /* bad ICV, the packet is destroyed since the
  735. * decryption is inplace, drop it */
  736. IWL_DEBUG_RX(priv, "Packet destroyed\n");
  737. return -1;
  738. }
  739. case RX_RES_STATUS_SEC_TYPE_CCMP:
  740. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  741. RX_RES_STATUS_DECRYPT_OK) {
  742. IWL_DEBUG_RX(priv, "hw decrypt successfully!!!\n");
  743. stats->flag |= RX_FLAG_DECRYPTED;
  744. }
  745. break;
  746. default:
  747. break;
  748. }
  749. return 0;
  750. }
  751. EXPORT_SYMBOL(iwl_set_decrypted_flag);
  752. static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  753. {
  754. u32 decrypt_out = 0;
  755. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  756. RX_RES_STATUS_STATION_FOUND)
  757. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  758. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  759. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  760. /* packet was not encrypted */
  761. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  762. RX_RES_STATUS_SEC_TYPE_NONE)
  763. return decrypt_out;
  764. /* packet was encrypted with unknown alg */
  765. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  766. RX_RES_STATUS_SEC_TYPE_ERR)
  767. return decrypt_out;
  768. /* decryption was not done in HW */
  769. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  770. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  771. return decrypt_out;
  772. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  773. case RX_RES_STATUS_SEC_TYPE_CCMP:
  774. /* alg is CCM: check MIC only */
  775. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  776. /* Bad MIC */
  777. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  778. else
  779. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  780. break;
  781. case RX_RES_STATUS_SEC_TYPE_TKIP:
  782. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  783. /* Bad TTAK */
  784. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  785. break;
  786. }
  787. /* fall through if TTAK OK */
  788. default:
  789. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  790. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  791. else
  792. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  793. break;
  794. };
  795. IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
  796. decrypt_in, decrypt_out);
  797. return decrypt_out;
  798. }
  799. static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
  800. struct ieee80211_hdr *hdr,
  801. u16 len,
  802. u32 ampdu_status,
  803. struct iwl_rx_mem_buffer *rxb,
  804. struct ieee80211_rx_status *stats)
  805. {
  806. struct sk_buff *skb;
  807. int ret = 0;
  808. /* We only process data packets if the interface is open */
  809. if (unlikely(!priv->is_open)) {
  810. IWL_DEBUG_DROP_LIMIT(priv,
  811. "Dropping packet while interface is not open.\n");
  812. return;
  813. }
  814. /* In case of HW accelerated crypto and bad decryption, drop */
  815. if (!priv->cfg->mod_params->sw_crypto &&
  816. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  817. return;
  818. skb = alloc_skb(IWL_LINK_HDR_MAX, GFP_ATOMIC);
  819. if (!skb) {
  820. IWL_ERR(priv, "alloc_skb failed\n");
  821. return;
  822. }
  823. skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
  824. /* mac80211 currently doesn't support paged SKB. Convert it to
  825. * linear SKB for management frame and data frame requires
  826. * software decryption or software defragementation. */
  827. if (ieee80211_is_mgmt(hdr->frame_control) ||
  828. ieee80211_has_protected(hdr->frame_control) ||
  829. ieee80211_has_morefrags(hdr->frame_control) ||
  830. le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
  831. ret = skb_linearize(skb);
  832. else
  833. ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
  834. 0 : -ENOMEM;
  835. if (ret) {
  836. kfree_skb(skb);
  837. goto out;
  838. }
  839. iwl_update_stats(priv, false, hdr->frame_control, len);
  840. memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
  841. ieee80211_rx(priv->hw, skb);
  842. out:
  843. priv->alloc_rxb_page--;
  844. rxb->page = NULL;
  845. }
  846. /* This is necessary only for a number of statistics, see the caller. */
  847. static int iwl_is_network_packet(struct iwl_priv *priv,
  848. struct ieee80211_hdr *header)
  849. {
  850. /* Filter incoming packets to determine if they are targeted toward
  851. * this network, discarding packets coming from ourselves */
  852. switch (priv->iw_mode) {
  853. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  854. /* packets to our IBSS update information */
  855. return !compare_ether_addr(header->addr3, priv->bssid);
  856. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  857. /* packets to our IBSS update information */
  858. return !compare_ether_addr(header->addr2, priv->bssid);
  859. default:
  860. return 1;
  861. }
  862. }
  863. /* Called for REPLY_RX (legacy ABG frames), or
  864. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  865. void iwl_rx_reply_rx(struct iwl_priv *priv,
  866. struct iwl_rx_mem_buffer *rxb)
  867. {
  868. struct ieee80211_hdr *header;
  869. struct ieee80211_rx_status rx_status;
  870. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  871. struct iwl_rx_phy_res *phy_res;
  872. __le32 rx_pkt_status;
  873. struct iwl4965_rx_mpdu_res_start *amsdu;
  874. u32 len;
  875. u32 ampdu_status;
  876. u16 fc;
  877. u32 rate_n_flags;
  878. /**
  879. * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
  880. * REPLY_RX: physical layer info is in this buffer
  881. * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
  882. * command and cached in priv->last_phy_res
  883. *
  884. * Here we set up local variables depending on which command is
  885. * received.
  886. */
  887. if (pkt->hdr.cmd == REPLY_RX) {
  888. phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
  889. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
  890. + phy_res->cfg_phy_cnt);
  891. len = le16_to_cpu(phy_res->byte_count);
  892. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
  893. phy_res->cfg_phy_cnt + len);
  894. ampdu_status = le32_to_cpu(rx_pkt_status);
  895. } else {
  896. if (!priv->last_phy_res[0]) {
  897. IWL_ERR(priv, "MPDU frame without cached PHY data\n");
  898. return;
  899. }
  900. phy_res = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  901. amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  902. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
  903. len = le16_to_cpu(amsdu->byte_count);
  904. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
  905. ampdu_status = iwl_translate_rx_status(priv,
  906. le32_to_cpu(rx_pkt_status));
  907. }
  908. if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
  909. IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
  910. phy_res->cfg_phy_cnt);
  911. return;
  912. }
  913. if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
  914. !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  915. IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
  916. le32_to_cpu(rx_pkt_status));
  917. return;
  918. }
  919. /* This will be used in several places later */
  920. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  921. /* rx_status carries information about the packet to mac80211 */
  922. rx_status.mactime = le64_to_cpu(phy_res->timestamp);
  923. rx_status.freq =
  924. ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
  925. rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  926. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  927. rx_status.rate_idx =
  928. iwl_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
  929. rx_status.flag = 0;
  930. /* TSF isn't reliable. In order to allow smooth user experience,
  931. * this W/A doesn't propagate it to the mac80211 */
  932. /*rx_status.flag |= RX_FLAG_TSFT;*/
  933. priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
  934. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  935. rx_status.signal = iwl_calc_rssi(priv, phy_res);
  936. /* Meaningful noise values are available only from beacon statistics,
  937. * which are gathered only when associated, and indicate noise
  938. * only for the associated network channel ...
  939. * Ignore these noise values while scanning (other channels) */
  940. if (iwl_is_associated(priv) &&
  941. !test_bit(STATUS_SCANNING, &priv->status)) {
  942. rx_status.noise = priv->last_rx_noise;
  943. rx_status.qual = iwl_calc_sig_qual(rx_status.signal,
  944. rx_status.noise);
  945. } else {
  946. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  947. rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0);
  948. }
  949. /* Reset beacon noise level if not associated. */
  950. if (!iwl_is_associated(priv))
  951. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  952. #ifdef CONFIG_IWLWIFI_DEBUG
  953. /* Set "1" to report good data frames in groups of 100 */
  954. if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX))
  955. iwl_dbg_report_frame(priv, phy_res, len, header, 1);
  956. #endif
  957. iwl_dbg_log_rx_data_frame(priv, len, header);
  958. IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, noise %d, qual %d, TSF %llu\n",
  959. rx_status.signal, rx_status.noise, rx_status.qual,
  960. (unsigned long long)rx_status.mactime);
  961. /*
  962. * "antenna number"
  963. *
  964. * It seems that the antenna field in the phy flags value
  965. * is actually a bit field. This is undefined by radiotap,
  966. * it wants an actual antenna number but I always get "7"
  967. * for most legacy frames I receive indicating that the
  968. * same frame was received on all three RX chains.
  969. *
  970. * I think this field should be removed in favor of a
  971. * new 802.11n radiotap field "RX chains" that is defined
  972. * as a bitmask.
  973. */
  974. rx_status.antenna =
  975. (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
  976. >> RX_RES_PHY_FLAGS_ANTENNA_POS;
  977. /* set the preamble flag if appropriate */
  978. if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  979. rx_status.flag |= RX_FLAG_SHORTPRE;
  980. /* Set up the HT phy flags */
  981. if (rate_n_flags & RATE_MCS_HT_MSK)
  982. rx_status.flag |= RX_FLAG_HT;
  983. if (rate_n_flags & RATE_MCS_HT40_MSK)
  984. rx_status.flag |= RX_FLAG_40MHZ;
  985. if (rate_n_flags & RATE_MCS_SGI_MSK)
  986. rx_status.flag |= RX_FLAG_SHORT_GI;
  987. if (iwl_is_network_packet(priv, header)) {
  988. priv->last_rx_rssi = rx_status.signal;
  989. priv->last_beacon_time = priv->ucode_beacon_time;
  990. priv->last_tsf = le64_to_cpu(phy_res->timestamp);
  991. }
  992. fc = le16_to_cpu(header->frame_control);
  993. switch (fc & IEEE80211_FCTL_FTYPE) {
  994. case IEEE80211_FTYPE_MGMT:
  995. case IEEE80211_FTYPE_DATA:
  996. if (priv->iw_mode == NL80211_IFTYPE_AP)
  997. iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  998. header->addr2);
  999. /* fall through */
  1000. default:
  1001. iwl_pass_packet_to_mac80211(priv, header, len, ampdu_status,
  1002. rxb, &rx_status);
  1003. break;
  1004. }
  1005. }
  1006. EXPORT_SYMBOL(iwl_rx_reply_rx);
  1007. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  1008. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  1009. void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
  1010. struct iwl_rx_mem_buffer *rxb)
  1011. {
  1012. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1013. priv->last_phy_res[0] = 1;
  1014. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  1015. sizeof(struct iwl_rx_phy_res));
  1016. }
  1017. EXPORT_SYMBOL(iwl_rx_reply_rx_phy);