tegra20.dtsi 8.2 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. host1x {
  6. compatible = "nvidia,tegra20-host1x", "simple-bus";
  7. reg = <0x50000000 0x00024000>;
  8. interrupts = <0 65 0x04 /* mpcore syncpt */
  9. 0 67 0x04>; /* mpcore general */
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. ranges = <0x54000000 0x54000000 0x04000000>;
  13. mpe {
  14. compatible = "nvidia,tegra20-mpe";
  15. reg = <0x54040000 0x00040000>;
  16. interrupts = <0 68 0x04>;
  17. };
  18. vi {
  19. compatible = "nvidia,tegra20-vi";
  20. reg = <0x54080000 0x00040000>;
  21. interrupts = <0 69 0x04>;
  22. };
  23. epp {
  24. compatible = "nvidia,tegra20-epp";
  25. reg = <0x540c0000 0x00040000>;
  26. interrupts = <0 70 0x04>;
  27. };
  28. isp {
  29. compatible = "nvidia,tegra20-isp";
  30. reg = <0x54100000 0x00040000>;
  31. interrupts = <0 71 0x04>;
  32. };
  33. gr2d {
  34. compatible = "nvidia,tegra20-gr2d";
  35. reg = <0x54140000 0x00040000>;
  36. interrupts = <0 72 0x04>;
  37. };
  38. gr3d {
  39. compatible = "nvidia,tegra20-gr3d";
  40. reg = <0x54180000 0x00040000>;
  41. };
  42. dc@54200000 {
  43. compatible = "nvidia,tegra20-dc";
  44. reg = <0x54200000 0x00040000>;
  45. interrupts = <0 73 0x04>;
  46. rgb {
  47. status = "disabled";
  48. };
  49. };
  50. dc@54240000 {
  51. compatible = "nvidia,tegra20-dc";
  52. reg = <0x54240000 0x00040000>;
  53. interrupts = <0 74 0x04>;
  54. rgb {
  55. status = "disabled";
  56. };
  57. };
  58. hdmi {
  59. compatible = "nvidia,tegra20-hdmi";
  60. reg = <0x54280000 0x00040000>;
  61. interrupts = <0 75 0x04>;
  62. status = "disabled";
  63. };
  64. tvo {
  65. compatible = "nvidia,tegra20-tvo";
  66. reg = <0x542c0000 0x00040000>;
  67. interrupts = <0 76 0x04>;
  68. status = "disabled";
  69. };
  70. dsi {
  71. compatible = "nvidia,tegra20-dsi";
  72. reg = <0x54300000 0x00040000>;
  73. status = "disabled";
  74. };
  75. };
  76. cache-controller@50043000 {
  77. compatible = "arm,pl310-cache";
  78. reg = <0x50043000 0x1000>;
  79. arm,data-latency = <5 5 2>;
  80. arm,tag-latency = <4 4 2>;
  81. cache-unified;
  82. cache-level = <2>;
  83. };
  84. intc: interrupt-controller {
  85. compatible = "arm,cortex-a9-gic";
  86. reg = <0x50041000 0x1000
  87. 0x50040100 0x0100>;
  88. interrupt-controller;
  89. #interrupt-cells = <3>;
  90. };
  91. timer@60005000 {
  92. compatible = "nvidia,tegra20-timer";
  93. reg = <0x60005000 0x60>;
  94. interrupts = <0 0 0x04
  95. 0 1 0x04
  96. 0 41 0x04
  97. 0 42 0x04>;
  98. };
  99. apbdma: dma {
  100. compatible = "nvidia,tegra20-apbdma";
  101. reg = <0x6000a000 0x1200>;
  102. interrupts = <0 104 0x04
  103. 0 105 0x04
  104. 0 106 0x04
  105. 0 107 0x04
  106. 0 108 0x04
  107. 0 109 0x04
  108. 0 110 0x04
  109. 0 111 0x04
  110. 0 112 0x04
  111. 0 113 0x04
  112. 0 114 0x04
  113. 0 115 0x04
  114. 0 116 0x04
  115. 0 117 0x04
  116. 0 118 0x04
  117. 0 119 0x04>;
  118. };
  119. ahb {
  120. compatible = "nvidia,tegra20-ahb";
  121. reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
  122. };
  123. gpio: gpio {
  124. compatible = "nvidia,tegra20-gpio";
  125. reg = <0x6000d000 0x1000>;
  126. interrupts = <0 32 0x04
  127. 0 33 0x04
  128. 0 34 0x04
  129. 0 35 0x04
  130. 0 55 0x04
  131. 0 87 0x04
  132. 0 89 0x04>;
  133. #gpio-cells = <2>;
  134. gpio-controller;
  135. #interrupt-cells = <2>;
  136. interrupt-controller;
  137. };
  138. pinmux: pinmux {
  139. compatible = "nvidia,tegra20-pinmux";
  140. reg = <0x70000014 0x10 /* Tri-state registers */
  141. 0x70000080 0x20 /* Mux registers */
  142. 0x700000a0 0x14 /* Pull-up/down registers */
  143. 0x70000868 0xa8>; /* Pad control registers */
  144. };
  145. das {
  146. compatible = "nvidia,tegra20-das";
  147. reg = <0x70000c00 0x80>;
  148. };
  149. tegra_i2s1: i2s@70002800 {
  150. compatible = "nvidia,tegra20-i2s";
  151. reg = <0x70002800 0x200>;
  152. interrupts = <0 13 0x04>;
  153. nvidia,dma-request-selector = <&apbdma 2>;
  154. status = "disabled";
  155. };
  156. tegra_i2s2: i2s@70002a00 {
  157. compatible = "nvidia,tegra20-i2s";
  158. reg = <0x70002a00 0x200>;
  159. interrupts = <0 3 0x04>;
  160. nvidia,dma-request-selector = <&apbdma 1>;
  161. status = "disabled";
  162. };
  163. serial@70006000 {
  164. compatible = "nvidia,tegra20-uart";
  165. reg = <0x70006000 0x40>;
  166. reg-shift = <2>;
  167. interrupts = <0 36 0x04>;
  168. status = "disabled";
  169. };
  170. serial@70006040 {
  171. compatible = "nvidia,tegra20-uart";
  172. reg = <0x70006040 0x40>;
  173. reg-shift = <2>;
  174. interrupts = <0 37 0x04>;
  175. status = "disabled";
  176. };
  177. serial@70006200 {
  178. compatible = "nvidia,tegra20-uart";
  179. reg = <0x70006200 0x100>;
  180. reg-shift = <2>;
  181. interrupts = <0 46 0x04>;
  182. status = "disabled";
  183. };
  184. serial@70006300 {
  185. compatible = "nvidia,tegra20-uart";
  186. reg = <0x70006300 0x100>;
  187. reg-shift = <2>;
  188. interrupts = <0 90 0x04>;
  189. status = "disabled";
  190. };
  191. serial@70006400 {
  192. compatible = "nvidia,tegra20-uart";
  193. reg = <0x70006400 0x100>;
  194. reg-shift = <2>;
  195. interrupts = <0 91 0x04>;
  196. status = "disabled";
  197. };
  198. pwm: pwm {
  199. compatible = "nvidia,tegra20-pwm";
  200. reg = <0x7000a000 0x100>;
  201. #pwm-cells = <2>;
  202. };
  203. i2c@7000c000 {
  204. compatible = "nvidia,tegra20-i2c";
  205. reg = <0x7000c000 0x100>;
  206. interrupts = <0 38 0x04>;
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. status = "disabled";
  210. };
  211. spi@7000c380 {
  212. compatible = "nvidia,tegra20-sflash";
  213. reg = <0x7000c380 0x80>;
  214. interrupts = <0 39 0x04>;
  215. nvidia,dma-request-selector = <&apbdma 11>;
  216. #address-cells = <1>;
  217. #size-cells = <0>;
  218. status = "disabled";
  219. };
  220. i2c@7000c400 {
  221. compatible = "nvidia,tegra20-i2c";
  222. reg = <0x7000c400 0x100>;
  223. interrupts = <0 84 0x04>;
  224. #address-cells = <1>;
  225. #size-cells = <0>;
  226. status = "disabled";
  227. };
  228. i2c@7000c500 {
  229. compatible = "nvidia,tegra20-i2c";
  230. reg = <0x7000c500 0x100>;
  231. interrupts = <0 92 0x04>;
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. status = "disabled";
  235. };
  236. i2c@7000d000 {
  237. compatible = "nvidia,tegra20-i2c-dvc";
  238. reg = <0x7000d000 0x200>;
  239. interrupts = <0 53 0x04>;
  240. #address-cells = <1>;
  241. #size-cells = <0>;
  242. status = "disabled";
  243. };
  244. spi@7000d400 {
  245. compatible = "nvidia,tegra20-slink";
  246. reg = <0x7000d400 0x200>;
  247. interrupts = <0 59 0x04>;
  248. nvidia,dma-request-selector = <&apbdma 15>;
  249. #address-cells = <1>;
  250. #size-cells = <0>;
  251. status = "disabled";
  252. };
  253. spi@7000d600 {
  254. compatible = "nvidia,tegra20-slink";
  255. reg = <0x7000d600 0x200>;
  256. interrupts = <0 82 0x04>;
  257. nvidia,dma-request-selector = <&apbdma 16>;
  258. #address-cells = <1>;
  259. #size-cells = <0>;
  260. status = "disabled";
  261. };
  262. spi@7000d800 {
  263. compatible = "nvidia,tegra20-slink";
  264. reg = <0x7000d480 0x200>;
  265. interrupts = <0 83 0x04>;
  266. nvidia,dma-request-selector = <&apbdma 17>;
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. status = "disabled";
  270. };
  271. spi@7000da00 {
  272. compatible = "nvidia,tegra20-slink";
  273. reg = <0x7000da00 0x200>;
  274. interrupts = <0 93 0x04>;
  275. nvidia,dma-request-selector = <&apbdma 18>;
  276. #address-cells = <1>;
  277. #size-cells = <0>;
  278. status = "disabled";
  279. };
  280. pmc {
  281. compatible = "nvidia,tegra20-pmc";
  282. reg = <0x7000e400 0x400>;
  283. };
  284. memory-controller@7000f000 {
  285. compatible = "nvidia,tegra20-mc";
  286. reg = <0x7000f000 0x024
  287. 0x7000f03c 0x3c4>;
  288. interrupts = <0 77 0x04>;
  289. };
  290. gart {
  291. compatible = "nvidia,tegra20-gart";
  292. reg = <0x7000f024 0x00000018 /* controller registers */
  293. 0x58000000 0x02000000>; /* GART aperture */
  294. };
  295. memory-controller@7000f400 {
  296. compatible = "nvidia,tegra20-emc";
  297. reg = <0x7000f400 0x200>;
  298. #address-cells = <1>;
  299. #size-cells = <0>;
  300. };
  301. usb@c5000000 {
  302. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  303. reg = <0xc5000000 0x4000>;
  304. interrupts = <0 20 0x04>;
  305. phy_type = "utmi";
  306. nvidia,has-legacy-mode;
  307. status = "disabled";
  308. };
  309. usb@c5004000 {
  310. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  311. reg = <0xc5004000 0x4000>;
  312. interrupts = <0 21 0x04>;
  313. phy_type = "ulpi";
  314. status = "disabled";
  315. };
  316. usb@c5008000 {
  317. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  318. reg = <0xc5008000 0x4000>;
  319. interrupts = <0 97 0x04>;
  320. phy_type = "utmi";
  321. status = "disabled";
  322. };
  323. sdhci@c8000000 {
  324. compatible = "nvidia,tegra20-sdhci";
  325. reg = <0xc8000000 0x200>;
  326. interrupts = <0 14 0x04>;
  327. status = "disabled";
  328. };
  329. sdhci@c8000200 {
  330. compatible = "nvidia,tegra20-sdhci";
  331. reg = <0xc8000200 0x200>;
  332. interrupts = <0 15 0x04>;
  333. status = "disabled";
  334. };
  335. sdhci@c8000400 {
  336. compatible = "nvidia,tegra20-sdhci";
  337. reg = <0xc8000400 0x200>;
  338. interrupts = <0 19 0x04>;
  339. status = "disabled";
  340. };
  341. sdhci@c8000600 {
  342. compatible = "nvidia,tegra20-sdhci";
  343. reg = <0xc8000600 0x200>;
  344. interrupts = <0 31 0x04>;
  345. status = "disabled";
  346. };
  347. pmu {
  348. compatible = "arm,cortex-a9-pmu";
  349. interrupts = <0 56 0x04
  350. 0 57 0x04>;
  351. };
  352. };