mpc834x_sys.c 8.0 KB

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  1. /*
  2. * arch/ppc/platforms/83xx/mpc834x_sys.c
  3. *
  4. * MPC834x SYS board specific routines
  5. *
  6. * Maintainer: Kumar Gala <kumar.gala@freescale.com>
  7. *
  8. * Copyright 2005 Freescale Semiconductor Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <linux/config.h>
  16. #include <linux/stddef.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/errno.h>
  20. #include <linux/reboot.h>
  21. #include <linux/pci.h>
  22. #include <linux/kdev_t.h>
  23. #include <linux/major.h>
  24. #include <linux/console.h>
  25. #include <linux/delay.h>
  26. #include <linux/seq_file.h>
  27. #include <linux/root_dev.h>
  28. #include <linux/serial.h>
  29. #include <linux/tty.h> /* for linux/serial_core.h */
  30. #include <linux/serial_core.h>
  31. #include <linux/initrd.h>
  32. #include <linux/module.h>
  33. #include <linux/fsl_devices.h>
  34. #include <asm/system.h>
  35. #include <asm/pgtable.h>
  36. #include <asm/page.h>
  37. #include <asm/atomic.h>
  38. #include <asm/time.h>
  39. #include <asm/io.h>
  40. #include <asm/machdep.h>
  41. #include <asm/ipic.h>
  42. #include <asm/bootinfo.h>
  43. #include <asm/pci-bridge.h>
  44. #include <asm/mpc83xx.h>
  45. #include <asm/irq.h>
  46. #include <asm/kgdb.h>
  47. #include <asm/ppc_sys.h>
  48. #include <mm/mmu_decl.h>
  49. #include <syslib/ppc83xx_setup.h>
  50. #ifndef CONFIG_PCI
  51. unsigned long isa_io_base = 0;
  52. unsigned long isa_mem_base = 0;
  53. #endif
  54. extern unsigned long total_memory; /* in mm/init */
  55. unsigned char __res[sizeof (bd_t)];
  56. #ifdef CONFIG_PCI
  57. int
  58. mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  59. {
  60. static char pci_irq_table[][4] =
  61. /*
  62. * PCI IDSEL/INTPIN->INTLINE
  63. * A B C D
  64. */
  65. {
  66. {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
  67. {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
  68. {PIRQD, PIRQA, PIRQB, PIRQC} /* idsel 0x13 */
  69. };
  70. const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4;
  71. return PCI_IRQ_TABLE_LOOKUP;
  72. }
  73. int
  74. mpc83xx_exclude_device(u_char bus, u_char devfn)
  75. {
  76. return PCIBIOS_SUCCESSFUL;
  77. }
  78. #endif /* CONFIG_PCI */
  79. /* ************************************************************************
  80. *
  81. * Setup the architecture
  82. *
  83. */
  84. static void __init
  85. mpc834x_sys_setup_arch(void)
  86. {
  87. bd_t *binfo = (bd_t *) __res;
  88. unsigned int freq;
  89. struct gianfar_platform_data *pdata;
  90. /* get the core frequency */
  91. freq = binfo->bi_intfreq;
  92. /* Set loops_per_jiffy to a half-way reasonable value,
  93. for use until calibrate_delay gets called. */
  94. loops_per_jiffy = freq / HZ;
  95. #ifdef CONFIG_PCI
  96. /* setup PCI host bridges */
  97. mpc83xx_setup_hose();
  98. #endif
  99. mpc83xx_early_serial_map();
  100. /* setup the board related information for the enet controllers */
  101. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1);
  102. if (pdata) {
  103. pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
  104. pdata->interruptPHY = MPC83xx_IRQ_EXT1;
  105. pdata->phyid = 0;
  106. /* fixup phy address */
  107. pdata->phy_reg_addr += binfo->bi_immr_base;
  108. memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
  109. }
  110. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2);
  111. if (pdata) {
  112. pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
  113. pdata->interruptPHY = MPC83xx_IRQ_EXT2;
  114. pdata->phyid = 1;
  115. /* fixup phy address */
  116. pdata->phy_reg_addr += binfo->bi_immr_base;
  117. memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
  118. }
  119. #ifdef CONFIG_BLK_DEV_INITRD
  120. if (initrd_start)
  121. ROOT_DEV = Root_RAM0;
  122. else
  123. #endif
  124. #ifdef CONFIG_ROOT_NFS
  125. ROOT_DEV = Root_NFS;
  126. #else
  127. ROOT_DEV = Root_HDA1;
  128. #endif
  129. }
  130. static void __init
  131. mpc834x_sys_map_io(void)
  132. {
  133. /* we steal the lowest ioremap addr for virt space */
  134. io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
  135. }
  136. int
  137. mpc834x_sys_show_cpuinfo(struct seq_file *m)
  138. {
  139. uint pvid, svid, phid1;
  140. bd_t *binfo = (bd_t *) __res;
  141. unsigned int freq;
  142. /* get the core frequency */
  143. freq = binfo->bi_intfreq;
  144. pvid = mfspr(SPRN_PVR);
  145. svid = mfspr(SPRN_SVR);
  146. seq_printf(m, "Vendor\t\t: Freescale Inc.\n");
  147. seq_printf(m, "Machine\t\t: mpc%s sys\n", cur_ppc_sys_spec->ppc_sys_name);
  148. seq_printf(m, "core clock\t: %d MHz\n"
  149. "bus clock\t: %d MHz\n",
  150. (int)(binfo->bi_intfreq / 1000000),
  151. (int)(binfo->bi_busfreq / 1000000));
  152. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  153. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  154. /* Display cpu Pll setting */
  155. phid1 = mfspr(SPRN_HID1);
  156. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  157. /* Display the amount of memory */
  158. seq_printf(m, "Memory\t\t: %d MB\n", (int)(binfo->bi_memsize / (1024 * 1024)));
  159. return 0;
  160. }
  161. void __init
  162. mpc834x_sys_init_IRQ(void)
  163. {
  164. bd_t *binfo = (bd_t *) __res;
  165. u8 senses[8] = {
  166. 0, /* EXT 0 */
  167. IRQ_SENSE_LEVEL, /* EXT 1 */
  168. IRQ_SENSE_LEVEL, /* EXT 2 */
  169. 0, /* EXT 3 */
  170. #ifdef CONFIG_PCI
  171. IRQ_SENSE_LEVEL, /* EXT 4 */
  172. IRQ_SENSE_LEVEL, /* EXT 5 */
  173. IRQ_SENSE_LEVEL, /* EXT 6 */
  174. IRQ_SENSE_LEVEL, /* EXT 7 */
  175. #else
  176. 0, /* EXT 4 */
  177. 0, /* EXT 5 */
  178. 0, /* EXT 6 */
  179. 0, /* EXT 7 */
  180. #endif
  181. };
  182. ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);
  183. /* Initialize the default interrupt mapping priorities,
  184. * in case the boot rom changed something on us.
  185. */
  186. ipic_set_default_priority();
  187. }
  188. #if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
  189. extern ulong ds1374_get_rtc_time(void);
  190. extern int ds1374_set_rtc_time(ulong);
  191. static int __init
  192. mpc834x_rtc_hookup(void)
  193. {
  194. struct timespec tv;
  195. ppc_md.get_rtc_time = ds1374_get_rtc_time;
  196. ppc_md.set_rtc_time = ds1374_set_rtc_time;
  197. tv.tv_nsec = 0;
  198. tv.tv_sec = (ppc_md.get_rtc_time)();
  199. do_settimeofday(&tv);
  200. return 0;
  201. }
  202. late_initcall(mpc834x_rtc_hookup);
  203. #endif
  204. static __inline__ void
  205. mpc834x_sys_set_bat(void)
  206. {
  207. /* we steal the lowest ioremap addr for virt space */
  208. mb();
  209. mtspr(SPRN_DBAT1U, VIRT_IMMRBAR | 0x1e);
  210. mtspr(SPRN_DBAT1L, immrbar | 0x2a);
  211. mb();
  212. }
  213. void __init
  214. platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
  215. unsigned long r6, unsigned long r7)
  216. {
  217. bd_t *binfo = (bd_t *) __res;
  218. /* parse_bootinfo must always be called first */
  219. parse_bootinfo(find_bootinfo());
  220. /*
  221. * If we were passed in a board information, copy it into the
  222. * residual data area.
  223. */
  224. if (r3) {
  225. memcpy((void *) __res, (void *) (r3 + KERNELBASE),
  226. sizeof (bd_t));
  227. }
  228. #if defined(CONFIG_BLK_DEV_INITRD)
  229. /*
  230. * If the init RAM disk has been configured in, and there's a valid
  231. * starting address for it, set it up.
  232. */
  233. if (r4) {
  234. initrd_start = r4 + KERNELBASE;
  235. initrd_end = r5 + KERNELBASE;
  236. }
  237. #endif /* CONFIG_BLK_DEV_INITRD */
  238. /* Copy the kernel command line arguments to a safe place. */
  239. if (r6) {
  240. *(char *) (r7 + KERNELBASE) = 0;
  241. strcpy(cmd_line, (char *) (r6 + KERNELBASE));
  242. }
  243. immrbar = binfo->bi_immr_base;
  244. mpc834x_sys_set_bat();
  245. #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
  246. {
  247. struct uart_port p;
  248. memset(&p, 0, sizeof (p));
  249. p.iotype = SERIAL_IO_MEM;
  250. p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4500);
  251. p.uartclk = binfo->bi_busfreq;
  252. gen550_init(0, &p);
  253. memset(&p, 0, sizeof (p));
  254. p.iotype = SERIAL_IO_MEM;
  255. p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4600);
  256. p.uartclk = binfo->bi_busfreq;
  257. gen550_init(1, &p);
  258. }
  259. #endif
  260. identify_ppc_sys_by_id(mfspr(SPRN_SVR));
  261. /* setup the PowerPC module struct */
  262. ppc_md.setup_arch = mpc834x_sys_setup_arch;
  263. ppc_md.show_cpuinfo = mpc834x_sys_show_cpuinfo;
  264. ppc_md.init_IRQ = mpc834x_sys_init_IRQ;
  265. ppc_md.get_irq = ipic_get_irq;
  266. ppc_md.restart = mpc83xx_restart;
  267. ppc_md.power_off = mpc83xx_power_off;
  268. ppc_md.halt = mpc83xx_halt;
  269. ppc_md.find_end_of_memory = mpc83xx_find_end_of_memory;
  270. ppc_md.setup_io_mappings = mpc834x_sys_map_io;
  271. ppc_md.time_init = mpc83xx_time_init;
  272. ppc_md.set_rtc_time = NULL;
  273. ppc_md.get_rtc_time = NULL;
  274. ppc_md.calibrate_decr = mpc83xx_calibrate_decr;
  275. ppc_md.early_serial_map = mpc83xx_early_serial_map;
  276. #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
  277. ppc_md.progress = gen550_progress;
  278. #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
  279. if (ppc_md.progress)
  280. ppc_md.progress("mpc834x_sys_init(): exit", 0);
  281. return;
  282. }