qlcnic_ctx.c 25 KB

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  1. /*
  2. * Copyright (C) 2009 - QLogic Corporation.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called "COPYING".
  22. *
  23. */
  24. #include "qlcnic.h"
  25. static u32
  26. qlcnic_poll_rsp(struct qlcnic_adapter *adapter)
  27. {
  28. u32 rsp;
  29. int timeout = 0;
  30. do {
  31. /* give atleast 1ms for firmware to respond */
  32. msleep(1);
  33. if (++timeout > QLCNIC_OS_CRB_RETRY_COUNT)
  34. return QLCNIC_CDRP_RSP_TIMEOUT;
  35. rsp = QLCRD32(adapter, QLCNIC_CDRP_CRB_OFFSET);
  36. } while (!QLCNIC_CDRP_IS_RSP(rsp));
  37. return rsp;
  38. }
  39. u32
  40. qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
  41. u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
  42. {
  43. u32 rsp;
  44. u32 signature;
  45. u32 rcode = QLCNIC_RCODE_SUCCESS;
  46. struct pci_dev *pdev = adapter->pdev;
  47. signature = QLCNIC_CDRP_SIGNATURE_MAKE(pci_fn, version);
  48. /* Acquire semaphore before accessing CRB */
  49. if (qlcnic_api_lock(adapter))
  50. return QLCNIC_RCODE_TIMEOUT;
  51. QLCWR32(adapter, QLCNIC_SIGN_CRB_OFFSET, signature);
  52. QLCWR32(adapter, QLCNIC_ARG1_CRB_OFFSET, arg1);
  53. QLCWR32(adapter, QLCNIC_ARG2_CRB_OFFSET, arg2);
  54. QLCWR32(adapter, QLCNIC_ARG3_CRB_OFFSET, arg3);
  55. QLCWR32(adapter, QLCNIC_CDRP_CRB_OFFSET, QLCNIC_CDRP_FORM_CMD(cmd));
  56. rsp = qlcnic_poll_rsp(adapter);
  57. if (rsp == QLCNIC_CDRP_RSP_TIMEOUT) {
  58. dev_err(&pdev->dev, "card response timeout.\n");
  59. rcode = QLCNIC_RCODE_TIMEOUT;
  60. } else if (rsp == QLCNIC_CDRP_RSP_FAIL) {
  61. rcode = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
  62. dev_err(&pdev->dev, "failed card response code:0x%x\n",
  63. rcode);
  64. }
  65. /* Release semaphore */
  66. qlcnic_api_unlock(adapter);
  67. return rcode;
  68. }
  69. int
  70. qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu)
  71. {
  72. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  73. if (recv_ctx->state == QLCNIC_HOST_CTX_STATE_ACTIVE) {
  74. if (qlcnic_issue_cmd(adapter,
  75. adapter->ahw.pci_func,
  76. adapter->fw_hal_version,
  77. recv_ctx->context_id,
  78. mtu,
  79. 0,
  80. QLCNIC_CDRP_CMD_SET_MTU)) {
  81. dev_err(&adapter->pdev->dev, "Failed to set mtu\n");
  82. return -EIO;
  83. }
  84. }
  85. return 0;
  86. }
  87. static int
  88. qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
  89. {
  90. void *addr;
  91. struct qlcnic_hostrq_rx_ctx *prq;
  92. struct qlcnic_cardrsp_rx_ctx *prsp;
  93. struct qlcnic_hostrq_rds_ring *prq_rds;
  94. struct qlcnic_hostrq_sds_ring *prq_sds;
  95. struct qlcnic_cardrsp_rds_ring *prsp_rds;
  96. struct qlcnic_cardrsp_sds_ring *prsp_sds;
  97. struct qlcnic_host_rds_ring *rds_ring;
  98. struct qlcnic_host_sds_ring *sds_ring;
  99. dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
  100. u64 phys_addr;
  101. int i, nrds_rings, nsds_rings;
  102. size_t rq_size, rsp_size;
  103. u32 cap, reg, val, reg2;
  104. int err;
  105. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  106. nrds_rings = adapter->max_rds_rings;
  107. nsds_rings = adapter->max_sds_rings;
  108. rq_size =
  109. SIZEOF_HOSTRQ_RX(struct qlcnic_hostrq_rx_ctx, nrds_rings,
  110. nsds_rings);
  111. rsp_size =
  112. SIZEOF_CARDRSP_RX(struct qlcnic_cardrsp_rx_ctx, nrds_rings,
  113. nsds_rings);
  114. addr = pci_alloc_consistent(adapter->pdev,
  115. rq_size, &hostrq_phys_addr);
  116. if (addr == NULL)
  117. return -ENOMEM;
  118. prq = (struct qlcnic_hostrq_rx_ctx *)addr;
  119. addr = pci_alloc_consistent(adapter->pdev,
  120. rsp_size, &cardrsp_phys_addr);
  121. if (addr == NULL) {
  122. err = -ENOMEM;
  123. goto out_free_rq;
  124. }
  125. prsp = (struct qlcnic_cardrsp_rx_ctx *)addr;
  126. prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
  127. cap = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN);
  128. cap |= (QLCNIC_CAP0_JUMBO_CONTIGUOUS | QLCNIC_CAP0_LRO_CONTIGUOUS);
  129. prq->capabilities[0] = cpu_to_le32(cap);
  130. prq->host_int_crb_mode =
  131. cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
  132. prq->host_rds_crb_mode =
  133. cpu_to_le32(QLCNIC_HOST_RDS_CRB_MODE_UNIQUE);
  134. prq->num_rds_rings = cpu_to_le16(nrds_rings);
  135. prq->num_sds_rings = cpu_to_le16(nsds_rings);
  136. prq->rds_ring_offset = cpu_to_le32(0);
  137. val = le32_to_cpu(prq->rds_ring_offset) +
  138. (sizeof(struct qlcnic_hostrq_rds_ring) * nrds_rings);
  139. prq->sds_ring_offset = cpu_to_le32(val);
  140. prq_rds = (struct qlcnic_hostrq_rds_ring *)(prq->data +
  141. le32_to_cpu(prq->rds_ring_offset));
  142. for (i = 0; i < nrds_rings; i++) {
  143. rds_ring = &recv_ctx->rds_rings[i];
  144. prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
  145. prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
  146. prq_rds[i].ring_kind = cpu_to_le32(i);
  147. prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
  148. }
  149. prq_sds = (struct qlcnic_hostrq_sds_ring *)(prq->data +
  150. le32_to_cpu(prq->sds_ring_offset));
  151. for (i = 0; i < nsds_rings; i++) {
  152. sds_ring = &recv_ctx->sds_rings[i];
  153. prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
  154. prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
  155. prq_sds[i].msi_index = cpu_to_le16(i);
  156. }
  157. phys_addr = hostrq_phys_addr;
  158. err = qlcnic_issue_cmd(adapter,
  159. adapter->ahw.pci_func,
  160. adapter->fw_hal_version,
  161. (u32)(phys_addr >> 32),
  162. (u32)(phys_addr & 0xffffffff),
  163. rq_size,
  164. QLCNIC_CDRP_CMD_CREATE_RX_CTX);
  165. if (err) {
  166. dev_err(&adapter->pdev->dev,
  167. "Failed to create rx ctx in firmware%d\n", err);
  168. goto out_free_rsp;
  169. }
  170. prsp_rds = ((struct qlcnic_cardrsp_rds_ring *)
  171. &prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
  172. for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
  173. rds_ring = &recv_ctx->rds_rings[i];
  174. reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
  175. if (adapter->fw_hal_version == QLCNIC_FW_BASE)
  176. rds_ring->crb_rcv_producer = qlcnic_get_ioaddr(adapter,
  177. QLCNIC_REG(reg - 0x200));
  178. else
  179. rds_ring->crb_rcv_producer = adapter->ahw.pci_base0 +
  180. reg;
  181. }
  182. prsp_sds = ((struct qlcnic_cardrsp_sds_ring *)
  183. &prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
  184. for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
  185. sds_ring = &recv_ctx->sds_rings[i];
  186. reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
  187. reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb);
  188. if (adapter->fw_hal_version == QLCNIC_FW_BASE) {
  189. sds_ring->crb_sts_consumer = qlcnic_get_ioaddr(adapter,
  190. QLCNIC_REG(reg - 0x200));
  191. sds_ring->crb_intr_mask = qlcnic_get_ioaddr(adapter,
  192. QLCNIC_REG(reg2 - 0x200));
  193. } else {
  194. sds_ring->crb_sts_consumer = adapter->ahw.pci_base0 +
  195. reg;
  196. sds_ring->crb_intr_mask = adapter->ahw.pci_base0 + reg2;
  197. }
  198. }
  199. recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
  200. recv_ctx->context_id = le16_to_cpu(prsp->context_id);
  201. recv_ctx->virt_port = prsp->virt_port;
  202. out_free_rsp:
  203. pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
  204. out_free_rq:
  205. pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
  206. return err;
  207. }
  208. static void
  209. qlcnic_fw_cmd_destroy_rx_ctx(struct qlcnic_adapter *adapter)
  210. {
  211. struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
  212. if (qlcnic_issue_cmd(adapter,
  213. adapter->ahw.pci_func,
  214. adapter->fw_hal_version,
  215. recv_ctx->context_id,
  216. QLCNIC_DESTROY_CTX_RESET,
  217. 0,
  218. QLCNIC_CDRP_CMD_DESTROY_RX_CTX)) {
  219. dev_err(&adapter->pdev->dev,
  220. "Failed to destroy rx ctx in firmware\n");
  221. }
  222. }
  223. static int
  224. qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter)
  225. {
  226. struct qlcnic_hostrq_tx_ctx *prq;
  227. struct qlcnic_hostrq_cds_ring *prq_cds;
  228. struct qlcnic_cardrsp_tx_ctx *prsp;
  229. void *rq_addr, *rsp_addr;
  230. size_t rq_size, rsp_size;
  231. u32 temp;
  232. int err;
  233. u64 phys_addr;
  234. dma_addr_t rq_phys_addr, rsp_phys_addr;
  235. struct qlcnic_host_tx_ring *tx_ring = adapter->tx_ring;
  236. rq_size = SIZEOF_HOSTRQ_TX(struct qlcnic_hostrq_tx_ctx);
  237. rq_addr = pci_alloc_consistent(adapter->pdev,
  238. rq_size, &rq_phys_addr);
  239. if (!rq_addr)
  240. return -ENOMEM;
  241. rsp_size = SIZEOF_CARDRSP_TX(struct qlcnic_cardrsp_tx_ctx);
  242. rsp_addr = pci_alloc_consistent(adapter->pdev,
  243. rsp_size, &rsp_phys_addr);
  244. if (!rsp_addr) {
  245. err = -ENOMEM;
  246. goto out_free_rq;
  247. }
  248. memset(rq_addr, 0, rq_size);
  249. prq = (struct qlcnic_hostrq_tx_ctx *)rq_addr;
  250. memset(rsp_addr, 0, rsp_size);
  251. prsp = (struct qlcnic_cardrsp_tx_ctx *)rsp_addr;
  252. prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
  253. temp = (QLCNIC_CAP0_LEGACY_CONTEXT | QLCNIC_CAP0_LEGACY_MN |
  254. QLCNIC_CAP0_LSO);
  255. prq->capabilities[0] = cpu_to_le32(temp);
  256. prq->host_int_crb_mode =
  257. cpu_to_le32(QLCNIC_HOST_INT_CRB_MODE_SHARED);
  258. prq->interrupt_ctl = 0;
  259. prq->msi_index = 0;
  260. prq->cmd_cons_dma_addr = cpu_to_le64(tx_ring->hw_cons_phys_addr);
  261. prq_cds = &prq->cds_ring;
  262. prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
  263. prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
  264. phys_addr = rq_phys_addr;
  265. err = qlcnic_issue_cmd(adapter,
  266. adapter->ahw.pci_func,
  267. adapter->fw_hal_version,
  268. (u32)(phys_addr >> 32),
  269. ((u32)phys_addr & 0xffffffff),
  270. rq_size,
  271. QLCNIC_CDRP_CMD_CREATE_TX_CTX);
  272. if (err == QLCNIC_RCODE_SUCCESS) {
  273. temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
  274. if (adapter->fw_hal_version == QLCNIC_FW_BASE)
  275. tx_ring->crb_cmd_producer = qlcnic_get_ioaddr(adapter,
  276. QLCNIC_REG(temp - 0x200));
  277. else
  278. tx_ring->crb_cmd_producer = adapter->ahw.pci_base0 +
  279. temp;
  280. adapter->tx_context_id =
  281. le16_to_cpu(prsp->context_id);
  282. } else {
  283. dev_err(&adapter->pdev->dev,
  284. "Failed to create tx ctx in firmware%d\n", err);
  285. err = -EIO;
  286. }
  287. pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
  288. out_free_rq:
  289. pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
  290. return err;
  291. }
  292. static void
  293. qlcnic_fw_cmd_destroy_tx_ctx(struct qlcnic_adapter *adapter)
  294. {
  295. if (qlcnic_issue_cmd(adapter,
  296. adapter->ahw.pci_func,
  297. adapter->fw_hal_version,
  298. adapter->tx_context_id,
  299. QLCNIC_DESTROY_CTX_RESET,
  300. 0,
  301. QLCNIC_CDRP_CMD_DESTROY_TX_CTX)) {
  302. dev_err(&adapter->pdev->dev,
  303. "Failed to destroy tx ctx in firmware\n");
  304. }
  305. }
  306. int
  307. qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val)
  308. {
  309. if (qlcnic_issue_cmd(adapter,
  310. adapter->ahw.pci_func,
  311. adapter->fw_hal_version,
  312. reg,
  313. 0,
  314. 0,
  315. QLCNIC_CDRP_CMD_READ_PHY)) {
  316. return -EIO;
  317. }
  318. return QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
  319. }
  320. int
  321. qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val)
  322. {
  323. return qlcnic_issue_cmd(adapter,
  324. adapter->ahw.pci_func,
  325. adapter->fw_hal_version,
  326. reg,
  327. val,
  328. 0,
  329. QLCNIC_CDRP_CMD_WRITE_PHY);
  330. }
  331. int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter)
  332. {
  333. void *addr;
  334. int err;
  335. int ring;
  336. struct qlcnic_recv_context *recv_ctx;
  337. struct qlcnic_host_rds_ring *rds_ring;
  338. struct qlcnic_host_sds_ring *sds_ring;
  339. struct qlcnic_host_tx_ring *tx_ring;
  340. struct pci_dev *pdev = adapter->pdev;
  341. recv_ctx = &adapter->recv_ctx;
  342. tx_ring = adapter->tx_ring;
  343. tx_ring->hw_consumer = (__le32 *)pci_alloc_consistent(pdev, sizeof(u32),
  344. &tx_ring->hw_cons_phys_addr);
  345. if (tx_ring->hw_consumer == NULL) {
  346. dev_err(&pdev->dev, "failed to allocate tx consumer\n");
  347. return -ENOMEM;
  348. }
  349. *(tx_ring->hw_consumer) = 0;
  350. /* cmd desc ring */
  351. addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
  352. &tx_ring->phys_addr);
  353. if (addr == NULL) {
  354. dev_err(&pdev->dev, "failed to allocate tx desc ring\n");
  355. err = -ENOMEM;
  356. goto err_out_free;
  357. }
  358. tx_ring->desc_head = (struct cmd_desc_type0 *)addr;
  359. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  360. rds_ring = &recv_ctx->rds_rings[ring];
  361. addr = pci_alloc_consistent(adapter->pdev,
  362. RCV_DESC_RINGSIZE(rds_ring),
  363. &rds_ring->phys_addr);
  364. if (addr == NULL) {
  365. dev_err(&pdev->dev,
  366. "failed to allocate rds ring [%d]\n", ring);
  367. err = -ENOMEM;
  368. goto err_out_free;
  369. }
  370. rds_ring->desc_head = (struct rcv_desc *)addr;
  371. }
  372. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  373. sds_ring = &recv_ctx->sds_rings[ring];
  374. addr = pci_alloc_consistent(adapter->pdev,
  375. STATUS_DESC_RINGSIZE(sds_ring),
  376. &sds_ring->phys_addr);
  377. if (addr == NULL) {
  378. dev_err(&pdev->dev,
  379. "failed to allocate sds ring [%d]\n", ring);
  380. err = -ENOMEM;
  381. goto err_out_free;
  382. }
  383. sds_ring->desc_head = (struct status_desc *)addr;
  384. }
  385. err = qlcnic_fw_cmd_create_rx_ctx(adapter);
  386. if (err)
  387. goto err_out_free;
  388. err = qlcnic_fw_cmd_create_tx_ctx(adapter);
  389. if (err)
  390. goto err_out_free;
  391. set_bit(__QLCNIC_FW_ATTACHED, &adapter->state);
  392. return 0;
  393. err_out_free:
  394. qlcnic_free_hw_resources(adapter);
  395. return err;
  396. }
  397. void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter)
  398. {
  399. struct qlcnic_recv_context *recv_ctx;
  400. struct qlcnic_host_rds_ring *rds_ring;
  401. struct qlcnic_host_sds_ring *sds_ring;
  402. struct qlcnic_host_tx_ring *tx_ring;
  403. int ring;
  404. if (test_and_clear_bit(__QLCNIC_FW_ATTACHED, &adapter->state)) {
  405. qlcnic_fw_cmd_destroy_rx_ctx(adapter);
  406. qlcnic_fw_cmd_destroy_tx_ctx(adapter);
  407. /* Allow dma queues to drain after context reset */
  408. msleep(20);
  409. }
  410. recv_ctx = &adapter->recv_ctx;
  411. tx_ring = adapter->tx_ring;
  412. if (tx_ring->hw_consumer != NULL) {
  413. pci_free_consistent(adapter->pdev,
  414. sizeof(u32),
  415. tx_ring->hw_consumer,
  416. tx_ring->hw_cons_phys_addr);
  417. tx_ring->hw_consumer = NULL;
  418. }
  419. if (tx_ring->desc_head != NULL) {
  420. pci_free_consistent(adapter->pdev,
  421. TX_DESC_RINGSIZE(tx_ring),
  422. tx_ring->desc_head, tx_ring->phys_addr);
  423. tx_ring->desc_head = NULL;
  424. }
  425. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  426. rds_ring = &recv_ctx->rds_rings[ring];
  427. if (rds_ring->desc_head != NULL) {
  428. pci_free_consistent(adapter->pdev,
  429. RCV_DESC_RINGSIZE(rds_ring),
  430. rds_ring->desc_head,
  431. rds_ring->phys_addr);
  432. rds_ring->desc_head = NULL;
  433. }
  434. }
  435. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  436. sds_ring = &recv_ctx->sds_rings[ring];
  437. if (sds_ring->desc_head != NULL) {
  438. pci_free_consistent(adapter->pdev,
  439. STATUS_DESC_RINGSIZE(sds_ring),
  440. sds_ring->desc_head,
  441. sds_ring->phys_addr);
  442. sds_ring->desc_head = NULL;
  443. }
  444. }
  445. }
  446. /* Set MAC address of a NIC partition */
  447. int qlcnic_set_mac_address(struct qlcnic_adapter *adapter, u8* mac)
  448. {
  449. int err = 0;
  450. u32 arg1, arg2, arg3;
  451. arg1 = adapter->ahw.pci_func | BIT_9;
  452. arg2 = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
  453. arg3 = mac[4] | (mac[5] << 16);
  454. err = qlcnic_issue_cmd(adapter,
  455. adapter->ahw.pci_func,
  456. adapter->fw_hal_version,
  457. arg1,
  458. arg2,
  459. arg3,
  460. QLCNIC_CDRP_CMD_MAC_ADDRESS);
  461. if (err != QLCNIC_RCODE_SUCCESS) {
  462. dev_err(&adapter->pdev->dev,
  463. "Failed to set mac address%d\n", err);
  464. err = -EIO;
  465. }
  466. return err;
  467. }
  468. /* Get MAC address of a NIC partition */
  469. int qlcnic_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac)
  470. {
  471. int err;
  472. u32 arg1;
  473. arg1 = adapter->ahw.pci_func | BIT_8;
  474. err = qlcnic_issue_cmd(adapter,
  475. adapter->ahw.pci_func,
  476. adapter->fw_hal_version,
  477. arg1,
  478. 0,
  479. 0,
  480. QLCNIC_CDRP_CMD_MAC_ADDRESS);
  481. if (err == QLCNIC_RCODE_SUCCESS) {
  482. qlcnic_fetch_mac(adapter, QLCNIC_ARG1_CRB_OFFSET,
  483. QLCNIC_ARG2_CRB_OFFSET, 0, mac);
  484. dev_info(&adapter->pdev->dev, "MAC address: %pM\n", mac);
  485. } else {
  486. dev_err(&adapter->pdev->dev,
  487. "Failed to get mac address%d\n", err);
  488. err = -EIO;
  489. }
  490. return err;
  491. }
  492. /* Get info of a NIC partition */
  493. int qlcnic_get_nic_info(struct qlcnic_adapter *adapter, u8 func_id)
  494. {
  495. int err;
  496. dma_addr_t nic_dma_t;
  497. struct qlcnic_info *nic_info;
  498. void *nic_info_addr;
  499. size_t nic_size = sizeof(struct qlcnic_info);
  500. nic_info_addr = pci_alloc_consistent(adapter->pdev,
  501. nic_size, &nic_dma_t);
  502. if (!nic_info_addr)
  503. return -ENOMEM;
  504. memset(nic_info_addr, 0, nic_size);
  505. nic_info = (struct qlcnic_info *) nic_info_addr;
  506. err = qlcnic_issue_cmd(adapter,
  507. adapter->ahw.pci_func,
  508. adapter->fw_hal_version,
  509. MSD(nic_dma_t),
  510. LSD(nic_dma_t),
  511. (func_id << 16 | nic_size),
  512. QLCNIC_CDRP_CMD_GET_NIC_INFO);
  513. if (err == QLCNIC_RCODE_SUCCESS) {
  514. adapter->physical_port = le16_to_cpu(nic_info->phys_port);
  515. adapter->switch_mode = le16_to_cpu(nic_info->switch_mode);
  516. adapter->max_tx_ques = le16_to_cpu(nic_info->max_tx_ques);
  517. adapter->max_rx_ques = le16_to_cpu(nic_info->max_rx_ques);
  518. adapter->min_tx_bw = le16_to_cpu(nic_info->min_tx_bw);
  519. adapter->max_tx_bw = le16_to_cpu(nic_info->max_tx_bw);
  520. adapter->max_mtu = le16_to_cpu(nic_info->max_mtu);
  521. adapter->capabilities = le32_to_cpu(nic_info->capabilities);
  522. adapter->max_mac_filters = nic_info->max_mac_filters;
  523. dev_info(&adapter->pdev->dev,
  524. "phy port: %d switch_mode: %d,\n"
  525. "\tmax_tx_q: %d max_rx_q: %d min_tx_bw: 0x%x,\n"
  526. "\tmax_tx_bw: 0x%x max_mtu:0x%x, capabilities: 0x%x\n",
  527. adapter->physical_port, adapter->switch_mode,
  528. adapter->max_tx_ques, adapter->max_rx_ques,
  529. adapter->min_tx_bw, adapter->max_tx_bw,
  530. adapter->max_mtu, adapter->capabilities);
  531. } else {
  532. dev_err(&adapter->pdev->dev,
  533. "Failed to get nic info%d\n", err);
  534. err = -EIO;
  535. }
  536. pci_free_consistent(adapter->pdev, nic_size, nic_info_addr, nic_dma_t);
  537. return err;
  538. }
  539. /* Configure a NIC partition */
  540. int qlcnic_set_nic_info(struct qlcnic_adapter *adapter, struct qlcnic_info *nic)
  541. {
  542. int err = -EIO;
  543. u32 func_state;
  544. dma_addr_t nic_dma_t;
  545. void *nic_info_addr;
  546. struct qlcnic_info *nic_info;
  547. size_t nic_size = sizeof(struct qlcnic_info);
  548. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  549. return err;
  550. if (qlcnic_api_lock(adapter))
  551. return err;
  552. func_state = QLCRD32(adapter, QLCNIC_CRB_DEV_REF_COUNT);
  553. if (QLC_DEV_CHECK_ACTIVE(func_state, nic->pci_func)) {
  554. qlcnic_api_unlock(adapter);
  555. return err;
  556. }
  557. qlcnic_api_unlock(adapter);
  558. nic_info_addr = pci_alloc_consistent(adapter->pdev, nic_size,
  559. &nic_dma_t);
  560. if (!nic_info_addr)
  561. return -ENOMEM;
  562. memset(nic_info_addr, 0, nic_size);
  563. nic_info = (struct qlcnic_info *)nic_info_addr;
  564. nic_info->pci_func = cpu_to_le16(nic->pci_func);
  565. nic_info->op_mode = cpu_to_le16(nic->op_mode);
  566. nic_info->phys_port = cpu_to_le16(nic->phys_port);
  567. nic_info->switch_mode = cpu_to_le16(nic->switch_mode);
  568. nic_info->capabilities = cpu_to_le32(nic->capabilities);
  569. nic_info->max_mac_filters = nic->max_mac_filters;
  570. nic_info->max_tx_ques = cpu_to_le16(nic->max_tx_ques);
  571. nic_info->max_rx_ques = cpu_to_le16(nic->max_rx_ques);
  572. nic_info->min_tx_bw = cpu_to_le16(nic->min_tx_bw);
  573. nic_info->max_tx_bw = cpu_to_le16(nic->max_tx_bw);
  574. err = qlcnic_issue_cmd(adapter,
  575. adapter->ahw.pci_func,
  576. adapter->fw_hal_version,
  577. MSD(nic_dma_t),
  578. LSD(nic_dma_t),
  579. nic_size,
  580. QLCNIC_CDRP_CMD_SET_NIC_INFO);
  581. if (err != QLCNIC_RCODE_SUCCESS) {
  582. dev_err(&adapter->pdev->dev,
  583. "Failed to set nic info%d\n", err);
  584. err = -EIO;
  585. }
  586. pci_free_consistent(adapter->pdev, nic_size, nic_info_addr, nic_dma_t);
  587. return err;
  588. }
  589. /* Get PCI Info of a partition */
  590. int qlcnic_get_pci_info(struct qlcnic_adapter *adapter)
  591. {
  592. int err = 0, i;
  593. dma_addr_t pci_info_dma_t;
  594. struct qlcnic_pci_info *npar;
  595. void *pci_info_addr;
  596. size_t npar_size = sizeof(struct qlcnic_pci_info);
  597. size_t pci_size = npar_size * QLCNIC_MAX_PCI_FUNC;
  598. pci_info_addr = pci_alloc_consistent(adapter->pdev, pci_size,
  599. &pci_info_dma_t);
  600. if (!pci_info_addr)
  601. return -ENOMEM;
  602. memset(pci_info_addr, 0, pci_size);
  603. if (!adapter->npars)
  604. adapter->npars = kzalloc(pci_size, GFP_KERNEL);
  605. if (!adapter->npars) {
  606. err = -ENOMEM;
  607. goto err_npar;
  608. }
  609. if (!adapter->eswitch)
  610. adapter->eswitch = kzalloc(sizeof(struct qlcnic_eswitch) *
  611. QLCNIC_NIU_MAX_XG_PORTS, GFP_KERNEL);
  612. if (!adapter->eswitch) {
  613. err = -ENOMEM;
  614. goto err_eswitch;
  615. }
  616. npar = (struct qlcnic_pci_info *) pci_info_addr;
  617. err = qlcnic_issue_cmd(adapter,
  618. adapter->ahw.pci_func,
  619. adapter->fw_hal_version,
  620. MSD(pci_info_dma_t),
  621. LSD(pci_info_dma_t),
  622. pci_size,
  623. QLCNIC_CDRP_CMD_GET_PCI_INFO);
  624. if (err == QLCNIC_RCODE_SUCCESS) {
  625. for (i = 0; i < QLCNIC_MAX_PCI_FUNC; i++, npar++) {
  626. adapter->npars[i].id = le32_to_cpu(npar->id);
  627. adapter->npars[i].active = le32_to_cpu(npar->active);
  628. adapter->npars[i].type = le32_to_cpu(npar->type);
  629. adapter->npars[i].default_port =
  630. le32_to_cpu(npar->default_port);
  631. adapter->npars[i].tx_min_bw =
  632. le32_to_cpu(npar->tx_min_bw);
  633. adapter->npars[i].tx_max_bw =
  634. le32_to_cpu(npar->tx_max_bw);
  635. memcpy(adapter->npars[i].mac, npar->mac, ETH_ALEN);
  636. }
  637. } else {
  638. dev_err(&adapter->pdev->dev,
  639. "Failed to get PCI Info%d\n", err);
  640. kfree(adapter->npars);
  641. err = -EIO;
  642. }
  643. goto err_npar;
  644. err_eswitch:
  645. kfree(adapter->npars);
  646. adapter->npars = NULL;
  647. err_npar:
  648. pci_free_consistent(adapter->pdev, pci_size, pci_info_addr,
  649. pci_info_dma_t);
  650. return err;
  651. }
  652. /* Reset a NIC partition */
  653. int qlcnic_reset_partition(struct qlcnic_adapter *adapter, u8 func_no)
  654. {
  655. int err = -EIO;
  656. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  657. return err;
  658. err = qlcnic_issue_cmd(adapter,
  659. adapter->ahw.pci_func,
  660. adapter->fw_hal_version,
  661. func_no,
  662. 0,
  663. 0,
  664. QLCNIC_CDRP_CMD_RESET_NPAR);
  665. if (err != QLCNIC_RCODE_SUCCESS) {
  666. dev_err(&adapter->pdev->dev,
  667. "Failed to issue reset partition%d\n", err);
  668. err = -EIO;
  669. }
  670. return err;
  671. }
  672. /* Get eSwitch Capabilities */
  673. int qlcnic_get_eswitch_capabilities(struct qlcnic_adapter *adapter, u8 port,
  674. struct qlcnic_eswitch *eswitch)
  675. {
  676. int err = -EIO;
  677. u32 arg1, arg2;
  678. if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC)
  679. return err;
  680. err = qlcnic_issue_cmd(adapter,
  681. adapter->ahw.pci_func,
  682. adapter->fw_hal_version,
  683. port,
  684. 0,
  685. 0,
  686. QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY);
  687. if (err == QLCNIC_RCODE_SUCCESS) {
  688. arg1 = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
  689. arg2 = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET);
  690. eswitch->port = arg1 & 0xf;
  691. eswitch->active_vports = LSB(arg2);
  692. eswitch->max_ucast_filters = MSB(arg2);
  693. eswitch->max_active_vlans = LSB(MSW(arg2));
  694. if (arg1 & BIT_6)
  695. eswitch->flags |= QLCNIC_SWITCH_VLAN_FILTERING;
  696. if (arg1 & BIT_7)
  697. eswitch->flags |= QLCNIC_SWITCH_PROMISC_MODE;
  698. if (arg1 & BIT_8)
  699. eswitch->flags |= QLCNIC_SWITCH_PORT_MIRRORING;
  700. } else {
  701. dev_err(&adapter->pdev->dev,
  702. "Failed to get eswitch capabilities%d\n", err);
  703. }
  704. return err;
  705. }
  706. /* Get current status of eswitch */
  707. int qlcnic_get_eswitch_status(struct qlcnic_adapter *adapter, u8 port,
  708. struct qlcnic_eswitch *eswitch)
  709. {
  710. int err = -EIO;
  711. u32 arg1, arg2;
  712. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  713. return err;
  714. err = qlcnic_issue_cmd(adapter,
  715. adapter->ahw.pci_func,
  716. adapter->fw_hal_version,
  717. port,
  718. 0,
  719. 0,
  720. QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS);
  721. if (err == QLCNIC_RCODE_SUCCESS) {
  722. arg1 = QLCRD32(adapter, QLCNIC_ARG1_CRB_OFFSET);
  723. arg2 = QLCRD32(adapter, QLCNIC_ARG2_CRB_OFFSET);
  724. eswitch->port = arg1 & 0xf;
  725. eswitch->active_vports = LSB(arg2);
  726. eswitch->active_ucast_filters = MSB(arg2);
  727. eswitch->active_vlans = LSB(MSW(arg2));
  728. if (arg1 & BIT_6)
  729. eswitch->flags |= QLCNIC_SWITCH_VLAN_FILTERING;
  730. if (arg1 & BIT_8)
  731. eswitch->flags |= QLCNIC_SWITCH_PORT_MIRRORING;
  732. } else {
  733. dev_err(&adapter->pdev->dev,
  734. "Failed to get eswitch status%d\n", err);
  735. }
  736. return err;
  737. }
  738. /* Enable/Disable eSwitch */
  739. int qlcnic_toggle_eswitch(struct qlcnic_adapter *adapter, u8 id, u8 enable)
  740. {
  741. int err = -EIO;
  742. u32 arg1, arg2;
  743. struct qlcnic_eswitch *eswitch;
  744. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  745. return err;
  746. eswitch = &adapter->eswitch[id];
  747. if (!eswitch)
  748. return err;
  749. arg1 = eswitch->port | (enable ? BIT_4 : 0);
  750. arg2 = eswitch->active_vports | (eswitch->max_ucast_filters << 8) |
  751. (eswitch->max_active_vlans << 16);
  752. err = qlcnic_issue_cmd(adapter,
  753. adapter->ahw.pci_func,
  754. adapter->fw_hal_version,
  755. arg1,
  756. arg2,
  757. 0,
  758. QLCNIC_CDRP_CMD_TOGGLE_ESWITCH);
  759. if (err != QLCNIC_RCODE_SUCCESS) {
  760. dev_err(&adapter->pdev->dev,
  761. "Failed to enable eswitch%d\n", eswitch->port);
  762. eswitch->flags &= ~QLCNIC_SWITCH_ENABLE;
  763. err = -EIO;
  764. } else {
  765. eswitch->flags |= QLCNIC_SWITCH_ENABLE;
  766. dev_info(&adapter->pdev->dev,
  767. "Enabled eSwitch for port %d\n", eswitch->port);
  768. }
  769. return err;
  770. }
  771. /* Configure eSwitch for port mirroring */
  772. int qlcnic_config_port_mirroring(struct qlcnic_adapter *adapter, u8 id,
  773. u8 enable_mirroring, u8 pci_func)
  774. {
  775. int err = -EIO;
  776. u32 arg1;
  777. if (adapter->op_mode != QLCNIC_MGMT_FUNC ||
  778. !(adapter->eswitch[id].flags & QLCNIC_SWITCH_ENABLE))
  779. return err;
  780. arg1 = id | (enable_mirroring ? BIT_4 : 0);
  781. arg1 |= pci_func << 8;
  782. err = qlcnic_issue_cmd(adapter,
  783. adapter->ahw.pci_func,
  784. adapter->fw_hal_version,
  785. arg1,
  786. 0,
  787. 0,
  788. QLCNIC_CDRP_CMD_SET_PORTMIRRORING);
  789. if (err != QLCNIC_RCODE_SUCCESS) {
  790. dev_err(&adapter->pdev->dev,
  791. "Failed to configure port mirroring%d on eswitch:%d\n",
  792. pci_func, id);
  793. } else {
  794. dev_info(&adapter->pdev->dev,
  795. "Configured eSwitch %d for port mirroring:%d\n",
  796. id, pci_func);
  797. }
  798. return err;
  799. }
  800. /* Configure eSwitch port */
  801. int qlcnic_config_switch_port(struct qlcnic_adapter *adapter, u8 id,
  802. int vlan_tagging, u8 discard_tagged, u8 promsc_mode,
  803. u8 mac_learn, u8 pci_func, u16 vlan_id)
  804. {
  805. int err = -EIO;
  806. u32 arg1;
  807. struct qlcnic_eswitch *eswitch;
  808. if (adapter->op_mode != QLCNIC_MGMT_FUNC)
  809. return err;
  810. eswitch = &adapter->eswitch[id];
  811. if (!(eswitch->flags & QLCNIC_SWITCH_ENABLE))
  812. return err;
  813. arg1 = eswitch->port | (discard_tagged ? BIT_4 : 0);
  814. arg1 |= (promsc_mode ? BIT_6 : 0) | (mac_learn ? BIT_7 : 0);
  815. arg1 |= pci_func << 8;
  816. if (vlan_tagging)
  817. arg1 |= BIT_5 | (vlan_id << 16);
  818. err = qlcnic_issue_cmd(adapter,
  819. adapter->ahw.pci_func,
  820. adapter->fw_hal_version,
  821. arg1,
  822. 0,
  823. 0,
  824. QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH);
  825. if (err != QLCNIC_RCODE_SUCCESS) {
  826. dev_err(&adapter->pdev->dev,
  827. "Failed to configure eswitch port%d\n", eswitch->port);
  828. eswitch->flags |= QLCNIC_SWITCH_ENABLE;
  829. } else {
  830. eswitch->flags &= ~QLCNIC_SWITCH_ENABLE;
  831. dev_info(&adapter->pdev->dev,
  832. "Configured eSwitch for port %d\n", eswitch->port);
  833. }
  834. return err;
  835. }