intel_sdvo.c 80 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "drm_crtc.h"
  34. #include "drm_edid.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  47. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  48. static const char *tv_format_names[] = {
  49. "NTSC_M" , "NTSC_J" , "NTSC_443",
  50. "PAL_B" , "PAL_D" , "PAL_G" ,
  51. "PAL_H" , "PAL_I" , "PAL_M" ,
  52. "PAL_N" , "PAL_NC" , "PAL_60" ,
  53. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  54. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  55. "SECAM_60"
  56. };
  57. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  58. struct intel_sdvo {
  59. struct intel_encoder base;
  60. u8 slave_addr;
  61. /* Register for the SDVO device: SDVOB or SDVOC */
  62. int sdvo_reg;
  63. /* Active outputs controlled by this SDVO output */
  64. uint16_t controlled_output;
  65. /*
  66. * Capabilities of the SDVO device returned by
  67. * i830_sdvo_get_capabilities()
  68. */
  69. struct intel_sdvo_caps caps;
  70. /* Pixel clock limitations reported by the SDVO device, in kHz */
  71. int pixel_clock_min, pixel_clock_max;
  72. /*
  73. * For multiple function SDVO device,
  74. * this is for current attached outputs.
  75. */
  76. uint16_t attached_output;
  77. /**
  78. * This is set if we're going to treat the device as TV-out.
  79. *
  80. * While we have these nice friendly flags for output types that ought
  81. * to decide this for us, the S-Video output on our HDMI+S-Video card
  82. * shows up as RGB1 (VGA).
  83. */
  84. bool is_tv;
  85. /* This is for current tv format name */
  86. int tv_format_index;
  87. /**
  88. * This is set if we treat the device as HDMI, instead of DVI.
  89. */
  90. bool is_hdmi;
  91. /**
  92. * This is set if we detect output of sdvo device as LVDS.
  93. */
  94. bool is_lvds;
  95. /**
  96. * This is sdvo flags for input timing.
  97. */
  98. uint8_t sdvo_flags;
  99. /**
  100. * This is sdvo fixed pannel mode pointer
  101. */
  102. struct drm_display_mode *sdvo_lvds_fixed_mode;
  103. /*
  104. * supported encoding mode, used to determine whether HDMI is
  105. * supported
  106. */
  107. struct intel_sdvo_encode encode;
  108. /* DDC bus used by this SDVO encoder */
  109. uint8_t ddc_bus;
  110. /* Mac mini hack -- use the same DDC as the analog connector */
  111. struct i2c_adapter *analog_ddc_bus;
  112. };
  113. struct intel_sdvo_connector {
  114. struct intel_connector base;
  115. /* Mark the type of connector */
  116. uint16_t output_flag;
  117. /* This contains all current supported TV format */
  118. u8 tv_format_supported[TV_FORMAT_NUM];
  119. int format_supported_num;
  120. struct drm_property *tv_format;
  121. /* add the property for the SDVO-TV */
  122. struct drm_property *left;
  123. struct drm_property *right;
  124. struct drm_property *top;
  125. struct drm_property *bottom;
  126. struct drm_property *hpos;
  127. struct drm_property *vpos;
  128. struct drm_property *contrast;
  129. struct drm_property *saturation;
  130. struct drm_property *hue;
  131. struct drm_property *sharpness;
  132. struct drm_property *flicker_filter;
  133. struct drm_property *flicker_filter_adaptive;
  134. struct drm_property *flicker_filter_2d;
  135. struct drm_property *tv_chroma_filter;
  136. struct drm_property *tv_luma_filter;
  137. struct drm_property *dot_crawl;
  138. /* add the property for the SDVO-TV/LVDS */
  139. struct drm_property *brightness;
  140. /* Add variable to record current setting for the above property */
  141. u32 left_margin, right_margin, top_margin, bottom_margin;
  142. /* this is to get the range of margin.*/
  143. u32 max_hscan, max_vscan;
  144. u32 max_hpos, cur_hpos;
  145. u32 max_vpos, cur_vpos;
  146. u32 cur_brightness, max_brightness;
  147. u32 cur_contrast, max_contrast;
  148. u32 cur_saturation, max_saturation;
  149. u32 cur_hue, max_hue;
  150. u32 cur_sharpness, max_sharpness;
  151. u32 cur_flicker_filter, max_flicker_filter;
  152. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  153. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  154. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  155. u32 cur_tv_luma_filter, max_tv_luma_filter;
  156. u32 cur_dot_crawl, max_dot_crawl;
  157. };
  158. static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
  159. {
  160. return container_of(enc_to_intel_encoder(encoder), struct intel_sdvo, base);
  161. }
  162. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  163. {
  164. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  165. }
  166. static bool
  167. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  168. static bool
  169. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  170. struct intel_sdvo_connector *intel_sdvo_connector,
  171. int type);
  172. static bool
  173. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  174. struct intel_sdvo_connector *intel_sdvo_connector);
  175. /**
  176. * Writes the SDVOB or SDVOC with the given value, but always writes both
  177. * SDVOB and SDVOC to work around apparent hardware issues (according to
  178. * comments in the BIOS).
  179. */
  180. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  181. {
  182. struct drm_device *dev = intel_sdvo->base.enc.dev;
  183. struct drm_i915_private *dev_priv = dev->dev_private;
  184. u32 bval = val, cval = val;
  185. int i;
  186. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  187. I915_WRITE(intel_sdvo->sdvo_reg, val);
  188. I915_READ(intel_sdvo->sdvo_reg);
  189. return;
  190. }
  191. if (intel_sdvo->sdvo_reg == SDVOB) {
  192. cval = I915_READ(SDVOC);
  193. } else {
  194. bval = I915_READ(SDVOB);
  195. }
  196. /*
  197. * Write the registers twice for luck. Sometimes,
  198. * writing them only once doesn't appear to 'stick'.
  199. * The BIOS does this too. Yay, magic
  200. */
  201. for (i = 0; i < 2; i++)
  202. {
  203. I915_WRITE(SDVOB, bval);
  204. I915_READ(SDVOB);
  205. I915_WRITE(SDVOC, cval);
  206. I915_READ(SDVOC);
  207. }
  208. }
  209. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  210. {
  211. u8 out_buf[2] = { addr, 0 };
  212. u8 buf[2];
  213. struct i2c_msg msgs[] = {
  214. {
  215. .addr = intel_sdvo->slave_addr >> 1,
  216. .flags = 0,
  217. .len = 1,
  218. .buf = out_buf,
  219. },
  220. {
  221. .addr = intel_sdvo->slave_addr >> 1,
  222. .flags = I2C_M_RD,
  223. .len = 1,
  224. .buf = buf,
  225. }
  226. };
  227. int ret;
  228. if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
  229. {
  230. *ch = buf[0];
  231. return true;
  232. }
  233. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  234. return false;
  235. }
  236. static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
  237. {
  238. u8 out_buf[2] = { addr, ch };
  239. struct i2c_msg msgs[] = {
  240. {
  241. .addr = intel_sdvo->slave_addr >> 1,
  242. .flags = 0,
  243. .len = 2,
  244. .buf = out_buf,
  245. }
  246. };
  247. return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
  248. }
  249. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  250. /** Mapping of command numbers to names, for debug output */
  251. static const struct _sdvo_cmd_name {
  252. u8 cmd;
  253. const char *name;
  254. } sdvo_cmd_names[] = {
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  298. /* Add the op code for SDVO enhancements */
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  343. /* HDMI op code */
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  362. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  363. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  364. };
  365. #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
  366. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  367. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  368. const void *args, int args_len)
  369. {
  370. int i;
  371. DRM_DEBUG_KMS("%s: W: %02X ",
  372. SDVO_NAME(intel_sdvo), cmd);
  373. for (i = 0; i < args_len; i++)
  374. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  375. for (; i < 8; i++)
  376. DRM_LOG_KMS(" ");
  377. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  378. if (cmd == sdvo_cmd_names[i].cmd) {
  379. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  380. break;
  381. }
  382. }
  383. if (i == ARRAY_SIZE(sdvo_cmd_names))
  384. DRM_LOG_KMS("(%02X)", cmd);
  385. DRM_LOG_KMS("\n");
  386. }
  387. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  388. const void *args, int args_len)
  389. {
  390. int i;
  391. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  392. for (i = 0; i < args_len; i++) {
  393. if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
  394. ((u8*)args)[i]))
  395. return false;
  396. }
  397. return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
  398. }
  399. static const char *cmd_status_names[] = {
  400. "Power on",
  401. "Success",
  402. "Not supported",
  403. "Invalid arg",
  404. "Pending",
  405. "Target not specified",
  406. "Scaling not supported"
  407. };
  408. static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
  409. void *response, int response_len,
  410. u8 status)
  411. {
  412. int i;
  413. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  414. for (i = 0; i < response_len; i++)
  415. DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
  416. for (; i < 8; i++)
  417. DRM_LOG_KMS(" ");
  418. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  419. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  420. else
  421. DRM_LOG_KMS("(??? %d)", status);
  422. DRM_LOG_KMS("\n");
  423. }
  424. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  425. void *response, int response_len)
  426. {
  427. int i;
  428. u8 status;
  429. u8 retry = 50;
  430. while (retry--) {
  431. /* Read the command response */
  432. for (i = 0; i < response_len; i++) {
  433. if (!intel_sdvo_read_byte(intel_sdvo,
  434. SDVO_I2C_RETURN_0 + i,
  435. &((u8 *)response)[i]))
  436. return false;
  437. }
  438. /* read the return status */
  439. if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
  440. &status))
  441. return false;
  442. intel_sdvo_debug_response(intel_sdvo, response, response_len,
  443. status);
  444. if (status != SDVO_CMD_STATUS_PENDING)
  445. break;
  446. mdelay(50);
  447. }
  448. return status == SDVO_CMD_STATUS_SUCCESS;
  449. }
  450. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  451. {
  452. if (mode->clock >= 100000)
  453. return 1;
  454. else if (mode->clock >= 50000)
  455. return 2;
  456. else
  457. return 4;
  458. }
  459. /**
  460. * Try to read the response after issuie the DDC switch command. But it
  461. * is noted that we must do the action of reading response and issuing DDC
  462. * switch command in one I2C transaction. Otherwise when we try to start
  463. * another I2C transaction after issuing the DDC bus switch, it will be
  464. * switched to the internal SDVO register.
  465. */
  466. static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  467. u8 target)
  468. {
  469. u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
  470. struct i2c_msg msgs[] = {
  471. {
  472. .addr = intel_sdvo->slave_addr >> 1,
  473. .flags = 0,
  474. .len = 2,
  475. .buf = out_buf,
  476. },
  477. /* the following two are to read the response */
  478. {
  479. .addr = intel_sdvo->slave_addr >> 1,
  480. .flags = 0,
  481. .len = 1,
  482. .buf = cmd_buf,
  483. },
  484. {
  485. .addr = intel_sdvo->slave_addr >> 1,
  486. .flags = I2C_M_RD,
  487. .len = 1,
  488. .buf = ret_value,
  489. },
  490. };
  491. intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  492. &target, 1);
  493. /* write the DDC switch command argument */
  494. intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
  495. out_buf[0] = SDVO_I2C_OPCODE;
  496. out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
  497. cmd_buf[0] = SDVO_I2C_CMD_STATUS;
  498. cmd_buf[1] = 0;
  499. ret_value[0] = 0;
  500. ret_value[1] = 0;
  501. ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
  502. if (ret != 3) {
  503. /* failure in I2C transfer */
  504. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  505. return;
  506. }
  507. if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
  508. DRM_DEBUG_KMS("DDC switch command returns response %d\n",
  509. ret_value[0]);
  510. return;
  511. }
  512. return;
  513. }
  514. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  515. {
  516. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  517. return false;
  518. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  519. }
  520. static bool
  521. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  522. {
  523. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  524. return false;
  525. return intel_sdvo_read_response(intel_sdvo, value, len);
  526. }
  527. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  528. {
  529. struct intel_sdvo_set_target_input_args targets = {0};
  530. return intel_sdvo_set_value(intel_sdvo,
  531. SDVO_CMD_SET_TARGET_INPUT,
  532. &targets, sizeof(targets));
  533. }
  534. /**
  535. * Return whether each input is trained.
  536. *
  537. * This function is making an assumption about the layout of the response,
  538. * which should be checked against the docs.
  539. */
  540. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  541. {
  542. struct intel_sdvo_get_trained_inputs_response response;
  543. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  544. &response, sizeof(response)))
  545. return false;
  546. *input_1 = response.input0_trained;
  547. *input_2 = response.input1_trained;
  548. return true;
  549. }
  550. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  551. u16 outputs)
  552. {
  553. return intel_sdvo_set_value(intel_sdvo,
  554. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  555. &outputs, sizeof(outputs));
  556. }
  557. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  558. int mode)
  559. {
  560. u8 state = SDVO_ENCODER_STATE_ON;
  561. switch (mode) {
  562. case DRM_MODE_DPMS_ON:
  563. state = SDVO_ENCODER_STATE_ON;
  564. break;
  565. case DRM_MODE_DPMS_STANDBY:
  566. state = SDVO_ENCODER_STATE_STANDBY;
  567. break;
  568. case DRM_MODE_DPMS_SUSPEND:
  569. state = SDVO_ENCODER_STATE_SUSPEND;
  570. break;
  571. case DRM_MODE_DPMS_OFF:
  572. state = SDVO_ENCODER_STATE_OFF;
  573. break;
  574. }
  575. return intel_sdvo_set_value(intel_sdvo,
  576. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  577. }
  578. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  579. int *clock_min,
  580. int *clock_max)
  581. {
  582. struct intel_sdvo_pixel_clock_range clocks;
  583. if (!intel_sdvo_get_value(intel_sdvo,
  584. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  585. &clocks, sizeof(clocks)))
  586. return false;
  587. /* Convert the values from units of 10 kHz to kHz. */
  588. *clock_min = clocks.min * 10;
  589. *clock_max = clocks.max * 10;
  590. return true;
  591. }
  592. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  593. u16 outputs)
  594. {
  595. return intel_sdvo_set_value(intel_sdvo,
  596. SDVO_CMD_SET_TARGET_OUTPUT,
  597. &outputs, sizeof(outputs));
  598. }
  599. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  600. struct intel_sdvo_dtd *dtd)
  601. {
  602. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  603. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  604. }
  605. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  606. struct intel_sdvo_dtd *dtd)
  607. {
  608. return intel_sdvo_set_timing(intel_sdvo,
  609. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  610. }
  611. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  612. struct intel_sdvo_dtd *dtd)
  613. {
  614. return intel_sdvo_set_timing(intel_sdvo,
  615. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  616. }
  617. static bool
  618. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  619. uint16_t clock,
  620. uint16_t width,
  621. uint16_t height)
  622. {
  623. struct intel_sdvo_preferred_input_timing_args args;
  624. memset(&args, 0, sizeof(args));
  625. args.clock = clock;
  626. args.width = width;
  627. args.height = height;
  628. args.interlace = 0;
  629. if (intel_sdvo->is_lvds &&
  630. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  631. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  632. args.scaled = 1;
  633. return intel_sdvo_set_value(intel_sdvo,
  634. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  635. &args, sizeof(args));
  636. }
  637. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  638. struct intel_sdvo_dtd *dtd)
  639. {
  640. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  641. &dtd->part1, sizeof(dtd->part1)) &&
  642. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  643. &dtd->part2, sizeof(dtd->part2));
  644. }
  645. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  646. {
  647. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  648. }
  649. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  650. const struct drm_display_mode *mode)
  651. {
  652. uint16_t width, height;
  653. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  654. uint16_t h_sync_offset, v_sync_offset;
  655. width = mode->crtc_hdisplay;
  656. height = mode->crtc_vdisplay;
  657. /* do some mode translations */
  658. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  659. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  660. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  661. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  662. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  663. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  664. dtd->part1.clock = mode->clock / 10;
  665. dtd->part1.h_active = width & 0xff;
  666. dtd->part1.h_blank = h_blank_len & 0xff;
  667. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  668. ((h_blank_len >> 8) & 0xf);
  669. dtd->part1.v_active = height & 0xff;
  670. dtd->part1.v_blank = v_blank_len & 0xff;
  671. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  672. ((v_blank_len >> 8) & 0xf);
  673. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  674. dtd->part2.h_sync_width = h_sync_len & 0xff;
  675. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  676. (v_sync_len & 0xf);
  677. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  678. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  679. ((v_sync_len & 0x30) >> 4);
  680. dtd->part2.dtd_flags = 0x18;
  681. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  682. dtd->part2.dtd_flags |= 0x2;
  683. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  684. dtd->part2.dtd_flags |= 0x4;
  685. dtd->part2.sdvo_flags = 0;
  686. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  687. dtd->part2.reserved = 0;
  688. }
  689. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  690. const struct intel_sdvo_dtd *dtd)
  691. {
  692. mode->hdisplay = dtd->part1.h_active;
  693. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  694. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  695. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  696. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  697. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  698. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  699. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  700. mode->vdisplay = dtd->part1.v_active;
  701. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  702. mode->vsync_start = mode->vdisplay;
  703. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  704. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  705. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  706. mode->vsync_end = mode->vsync_start +
  707. (dtd->part2.v_sync_off_width & 0xf);
  708. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  709. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  710. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  711. mode->clock = dtd->part1.clock * 10;
  712. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  713. if (dtd->part2.dtd_flags & 0x2)
  714. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  715. if (dtd->part2.dtd_flags & 0x4)
  716. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  717. }
  718. static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
  719. struct intel_sdvo_encode *encode)
  720. {
  721. if (intel_sdvo_get_value(intel_sdvo,
  722. SDVO_CMD_GET_SUPP_ENCODE,
  723. encode, sizeof(*encode)))
  724. return true;
  725. /* non-support means DVI */
  726. memset(encode, 0, sizeof(*encode));
  727. return false;
  728. }
  729. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  730. uint8_t mode)
  731. {
  732. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  733. }
  734. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  735. uint8_t mode)
  736. {
  737. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  738. }
  739. #if 0
  740. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  741. {
  742. int i, j;
  743. uint8_t set_buf_index[2];
  744. uint8_t av_split;
  745. uint8_t buf_size;
  746. uint8_t buf[48];
  747. uint8_t *pos;
  748. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  749. for (i = 0; i <= av_split; i++) {
  750. set_buf_index[0] = i; set_buf_index[1] = 0;
  751. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  752. set_buf_index, 2);
  753. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  754. intel_sdvo_read_response(encoder, &buf_size, 1);
  755. pos = buf;
  756. for (j = 0; j <= buf_size; j += 8) {
  757. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  758. NULL, 0);
  759. intel_sdvo_read_response(encoder, pos, 8);
  760. pos += 8;
  761. }
  762. }
  763. }
  764. #endif
  765. static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
  766. int index,
  767. uint8_t *data, int8_t size, uint8_t tx_rate)
  768. {
  769. uint8_t set_buf_index[2];
  770. set_buf_index[0] = index;
  771. set_buf_index[1] = 0;
  772. if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
  773. set_buf_index, 2))
  774. return false;
  775. for (; size > 0; size -= 8) {
  776. if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
  777. return false;
  778. data += 8;
  779. }
  780. return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
  781. }
  782. static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
  783. {
  784. uint8_t csum = 0;
  785. int i;
  786. for (i = 0; i < size; i++)
  787. csum += data[i];
  788. return 0x100 - csum;
  789. }
  790. #define DIP_TYPE_AVI 0x82
  791. #define DIP_VERSION_AVI 0x2
  792. #define DIP_LEN_AVI 13
  793. struct dip_infoframe {
  794. uint8_t type;
  795. uint8_t version;
  796. uint8_t len;
  797. uint8_t checksum;
  798. union {
  799. struct {
  800. /* Packet Byte #1 */
  801. uint8_t S:2;
  802. uint8_t B:2;
  803. uint8_t A:1;
  804. uint8_t Y:2;
  805. uint8_t rsvd1:1;
  806. /* Packet Byte #2 */
  807. uint8_t R:4;
  808. uint8_t M:2;
  809. uint8_t C:2;
  810. /* Packet Byte #3 */
  811. uint8_t SC:2;
  812. uint8_t Q:2;
  813. uint8_t EC:3;
  814. uint8_t ITC:1;
  815. /* Packet Byte #4 */
  816. uint8_t VIC:7;
  817. uint8_t rsvd2:1;
  818. /* Packet Byte #5 */
  819. uint8_t PR:4;
  820. uint8_t rsvd3:4;
  821. /* Packet Byte #6~13 */
  822. uint16_t top_bar_end;
  823. uint16_t bottom_bar_start;
  824. uint16_t left_bar_end;
  825. uint16_t right_bar_start;
  826. } avi;
  827. struct {
  828. /* Packet Byte #1 */
  829. uint8_t channel_count:3;
  830. uint8_t rsvd1:1;
  831. uint8_t coding_type:4;
  832. /* Packet Byte #2 */
  833. uint8_t sample_size:2; /* SS0, SS1 */
  834. uint8_t sample_frequency:3;
  835. uint8_t rsvd2:3;
  836. /* Packet Byte #3 */
  837. uint8_t coding_type_private:5;
  838. uint8_t rsvd3:3;
  839. /* Packet Byte #4 */
  840. uint8_t channel_allocation;
  841. /* Packet Byte #5 */
  842. uint8_t rsvd4:3;
  843. uint8_t level_shift:4;
  844. uint8_t downmix_inhibit:1;
  845. } audio;
  846. uint8_t payload[28];
  847. } __attribute__ ((packed)) u;
  848. } __attribute__((packed));
  849. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
  850. struct drm_display_mode * mode)
  851. {
  852. struct dip_infoframe avi_if = {
  853. .type = DIP_TYPE_AVI,
  854. .version = DIP_VERSION_AVI,
  855. .len = DIP_LEN_AVI,
  856. };
  857. avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
  858. 4 + avi_if.len);
  859. return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
  860. 4 + avi_if.len,
  861. SDVO_HBUF_TX_VSYNC);
  862. }
  863. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  864. {
  865. struct intel_sdvo_tv_format format;
  866. uint32_t format_map;
  867. format_map = 1 << intel_sdvo->tv_format_index;
  868. memset(&format, 0, sizeof(format));
  869. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  870. BUILD_BUG_ON(sizeof(format) != 6);
  871. return intel_sdvo_set_value(intel_sdvo,
  872. SDVO_CMD_SET_TV_FORMAT,
  873. &format, sizeof(format));
  874. }
  875. static bool
  876. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  877. struct drm_display_mode *mode)
  878. {
  879. struct intel_sdvo_dtd output_dtd;
  880. if (!intel_sdvo_set_target_output(intel_sdvo,
  881. intel_sdvo->attached_output))
  882. return false;
  883. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  884. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  885. return false;
  886. return true;
  887. }
  888. static bool
  889. intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
  890. struct drm_display_mode *mode,
  891. struct drm_display_mode *adjusted_mode)
  892. {
  893. struct intel_sdvo_dtd input_dtd;
  894. /* Reset the input timing to the screen. Assume always input 0. */
  895. if (!intel_sdvo_set_target_input(intel_sdvo))
  896. return false;
  897. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  898. mode->clock / 10,
  899. mode->hdisplay,
  900. mode->vdisplay))
  901. return false;
  902. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  903. &input_dtd))
  904. return false;
  905. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  906. intel_sdvo->sdvo_flags = input_dtd.part2.sdvo_flags;
  907. drm_mode_set_crtcinfo(adjusted_mode, 0);
  908. mode->clock = adjusted_mode->clock;
  909. return true;
  910. }
  911. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  912. struct drm_display_mode *mode,
  913. struct drm_display_mode *adjusted_mode)
  914. {
  915. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  916. /* We need to construct preferred input timings based on our
  917. * output timings. To do that, we have to set the output
  918. * timings, even though this isn't really the right place in
  919. * the sequence to do it. Oh well.
  920. */
  921. if (intel_sdvo->is_tv) {
  922. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  923. return false;
  924. if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
  925. return false;
  926. } else if (intel_sdvo->is_lvds) {
  927. drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
  928. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  929. intel_sdvo->sdvo_lvds_fixed_mode))
  930. return false;
  931. if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
  932. return false;
  933. }
  934. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  935. * SDVO device will be told of the multiplier during mode_set.
  936. */
  937. adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
  938. return true;
  939. }
  940. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  941. struct drm_display_mode *mode,
  942. struct drm_display_mode *adjusted_mode)
  943. {
  944. struct drm_device *dev = encoder->dev;
  945. struct drm_i915_private *dev_priv = dev->dev_private;
  946. struct drm_crtc *crtc = encoder->crtc;
  947. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  948. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  949. u32 sdvox = 0;
  950. int sdvo_pixel_multiply, rate;
  951. struct intel_sdvo_in_out_map in_out;
  952. struct intel_sdvo_dtd input_dtd;
  953. if (!mode)
  954. return;
  955. /* First, set the input mapping for the first input to our controlled
  956. * output. This is only correct if we're a single-input device, in
  957. * which case the first input is the output from the appropriate SDVO
  958. * channel on the motherboard. In a two-input device, the first input
  959. * will be SDVOB and the second SDVOC.
  960. */
  961. in_out.in0 = intel_sdvo->attached_output;
  962. in_out.in1 = 0;
  963. if (!intel_sdvo_set_value(intel_sdvo,
  964. SDVO_CMD_SET_IN_OUT_MAP,
  965. &in_out, sizeof(in_out)))
  966. return;
  967. if (intel_sdvo->is_hdmi) {
  968. if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
  969. return;
  970. sdvox |= SDVO_AUDIO_ENABLE;
  971. }
  972. /* We have tried to get input timing in mode_fixup, and filled into
  973. adjusted_mode */
  974. if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
  975. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  976. input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
  977. } else
  978. intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
  979. /* If it's a TV, we already set the output timing in mode_fixup.
  980. * Otherwise, the output timing is equal to the input timing.
  981. */
  982. if (!intel_sdvo->is_tv && !intel_sdvo->is_lvds) {
  983. /* Set the output timing to the screen */
  984. if (!intel_sdvo_set_target_output(intel_sdvo,
  985. intel_sdvo->attached_output))
  986. return;
  987. if (!intel_sdvo_set_output_timing(intel_sdvo, &input_dtd))
  988. return;
  989. }
  990. /* Set the input timing to the screen. Assume always input 0. */
  991. if (!intel_sdvo_set_target_input(intel_sdvo))
  992. return;
  993. if (intel_sdvo->is_tv) {
  994. if (!intel_sdvo_set_tv_format(intel_sdvo))
  995. return;
  996. }
  997. /* We would like to use intel_sdvo_create_preferred_input_timing() to
  998. * provide the device with a timing it can support, if it supports that
  999. * feature. However, presumably we would need to adjust the CRTC to
  1000. * output the preferred timing, and we don't support that currently.
  1001. */
  1002. #if 0
  1003. success = intel_sdvo_create_preferred_input_timing(encoder, clock,
  1004. width, height);
  1005. if (success) {
  1006. struct intel_sdvo_dtd *input_dtd;
  1007. intel_sdvo_get_preferred_input_timing(encoder, &input_dtd);
  1008. intel_sdvo_set_input_timing(encoder, &input_dtd);
  1009. }
  1010. #else
  1011. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  1012. return;
  1013. #endif
  1014. sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
  1015. switch (sdvo_pixel_multiply) {
  1016. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  1017. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  1018. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  1019. }
  1020. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  1021. return;
  1022. /* Set the SDVO control regs. */
  1023. if (IS_I965G(dev)) {
  1024. sdvox |= SDVO_BORDER_ENABLE;
  1025. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  1026. sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  1027. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  1028. sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  1029. } else {
  1030. sdvox |= I915_READ(intel_sdvo->sdvo_reg);
  1031. switch (intel_sdvo->sdvo_reg) {
  1032. case SDVOB:
  1033. sdvox &= SDVOB_PRESERVE_MASK;
  1034. break;
  1035. case SDVOC:
  1036. sdvox &= SDVOC_PRESERVE_MASK;
  1037. break;
  1038. }
  1039. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1040. }
  1041. if (intel_crtc->pipe == 1)
  1042. sdvox |= SDVO_PIPE_B_SELECT;
  1043. if (IS_I965G(dev)) {
  1044. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1045. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1046. /* done in crtc_mode_set as it lives inside the dpll register */
  1047. } else {
  1048. sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  1049. }
  1050. if (intel_sdvo->sdvo_flags & SDVO_NEED_TO_STALL)
  1051. sdvox |= SDVO_STALL_SELECT;
  1052. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  1053. }
  1054. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  1055. {
  1056. struct drm_device *dev = encoder->dev;
  1057. struct drm_i915_private *dev_priv = dev->dev_private;
  1058. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1059. u32 temp;
  1060. if (mode != DRM_MODE_DPMS_ON) {
  1061. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1062. if (0)
  1063. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1064. if (mode == DRM_MODE_DPMS_OFF) {
  1065. temp = I915_READ(intel_sdvo->sdvo_reg);
  1066. if ((temp & SDVO_ENABLE) != 0) {
  1067. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1068. }
  1069. }
  1070. } else {
  1071. bool input1, input2;
  1072. int i;
  1073. u8 status;
  1074. temp = I915_READ(intel_sdvo->sdvo_reg);
  1075. if ((temp & SDVO_ENABLE) == 0)
  1076. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1077. for (i = 0; i < 2; i++)
  1078. intel_wait_for_vblank(dev);
  1079. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1080. /* Warn if the device reported failure to sync.
  1081. * A lot of SDVO devices fail to notify of sync, but it's
  1082. * a given it the status is a success, we succeeded.
  1083. */
  1084. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1085. DRM_DEBUG_KMS("First %s output reported failure to "
  1086. "sync\n", SDVO_NAME(intel_sdvo));
  1087. }
  1088. if (0)
  1089. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1090. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1091. }
  1092. return;
  1093. }
  1094. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1095. struct drm_display_mode *mode)
  1096. {
  1097. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1098. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1099. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1100. return MODE_NO_DBLESCAN;
  1101. if (intel_sdvo->pixel_clock_min > mode->clock)
  1102. return MODE_CLOCK_LOW;
  1103. if (intel_sdvo->pixel_clock_max < mode->clock)
  1104. return MODE_CLOCK_HIGH;
  1105. if (intel_sdvo->is_lvds == true) {
  1106. if (intel_sdvo->sdvo_lvds_fixed_mode == NULL)
  1107. return MODE_PANEL;
  1108. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1109. return MODE_PANEL;
  1110. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1111. return MODE_PANEL;
  1112. }
  1113. return MODE_OK;
  1114. }
  1115. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1116. {
  1117. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
  1118. }
  1119. /* No use! */
  1120. #if 0
  1121. struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1122. {
  1123. struct drm_connector *connector = NULL;
  1124. struct intel_sdvo *iout = NULL;
  1125. struct intel_sdvo *sdvo;
  1126. /* find the sdvo connector */
  1127. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1128. iout = to_intel_sdvo(connector);
  1129. if (iout->type != INTEL_OUTPUT_SDVO)
  1130. continue;
  1131. sdvo = iout->dev_priv;
  1132. if (sdvo->sdvo_reg == SDVOB && sdvoB)
  1133. return connector;
  1134. if (sdvo->sdvo_reg == SDVOC && !sdvoB)
  1135. return connector;
  1136. }
  1137. return NULL;
  1138. }
  1139. int intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1140. {
  1141. u8 response[2];
  1142. u8 status;
  1143. struct intel_sdvo *intel_sdvo;
  1144. DRM_DEBUG_KMS("\n");
  1145. if (!connector)
  1146. return 0;
  1147. intel_sdvo = to_intel_sdvo(connector);
  1148. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1149. &response, 2) && response[0];
  1150. }
  1151. void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1152. {
  1153. u8 response[2];
  1154. u8 status;
  1155. struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
  1156. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1157. intel_sdvo_read_response(intel_sdvo, &response, 2);
  1158. if (on) {
  1159. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1160. status = intel_sdvo_read_response(intel_sdvo, &response, 2);
  1161. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1162. } else {
  1163. response[0] = 0;
  1164. response[1] = 0;
  1165. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1166. }
  1167. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1168. intel_sdvo_read_response(intel_sdvo, &response, 2);
  1169. }
  1170. #endif
  1171. static bool
  1172. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1173. {
  1174. int caps = 0;
  1175. if (intel_sdvo->caps.output_flags &
  1176. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
  1177. caps++;
  1178. if (intel_sdvo->caps.output_flags &
  1179. (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
  1180. caps++;
  1181. if (intel_sdvo->caps.output_flags &
  1182. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
  1183. caps++;
  1184. if (intel_sdvo->caps.output_flags &
  1185. (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
  1186. caps++;
  1187. if (intel_sdvo->caps.output_flags &
  1188. (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
  1189. caps++;
  1190. if (intel_sdvo->caps.output_flags &
  1191. (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
  1192. caps++;
  1193. if (intel_sdvo->caps.output_flags &
  1194. (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
  1195. caps++;
  1196. return (caps > 1);
  1197. }
  1198. static struct drm_connector *
  1199. intel_find_analog_connector(struct drm_device *dev)
  1200. {
  1201. struct drm_connector *connector;
  1202. struct drm_encoder *encoder;
  1203. struct intel_sdvo *intel_sdvo;
  1204. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1205. intel_sdvo = enc_to_intel_sdvo(encoder);
  1206. if (intel_sdvo->base.type == INTEL_OUTPUT_ANALOG) {
  1207. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1208. if (encoder == intel_attached_encoder(connector))
  1209. return connector;
  1210. }
  1211. }
  1212. }
  1213. return NULL;
  1214. }
  1215. static int
  1216. intel_analog_is_connected(struct drm_device *dev)
  1217. {
  1218. struct drm_connector *analog_connector;
  1219. analog_connector = intel_find_analog_connector(dev);
  1220. if (!analog_connector)
  1221. return false;
  1222. if (analog_connector->funcs->detect(analog_connector) ==
  1223. connector_status_disconnected)
  1224. return false;
  1225. return true;
  1226. }
  1227. enum drm_connector_status
  1228. intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1229. {
  1230. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1231. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1232. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1233. enum drm_connector_status status = connector_status_connected;
  1234. struct edid *edid = NULL;
  1235. edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
  1236. /* This is only applied to SDVO cards with multiple outputs */
  1237. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1238. uint8_t saved_ddc, temp_ddc;
  1239. saved_ddc = intel_sdvo->ddc_bus;
  1240. temp_ddc = intel_sdvo->ddc_bus >> 1;
  1241. /*
  1242. * Don't use the 1 as the argument of DDC bus switch to get
  1243. * the EDID. It is used for SDVO SPD ROM.
  1244. */
  1245. while(temp_ddc > 1) {
  1246. intel_sdvo->ddc_bus = temp_ddc;
  1247. edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
  1248. if (edid) {
  1249. /*
  1250. * When we can get the EDID, maybe it is the
  1251. * correct DDC bus. Update it.
  1252. */
  1253. intel_sdvo->ddc_bus = temp_ddc;
  1254. break;
  1255. }
  1256. temp_ddc >>= 1;
  1257. }
  1258. if (edid == NULL)
  1259. intel_sdvo->ddc_bus = saved_ddc;
  1260. }
  1261. /* when there is no edid and no monitor is connected with VGA
  1262. * port, try to use the CRT ddc to read the EDID for DVI-connector
  1263. */
  1264. if (edid == NULL && intel_sdvo->analog_ddc_bus &&
  1265. !intel_analog_is_connected(connector->dev))
  1266. edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
  1267. if (edid != NULL) {
  1268. bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1269. bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
  1270. /* DDC bus is shared, match EDID to connector type */
  1271. if (is_digital && need_digital)
  1272. intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
  1273. else if (is_digital != need_digital)
  1274. status = connector_status_disconnected;
  1275. connector->display_info.raw_edid = NULL;
  1276. } else
  1277. status = connector_status_disconnected;
  1278. kfree(edid);
  1279. return status;
  1280. }
  1281. static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
  1282. {
  1283. uint16_t response;
  1284. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1285. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1286. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1287. enum drm_connector_status ret;
  1288. if (!intel_sdvo_write_cmd(intel_sdvo,
  1289. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1290. return connector_status_unknown;
  1291. if (intel_sdvo->is_tv) {
  1292. /* add 30ms delay when the output type is SDVO-TV */
  1293. mdelay(30);
  1294. }
  1295. if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
  1296. return connector_status_unknown;
  1297. DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
  1298. if (response == 0)
  1299. return connector_status_disconnected;
  1300. intel_sdvo->attached_output = response;
  1301. if ((intel_sdvo_connector->output_flag & response) == 0)
  1302. ret = connector_status_disconnected;
  1303. else if (response & SDVO_TMDS_MASK)
  1304. ret = intel_sdvo_hdmi_sink_detect(connector);
  1305. else
  1306. ret = connector_status_connected;
  1307. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1308. if (ret == connector_status_connected) {
  1309. intel_sdvo->is_tv = false;
  1310. intel_sdvo->is_lvds = false;
  1311. intel_sdvo->base.needs_tv_clock = false;
  1312. if (response & SDVO_TV_MASK) {
  1313. intel_sdvo->is_tv = true;
  1314. intel_sdvo->base.needs_tv_clock = true;
  1315. }
  1316. if (response & SDVO_LVDS_MASK)
  1317. intel_sdvo->is_lvds = true;
  1318. }
  1319. return ret;
  1320. }
  1321. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1322. {
  1323. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1324. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1325. int num_modes;
  1326. /* set the bus switch and get the modes */
  1327. num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
  1328. /*
  1329. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1330. * link between analog and digital outputs. So, if the regular SDVO
  1331. * DDC fails, check to see if the analog output is disconnected, in
  1332. * which case we'll look there for the digital DDC data.
  1333. */
  1334. if (num_modes == 0 &&
  1335. intel_sdvo->analog_ddc_bus &&
  1336. !intel_analog_is_connected(connector->dev)) {
  1337. /* Switch to the analog ddc bus and try that
  1338. */
  1339. (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
  1340. }
  1341. }
  1342. /*
  1343. * Set of SDVO TV modes.
  1344. * Note! This is in reply order (see loop in get_tv_modes).
  1345. * XXX: all 60Hz refresh?
  1346. */
  1347. struct drm_display_mode sdvo_tv_modes[] = {
  1348. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1349. 416, 0, 200, 201, 232, 233, 0,
  1350. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1351. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1352. 416, 0, 240, 241, 272, 273, 0,
  1353. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1354. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1355. 496, 0, 300, 301, 332, 333, 0,
  1356. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1357. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1358. 736, 0, 350, 351, 382, 383, 0,
  1359. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1360. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1361. 736, 0, 400, 401, 432, 433, 0,
  1362. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1363. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1364. 736, 0, 480, 481, 512, 513, 0,
  1365. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1366. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1367. 800, 0, 480, 481, 512, 513, 0,
  1368. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1369. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1370. 800, 0, 576, 577, 608, 609, 0,
  1371. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1372. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1373. 816, 0, 350, 351, 382, 383, 0,
  1374. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1375. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1376. 816, 0, 400, 401, 432, 433, 0,
  1377. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1378. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1379. 816, 0, 480, 481, 512, 513, 0,
  1380. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1381. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1382. 816, 0, 540, 541, 572, 573, 0,
  1383. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1384. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1385. 816, 0, 576, 577, 608, 609, 0,
  1386. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1387. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1388. 864, 0, 576, 577, 608, 609, 0,
  1389. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1390. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1391. 896, 0, 600, 601, 632, 633, 0,
  1392. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1393. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1394. 928, 0, 624, 625, 656, 657, 0,
  1395. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1396. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1397. 1016, 0, 766, 767, 798, 799, 0,
  1398. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1399. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1400. 1120, 0, 768, 769, 800, 801, 0,
  1401. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1402. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1403. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1404. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1405. };
  1406. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1407. {
  1408. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1409. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1410. struct intel_sdvo_sdtv_resolution_request tv_res;
  1411. uint32_t reply = 0, format_map = 0;
  1412. int i;
  1413. /* Read the list of supported input resolutions for the selected TV
  1414. * format.
  1415. */
  1416. format_map = 1 << intel_sdvo->tv_format_index;
  1417. memcpy(&tv_res, &format_map,
  1418. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1419. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1420. return;
  1421. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1422. if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1423. &tv_res, sizeof(tv_res)))
  1424. return;
  1425. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1426. return;
  1427. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1428. if (reply & (1 << i)) {
  1429. struct drm_display_mode *nmode;
  1430. nmode = drm_mode_duplicate(connector->dev,
  1431. &sdvo_tv_modes[i]);
  1432. if (nmode)
  1433. drm_mode_probed_add(connector, nmode);
  1434. }
  1435. }
  1436. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1437. {
  1438. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1439. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1440. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1441. struct drm_display_mode *newmode;
  1442. /*
  1443. * Attempt to get the mode list from DDC.
  1444. * Assume that the preferred modes are
  1445. * arranged in priority order.
  1446. */
  1447. intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
  1448. if (list_empty(&connector->probed_modes) == false)
  1449. goto end;
  1450. /* Fetch modes from VBT */
  1451. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1452. newmode = drm_mode_duplicate(connector->dev,
  1453. dev_priv->sdvo_lvds_vbt_mode);
  1454. if (newmode != NULL) {
  1455. /* Guarantee the mode is preferred */
  1456. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1457. DRM_MODE_TYPE_DRIVER);
  1458. drm_mode_probed_add(connector, newmode);
  1459. }
  1460. }
  1461. end:
  1462. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1463. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1464. intel_sdvo->sdvo_lvds_fixed_mode =
  1465. drm_mode_duplicate(connector->dev, newmode);
  1466. break;
  1467. }
  1468. }
  1469. }
  1470. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1471. {
  1472. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1473. if (IS_TV(intel_sdvo_connector))
  1474. intel_sdvo_get_tv_modes(connector);
  1475. else if (IS_LVDS(intel_sdvo_connector))
  1476. intel_sdvo_get_lvds_modes(connector);
  1477. else
  1478. intel_sdvo_get_ddc_modes(connector);
  1479. return !list_empty(&connector->probed_modes);
  1480. }
  1481. static void
  1482. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1483. {
  1484. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1485. struct drm_device *dev = connector->dev;
  1486. if (intel_sdvo_connector->left)
  1487. drm_property_destroy(dev, intel_sdvo_connector->left);
  1488. if (intel_sdvo_connector->right)
  1489. drm_property_destroy(dev, intel_sdvo_connector->right);
  1490. if (intel_sdvo_connector->top)
  1491. drm_property_destroy(dev, intel_sdvo_connector->top);
  1492. if (intel_sdvo_connector->bottom)
  1493. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1494. if (intel_sdvo_connector->hpos)
  1495. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1496. if (intel_sdvo_connector->vpos)
  1497. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1498. if (intel_sdvo_connector->saturation)
  1499. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1500. if (intel_sdvo_connector->contrast)
  1501. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1502. if (intel_sdvo_connector->hue)
  1503. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1504. if (intel_sdvo_connector->sharpness)
  1505. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1506. if (intel_sdvo_connector->flicker_filter)
  1507. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1508. if (intel_sdvo_connector->flicker_filter_2d)
  1509. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1510. if (intel_sdvo_connector->flicker_filter_adaptive)
  1511. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1512. if (intel_sdvo_connector->tv_luma_filter)
  1513. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1514. if (intel_sdvo_connector->tv_chroma_filter)
  1515. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1516. if (intel_sdvo_connector->dot_crawl)
  1517. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1518. if (intel_sdvo_connector->brightness)
  1519. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1520. }
  1521. static void intel_sdvo_destroy(struct drm_connector *connector)
  1522. {
  1523. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1524. if (intel_sdvo_connector->tv_format)
  1525. drm_property_destroy(connector->dev,
  1526. intel_sdvo_connector->tv_format);
  1527. intel_sdvo_destroy_enhance_property(connector);
  1528. drm_sysfs_connector_remove(connector);
  1529. drm_connector_cleanup(connector);
  1530. kfree(connector);
  1531. }
  1532. static int
  1533. intel_sdvo_set_property(struct drm_connector *connector,
  1534. struct drm_property *property,
  1535. uint64_t val)
  1536. {
  1537. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1538. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1539. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1540. uint16_t temp_value;
  1541. uint8_t cmd;
  1542. int ret;
  1543. ret = drm_connector_property_set_value(connector, property, val);
  1544. if (ret)
  1545. return ret;
  1546. #define CHECK_PROPERTY(name, NAME) \
  1547. if (intel_sdvo_connector->name == property) { \
  1548. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1549. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1550. cmd = SDVO_CMD_SET_##NAME; \
  1551. intel_sdvo_connector->cur_##name = temp_value; \
  1552. goto set_value; \
  1553. }
  1554. if (property == intel_sdvo_connector->tv_format) {
  1555. if (val >= TV_FORMAT_NUM)
  1556. return -EINVAL;
  1557. if (intel_sdvo->tv_format_index ==
  1558. intel_sdvo_connector->tv_format_supported[val])
  1559. return 0;
  1560. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1561. goto done;
  1562. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1563. temp_value = val;
  1564. if (intel_sdvo_connector->left == property) {
  1565. drm_connector_property_set_value(connector,
  1566. intel_sdvo_connector->right, val);
  1567. if (intel_sdvo_connector->left_margin == temp_value)
  1568. return 0;
  1569. intel_sdvo_connector->left_margin = temp_value;
  1570. intel_sdvo_connector->right_margin = temp_value;
  1571. temp_value = intel_sdvo_connector->max_hscan -
  1572. intel_sdvo_connector->left_margin;
  1573. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1574. goto set_value;
  1575. } else if (intel_sdvo_connector->right == property) {
  1576. drm_connector_property_set_value(connector,
  1577. intel_sdvo_connector->left, val);
  1578. if (intel_sdvo_connector->right_margin == temp_value)
  1579. return 0;
  1580. intel_sdvo_connector->left_margin = temp_value;
  1581. intel_sdvo_connector->right_margin = temp_value;
  1582. temp_value = intel_sdvo_connector->max_hscan -
  1583. intel_sdvo_connector->left_margin;
  1584. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1585. goto set_value;
  1586. } else if (intel_sdvo_connector->top == property) {
  1587. drm_connector_property_set_value(connector,
  1588. intel_sdvo_connector->bottom, val);
  1589. if (intel_sdvo_connector->top_margin == temp_value)
  1590. return 0;
  1591. intel_sdvo_connector->top_margin = temp_value;
  1592. intel_sdvo_connector->bottom_margin = temp_value;
  1593. temp_value = intel_sdvo_connector->max_vscan -
  1594. intel_sdvo_connector->top_margin;
  1595. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1596. goto set_value;
  1597. } else if (intel_sdvo_connector->bottom == property) {
  1598. drm_connector_property_set_value(connector,
  1599. intel_sdvo_connector->top, val);
  1600. if (intel_sdvo_connector->bottom_margin == temp_value)
  1601. return 0;
  1602. intel_sdvo_connector->top_margin = temp_value;
  1603. intel_sdvo_connector->bottom_margin = temp_value;
  1604. temp_value = intel_sdvo_connector->max_vscan -
  1605. intel_sdvo_connector->top_margin;
  1606. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1607. goto set_value;
  1608. }
  1609. CHECK_PROPERTY(hpos, HPOS)
  1610. CHECK_PROPERTY(vpos, VPOS)
  1611. CHECK_PROPERTY(saturation, SATURATION)
  1612. CHECK_PROPERTY(contrast, CONTRAST)
  1613. CHECK_PROPERTY(hue, HUE)
  1614. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1615. CHECK_PROPERTY(sharpness, SHARPNESS)
  1616. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1617. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1618. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1619. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1620. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1621. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1622. }
  1623. return -EINVAL; /* unknown property */
  1624. set_value:
  1625. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1626. return -EIO;
  1627. done:
  1628. if (encoder->crtc) {
  1629. struct drm_crtc *crtc = encoder->crtc;
  1630. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1631. crtc->y, crtc->fb);
  1632. }
  1633. return 0;
  1634. #undef CHECK_PROPERTY
  1635. }
  1636. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1637. .dpms = intel_sdvo_dpms,
  1638. .mode_fixup = intel_sdvo_mode_fixup,
  1639. .prepare = intel_encoder_prepare,
  1640. .mode_set = intel_sdvo_mode_set,
  1641. .commit = intel_encoder_commit,
  1642. };
  1643. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1644. .dpms = drm_helper_connector_dpms,
  1645. .detect = intel_sdvo_detect,
  1646. .fill_modes = drm_helper_probe_single_connector_modes,
  1647. .set_property = intel_sdvo_set_property,
  1648. .destroy = intel_sdvo_destroy,
  1649. };
  1650. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1651. .get_modes = intel_sdvo_get_modes,
  1652. .mode_valid = intel_sdvo_mode_valid,
  1653. .best_encoder = intel_attached_encoder,
  1654. };
  1655. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1656. {
  1657. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1658. if (intel_sdvo->analog_ddc_bus)
  1659. intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
  1660. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1661. drm_mode_destroy(encoder->dev,
  1662. intel_sdvo->sdvo_lvds_fixed_mode);
  1663. intel_encoder_destroy(encoder);
  1664. }
  1665. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1666. .destroy = intel_sdvo_enc_destroy,
  1667. };
  1668. /**
  1669. * Choose the appropriate DDC bus for control bus switch command for this
  1670. * SDVO output based on the controlled output.
  1671. *
  1672. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1673. * outputs, then LVDS outputs.
  1674. */
  1675. static void
  1676. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1677. struct intel_sdvo *sdvo, u32 reg)
  1678. {
  1679. struct sdvo_device_mapping *mapping;
  1680. if (IS_SDVOB(reg))
  1681. mapping = &(dev_priv->sdvo_mappings[0]);
  1682. else
  1683. mapping = &(dev_priv->sdvo_mappings[1]);
  1684. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1685. }
  1686. static bool
  1687. intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
  1688. {
  1689. return intel_sdvo_set_target_output(intel_sdvo,
  1690. device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
  1691. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
  1692. &intel_sdvo->is_hdmi, 1);
  1693. }
  1694. static struct intel_sdvo *
  1695. intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
  1696. {
  1697. struct drm_device *dev = chan->drm_dev;
  1698. struct drm_encoder *encoder;
  1699. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1700. struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
  1701. if (intel_sdvo->base.ddc_bus == &chan->adapter)
  1702. return intel_sdvo;
  1703. }
  1704. return NULL;
  1705. }
  1706. static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
  1707. struct i2c_msg msgs[], int num)
  1708. {
  1709. struct intel_sdvo *intel_sdvo;
  1710. struct i2c_algo_bit_data *algo_data;
  1711. const struct i2c_algorithm *algo;
  1712. algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
  1713. intel_sdvo =
  1714. intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
  1715. (algo_data->data));
  1716. if (intel_sdvo == NULL)
  1717. return -EINVAL;
  1718. algo = intel_sdvo->base.i2c_bus->algo;
  1719. intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
  1720. return algo->master_xfer(i2c_adap, msgs, num);
  1721. }
  1722. static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
  1723. .master_xfer = intel_sdvo_master_xfer,
  1724. };
  1725. static u8
  1726. intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1727. {
  1728. struct drm_i915_private *dev_priv = dev->dev_private;
  1729. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1730. if (IS_SDVOB(sdvo_reg)) {
  1731. my_mapping = &dev_priv->sdvo_mappings[0];
  1732. other_mapping = &dev_priv->sdvo_mappings[1];
  1733. } else {
  1734. my_mapping = &dev_priv->sdvo_mappings[1];
  1735. other_mapping = &dev_priv->sdvo_mappings[0];
  1736. }
  1737. /* If the BIOS described our SDVO device, take advantage of it. */
  1738. if (my_mapping->slave_addr)
  1739. return my_mapping->slave_addr;
  1740. /* If the BIOS only described a different SDVO device, use the
  1741. * address that it isn't using.
  1742. */
  1743. if (other_mapping->slave_addr) {
  1744. if (other_mapping->slave_addr == 0x70)
  1745. return 0x72;
  1746. else
  1747. return 0x70;
  1748. }
  1749. /* No SDVO device info is found for another DVO port,
  1750. * so use mapping assumption we had before BIOS parsing.
  1751. */
  1752. if (IS_SDVOB(sdvo_reg))
  1753. return 0x70;
  1754. else
  1755. return 0x72;
  1756. }
  1757. static void
  1758. intel_sdvo_connector_init(struct drm_encoder *encoder,
  1759. struct drm_connector *connector)
  1760. {
  1761. drm_connector_init(encoder->dev, connector, &intel_sdvo_connector_funcs,
  1762. connector->connector_type);
  1763. drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
  1764. connector->interlace_allowed = 0;
  1765. connector->doublescan_allowed = 0;
  1766. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  1767. drm_mode_connector_attach_encoder(connector, encoder);
  1768. drm_sysfs_connector_add(connector);
  1769. }
  1770. static bool
  1771. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1772. {
  1773. struct drm_encoder *encoder = &intel_sdvo->base.enc;
  1774. struct drm_connector *connector;
  1775. struct intel_connector *intel_connector;
  1776. struct intel_sdvo_connector *intel_sdvo_connector;
  1777. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1778. if (!intel_sdvo_connector)
  1779. return false;
  1780. if (device == 0) {
  1781. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1782. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1783. } else if (device == 1) {
  1784. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1785. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1786. }
  1787. intel_connector = &intel_sdvo_connector->base;
  1788. connector = &intel_connector->base;
  1789. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1790. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1791. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1792. if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
  1793. && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
  1794. && intel_sdvo->is_hdmi) {
  1795. /* enable hdmi encoding mode if supported */
  1796. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  1797. intel_sdvo_set_colorimetry(intel_sdvo,
  1798. SDVO_COLORIMETRY_RGB256);
  1799. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1800. }
  1801. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1802. (1 << INTEL_ANALOG_CLONE_BIT));
  1803. intel_sdvo_connector_init(encoder, connector);
  1804. return true;
  1805. }
  1806. static bool
  1807. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1808. {
  1809. struct drm_encoder *encoder = &intel_sdvo->base.enc;
  1810. struct drm_connector *connector;
  1811. struct intel_connector *intel_connector;
  1812. struct intel_sdvo_connector *intel_sdvo_connector;
  1813. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1814. if (!intel_sdvo_connector)
  1815. return false;
  1816. intel_connector = &intel_sdvo_connector->base;
  1817. connector = &intel_connector->base;
  1818. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1819. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1820. intel_sdvo->controlled_output |= type;
  1821. intel_sdvo_connector->output_flag = type;
  1822. intel_sdvo->is_tv = true;
  1823. intel_sdvo->base.needs_tv_clock = true;
  1824. intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1825. intel_sdvo_connector_init(encoder, connector);
  1826. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1827. goto err;
  1828. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1829. goto err;
  1830. return true;
  1831. err:
  1832. intel_sdvo_destroy_enhance_property(connector);
  1833. kfree(intel_sdvo_connector);
  1834. return false;
  1835. }
  1836. static bool
  1837. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1838. {
  1839. struct drm_encoder *encoder = &intel_sdvo->base.enc;
  1840. struct drm_connector *connector;
  1841. struct intel_connector *intel_connector;
  1842. struct intel_sdvo_connector *intel_sdvo_connector;
  1843. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1844. if (!intel_sdvo_connector)
  1845. return false;
  1846. intel_connector = &intel_sdvo_connector->base;
  1847. connector = &intel_connector->base;
  1848. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1849. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1850. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1851. if (device == 0) {
  1852. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1853. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1854. } else if (device == 1) {
  1855. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1856. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1857. }
  1858. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1859. (1 << INTEL_ANALOG_CLONE_BIT));
  1860. intel_sdvo_connector_init(encoder, connector);
  1861. return true;
  1862. }
  1863. static bool
  1864. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  1865. {
  1866. struct drm_encoder *encoder = &intel_sdvo->base.enc;
  1867. struct drm_connector *connector;
  1868. struct intel_connector *intel_connector;
  1869. struct intel_sdvo_connector *intel_sdvo_connector;
  1870. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1871. if (!intel_sdvo_connector)
  1872. return false;
  1873. intel_connector = &intel_sdvo_connector->base;
  1874. connector = &intel_connector->base;
  1875. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1876. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1877. intel_sdvo->is_lvds = true;
  1878. if (device == 0) {
  1879. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1880. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1881. } else if (device == 1) {
  1882. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1883. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1884. }
  1885. intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1886. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1887. intel_sdvo_connector_init(encoder, connector);
  1888. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1889. goto err;
  1890. return true;
  1891. err:
  1892. intel_sdvo_destroy_enhance_property(connector);
  1893. kfree(intel_sdvo_connector);
  1894. return false;
  1895. }
  1896. static bool
  1897. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  1898. {
  1899. intel_sdvo->is_tv = false;
  1900. intel_sdvo->base.needs_tv_clock = false;
  1901. intel_sdvo->is_lvds = false;
  1902. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1903. if (flags & SDVO_OUTPUT_TMDS0)
  1904. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  1905. return false;
  1906. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1907. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  1908. return false;
  1909. /* TV has no XXX1 function block */
  1910. if (flags & SDVO_OUTPUT_SVID0)
  1911. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  1912. return false;
  1913. if (flags & SDVO_OUTPUT_CVBS0)
  1914. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  1915. return false;
  1916. if (flags & SDVO_OUTPUT_RGB0)
  1917. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  1918. return false;
  1919. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1920. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  1921. return false;
  1922. if (flags & SDVO_OUTPUT_LVDS0)
  1923. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  1924. return false;
  1925. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1926. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  1927. return false;
  1928. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1929. unsigned char bytes[2];
  1930. intel_sdvo->controlled_output = 0;
  1931. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  1932. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1933. SDVO_NAME(intel_sdvo),
  1934. bytes[0], bytes[1]);
  1935. return false;
  1936. }
  1937. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
  1938. return true;
  1939. }
  1940. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  1941. struct intel_sdvo_connector *intel_sdvo_connector,
  1942. int type)
  1943. {
  1944. struct drm_device *dev = intel_sdvo->base.enc.dev;
  1945. struct intel_sdvo_tv_format format;
  1946. uint32_t format_map, i;
  1947. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  1948. return false;
  1949. if (!intel_sdvo_get_value(intel_sdvo,
  1950. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1951. &format, sizeof(format)))
  1952. return false;
  1953. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1954. if (format_map == 0)
  1955. return false;
  1956. intel_sdvo_connector->format_supported_num = 0;
  1957. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1958. if (format_map & (1 << i))
  1959. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  1960. intel_sdvo_connector->tv_format =
  1961. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1962. "mode", intel_sdvo_connector->format_supported_num);
  1963. if (!intel_sdvo_connector->tv_format)
  1964. return false;
  1965. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  1966. drm_property_add_enum(
  1967. intel_sdvo_connector->tv_format, i,
  1968. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  1969. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  1970. drm_connector_attach_property(&intel_sdvo_connector->base.base,
  1971. intel_sdvo_connector->tv_format, 0);
  1972. return true;
  1973. }
  1974. #define ENHANCEMENT(name, NAME) do { \
  1975. if (enhancements.name) { \
  1976. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1977. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1978. return false; \
  1979. intel_sdvo_connector->max_##name = data_value[0]; \
  1980. intel_sdvo_connector->cur_##name = response; \
  1981. intel_sdvo_connector->name = \
  1982. drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
  1983. if (!intel_sdvo_connector->name) return false; \
  1984. intel_sdvo_connector->name->values[0] = 0; \
  1985. intel_sdvo_connector->name->values[1] = data_value[0]; \
  1986. drm_connector_attach_property(connector, \
  1987. intel_sdvo_connector->name, \
  1988. intel_sdvo_connector->cur_##name); \
  1989. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1990. data_value[0], data_value[1], response); \
  1991. } \
  1992. } while(0)
  1993. static bool
  1994. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  1995. struct intel_sdvo_connector *intel_sdvo_connector,
  1996. struct intel_sdvo_enhancements_reply enhancements)
  1997. {
  1998. struct drm_device *dev = intel_sdvo->base.enc.dev;
  1999. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2000. uint16_t response, data_value[2];
  2001. /* when horizontal overscan is supported, Add the left/right property */
  2002. if (enhancements.overscan_h) {
  2003. if (!intel_sdvo_get_value(intel_sdvo,
  2004. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2005. &data_value, 4))
  2006. return false;
  2007. if (!intel_sdvo_get_value(intel_sdvo,
  2008. SDVO_CMD_GET_OVERSCAN_H,
  2009. &response, 2))
  2010. return false;
  2011. intel_sdvo_connector->max_hscan = data_value[0];
  2012. intel_sdvo_connector->left_margin = data_value[0] - response;
  2013. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2014. intel_sdvo_connector->left =
  2015. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2016. "left_margin", 2);
  2017. if (!intel_sdvo_connector->left)
  2018. return false;
  2019. intel_sdvo_connector->left->values[0] = 0;
  2020. intel_sdvo_connector->left->values[1] = data_value[0];
  2021. drm_connector_attach_property(connector,
  2022. intel_sdvo_connector->left,
  2023. intel_sdvo_connector->left_margin);
  2024. intel_sdvo_connector->right =
  2025. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2026. "right_margin", 2);
  2027. if (!intel_sdvo_connector->right)
  2028. return false;
  2029. intel_sdvo_connector->right->values[0] = 0;
  2030. intel_sdvo_connector->right->values[1] = data_value[0];
  2031. drm_connector_attach_property(connector,
  2032. intel_sdvo_connector->right,
  2033. intel_sdvo_connector->right_margin);
  2034. DRM_DEBUG_KMS("h_overscan: max %d, "
  2035. "default %d, current %d\n",
  2036. data_value[0], data_value[1], response);
  2037. }
  2038. if (enhancements.overscan_v) {
  2039. if (!intel_sdvo_get_value(intel_sdvo,
  2040. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2041. &data_value, 4))
  2042. return false;
  2043. if (!intel_sdvo_get_value(intel_sdvo,
  2044. SDVO_CMD_GET_OVERSCAN_V,
  2045. &response, 2))
  2046. return false;
  2047. intel_sdvo_connector->max_vscan = data_value[0];
  2048. intel_sdvo_connector->top_margin = data_value[0] - response;
  2049. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2050. intel_sdvo_connector->top =
  2051. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2052. "top_margin", 2);
  2053. if (!intel_sdvo_connector->top)
  2054. return false;
  2055. intel_sdvo_connector->top->values[0] = 0;
  2056. intel_sdvo_connector->top->values[1] = data_value[0];
  2057. drm_connector_attach_property(connector,
  2058. intel_sdvo_connector->top,
  2059. intel_sdvo_connector->top_margin);
  2060. intel_sdvo_connector->bottom =
  2061. drm_property_create(dev, DRM_MODE_PROP_RANGE,
  2062. "bottom_margin", 2);
  2063. if (!intel_sdvo_connector->bottom)
  2064. return false;
  2065. intel_sdvo_connector->bottom->values[0] = 0;
  2066. intel_sdvo_connector->bottom->values[1] = data_value[0];
  2067. drm_connector_attach_property(connector,
  2068. intel_sdvo_connector->bottom,
  2069. intel_sdvo_connector->bottom_margin);
  2070. DRM_DEBUG_KMS("v_overscan: max %d, "
  2071. "default %d, current %d\n",
  2072. data_value[0], data_value[1], response);
  2073. }
  2074. ENHANCEMENT(hpos, HPOS);
  2075. ENHANCEMENT(vpos, VPOS);
  2076. ENHANCEMENT(saturation, SATURATION);
  2077. ENHANCEMENT(contrast, CONTRAST);
  2078. ENHANCEMENT(hue, HUE);
  2079. ENHANCEMENT(sharpness, SHARPNESS);
  2080. ENHANCEMENT(brightness, BRIGHTNESS);
  2081. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2082. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2083. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2084. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2085. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2086. if (enhancements.dot_crawl) {
  2087. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2088. return false;
  2089. intel_sdvo_connector->max_dot_crawl = 1;
  2090. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2091. intel_sdvo_connector->dot_crawl =
  2092. drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
  2093. if (!intel_sdvo_connector->dot_crawl)
  2094. return false;
  2095. intel_sdvo_connector->dot_crawl->values[0] = 0;
  2096. intel_sdvo_connector->dot_crawl->values[1] = 1;
  2097. drm_connector_attach_property(connector,
  2098. intel_sdvo_connector->dot_crawl,
  2099. intel_sdvo_connector->cur_dot_crawl);
  2100. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2101. }
  2102. return true;
  2103. }
  2104. static bool
  2105. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2106. struct intel_sdvo_connector *intel_sdvo_connector,
  2107. struct intel_sdvo_enhancements_reply enhancements)
  2108. {
  2109. struct drm_device *dev = intel_sdvo->base.enc.dev;
  2110. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2111. uint16_t response, data_value[2];
  2112. ENHANCEMENT(brightness, BRIGHTNESS);
  2113. return true;
  2114. }
  2115. #undef ENHANCEMENT
  2116. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2117. struct intel_sdvo_connector *intel_sdvo_connector)
  2118. {
  2119. union {
  2120. struct intel_sdvo_enhancements_reply reply;
  2121. uint16_t response;
  2122. } enhancements;
  2123. if (!intel_sdvo_get_value(intel_sdvo,
  2124. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2125. &enhancements, sizeof(enhancements)))
  2126. return false;
  2127. if (enhancements.response == 0) {
  2128. DRM_DEBUG_KMS("No enhancement is supported\n");
  2129. return true;
  2130. }
  2131. if (IS_TV(intel_sdvo_connector))
  2132. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2133. else if(IS_LVDS(intel_sdvo_connector))
  2134. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2135. else
  2136. return true;
  2137. }
  2138. bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2139. {
  2140. struct drm_i915_private *dev_priv = dev->dev_private;
  2141. struct intel_encoder *intel_encoder;
  2142. struct intel_sdvo *intel_sdvo;
  2143. u8 ch[0x40];
  2144. int i;
  2145. u32 i2c_reg, ddc_reg, analog_ddc_reg;
  2146. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2147. if (!intel_sdvo)
  2148. return false;
  2149. intel_sdvo->sdvo_reg = sdvo_reg;
  2150. intel_encoder = &intel_sdvo->base;
  2151. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2152. if (HAS_PCH_SPLIT(dev)) {
  2153. i2c_reg = PCH_GPIOE;
  2154. ddc_reg = PCH_GPIOE;
  2155. analog_ddc_reg = PCH_GPIOA;
  2156. } else {
  2157. i2c_reg = GPIOE;
  2158. ddc_reg = GPIOE;
  2159. analog_ddc_reg = GPIOA;
  2160. }
  2161. /* setup the DDC bus. */
  2162. if (IS_SDVOB(sdvo_reg))
  2163. intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
  2164. else
  2165. intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
  2166. if (!intel_encoder->i2c_bus)
  2167. goto err_inteloutput;
  2168. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
  2169. /* Save the bit-banging i2c functionality for use by the DDC wrapper */
  2170. intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
  2171. /* Read the regs to test if we can talk to the device */
  2172. for (i = 0; i < 0x40; i++) {
  2173. if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
  2174. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2175. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2176. goto err_i2c;
  2177. }
  2178. }
  2179. /* setup the DDC bus. */
  2180. if (IS_SDVOB(sdvo_reg)) {
  2181. intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
  2182. intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
  2183. "SDVOB/VGA DDC BUS");
  2184. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2185. } else {
  2186. intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
  2187. intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
  2188. "SDVOC/VGA DDC BUS");
  2189. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2190. }
  2191. if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
  2192. goto err_i2c;
  2193. /* Wrap with our custom algo which switches to DDC mode */
  2194. intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
  2195. /* encoder type will be decided later */
  2196. drm_encoder_init(dev, &intel_encoder->enc, &intel_sdvo_enc_funcs, 0);
  2197. drm_encoder_helper_add(&intel_encoder->enc, &intel_sdvo_helper_funcs);
  2198. /* In default case sdvo lvds is false */
  2199. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2200. goto err_enc;
  2201. if (intel_sdvo_output_setup(intel_sdvo,
  2202. intel_sdvo->caps.output_flags) != true) {
  2203. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2204. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2205. goto err_enc;
  2206. }
  2207. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2208. /* Set the input timing to the screen. Assume always input 0. */
  2209. if (!intel_sdvo_set_target_input(intel_sdvo))
  2210. goto err_enc;
  2211. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2212. &intel_sdvo->pixel_clock_min,
  2213. &intel_sdvo->pixel_clock_max))
  2214. goto err_enc;
  2215. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2216. "clock range %dMHz - %dMHz, "
  2217. "input 1: %c, input 2: %c, "
  2218. "output 1: %c, output 2: %c\n",
  2219. SDVO_NAME(intel_sdvo),
  2220. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2221. intel_sdvo->caps.device_rev_id,
  2222. intel_sdvo->pixel_clock_min / 1000,
  2223. intel_sdvo->pixel_clock_max / 1000,
  2224. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2225. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2226. /* check currently supported outputs */
  2227. intel_sdvo->caps.output_flags &
  2228. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2229. intel_sdvo->caps.output_flags &
  2230. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2231. return true;
  2232. err_enc:
  2233. drm_encoder_cleanup(&intel_encoder->enc);
  2234. err_i2c:
  2235. if (intel_sdvo->analog_ddc_bus != NULL)
  2236. intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
  2237. if (intel_encoder->ddc_bus != NULL)
  2238. intel_i2c_destroy(intel_encoder->ddc_bus);
  2239. if (intel_encoder->i2c_bus != NULL)
  2240. intel_i2c_destroy(intel_encoder->i2c_bus);
  2241. err_inteloutput:
  2242. kfree(intel_sdvo);
  2243. return false;
  2244. }