mac.c 31 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. ****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../pci.h"
  31. #include "../usb.h"
  32. #include "../ps.h"
  33. #include "../cam.h"
  34. #include "reg.h"
  35. #include "def.h"
  36. #include "phy.h"
  37. #include "rf.h"
  38. #include "dm.h"
  39. #include "mac.h"
  40. #include "trx.h"
  41. #include <linux/module.h>
  42. /* macro to shorten lines */
  43. #define LINK_Q ui_link_quality
  44. #define RX_EVM rx_evm_percentage
  45. #define RX_SIGQ rx_mimo_signalquality
  46. void rtl92c_read_chip_version(struct ieee80211_hw *hw)
  47. {
  48. struct rtl_priv *rtlpriv = rtl_priv(hw);
  49. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  50. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  51. enum version_8192c chip_version = VERSION_UNKNOWN;
  52. const char *versionid;
  53. u32 value32;
  54. value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
  55. if (value32 & TRP_VAUX_EN) {
  56. chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
  57. VERSION_TEST_CHIP_88C;
  58. } else {
  59. /* Normal mass production chip. */
  60. chip_version = NORMAL_CHIP;
  61. chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
  62. chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
  63. /* RTL8723 with BT function. */
  64. chip_version |= ((value32 & BT_FUNC) ? CHIP_8723 : 0);
  65. if (IS_VENDOR_UMC(chip_version))
  66. chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
  67. CHIP_VENDOR_UMC_B_CUT : 0);
  68. if (IS_92C_SERIAL(chip_version)) {
  69. value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
  70. chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
  71. CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
  72. } else if (IS_8723_SERIES(chip_version)) {
  73. value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
  74. chip_version |= ((value32 & RF_RL_ID) ?
  75. CHIP_8723_DRV_REV : 0);
  76. }
  77. }
  78. rtlhal->version = (enum version_8192c)chip_version;
  79. pr_info("Chip version 0x%x\n", chip_version);
  80. switch (rtlhal->version) {
  81. case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
  82. versionid = "NORMAL_B_CHIP_92C";
  83. break;
  84. case VERSION_NORMAL_TSMC_CHIP_92C:
  85. versionid = "NORMAL_TSMC_CHIP_92C";
  86. break;
  87. case VERSION_NORMAL_TSMC_CHIP_88C:
  88. versionid = "NORMAL_TSMC_CHIP_88C";
  89. break;
  90. case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
  91. versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT";
  92. break;
  93. case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
  94. versionid = "NORMAL_UMC_CHIP_92C_A_CUT";
  95. break;
  96. case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
  97. versionid = "NORMAL_UMC_CHIP_88C_A_CUT";
  98. break;
  99. case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
  100. versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT";
  101. break;
  102. case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
  103. versionid = "NORMAL_UMC_CHIP_92C_B_CUT";
  104. break;
  105. case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
  106. versionid = "NORMAL_UMC_CHIP_88C_B_CUT";
  107. break;
  108. case VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT:
  109. versionid = "NORMAL_UMC_CHIP_8723_1T1R_A_CUT";
  110. break;
  111. case VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT:
  112. versionid = "NORMAL_UMC_CHIP_8723_1T1R_B_CUT";
  113. break;
  114. case VERSION_TEST_CHIP_92C:
  115. versionid = "TEST_CHIP_92C";
  116. break;
  117. case VERSION_TEST_CHIP_88C:
  118. versionid = "TEST_CHIP_88C";
  119. break;
  120. default:
  121. versionid = "UNKNOWN";
  122. break;
  123. }
  124. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  125. "Chip Version ID: %s\n", versionid);
  126. if (IS_92C_SERIAL(rtlhal->version))
  127. rtlphy->rf_type =
  128. (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
  129. else
  130. rtlphy->rf_type = RF_1T1R;
  131. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  132. "Chip RF Type: %s\n",
  133. rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
  134. if (get_rf_type(rtlphy) == RF_1T1R)
  135. rtlpriv->dm.rfpath_rxenable[0] = true;
  136. else
  137. rtlpriv->dm.rfpath_rxenable[0] =
  138. rtlpriv->dm.rfpath_rxenable[1] = true;
  139. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
  140. rtlhal->version);
  141. }
  142. /**
  143. * writeLLT - LLT table write access
  144. * @io: io callback
  145. * @address: LLT logical address.
  146. * @data: LLT data content
  147. *
  148. * Realtek hardware access function.
  149. *
  150. */
  151. bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
  152. {
  153. struct rtl_priv *rtlpriv = rtl_priv(hw);
  154. bool status = true;
  155. long count = 0;
  156. u32 value = _LLT_INIT_ADDR(address) |
  157. _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
  158. rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
  159. do {
  160. value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
  161. if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
  162. break;
  163. if (count > POLLING_LLT_THRESHOLD) {
  164. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  165. "Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n",
  166. address, _LLT_OP_VALUE(value));
  167. status = false;
  168. break;
  169. }
  170. } while (++count);
  171. return status;
  172. }
  173. /**
  174. * rtl92c_init_LLT_table - Init LLT table
  175. * @io: io callback
  176. * @boundary:
  177. *
  178. * Realtek hardware access function.
  179. *
  180. */
  181. bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
  182. {
  183. bool rst = true;
  184. u32 i;
  185. for (i = 0; i < (boundary - 1); i++) {
  186. rst = rtl92c_llt_write(hw, i , i + 1);
  187. if (true != rst) {
  188. pr_err("===> %s #1 fail\n", __func__);
  189. return rst;
  190. }
  191. }
  192. /* end of list */
  193. rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
  194. if (true != rst) {
  195. pr_err("===> %s #2 fail\n", __func__);
  196. return rst;
  197. }
  198. /* Make the other pages as ring buffer
  199. * This ring buffer is used as beacon buffer if we config this MAC
  200. * as two MAC transfer.
  201. * Otherwise used as local loopback buffer.
  202. */
  203. for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
  204. rst = rtl92c_llt_write(hw, i, (i + 1));
  205. if (true != rst) {
  206. pr_err("===> %s #3 fail\n", __func__);
  207. return rst;
  208. }
  209. }
  210. /* Let last entry point to the start entry of ring buffer */
  211. rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
  212. if (true != rst) {
  213. pr_err("===> %s #4 fail\n", __func__);
  214. return rst;
  215. }
  216. return rst;
  217. }
  218. void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
  219. u8 *p_macaddr, bool is_group, u8 enc_algo,
  220. bool is_wepkey, bool clear_all)
  221. {
  222. struct rtl_priv *rtlpriv = rtl_priv(hw);
  223. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  224. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  225. u8 *macaddr = p_macaddr;
  226. u32 entry_id = 0;
  227. bool is_pairwise = false;
  228. static u8 cam_const_addr[4][6] = {
  229. {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  230. {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
  231. {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
  232. {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
  233. };
  234. static u8 cam_const_broad[] = {
  235. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
  236. };
  237. if (clear_all) {
  238. u8 idx = 0;
  239. u8 cam_offset = 0;
  240. u8 clear_number = 5;
  241. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
  242. for (idx = 0; idx < clear_number; idx++) {
  243. rtl_cam_mark_invalid(hw, cam_offset + idx);
  244. rtl_cam_empty_entry(hw, cam_offset + idx);
  245. if (idx < 5) {
  246. memset(rtlpriv->sec.key_buf[idx], 0,
  247. MAX_KEY_LEN);
  248. rtlpriv->sec.key_len[idx] = 0;
  249. }
  250. }
  251. } else {
  252. switch (enc_algo) {
  253. case WEP40_ENCRYPTION:
  254. enc_algo = CAM_WEP40;
  255. break;
  256. case WEP104_ENCRYPTION:
  257. enc_algo = CAM_WEP104;
  258. break;
  259. case TKIP_ENCRYPTION:
  260. enc_algo = CAM_TKIP;
  261. break;
  262. case AESCCMP_ENCRYPTION:
  263. enc_algo = CAM_AES;
  264. break;
  265. default:
  266. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  267. "illegal switch case\n");
  268. enc_algo = CAM_TKIP;
  269. break;
  270. }
  271. if (is_wepkey || rtlpriv->sec.use_defaultkey) {
  272. macaddr = cam_const_addr[key_index];
  273. entry_id = key_index;
  274. } else {
  275. if (is_group) {
  276. macaddr = cam_const_broad;
  277. entry_id = key_index;
  278. } else {
  279. key_index = PAIRWISE_KEYIDX;
  280. entry_id = CAM_PAIRWISE_KEY_POSITION;
  281. is_pairwise = true;
  282. }
  283. }
  284. if (rtlpriv->sec.key_len[key_index] == 0) {
  285. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  286. "delete one entry\n");
  287. rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
  288. } else {
  289. RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
  290. "The insert KEY length is %d\n",
  291. rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
  292. RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
  293. "The insert KEY is %x %x\n",
  294. rtlpriv->sec.key_buf[0][0],
  295. rtlpriv->sec.key_buf[0][1]);
  296. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  297. "add one entry\n");
  298. if (is_pairwise) {
  299. RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
  300. "Pairwise Key content",
  301. rtlpriv->sec.pairwise_key,
  302. rtlpriv->sec.
  303. key_len[PAIRWISE_KEYIDX]);
  304. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  305. "set Pairwise key\n");
  306. rtl_cam_add_one_entry(hw, macaddr, key_index,
  307. entry_id, enc_algo,
  308. CAM_CONFIG_NO_USEDK,
  309. rtlpriv->sec.
  310. key_buf[key_index]);
  311. } else {
  312. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  313. "set group key\n");
  314. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  315. rtl_cam_add_one_entry(hw,
  316. rtlefuse->dev_addr,
  317. PAIRWISE_KEYIDX,
  318. CAM_PAIRWISE_KEY_POSITION,
  319. enc_algo,
  320. CAM_CONFIG_NO_USEDK,
  321. rtlpriv->sec.key_buf
  322. [entry_id]);
  323. }
  324. rtl_cam_add_one_entry(hw, macaddr, key_index,
  325. entry_id, enc_algo,
  326. CAM_CONFIG_NO_USEDK,
  327. rtlpriv->sec.key_buf[entry_id]);
  328. }
  329. }
  330. }
  331. }
  332. u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw)
  333. {
  334. struct rtl_priv *rtlpriv = rtl_priv(hw);
  335. return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS);
  336. }
  337. void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
  338. {
  339. struct rtl_priv *rtlpriv = rtl_priv(hw);
  340. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  341. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  342. struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
  343. if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
  344. rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
  345. 0xFFFFFFFF);
  346. rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
  347. 0xFFFFFFFF);
  348. } else {
  349. rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
  350. 0xFFFFFFFF);
  351. rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
  352. 0xFFFFFFFF);
  353. }
  354. }
  355. void rtl92c_init_interrupt(struct ieee80211_hw *hw)
  356. {
  357. rtl92c_enable_interrupt(hw);
  358. }
  359. void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
  360. {
  361. struct rtl_priv *rtlpriv = rtl_priv(hw);
  362. rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
  363. rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
  364. }
  365. void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
  366. {
  367. struct rtl_priv *rtlpriv = rtl_priv(hw);
  368. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  369. u32 u4b_ac_param;
  370. rtl92c_dm_init_edca_turbo(hw);
  371. u4b_ac_param = (u32) mac->ac[aci].aifs;
  372. u4b_ac_param |=
  373. ((u32) le16_to_cpu(mac->ac[aci].cw_min) & 0xF) <<
  374. AC_PARAM_ECW_MIN_OFFSET;
  375. u4b_ac_param |=
  376. ((u32) le16_to_cpu(mac->ac[aci].cw_max) & 0xF) <<
  377. AC_PARAM_ECW_MAX_OFFSET;
  378. u4b_ac_param |= (u32) le16_to_cpu(mac->ac[aci].tx_op) <<
  379. AC_PARAM_TXOP_OFFSET;
  380. RT_TRACE(rtlpriv, COMP_QOS, DBG_LOUD, "queue:%x, ac_param:%x\n",
  381. aci, u4b_ac_param);
  382. switch (aci) {
  383. case AC1_BK:
  384. rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
  385. break;
  386. case AC0_BE:
  387. rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
  388. break;
  389. case AC2_VI:
  390. rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
  391. break;
  392. case AC3_VO:
  393. rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
  394. break;
  395. default:
  396. RT_ASSERT(false, "invalid aci: %d !\n", aci);
  397. break;
  398. }
  399. }
  400. /*-------------------------------------------------------------------------
  401. * HW MAC Address
  402. *-------------------------------------------------------------------------*/
  403. void rtl92c_set_mac_addr(struct ieee80211_hw *hw, const u8 *addr)
  404. {
  405. u32 i;
  406. struct rtl_priv *rtlpriv = rtl_priv(hw);
  407. for (i = 0 ; i < ETH_ALEN ; i++)
  408. rtl_write_byte(rtlpriv, (REG_MACID + i), *(addr+i));
  409. RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
  410. "MAC Address: %02X-%02X-%02X-%02X-%02X-%02X\n",
  411. rtl_read_byte(rtlpriv, REG_MACID),
  412. rtl_read_byte(rtlpriv, REG_MACID+1),
  413. rtl_read_byte(rtlpriv, REG_MACID+2),
  414. rtl_read_byte(rtlpriv, REG_MACID+3),
  415. rtl_read_byte(rtlpriv, REG_MACID+4),
  416. rtl_read_byte(rtlpriv, REG_MACID+5));
  417. }
  418. void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size)
  419. {
  420. struct rtl_priv *rtlpriv = rtl_priv(hw);
  421. rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size);
  422. }
  423. int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
  424. {
  425. u8 value;
  426. struct rtl_priv *rtlpriv = rtl_priv(hw);
  427. switch (type) {
  428. case NL80211_IFTYPE_UNSPECIFIED:
  429. value = NT_NO_LINK;
  430. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  431. "Set Network type to NO LINK!\n");
  432. break;
  433. case NL80211_IFTYPE_ADHOC:
  434. value = NT_LINK_AD_HOC;
  435. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  436. "Set Network type to Ad Hoc!\n");
  437. break;
  438. case NL80211_IFTYPE_STATION:
  439. value = NT_LINK_AP;
  440. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  441. "Set Network type to STA!\n");
  442. break;
  443. case NL80211_IFTYPE_AP:
  444. value = NT_AS_AP;
  445. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  446. "Set Network type to AP!\n");
  447. break;
  448. default:
  449. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  450. "Network type %d not supported!\n", type);
  451. return -EOPNOTSUPP;
  452. }
  453. rtl_write_byte(rtlpriv, (REG_CR + 2), value);
  454. return 0;
  455. }
  456. void rtl92c_init_network_type(struct ieee80211_hw *hw)
  457. {
  458. rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED);
  459. }
  460. void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
  461. {
  462. u16 value16;
  463. u32 value32;
  464. struct rtl_priv *rtlpriv = rtl_priv(hw);
  465. /* Response Rate Set */
  466. value32 = rtl_read_dword(rtlpriv, REG_RRSR);
  467. value32 &= ~RATE_BITMAP_ALL;
  468. value32 |= RATE_RRSR_CCK_ONLY_1M;
  469. rtl_write_dword(rtlpriv, REG_RRSR, value32);
  470. /* SIFS (used in NAV) */
  471. value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
  472. rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16);
  473. /* Retry Limit */
  474. value16 = _LRL(0x30) | _SRL(0x30);
  475. rtl_write_dword(rtlpriv, REG_RL, value16);
  476. }
  477. void rtl92c_init_rate_fallback(struct ieee80211_hw *hw)
  478. {
  479. struct rtl_priv *rtlpriv = rtl_priv(hw);
  480. /* Set Data Auto Rate Fallback Retry Count register. */
  481. rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000);
  482. rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404);
  483. rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201);
  484. rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605);
  485. }
  486. static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
  487. u8 ctx_sifs)
  488. {
  489. struct rtl_priv *rtlpriv = rtl_priv(hw);
  490. rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs);
  491. rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs);
  492. }
  493. static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
  494. u8 ctx_sifs)
  495. {
  496. struct rtl_priv *rtlpriv = rtl_priv(hw);
  497. rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs);
  498. rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs);
  499. }
  500. void rtl92c_init_edca_param(struct ieee80211_hw *hw,
  501. u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
  502. {
  503. /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
  504. * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
  505. */
  506. u32 value;
  507. struct rtl_priv *rtlpriv = rtl_priv(hw);
  508. value = (u32)aifs;
  509. value |= ((u32)cw_min & 0xF) << 8;
  510. value |= ((u32)cw_max & 0xF) << 12;
  511. value |= (u32)txop << 16;
  512. /* 92C hardware register sequence is the same as queue number. */
  513. rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
  514. }
  515. void rtl92c_init_edca(struct ieee80211_hw *hw)
  516. {
  517. u16 value16;
  518. struct rtl_priv *rtlpriv = rtl_priv(hw);
  519. /* disable EDCCA count down, to reduce collison and retry */
  520. value16 = rtl_read_word(rtlpriv, REG_RD_CTRL);
  521. value16 |= DIS_EDCA_CNT_DWN;
  522. rtl_write_word(rtlpriv, REG_RD_CTRL, value16);
  523. /* Update SIFS timing. ??????????
  524. * pHalData->SifsTime = 0x0e0e0a0a; */
  525. rtl92c_set_cck_sifs(hw, 0xa, 0xa);
  526. rtl92c_set_ofdm_sifs(hw, 0xe, 0xe);
  527. /* Set CCK/OFDM SIFS to be 10us. */
  528. rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a);
  529. rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010);
  530. rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204);
  531. rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);
  532. /* TXOP */
  533. rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);
  534. rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);
  535. rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);
  536. rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);
  537. /* PIFS */
  538. rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
  539. /* AGGR BREAK TIME Register */
  540. rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
  541. rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
  542. rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02);
  543. rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02);
  544. }
  545. void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
  546. {
  547. struct rtl_priv *rtlpriv = rtl_priv(hw);
  548. rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
  549. rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
  550. /* init AMPDU aggregation number, tuning for Tx's TP, */
  551. rtl_write_word(rtlpriv, 0x4CA, 0x0708);
  552. }
  553. void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw, bool infra_mode)
  554. {
  555. struct rtl_priv *rtlpriv = rtl_priv(hw);
  556. rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
  557. }
  558. void rtl92c_init_rdg_setting(struct ieee80211_hw *hw)
  559. {
  560. struct rtl_priv *rtlpriv = rtl_priv(hw);
  561. rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF);
  562. rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
  563. rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
  564. }
  565. void rtl92c_init_retry_function(struct ieee80211_hw *hw)
  566. {
  567. u8 value8;
  568. struct rtl_priv *rtlpriv = rtl_priv(hw);
  569. value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL);
  570. value8 |= EN_AMPDU_RTY_NEW;
  571. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8);
  572. /* Set ACK timeout */
  573. rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
  574. }
  575. void rtl92c_init_beacon_parameters(struct ieee80211_hw *hw,
  576. enum version_8192c version)
  577. {
  578. struct rtl_priv *rtlpriv = rtl_priv(hw);
  579. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  580. rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);/* ms */
  581. rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/*ms*/
  582. rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
  583. if (IS_NORMAL_CHIP(rtlhal->version))
  584. rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
  585. else
  586. rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
  587. }
  588. void rtl92c_disable_fast_edca(struct ieee80211_hw *hw)
  589. {
  590. struct rtl_priv *rtlpriv = rtl_priv(hw);
  591. rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0);
  592. }
  593. void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T)
  594. {
  595. struct rtl_priv *rtlpriv = rtl_priv(hw);
  596. u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T;
  597. rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value);
  598. }
  599. u16 rtl92c_get_mgt_filter(struct ieee80211_hw *hw)
  600. {
  601. struct rtl_priv *rtlpriv = rtl_priv(hw);
  602. return rtl_read_word(rtlpriv, REG_RXFLTMAP0);
  603. }
  604. void rtl92c_set_mgt_filter(struct ieee80211_hw *hw, u16 filter)
  605. {
  606. struct rtl_priv *rtlpriv = rtl_priv(hw);
  607. rtl_write_word(rtlpriv, REG_RXFLTMAP0, filter);
  608. }
  609. u16 rtl92c_get_ctrl_filter(struct ieee80211_hw *hw)
  610. {
  611. struct rtl_priv *rtlpriv = rtl_priv(hw);
  612. return rtl_read_word(rtlpriv, REG_RXFLTMAP1);
  613. }
  614. void rtl92c_set_ctrl_filter(struct ieee80211_hw *hw, u16 filter)
  615. {
  616. struct rtl_priv *rtlpriv = rtl_priv(hw);
  617. rtl_write_word(rtlpriv, REG_RXFLTMAP1, filter);
  618. }
  619. u16 rtl92c_get_data_filter(struct ieee80211_hw *hw)
  620. {
  621. struct rtl_priv *rtlpriv = rtl_priv(hw);
  622. return rtl_read_word(rtlpriv, REG_RXFLTMAP2);
  623. }
  624. void rtl92c_set_data_filter(struct ieee80211_hw *hw, u16 filter)
  625. {
  626. struct rtl_priv *rtlpriv = rtl_priv(hw);
  627. rtl_write_word(rtlpriv, REG_RXFLTMAP2, filter);
  628. }
  629. /*==============================================================*/
  630. static u8 _rtl92c_query_rxpwrpercentage(char antpower)
  631. {
  632. if ((antpower <= -100) || (antpower >= 20))
  633. return 0;
  634. else if (antpower >= 0)
  635. return 100;
  636. else
  637. return 100 + antpower;
  638. }
  639. static u8 _rtl92c_evm_db_to_percentage(char value)
  640. {
  641. char ret_val;
  642. ret_val = value;
  643. if (ret_val >= 0)
  644. ret_val = 0;
  645. if (ret_val <= -33)
  646. ret_val = -33;
  647. ret_val = 0 - ret_val;
  648. ret_val *= 3;
  649. if (ret_val == 99)
  650. ret_val = 100;
  651. return ret_val;
  652. }
  653. static long _rtl92c_translate_todbm(struct ieee80211_hw *hw,
  654. u8 signal_strength_index)
  655. {
  656. long signal_power;
  657. signal_power = (long)((signal_strength_index + 1) >> 1);
  658. signal_power -= 95;
  659. return signal_power;
  660. }
  661. static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw,
  662. long currsig)
  663. {
  664. long retsig;
  665. if (currsig >= 61 && currsig <= 100)
  666. retsig = 90 + ((currsig - 60) / 4);
  667. else if (currsig >= 41 && currsig <= 60)
  668. retsig = 78 + ((currsig - 40) / 2);
  669. else if (currsig >= 31 && currsig <= 40)
  670. retsig = 66 + (currsig - 30);
  671. else if (currsig >= 21 && currsig <= 30)
  672. retsig = 54 + (currsig - 20);
  673. else if (currsig >= 5 && currsig <= 20)
  674. retsig = 42 + (((currsig - 5) * 2) / 3);
  675. else if (currsig == 4)
  676. retsig = 36;
  677. else if (currsig == 3)
  678. retsig = 27;
  679. else if (currsig == 2)
  680. retsig = 18;
  681. else if (currsig == 1)
  682. retsig = 9;
  683. else
  684. retsig = currsig;
  685. return retsig;
  686. }
  687. static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
  688. struct rtl_stats *pstats,
  689. struct rx_desc_92c *pdesc,
  690. struct rx_fwinfo_92c *p_drvinfo,
  691. bool packet_match_bssid,
  692. bool packet_toself,
  693. bool packet_beacon)
  694. {
  695. struct rtl_priv *rtlpriv = rtl_priv(hw);
  696. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  697. struct phy_sts_cck_8192s_t *cck_buf;
  698. s8 rx_pwr_all = 0, rx_pwr[4];
  699. u8 rf_rx_num = 0, evm, pwdb_all;
  700. u8 i, max_spatial_stream;
  701. u32 rssi, total_rssi = 0;
  702. bool in_powersavemode = false;
  703. bool is_cck_rate;
  704. is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
  705. pstats->packet_matchbssid = packet_match_bssid;
  706. pstats->packet_toself = packet_toself;
  707. pstats->is_cck = is_cck_rate;
  708. pstats->packet_beacon = packet_beacon;
  709. pstats->is_cck = is_cck_rate;
  710. pstats->RX_SIGQ[0] = -1;
  711. pstats->RX_SIGQ[1] = -1;
  712. if (is_cck_rate) {
  713. u8 report, cck_highpwr;
  714. cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
  715. if (!in_powersavemode)
  716. cck_highpwr = rtlphy->cck_high_power;
  717. else
  718. cck_highpwr = false;
  719. if (!cck_highpwr) {
  720. u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
  721. report = cck_buf->cck_agc_rpt & 0xc0;
  722. report = report >> 6;
  723. switch (report) {
  724. case 0x3:
  725. rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
  726. break;
  727. case 0x2:
  728. rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
  729. break;
  730. case 0x1:
  731. rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
  732. break;
  733. case 0x0:
  734. rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
  735. break;
  736. }
  737. } else {
  738. u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
  739. report = p_drvinfo->cfosho[0] & 0x60;
  740. report = report >> 5;
  741. switch (report) {
  742. case 0x3:
  743. rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
  744. break;
  745. case 0x2:
  746. rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
  747. break;
  748. case 0x1:
  749. rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
  750. break;
  751. case 0x0:
  752. rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
  753. break;
  754. }
  755. }
  756. pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
  757. pstats->rx_pwdb_all = pwdb_all;
  758. pstats->recvsignalpower = rx_pwr_all;
  759. if (packet_match_bssid) {
  760. u8 sq;
  761. if (pstats->rx_pwdb_all > 40)
  762. sq = 100;
  763. else {
  764. sq = cck_buf->sq_rpt;
  765. if (sq > 64)
  766. sq = 0;
  767. else if (sq < 20)
  768. sq = 100;
  769. else
  770. sq = ((64 - sq) * 100) / 44;
  771. }
  772. pstats->signalquality = sq;
  773. pstats->RX_SIGQ[0] = sq;
  774. pstats->RX_SIGQ[1] = -1;
  775. }
  776. } else {
  777. rtlpriv->dm.rfpath_rxenable[0] =
  778. rtlpriv->dm.rfpath_rxenable[1] = true;
  779. for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
  780. if (rtlpriv->dm.rfpath_rxenable[i])
  781. rf_rx_num++;
  782. rx_pwr[i] =
  783. ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
  784. rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
  785. total_rssi += rssi;
  786. rtlpriv->stats.rx_snr_db[i] =
  787. (long)(p_drvinfo->rxsnr[i] / 2);
  788. if (packet_match_bssid)
  789. pstats->rx_mimo_signalstrength[i] = (u8) rssi;
  790. }
  791. rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
  792. pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
  793. pstats->rx_pwdb_all = pwdb_all;
  794. pstats->rxpower = rx_pwr_all;
  795. pstats->recvsignalpower = rx_pwr_all;
  796. if (GET_RX_DESC_RX_MCS(pdesc) &&
  797. GET_RX_DESC_RX_MCS(pdesc) >= DESC92_RATEMCS8 &&
  798. GET_RX_DESC_RX_MCS(pdesc) <= DESC92_RATEMCS15)
  799. max_spatial_stream = 2;
  800. else
  801. max_spatial_stream = 1;
  802. for (i = 0; i < max_spatial_stream; i++) {
  803. evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
  804. if (packet_match_bssid) {
  805. if (i == 0)
  806. pstats->signalquality =
  807. (u8) (evm & 0xff);
  808. pstats->RX_SIGQ[i] =
  809. (u8) (evm & 0xff);
  810. }
  811. }
  812. }
  813. if (is_cck_rate)
  814. pstats->signalstrength =
  815. (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all));
  816. else if (rf_rx_num != 0)
  817. pstats->signalstrength =
  818. (u8) (_rtl92c_signal_scale_mapping
  819. (hw, total_rssi /= rf_rx_num));
  820. }
  821. static void _rtl92c_process_ui_rssi(struct ieee80211_hw *hw,
  822. struct rtl_stats *pstats)
  823. {
  824. struct rtl_priv *rtlpriv = rtl_priv(hw);
  825. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  826. u8 rfpath;
  827. u32 last_rssi, tmpval;
  828. if (pstats->packet_toself || pstats->packet_beacon) {
  829. rtlpriv->stats.rssi_calculate_cnt++;
  830. if (rtlpriv->stats.ui_rssi.total_num++ >=
  831. PHY_RSSI_SLID_WIN_MAX) {
  832. rtlpriv->stats.ui_rssi.total_num =
  833. PHY_RSSI_SLID_WIN_MAX;
  834. last_rssi =
  835. rtlpriv->stats.ui_rssi.elements[rtlpriv->
  836. stats.ui_rssi.index];
  837. rtlpriv->stats.ui_rssi.total_val -= last_rssi;
  838. }
  839. rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength;
  840. rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.
  841. index++] = pstats->signalstrength;
  842. if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
  843. rtlpriv->stats.ui_rssi.index = 0;
  844. tmpval = rtlpriv->stats.ui_rssi.total_val /
  845. rtlpriv->stats.ui_rssi.total_num;
  846. rtlpriv->stats.signal_strength =
  847. _rtl92c_translate_todbm(hw, (u8) tmpval);
  848. pstats->rssi = rtlpriv->stats.signal_strength;
  849. }
  850. if (!pstats->is_cck && pstats->packet_toself) {
  851. for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
  852. rfpath++) {
  853. if (!rtl8192_phy_check_is_legal_rfpath(hw, rfpath))
  854. continue;
  855. if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
  856. rtlpriv->stats.rx_rssi_percentage[rfpath] =
  857. pstats->rx_mimo_signalstrength[rfpath];
  858. }
  859. if (pstats->rx_mimo_signalstrength[rfpath] >
  860. rtlpriv->stats.rx_rssi_percentage[rfpath]) {
  861. rtlpriv->stats.rx_rssi_percentage[rfpath] =
  862. ((rtlpriv->stats.
  863. rx_rssi_percentage[rfpath] *
  864. (RX_SMOOTH_FACTOR - 1)) +
  865. (pstats->rx_mimo_signalstrength[rfpath])) /
  866. (RX_SMOOTH_FACTOR);
  867. rtlpriv->stats.rx_rssi_percentage[rfpath] =
  868. rtlpriv->stats.rx_rssi_percentage[rfpath] +
  869. 1;
  870. } else {
  871. rtlpriv->stats.rx_rssi_percentage[rfpath] =
  872. ((rtlpriv->stats.
  873. rx_rssi_percentage[rfpath] *
  874. (RX_SMOOTH_FACTOR - 1)) +
  875. (pstats->rx_mimo_signalstrength[rfpath])) /
  876. (RX_SMOOTH_FACTOR);
  877. }
  878. }
  879. }
  880. }
  881. static void _rtl92c_update_rxsignalstatistics(struct ieee80211_hw *hw,
  882. struct rtl_stats *pstats)
  883. {
  884. struct rtl_priv *rtlpriv = rtl_priv(hw);
  885. int weighting = 0;
  886. if (rtlpriv->stats.recv_signal_power == 0)
  887. rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
  888. if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power)
  889. weighting = 5;
  890. else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power)
  891. weighting = (-5);
  892. rtlpriv->stats.recv_signal_power =
  893. (rtlpriv->stats.recv_signal_power * 5 +
  894. pstats->recvsignalpower + weighting) / 6;
  895. }
  896. static void _rtl92c_process_pwdb(struct ieee80211_hw *hw,
  897. struct rtl_stats *pstats)
  898. {
  899. struct rtl_priv *rtlpriv = rtl_priv(hw);
  900. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  901. long undecorated_smoothed_pwdb = 0;
  902. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  903. return;
  904. } else {
  905. undecorated_smoothed_pwdb =
  906. rtlpriv->dm.undecorated_smoothed_pwdb;
  907. }
  908. if (pstats->packet_toself || pstats->packet_beacon) {
  909. if (undecorated_smoothed_pwdb < 0)
  910. undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
  911. if (pstats->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
  912. undecorated_smoothed_pwdb =
  913. (((undecorated_smoothed_pwdb) *
  914. (RX_SMOOTH_FACTOR - 1)) +
  915. (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
  916. undecorated_smoothed_pwdb = undecorated_smoothed_pwdb
  917. + 1;
  918. } else {
  919. undecorated_smoothed_pwdb =
  920. (((undecorated_smoothed_pwdb) *
  921. (RX_SMOOTH_FACTOR - 1)) +
  922. (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
  923. }
  924. rtlpriv->dm.undecorated_smoothed_pwdb =
  925. undecorated_smoothed_pwdb;
  926. _rtl92c_update_rxsignalstatistics(hw, pstats);
  927. }
  928. }
  929. static void _rtl92c_process_LINK_Q(struct ieee80211_hw *hw,
  930. struct rtl_stats *pstats)
  931. {
  932. struct rtl_priv *rtlpriv = rtl_priv(hw);
  933. u32 last_evm = 0, n_stream, tmpval;
  934. if (pstats->signalquality != 0) {
  935. if (pstats->packet_toself || pstats->packet_beacon) {
  936. if (rtlpriv->stats.LINK_Q.total_num++ >=
  937. PHY_LINKQUALITY_SLID_WIN_MAX) {
  938. rtlpriv->stats.LINK_Q.total_num =
  939. PHY_LINKQUALITY_SLID_WIN_MAX;
  940. last_evm =
  941. rtlpriv->stats.LINK_Q.elements
  942. [rtlpriv->stats.LINK_Q.index];
  943. rtlpriv->stats.LINK_Q.total_val -=
  944. last_evm;
  945. }
  946. rtlpriv->stats.LINK_Q.total_val +=
  947. pstats->signalquality;
  948. rtlpriv->stats.LINK_Q.elements
  949. [rtlpriv->stats.LINK_Q.index++] =
  950. pstats->signalquality;
  951. if (rtlpriv->stats.LINK_Q.index >=
  952. PHY_LINKQUALITY_SLID_WIN_MAX)
  953. rtlpriv->stats.LINK_Q.index = 0;
  954. tmpval = rtlpriv->stats.LINK_Q.total_val /
  955. rtlpriv->stats.LINK_Q.total_num;
  956. rtlpriv->stats.signal_quality = tmpval;
  957. rtlpriv->stats.last_sigstrength_inpercent = tmpval;
  958. for (n_stream = 0; n_stream < 2;
  959. n_stream++) {
  960. if (pstats->RX_SIGQ[n_stream] != -1) {
  961. if (!rtlpriv->stats.RX_EVM[n_stream]) {
  962. rtlpriv->stats.RX_EVM[n_stream]
  963. = pstats->RX_SIGQ[n_stream];
  964. }
  965. rtlpriv->stats.RX_EVM[n_stream] =
  966. ((rtlpriv->stats.RX_EVM
  967. [n_stream] *
  968. (RX_SMOOTH_FACTOR - 1)) +
  969. (pstats->RX_SIGQ
  970. [n_stream] * 1)) /
  971. (RX_SMOOTH_FACTOR);
  972. }
  973. }
  974. }
  975. } else {
  976. ;
  977. }
  978. }
  979. static void _rtl92c_process_phyinfo(struct ieee80211_hw *hw,
  980. u8 *buffer,
  981. struct rtl_stats *pcurrent_stats)
  982. {
  983. if (!pcurrent_stats->packet_matchbssid &&
  984. !pcurrent_stats->packet_beacon)
  985. return;
  986. _rtl92c_process_ui_rssi(hw, pcurrent_stats);
  987. _rtl92c_process_pwdb(hw, pcurrent_stats);
  988. _rtl92c_process_LINK_Q(hw, pcurrent_stats);
  989. }
  990. void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
  991. struct sk_buff *skb,
  992. struct rtl_stats *pstats,
  993. struct rx_desc_92c *pdesc,
  994. struct rx_fwinfo_92c *p_drvinfo)
  995. {
  996. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  997. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  998. struct ieee80211_hdr *hdr;
  999. u8 *tmp_buf;
  1000. u8 *praddr;
  1001. __le16 fc;
  1002. u16 type, cpu_fc;
  1003. bool packet_matchbssid, packet_toself, packet_beacon;
  1004. tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
  1005. hdr = (struct ieee80211_hdr *)tmp_buf;
  1006. fc = hdr->frame_control;
  1007. cpu_fc = le16_to_cpu(fc);
  1008. type = WLAN_FC_GET_TYPE(fc);
  1009. praddr = hdr->addr1;
  1010. packet_matchbssid =
  1011. ((IEEE80211_FTYPE_CTL != type) &&
  1012. ether_addr_equal(mac->bssid,
  1013. (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
  1014. (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
  1015. hdr->addr3) &&
  1016. (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
  1017. packet_toself = packet_matchbssid &&
  1018. ether_addr_equal(praddr, rtlefuse->dev_addr);
  1019. if (ieee80211_is_beacon(fc))
  1020. packet_beacon = true;
  1021. _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
  1022. packet_matchbssid, packet_toself,
  1023. packet_beacon);
  1024. _rtl92c_process_phyinfo(hw, tmp_buf, pstats);
  1025. }