mci.c 15 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include "ath9k.h"
  19. #include "mci.h"
  20. static const u8 ath_mci_duty_cycle[] = { 0, 50, 60, 70, 80, 85, 90, 95, 98 };
  21. static struct ath_mci_profile_info*
  22. ath_mci_find_profile(struct ath_mci_profile *mci,
  23. struct ath_mci_profile_info *info)
  24. {
  25. struct ath_mci_profile_info *entry;
  26. list_for_each_entry(entry, &mci->info, list) {
  27. if (entry->conn_handle == info->conn_handle)
  28. break;
  29. }
  30. return entry;
  31. }
  32. static bool ath_mci_add_profile(struct ath_common *common,
  33. struct ath_mci_profile *mci,
  34. struct ath_mci_profile_info *info)
  35. {
  36. struct ath_mci_profile_info *entry;
  37. if ((mci->num_sco == ATH_MCI_MAX_SCO_PROFILE) &&
  38. (info->type == MCI_GPM_COEX_PROFILE_VOICE))
  39. return false;
  40. if (((NUM_PROF(mci) - mci->num_sco) == ATH_MCI_MAX_ACL_PROFILE) &&
  41. (info->type != MCI_GPM_COEX_PROFILE_VOICE))
  42. return false;
  43. entry = ath_mci_find_profile(mci, info);
  44. if (entry) {
  45. memcpy(entry, info, 10);
  46. } else {
  47. entry = kzalloc(sizeof(*entry), GFP_KERNEL);
  48. if (!entry)
  49. return false;
  50. memcpy(entry, info, 10);
  51. INC_PROF(mci, info);
  52. list_add_tail(&info->list, &mci->info);
  53. }
  54. return true;
  55. }
  56. static void ath_mci_del_profile(struct ath_common *common,
  57. struct ath_mci_profile *mci,
  58. struct ath_mci_profile_info *info)
  59. {
  60. struct ath_mci_profile_info *entry;
  61. entry = ath_mci_find_profile(mci, info);
  62. if (!entry)
  63. return;
  64. DEC_PROF(mci, entry);
  65. list_del(&entry->list);
  66. kfree(entry);
  67. }
  68. void ath_mci_flush_profile(struct ath_mci_profile *mci)
  69. {
  70. struct ath_mci_profile_info *info, *tinfo;
  71. list_for_each_entry_safe(info, tinfo, &mci->info, list) {
  72. list_del(&info->list);
  73. DEC_PROF(mci, info);
  74. kfree(info);
  75. }
  76. mci->aggr_limit = 0;
  77. }
  78. static void ath_mci_adjust_aggr_limit(struct ath_btcoex *btcoex)
  79. {
  80. struct ath_mci_profile *mci = &btcoex->mci;
  81. u32 wlan_airtime = btcoex->btcoex_period *
  82. (100 - btcoex->duty_cycle) / 100;
  83. /*
  84. * Scale: wlan_airtime is in ms, aggr_limit is in 0.25 ms.
  85. * When wlan_airtime is less than 4ms, aggregation limit has to be
  86. * adjusted half of wlan_airtime to ensure that the aggregation can fit
  87. * without collision with BT traffic.
  88. */
  89. if ((wlan_airtime <= 4) &&
  90. (!mci->aggr_limit || (mci->aggr_limit > (2 * wlan_airtime))))
  91. mci->aggr_limit = 2 * wlan_airtime;
  92. }
  93. static void ath_mci_update_scheme(struct ath_softc *sc)
  94. {
  95. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  96. struct ath_btcoex *btcoex = &sc->btcoex;
  97. struct ath_mci_profile *mci = &btcoex->mci;
  98. struct ath_mci_profile_info *info;
  99. u32 num_profile = NUM_PROF(mci);
  100. if (num_profile == 1) {
  101. info = list_first_entry(&mci->info,
  102. struct ath_mci_profile_info,
  103. list);
  104. if (mci->num_sco && info->T == 12) {
  105. mci->aggr_limit = 8;
  106. ath_dbg(common, MCI,
  107. "Single SCO, aggregation limit 2 ms\n");
  108. } else if ((info->type == MCI_GPM_COEX_PROFILE_BNEP) &&
  109. !info->master) {
  110. btcoex->btcoex_period = 60;
  111. ath_dbg(common, MCI,
  112. "Single slave PAN/FTP, bt period 60 ms\n");
  113. } else if ((info->type == MCI_GPM_COEX_PROFILE_HID) &&
  114. (info->T > 0 && info->T < 50) &&
  115. (info->A > 1 || info->W > 1)) {
  116. btcoex->duty_cycle = 30;
  117. mci->aggr_limit = 8;
  118. ath_dbg(common, MCI,
  119. "Multiple attempt/timeout single HID "
  120. "aggregation limit 2 ms dutycycle 30%%\n");
  121. }
  122. } else if ((num_profile == 2) && (mci->num_hid == 2)) {
  123. btcoex->duty_cycle = 30;
  124. mci->aggr_limit = 8;
  125. ath_dbg(common, MCI,
  126. "Two HIDs aggregation limit 2 ms dutycycle 30%%\n");
  127. } else if (num_profile > 3) {
  128. mci->aggr_limit = 6;
  129. ath_dbg(common, MCI,
  130. "Three or more profiles aggregation limit 1.5 ms\n");
  131. }
  132. if (IS_CHAN_2GHZ(sc->sc_ah->curchan)) {
  133. if (IS_CHAN_HT(sc->sc_ah->curchan))
  134. ath_mci_adjust_aggr_limit(btcoex);
  135. else
  136. btcoex->btcoex_period >>= 1;
  137. }
  138. ath9k_hw_btcoex_disable(sc->sc_ah);
  139. ath9k_btcoex_timer_pause(sc);
  140. if (IS_CHAN_5GHZ(sc->sc_ah->curchan))
  141. return;
  142. btcoex->duty_cycle += (mci->num_bdr ? ATH_MCI_MAX_DUTY_CYCLE : 0);
  143. if (btcoex->duty_cycle > ATH_MCI_MAX_DUTY_CYCLE)
  144. btcoex->duty_cycle = ATH_MCI_MAX_DUTY_CYCLE;
  145. btcoex->btcoex_period *= 1000;
  146. btcoex->btcoex_no_stomp = btcoex->btcoex_period *
  147. (100 - btcoex->duty_cycle) / 100;
  148. ath9k_hw_btcoex_enable(sc->sc_ah);
  149. ath9k_btcoex_timer_resume(sc);
  150. }
  151. static void ath_mci_cal_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  152. {
  153. struct ath_hw *ah = sc->sc_ah;
  154. struct ath_common *common = ath9k_hw_common(ah);
  155. u32 payload[4] = {0, 0, 0, 0};
  156. switch (opcode) {
  157. case MCI_GPM_BT_CAL_REQ:
  158. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  159. ar9003_mci_state(ah, MCI_STATE_SET_BT_CAL_START, NULL);
  160. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  161. } else {
  162. ath_dbg(common, MCI, "MCI State mismatch: %d\n",
  163. ar9003_mci_state(ah, MCI_STATE_BT, NULL));
  164. }
  165. break;
  166. case MCI_GPM_BT_CAL_DONE:
  167. ar9003_mci_state(ah, MCI_STATE_BT, NULL);
  168. break;
  169. case MCI_GPM_BT_CAL_GRANT:
  170. MCI_GPM_SET_CAL_TYPE(payload, MCI_GPM_WLAN_CAL_DONE);
  171. ar9003_mci_send_message(sc->sc_ah, MCI_GPM, 0, payload,
  172. 16, false, true);
  173. break;
  174. default:
  175. ath_dbg(common, MCI, "Unknown GPM CAL message\n");
  176. break;
  177. }
  178. }
  179. static void ath_mci_process_profile(struct ath_softc *sc,
  180. struct ath_mci_profile_info *info)
  181. {
  182. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  183. struct ath_btcoex *btcoex = &sc->btcoex;
  184. struct ath_mci_profile *mci = &btcoex->mci;
  185. if (info->start) {
  186. if (!ath_mci_add_profile(common, mci, info))
  187. return;
  188. } else
  189. ath_mci_del_profile(common, mci, info);
  190. btcoex->btcoex_period = ATH_MCI_DEF_BT_PERIOD;
  191. mci->aggr_limit = mci->num_sco ? 6 : 0;
  192. if (NUM_PROF(mci)) {
  193. btcoex->bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
  194. btcoex->duty_cycle = ath_mci_duty_cycle[NUM_PROF(mci)];
  195. } else {
  196. btcoex->bt_stomp_type = mci->num_mgmt ? ATH_BTCOEX_STOMP_ALL :
  197. ATH_BTCOEX_STOMP_LOW;
  198. btcoex->duty_cycle = ATH_BTCOEX_DEF_DUTY_CYCLE;
  199. }
  200. ath_mci_update_scheme(sc);
  201. }
  202. static void ath_mci_process_status(struct ath_softc *sc,
  203. struct ath_mci_profile_status *status)
  204. {
  205. struct ath_btcoex *btcoex = &sc->btcoex;
  206. struct ath_mci_profile *mci = &btcoex->mci;
  207. struct ath_mci_profile_info info;
  208. int i = 0, old_num_mgmt = mci->num_mgmt;
  209. /* Link status type are not handled */
  210. if (status->is_link)
  211. return;
  212. memset(&info, 0, sizeof(struct ath_mci_profile_info));
  213. info.conn_handle = status->conn_handle;
  214. if (ath_mci_find_profile(mci, &info))
  215. return;
  216. if (status->conn_handle >= ATH_MCI_MAX_PROFILE)
  217. return;
  218. if (status->is_critical)
  219. __set_bit(status->conn_handle, mci->status);
  220. else
  221. __clear_bit(status->conn_handle, mci->status);
  222. mci->num_mgmt = 0;
  223. do {
  224. if (test_bit(i, mci->status))
  225. mci->num_mgmt++;
  226. } while (++i < ATH_MCI_MAX_PROFILE);
  227. if (old_num_mgmt != mci->num_mgmt)
  228. ath_mci_update_scheme(sc);
  229. }
  230. static void ath_mci_msg(struct ath_softc *sc, u8 opcode, u8 *rx_payload)
  231. {
  232. struct ath_hw *ah = sc->sc_ah;
  233. struct ath_mci_profile_info profile_info;
  234. struct ath_mci_profile_status profile_status;
  235. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  236. u32 version;
  237. u8 major;
  238. u8 minor;
  239. u32 seq_num;
  240. switch (opcode) {
  241. case MCI_GPM_COEX_VERSION_QUERY:
  242. version = ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_COEX_VERSION,
  243. NULL);
  244. break;
  245. case MCI_GPM_COEX_VERSION_RESPONSE:
  246. major = *(rx_payload + MCI_GPM_COEX_B_MAJOR_VERSION);
  247. minor = *(rx_payload + MCI_GPM_COEX_B_MINOR_VERSION);
  248. version = (major << 8) + minor;
  249. version = ar9003_mci_state(ah, MCI_STATE_SET_BT_COEX_VERSION,
  250. &version);
  251. break;
  252. case MCI_GPM_COEX_STATUS_QUERY:
  253. ar9003_mci_state(ah, MCI_STATE_SEND_WLAN_CHANNELS, NULL);
  254. break;
  255. case MCI_GPM_COEX_BT_PROFILE_INFO:
  256. memcpy(&profile_info,
  257. (rx_payload + MCI_GPM_COEX_B_PROFILE_TYPE), 10);
  258. if ((profile_info.type == MCI_GPM_COEX_PROFILE_UNKNOWN) ||
  259. (profile_info.type >= MCI_GPM_COEX_PROFILE_MAX)) {
  260. ath_dbg(common, MCI,
  261. "Illegal profile type = %d, state = %d\n",
  262. profile_info.type,
  263. profile_info.start);
  264. break;
  265. }
  266. ath_mci_process_profile(sc, &profile_info);
  267. break;
  268. case MCI_GPM_COEX_BT_STATUS_UPDATE:
  269. profile_status.is_link = *(rx_payload +
  270. MCI_GPM_COEX_B_STATUS_TYPE);
  271. profile_status.conn_handle = *(rx_payload +
  272. MCI_GPM_COEX_B_STATUS_LINKID);
  273. profile_status.is_critical = *(rx_payload +
  274. MCI_GPM_COEX_B_STATUS_STATE);
  275. seq_num = *((u32 *)(rx_payload + 12));
  276. ath_dbg(common, MCI,
  277. "BT_Status_Update: is_link=%d, linkId=%d, state=%d, SEQ=%d\n",
  278. profile_status.is_link, profile_status.conn_handle,
  279. profile_status.is_critical, seq_num);
  280. ath_mci_process_status(sc, &profile_status);
  281. break;
  282. default:
  283. ath_dbg(common, MCI, "Unknown GPM COEX message = 0x%02x\n", opcode);
  284. break;
  285. }
  286. }
  287. int ath_mci_setup(struct ath_softc *sc)
  288. {
  289. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  290. struct ath_mci_coex *mci = &sc->mci_coex;
  291. struct ath_mci_buf *buf = &mci->sched_buf;
  292. buf->bf_addr = dma_alloc_coherent(sc->dev,
  293. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  294. &buf->bf_paddr, GFP_KERNEL);
  295. if (buf->bf_addr == NULL) {
  296. ath_dbg(common, FATAL, "MCI buffer alloc failed\n");
  297. return -ENOMEM;
  298. }
  299. memset(buf->bf_addr, MCI_GPM_RSVD_PATTERN,
  300. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE);
  301. mci->sched_buf.bf_len = ATH_MCI_SCHED_BUF_SIZE;
  302. mci->gpm_buf.bf_len = ATH_MCI_GPM_BUF_SIZE;
  303. mci->gpm_buf.bf_addr = (u8 *)mci->sched_buf.bf_addr + mci->sched_buf.bf_len;
  304. mci->gpm_buf.bf_paddr = mci->sched_buf.bf_paddr + mci->sched_buf.bf_len;
  305. ar9003_mci_setup(sc->sc_ah, mci->gpm_buf.bf_paddr,
  306. mci->gpm_buf.bf_addr, (mci->gpm_buf.bf_len >> 4),
  307. mci->sched_buf.bf_paddr);
  308. ath_dbg(common, MCI, "MCI Initialized\n");
  309. return 0;
  310. }
  311. void ath_mci_cleanup(struct ath_softc *sc)
  312. {
  313. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  314. struct ath_hw *ah = sc->sc_ah;
  315. struct ath_mci_coex *mci = &sc->mci_coex;
  316. struct ath_mci_buf *buf = &mci->sched_buf;
  317. if (buf->bf_addr)
  318. dma_free_coherent(sc->dev,
  319. ATH_MCI_SCHED_BUF_SIZE + ATH_MCI_GPM_BUF_SIZE,
  320. buf->bf_addr, buf->bf_paddr);
  321. ar9003_mci_cleanup(ah);
  322. ath_dbg(common, MCI, "MCI De-Initialized\n");
  323. }
  324. void ath_mci_intr(struct ath_softc *sc)
  325. {
  326. struct ath_mci_coex *mci = &sc->mci_coex;
  327. struct ath_hw *ah = sc->sc_ah;
  328. struct ath_common *common = ath9k_hw_common(ah);
  329. u32 mci_int, mci_int_rxmsg;
  330. u32 offset, subtype, opcode;
  331. u32 *pgpm;
  332. u32 more_data = MCI_GPM_MORE;
  333. bool skip_gpm = false;
  334. ar9003_mci_get_interrupt(sc->sc_ah, &mci_int, &mci_int_rxmsg);
  335. if (ar9003_mci_state(ah, MCI_STATE_ENABLE, NULL) == 0) {
  336. ar9003_mci_state(ah, MCI_STATE_INIT_GPM_OFFSET, NULL);
  337. return;
  338. }
  339. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) {
  340. u32 payload[4] = { 0xffffffff, 0xffffffff,
  341. 0xffffffff, 0xffffff00};
  342. /*
  343. * The following REMOTE_RESET and SYS_WAKING used to sent
  344. * only when BT wake up. Now they are always sent, as a
  345. * recovery method to reset BT MCI's RX alignment.
  346. */
  347. ar9003_mci_send_message(ah, MCI_REMOTE_RESET, 0,
  348. payload, 16, true, false);
  349. ar9003_mci_send_message(ah, MCI_SYS_WAKING, 0,
  350. NULL, 0, true, false);
  351. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE;
  352. ar9003_mci_state(ah, MCI_STATE_RESET_REQ_WAKE, NULL);
  353. /*
  354. * always do this for recovery and 2G/5G toggling and LNA_TRANS
  355. */
  356. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE, NULL);
  357. }
  358. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING) {
  359. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING;
  360. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_SLEEP) {
  361. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
  362. MCI_BT_SLEEP)
  363. ar9003_mci_state(ah, MCI_STATE_SET_BT_AWAKE,
  364. NULL);
  365. }
  366. }
  367. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING) {
  368. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING;
  369. if (ar9003_mci_state(ah, MCI_STATE_BT, NULL) == MCI_BT_AWAKE) {
  370. if (ar9003_mci_state(ah, MCI_STATE_REMOTE_SLEEP, NULL) !=
  371. MCI_BT_AWAKE)
  372. ar9003_mci_state(ah, MCI_STATE_SET_BT_SLEEP,
  373. NULL);
  374. }
  375. }
  376. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  377. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT)) {
  378. ar9003_mci_state(ah, MCI_STATE_RECOVER_RX, NULL);
  379. skip_gpm = true;
  380. }
  381. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO) {
  382. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO;
  383. offset = ar9003_mci_state(ah, MCI_STATE_LAST_SCHD_MSG_OFFSET,
  384. NULL);
  385. }
  386. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_GPM) {
  387. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_GPM;
  388. while (more_data == MCI_GPM_MORE) {
  389. pgpm = mci->gpm_buf.bf_addr;
  390. offset = ar9003_mci_state(ah, MCI_STATE_NEXT_GPM_OFFSET,
  391. &more_data);
  392. if (offset == MCI_GPM_INVALID)
  393. break;
  394. pgpm += (offset >> 2);
  395. /*
  396. * The first dword is timer.
  397. * The real data starts from 2nd dword.
  398. */
  399. subtype = MCI_GPM_TYPE(pgpm);
  400. opcode = MCI_GPM_OPCODE(pgpm);
  401. if (skip_gpm)
  402. goto recycle;
  403. if (MCI_GPM_IS_CAL_TYPE(subtype)) {
  404. ath_mci_cal_msg(sc, subtype, (u8 *)pgpm);
  405. } else {
  406. switch (subtype) {
  407. case MCI_GPM_COEX_AGENT:
  408. ath_mci_msg(sc, opcode, (u8 *)pgpm);
  409. break;
  410. default:
  411. break;
  412. }
  413. }
  414. recycle:
  415. MCI_GPM_RECYCLE(pgpm);
  416. }
  417. }
  418. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_HW_MSG_MASK) {
  419. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL)
  420. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL;
  421. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_LNA_INFO)
  422. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_LNA_INFO;
  423. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO) {
  424. int value_dbm = ar9003_mci_state(ah,
  425. MCI_STATE_CONT_RSSI_POWER, NULL);
  426. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_INFO;
  427. if (ar9003_mci_state(ah, MCI_STATE_CONT_TXRX, NULL))
  428. ath_dbg(common, MCI,
  429. "MCI CONT_INFO: (tx) pri = %d, pwr = %d dBm\n",
  430. ar9003_mci_state(ah,
  431. MCI_STATE_CONT_PRIORITY, NULL),
  432. value_dbm);
  433. else
  434. ath_dbg(common, MCI,
  435. "MCI CONT_INFO: (rx) pri = %d,pwr = %d dBm\n",
  436. ar9003_mci_state(ah,
  437. MCI_STATE_CONT_PRIORITY, NULL),
  438. value_dbm);
  439. }
  440. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_NACK)
  441. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_NACK;
  442. if (mci_int_rxmsg & AR_MCI_INTERRUPT_RX_MSG_CONT_RST)
  443. mci_int_rxmsg &= ~AR_MCI_INTERRUPT_RX_MSG_CONT_RST;
  444. }
  445. if ((mci_int & AR_MCI_INTERRUPT_RX_INVALID_HDR) ||
  446. (mci_int & AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT))
  447. mci_int &= ~(AR_MCI_INTERRUPT_RX_INVALID_HDR |
  448. AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT);
  449. }