eeprom.c 14 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
  18. {
  19. REG_WRITE(ah, reg, val);
  20. if (ah->config.analog_shiftreg)
  21. udelay(100);
  22. }
  23. void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
  24. u32 shift, u32 val)
  25. {
  26. u32 regVal;
  27. regVal = REG_READ(ah, reg) & ~mask;
  28. regVal |= (val << shift) & mask;
  29. REG_WRITE(ah, reg, regVal);
  30. if (ah->config.analog_shiftreg)
  31. udelay(100);
  32. }
  33. int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
  34. int16_t targetLeft, int16_t targetRight)
  35. {
  36. int16_t rv;
  37. if (srcRight == srcLeft) {
  38. rv = targetLeft;
  39. } else {
  40. rv = (int16_t) (((target - srcLeft) * targetRight +
  41. (srcRight - target) * targetLeft) /
  42. (srcRight - srcLeft));
  43. }
  44. return rv;
  45. }
  46. bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
  47. u16 *indexL, u16 *indexR)
  48. {
  49. u16 i;
  50. if (target <= pList[0]) {
  51. *indexL = *indexR = 0;
  52. return true;
  53. }
  54. if (target >= pList[listSize - 1]) {
  55. *indexL = *indexR = (u16) (listSize - 1);
  56. return true;
  57. }
  58. for (i = 0; i < listSize - 1; i++) {
  59. if (pList[i] == target) {
  60. *indexL = *indexR = i;
  61. return true;
  62. }
  63. if (target < pList[i + 1]) {
  64. *indexL = i;
  65. *indexR = (u16) (i + 1);
  66. return false;
  67. }
  68. }
  69. return false;
  70. }
  71. void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
  72. int eep_start_loc, int size)
  73. {
  74. int i = 0, j, addr;
  75. u32 addrdata[8];
  76. u32 data[8];
  77. for (addr = 0; addr < size; addr++) {
  78. addrdata[i] = AR5416_EEPROM_OFFSET +
  79. ((addr + eep_start_loc) << AR5416_EEPROM_S);
  80. i++;
  81. if (i == 8) {
  82. REG_READ_MULTI(ah, addrdata, data, i);
  83. for (j = 0; j < i; j++) {
  84. *eep_data = data[j];
  85. eep_data++;
  86. }
  87. i = 0;
  88. }
  89. }
  90. if (i != 0) {
  91. REG_READ_MULTI(ah, addrdata, data, i);
  92. for (j = 0; j < i; j++) {
  93. *eep_data = data[j];
  94. eep_data++;
  95. }
  96. }
  97. }
  98. bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
  99. {
  100. return common->bus_ops->eeprom_read(common, off, data);
  101. }
  102. void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
  103. u8 *pVpdList, u16 numIntercepts,
  104. u8 *pRetVpdList)
  105. {
  106. u16 i, k;
  107. u8 currPwr = pwrMin;
  108. u16 idxL = 0, idxR = 0;
  109. for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
  110. ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
  111. numIntercepts, &(idxL),
  112. &(idxR));
  113. if (idxR < 1)
  114. idxR = 1;
  115. if (idxL == numIntercepts - 1)
  116. idxL = (u16) (numIntercepts - 2);
  117. if (pPwrList[idxL] == pPwrList[idxR])
  118. k = pVpdList[idxL];
  119. else
  120. k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
  121. (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
  122. (pPwrList[idxR] - pPwrList[idxL]));
  123. pRetVpdList[i] = (u8) k;
  124. currPwr += 2;
  125. }
  126. }
  127. void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
  128. struct ath9k_channel *chan,
  129. struct cal_target_power_leg *powInfo,
  130. u16 numChannels,
  131. struct cal_target_power_leg *pNewPower,
  132. u16 numRates, bool isExtTarget)
  133. {
  134. struct chan_centers centers;
  135. u16 clo, chi;
  136. int i;
  137. int matchIndex = -1, lowIndex = -1;
  138. u16 freq;
  139. ath9k_hw_get_channel_centers(ah, chan, &centers);
  140. freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
  141. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
  142. IS_CHAN_2GHZ(chan))) {
  143. matchIndex = 0;
  144. } else {
  145. for (i = 0; (i < numChannels) &&
  146. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  147. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  148. IS_CHAN_2GHZ(chan))) {
  149. matchIndex = i;
  150. break;
  151. } else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  152. IS_CHAN_2GHZ(chan)) && i > 0 &&
  153. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  154. IS_CHAN_2GHZ(chan))) {
  155. lowIndex = i - 1;
  156. break;
  157. }
  158. }
  159. if ((matchIndex == -1) && (lowIndex == -1))
  160. matchIndex = i - 1;
  161. }
  162. if (matchIndex != -1) {
  163. *pNewPower = powInfo[matchIndex];
  164. } else {
  165. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  166. IS_CHAN_2GHZ(chan));
  167. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  168. IS_CHAN_2GHZ(chan));
  169. for (i = 0; i < numRates; i++) {
  170. pNewPower->tPow2x[i] =
  171. (u8)ath9k_hw_interpolate(freq, clo, chi,
  172. powInfo[lowIndex].tPow2x[i],
  173. powInfo[lowIndex + 1].tPow2x[i]);
  174. }
  175. }
  176. }
  177. void ath9k_hw_get_target_powers(struct ath_hw *ah,
  178. struct ath9k_channel *chan,
  179. struct cal_target_power_ht *powInfo,
  180. u16 numChannels,
  181. struct cal_target_power_ht *pNewPower,
  182. u16 numRates, bool isHt40Target)
  183. {
  184. struct chan_centers centers;
  185. u16 clo, chi;
  186. int i;
  187. int matchIndex = -1, lowIndex = -1;
  188. u16 freq;
  189. ath9k_hw_get_channel_centers(ah, chan, &centers);
  190. freq = isHt40Target ? centers.synth_center : centers.ctl_center;
  191. if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
  192. matchIndex = 0;
  193. } else {
  194. for (i = 0; (i < numChannels) &&
  195. (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  196. if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
  197. IS_CHAN_2GHZ(chan))) {
  198. matchIndex = i;
  199. break;
  200. } else
  201. if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
  202. IS_CHAN_2GHZ(chan)) && i > 0 &&
  203. freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
  204. IS_CHAN_2GHZ(chan))) {
  205. lowIndex = i - 1;
  206. break;
  207. }
  208. }
  209. if ((matchIndex == -1) && (lowIndex == -1))
  210. matchIndex = i - 1;
  211. }
  212. if (matchIndex != -1) {
  213. *pNewPower = powInfo[matchIndex];
  214. } else {
  215. clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
  216. IS_CHAN_2GHZ(chan));
  217. chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
  218. IS_CHAN_2GHZ(chan));
  219. for (i = 0; i < numRates; i++) {
  220. pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
  221. clo, chi,
  222. powInfo[lowIndex].tPow2x[i],
  223. powInfo[lowIndex + 1].tPow2x[i]);
  224. }
  225. }
  226. }
  227. u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
  228. bool is2GHz, int num_band_edges)
  229. {
  230. u16 twiceMaxEdgePower = MAX_RATE_POWER;
  231. int i;
  232. for (i = 0; (i < num_band_edges) &&
  233. (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
  234. if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
  235. twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
  236. break;
  237. } else if ((i > 0) &&
  238. (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
  239. is2GHz))) {
  240. if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
  241. is2GHz) < freq &&
  242. CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
  243. twiceMaxEdgePower =
  244. CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
  245. }
  246. break;
  247. }
  248. }
  249. return twiceMaxEdgePower;
  250. }
  251. u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
  252. u8 antenna_reduction)
  253. {
  254. u16 reduction = antenna_reduction;
  255. /*
  256. * Reduce scaled Power by number of chains active
  257. * to get the per chain tx power level.
  258. */
  259. switch (ar5416_get_ntxchains(ah->txchainmask)) {
  260. case 1:
  261. break;
  262. case 2:
  263. reduction += POWER_CORRECTION_FOR_TWO_CHAIN;
  264. break;
  265. case 3:
  266. reduction += POWER_CORRECTION_FOR_THREE_CHAIN;
  267. break;
  268. }
  269. if (power_limit > reduction)
  270. power_limit -= reduction;
  271. else
  272. power_limit = 0;
  273. return power_limit;
  274. }
  275. void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
  276. {
  277. struct ath_common *common = ath9k_hw_common(ah);
  278. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  279. switch (ar5416_get_ntxchains(ah->txchainmask)) {
  280. case 1:
  281. break;
  282. case 2:
  283. regulatory->max_power_level += POWER_CORRECTION_FOR_TWO_CHAIN;
  284. break;
  285. case 3:
  286. regulatory->max_power_level += POWER_CORRECTION_FOR_THREE_CHAIN;
  287. break;
  288. default:
  289. ath_dbg(common, EEPROM, "Invalid chainmask configuration\n");
  290. break;
  291. }
  292. }
  293. void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
  294. struct ath9k_channel *chan,
  295. void *pRawDataSet,
  296. u8 *bChans, u16 availPiers,
  297. u16 tPdGainOverlap,
  298. u16 *pPdGainBoundaries, u8 *pPDADCValues,
  299. u16 numXpdGains)
  300. {
  301. int i, j, k;
  302. int16_t ss;
  303. u16 idxL = 0, idxR = 0, numPiers;
  304. static u8 vpdTableL[AR5416_NUM_PD_GAINS]
  305. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  306. static u8 vpdTableR[AR5416_NUM_PD_GAINS]
  307. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  308. static u8 vpdTableI[AR5416_NUM_PD_GAINS]
  309. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  310. u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
  311. u8 minPwrT4[AR5416_NUM_PD_GAINS];
  312. u8 maxPwrT4[AR5416_NUM_PD_GAINS];
  313. int16_t vpdStep;
  314. int16_t tmpVal;
  315. u16 sizeCurrVpdTable, maxIndex, tgtIndex;
  316. bool match;
  317. int16_t minDelta = 0;
  318. struct chan_centers centers;
  319. int pdgain_boundary_default;
  320. struct cal_data_per_freq *data_def = pRawDataSet;
  321. struct cal_data_per_freq_4k *data_4k = pRawDataSet;
  322. struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
  323. bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
  324. int intercepts;
  325. if (AR_SREV_9287(ah))
  326. intercepts = AR9287_PD_GAIN_ICEPTS;
  327. else
  328. intercepts = AR5416_PD_GAIN_ICEPTS;
  329. memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
  330. ath9k_hw_get_channel_centers(ah, chan, &centers);
  331. for (numPiers = 0; numPiers < availPiers; numPiers++) {
  332. if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
  333. break;
  334. }
  335. match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
  336. IS_CHAN_2GHZ(chan)),
  337. bChans, numPiers, &idxL, &idxR);
  338. if (match) {
  339. if (AR_SREV_9287(ah)) {
  340. /* FIXME: array overrun? */
  341. for (i = 0; i < numXpdGains; i++) {
  342. minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
  343. maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
  344. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  345. data_9287[idxL].pwrPdg[i],
  346. data_9287[idxL].vpdPdg[i],
  347. intercepts,
  348. vpdTableI[i]);
  349. }
  350. } else if (eeprom_4k) {
  351. for (i = 0; i < numXpdGains; i++) {
  352. minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
  353. maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
  354. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  355. data_4k[idxL].pwrPdg[i],
  356. data_4k[idxL].vpdPdg[i],
  357. intercepts,
  358. vpdTableI[i]);
  359. }
  360. } else {
  361. for (i = 0; i < numXpdGains; i++) {
  362. minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
  363. maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
  364. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  365. data_def[idxL].pwrPdg[i],
  366. data_def[idxL].vpdPdg[i],
  367. intercepts,
  368. vpdTableI[i]);
  369. }
  370. }
  371. } else {
  372. for (i = 0; i < numXpdGains; i++) {
  373. if (AR_SREV_9287(ah)) {
  374. pVpdL = data_9287[idxL].vpdPdg[i];
  375. pPwrL = data_9287[idxL].pwrPdg[i];
  376. pVpdR = data_9287[idxR].vpdPdg[i];
  377. pPwrR = data_9287[idxR].pwrPdg[i];
  378. } else if (eeprom_4k) {
  379. pVpdL = data_4k[idxL].vpdPdg[i];
  380. pPwrL = data_4k[idxL].pwrPdg[i];
  381. pVpdR = data_4k[idxR].vpdPdg[i];
  382. pPwrR = data_4k[idxR].pwrPdg[i];
  383. } else {
  384. pVpdL = data_def[idxL].vpdPdg[i];
  385. pPwrL = data_def[idxL].pwrPdg[i];
  386. pVpdR = data_def[idxR].vpdPdg[i];
  387. pPwrR = data_def[idxR].pwrPdg[i];
  388. }
  389. minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
  390. maxPwrT4[i] =
  391. min(pPwrL[intercepts - 1],
  392. pPwrR[intercepts - 1]);
  393. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  394. pPwrL, pVpdL,
  395. intercepts,
  396. vpdTableL[i]);
  397. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  398. pPwrR, pVpdR,
  399. intercepts,
  400. vpdTableR[i]);
  401. for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
  402. vpdTableI[i][j] =
  403. (u8)(ath9k_hw_interpolate((u16)
  404. FREQ2FBIN(centers.
  405. synth_center,
  406. IS_CHAN_2GHZ
  407. (chan)),
  408. bChans[idxL], bChans[idxR],
  409. vpdTableL[i][j], vpdTableR[i][j]));
  410. }
  411. }
  412. }
  413. k = 0;
  414. for (i = 0; i < numXpdGains; i++) {
  415. if (i == (numXpdGains - 1))
  416. pPdGainBoundaries[i] =
  417. (u16)(maxPwrT4[i] / 2);
  418. else
  419. pPdGainBoundaries[i] =
  420. (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
  421. pPdGainBoundaries[i] =
  422. min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
  423. minDelta = 0;
  424. if (i == 0) {
  425. if (AR_SREV_9280_20_OR_LATER(ah))
  426. ss = (int16_t)(0 - (minPwrT4[i] / 2));
  427. else
  428. ss = 0;
  429. } else {
  430. ss = (int16_t)((pPdGainBoundaries[i - 1] -
  431. (minPwrT4[i] / 2)) -
  432. tPdGainOverlap + 1 + minDelta);
  433. }
  434. vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
  435. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  436. while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  437. tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
  438. pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
  439. ss++;
  440. }
  441. sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
  442. tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
  443. (minPwrT4[i] / 2));
  444. maxIndex = (tgtIndex < sizeCurrVpdTable) ?
  445. tgtIndex : sizeCurrVpdTable;
  446. while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  447. pPDADCValues[k++] = vpdTableI[i][ss++];
  448. }
  449. vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
  450. vpdTableI[i][sizeCurrVpdTable - 2]);
  451. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  452. if (tgtIndex >= maxIndex) {
  453. while ((ss <= tgtIndex) &&
  454. (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  455. tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
  456. (ss - maxIndex + 1) * vpdStep));
  457. pPDADCValues[k++] = (u8)((tmpVal > 255) ?
  458. 255 : tmpVal);
  459. ss++;
  460. }
  461. }
  462. }
  463. if (eeprom_4k)
  464. pdgain_boundary_default = 58;
  465. else
  466. pdgain_boundary_default = pPdGainBoundaries[i - 1];
  467. while (i < AR5416_PD_GAINS_IN_MASK) {
  468. pPdGainBoundaries[i] = pdgain_boundary_default;
  469. i++;
  470. }
  471. while (k < AR5416_NUM_PDADC_VALUES) {
  472. pPDADCValues[k] = pPDADCValues[k - 1];
  473. k++;
  474. }
  475. }
  476. int ath9k_hw_eeprom_init(struct ath_hw *ah)
  477. {
  478. int status;
  479. if (AR_SREV_9300_20_OR_LATER(ah))
  480. ah->eep_ops = &eep_ar9300_ops;
  481. else if (AR_SREV_9287(ah)) {
  482. ah->eep_ops = &eep_ar9287_ops;
  483. } else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
  484. ah->eep_ops = &eep_4k_ops;
  485. } else {
  486. ah->eep_ops = &eep_def_ops;
  487. }
  488. if (!ah->eep_ops->fill_eeprom(ah))
  489. return -EIO;
  490. status = ah->eep_ops->check_eeprom(ah);
  491. return status;
  492. }