debug.h 8.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332
  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef DEBUG_H
  17. #define DEBUG_H
  18. #include "hw.h"
  19. #include "rc.h"
  20. #include "dfs_debug.h"
  21. struct ath_txq;
  22. struct ath_buf;
  23. #ifdef CONFIG_ATH9K_DEBUGFS
  24. #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  25. #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
  26. #else
  27. #define TX_STAT_INC(q, c) do { } while (0)
  28. #define RESET_STAT_INC(sc, type) do { } while (0)
  29. #endif
  30. #ifdef CONFIG_ATH9K_DEBUGFS
  31. /**
  32. * struct ath_interrupt_stats - Contains statistics about interrupts
  33. * @total: Total no. of interrupts generated so far
  34. * @rxok: RX with no errors
  35. * @rxlp: RX with low priority RX
  36. * @rxhp: RX with high priority, uapsd only
  37. * @rxeol: RX with no more RXDESC available
  38. * @rxorn: RX FIFO overrun
  39. * @txok: TX completed at the requested rate
  40. * @txurn: TX FIFO underrun
  41. * @mib: MIB regs reaching its threshold
  42. * @rxphyerr: RX with phy errors
  43. * @rx_keycache_miss: RX with key cache misses
  44. * @swba: Software Beacon Alert
  45. * @bmiss: Beacon Miss
  46. * @bnr: Beacon Not Ready
  47. * @cst: Carrier Sense TImeout
  48. * @gtt: Global TX Timeout
  49. * @tim: RX beacon TIM occurrence
  50. * @cabend: RX End of CAB traffic
  51. * @dtimsync: DTIM sync lossage
  52. * @dtim: RX Beacon with DTIM
  53. * @bb_watchdog: Baseband watchdog
  54. * @tsfoor: TSF out of range, indicates that the corrected TSF received
  55. * from a beacon differs from the PCU's internal TSF by more than a
  56. * (programmable) threshold
  57. * @local_timeout: Internal bus timeout.
  58. */
  59. struct ath_interrupt_stats {
  60. u32 total;
  61. u32 rxok;
  62. u32 rxlp;
  63. u32 rxhp;
  64. u32 rxeol;
  65. u32 rxorn;
  66. u32 txok;
  67. u32 txeol;
  68. u32 txurn;
  69. u32 mib;
  70. u32 rxphyerr;
  71. u32 rx_keycache_miss;
  72. u32 swba;
  73. u32 bmiss;
  74. u32 bnr;
  75. u32 cst;
  76. u32 gtt;
  77. u32 tim;
  78. u32 cabend;
  79. u32 dtimsync;
  80. u32 dtim;
  81. u32 bb_watchdog;
  82. u32 tsfoor;
  83. /* Sync-cause stats */
  84. u32 sync_cause_all;
  85. u32 sync_rtc_irq;
  86. u32 sync_mac_irq;
  87. u32 eeprom_illegal_access;
  88. u32 apb_timeout;
  89. u32 pci_mode_conflict;
  90. u32 host1_fatal;
  91. u32 host1_perr;
  92. u32 trcv_fifo_perr;
  93. u32 radm_cpl_ep;
  94. u32 radm_cpl_dllp_abort;
  95. u32 radm_cpl_tlp_abort;
  96. u32 radm_cpl_ecrc_err;
  97. u32 radm_cpl_timeout;
  98. u32 local_timeout;
  99. u32 pm_access;
  100. u32 mac_awake;
  101. u32 mac_asleep;
  102. u32 mac_sleep_access;
  103. };
  104. /**
  105. * struct ath_tx_stats - Statistics about TX
  106. * @tx_pkts_all: No. of total frames transmitted, including ones that
  107. may have had errors.
  108. * @tx_bytes_all: No. of total bytes transmitted, including ones that
  109. may have had errors.
  110. * @queued: Total MPDUs (non-aggr) queued
  111. * @completed: Total MPDUs (non-aggr) completed
  112. * @a_aggr: Total no. of aggregates queued
  113. * @a_queued_hw: Total AMPDUs queued to hardware
  114. * @a_queued_sw: Total AMPDUs queued to software queues
  115. * @a_completed: Total AMPDUs completed
  116. * @a_retries: No. of AMPDUs retried (SW)
  117. * @a_xretries: No. of AMPDUs dropped due to xretries
  118. * @fifo_underrun: FIFO underrun occurrences
  119. Valid only for:
  120. - non-aggregate condition.
  121. - first packet of aggregate.
  122. * @xtxop: No. of frames filtered because of TXOP limit
  123. * @timer_exp: Transmit timer expiry
  124. * @desc_cfg_err: Descriptor configuration errors
  125. * @data_urn: TX data underrun errors
  126. * @delim_urn: TX delimiter underrun errors
  127. * @puttxbuf: Number of times hardware was given txbuf to write.
  128. * @txstart: Number of times hardware was told to start tx.
  129. * @txprocdesc: Number of times tx descriptor was processed
  130. * @txfailed: Out-of-memory or other errors in xmit path.
  131. */
  132. struct ath_tx_stats {
  133. u32 tx_pkts_all;
  134. u32 tx_bytes_all;
  135. u32 queued;
  136. u32 completed;
  137. u32 xretries;
  138. u32 a_aggr;
  139. u32 a_queued_hw;
  140. u32 a_queued_sw;
  141. u32 a_completed;
  142. u32 a_retries;
  143. u32 a_xretries;
  144. u32 fifo_underrun;
  145. u32 xtxop;
  146. u32 timer_exp;
  147. u32 desc_cfg_err;
  148. u32 data_underrun;
  149. u32 delim_underrun;
  150. u32 puttxbuf;
  151. u32 txstart;
  152. u32 txprocdesc;
  153. u32 txfailed;
  154. };
  155. #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
  156. /**
  157. * struct ath_rx_stats - RX Statistics
  158. * @rx_pkts_all: No. of total frames received, including ones that
  159. may have had errors.
  160. * @rx_bytes_all: No. of total bytes received, including ones that
  161. may have had errors.
  162. * @crc_err: No. of frames with incorrect CRC value
  163. * @decrypt_crc_err: No. of frames whose CRC check failed after
  164. decryption process completed
  165. * @phy_err: No. of frames whose reception failed because the PHY
  166. encountered an error
  167. * @mic_err: No. of frames with incorrect TKIP MIC verification failure
  168. * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
  169. * @post_delim_crc_err: Post-Frame delimiter CRC error detections
  170. * @decrypt_busy_err: Decryption interruptions counter
  171. * @phy_err_stats: Individual PHY error statistics
  172. * @rx_len_err: No. of frames discarded due to bad length.
  173. * @rx_oom_err: No. of frames dropped due to OOM issues.
  174. * @rx_rate_err: No. of frames dropped due to rate errors.
  175. * @rx_too_many_frags_err: Frames dropped due to too-many-frags received.
  176. * @rx_drop_rxflush: No. of frames dropped due to RX-FLUSH.
  177. * @rx_beacons: No. of beacons received.
  178. * @rx_frags: No. of rx-fragements received.
  179. */
  180. struct ath_rx_stats {
  181. u32 rx_pkts_all;
  182. u32 rx_bytes_all;
  183. u32 crc_err;
  184. u32 decrypt_crc_err;
  185. u32 phy_err;
  186. u32 mic_err;
  187. u32 pre_delim_crc_err;
  188. u32 post_delim_crc_err;
  189. u32 decrypt_busy_err;
  190. u32 phy_err_stats[ATH9K_PHYERR_MAX];
  191. u32 rx_len_err;
  192. u32 rx_oom_err;
  193. u32 rx_rate_err;
  194. u32 rx_too_many_frags_err;
  195. u32 rx_drop_rxflush;
  196. u32 rx_beacons;
  197. u32 rx_frags;
  198. };
  199. enum ath_reset_type {
  200. RESET_TYPE_BB_HANG,
  201. RESET_TYPE_BB_WATCHDOG,
  202. RESET_TYPE_FATAL_INT,
  203. RESET_TYPE_TX_ERROR,
  204. RESET_TYPE_TX_HANG,
  205. RESET_TYPE_PLL_HANG,
  206. RESET_TYPE_MAC_HANG,
  207. __RESET_TYPE_MAX
  208. };
  209. struct ath_stats {
  210. struct ath_interrupt_stats istats;
  211. struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
  212. struct ath_rx_stats rxstats;
  213. struct ath_dfs_stats dfs_stats;
  214. u32 reset[__RESET_TYPE_MAX];
  215. };
  216. #define ATH_DBG_MAX_SAMPLES 10
  217. struct ath_dbg_bb_mac_samp {
  218. u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
  219. u32 pcu_obs, pcu_cr, noise;
  220. struct {
  221. u64 jiffies;
  222. int8_t rssi_ctl0;
  223. int8_t rssi_ctl1;
  224. int8_t rssi_ctl2;
  225. int8_t rssi_ext0;
  226. int8_t rssi_ext1;
  227. int8_t rssi_ext2;
  228. int8_t rssi;
  229. bool isok;
  230. u8 rts_fail_cnt;
  231. u8 data_fail_cnt;
  232. u8 rateindex;
  233. u8 qid;
  234. u8 tid;
  235. u32 ba_low;
  236. u32 ba_high;
  237. } ts[ATH_DBG_MAX_SAMPLES];
  238. struct {
  239. u64 jiffies;
  240. int8_t rssi_ctl0;
  241. int8_t rssi_ctl1;
  242. int8_t rssi_ctl2;
  243. int8_t rssi_ext0;
  244. int8_t rssi_ext1;
  245. int8_t rssi_ext2;
  246. int8_t rssi;
  247. bool is_mybeacon;
  248. u8 antenna;
  249. u8 rate;
  250. } rs[ATH_DBG_MAX_SAMPLES];
  251. struct ath_cycle_counters cc;
  252. struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
  253. };
  254. struct ath9k_debug {
  255. struct dentry *debugfs_phy;
  256. u32 regidx;
  257. struct ath_stats stats;
  258. #ifdef CONFIG_ATH9K_MAC_DEBUG
  259. spinlock_t samp_lock;
  260. struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
  261. u8 sampidx;
  262. u8 tsidx;
  263. u8 rsidx;
  264. #endif
  265. };
  266. int ath9k_init_debug(struct ath_hw *ah);
  267. void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
  268. void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
  269. struct ath_tx_status *ts, struct ath_txq *txq,
  270. unsigned int flags);
  271. void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
  272. #else
  273. #define RX_STAT_INC(c) /* NOP */
  274. static inline int ath9k_init_debug(struct ath_hw *ah)
  275. {
  276. return 0;
  277. }
  278. static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
  279. enum ath9k_int status)
  280. {
  281. }
  282. static inline void ath_debug_stat_tx(struct ath_softc *sc,
  283. struct ath_buf *bf,
  284. struct ath_tx_status *ts,
  285. struct ath_txq *txq,
  286. unsigned int flags)
  287. {
  288. }
  289. static inline void ath_debug_stat_rx(struct ath_softc *sc,
  290. struct ath_rx_status *rs)
  291. {
  292. }
  293. #endif /* CONFIG_ATH9K_DEBUGFS */
  294. #ifdef CONFIG_ATH9K_MAC_DEBUG
  295. void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
  296. #else
  297. static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
  298. {
  299. }
  300. #endif
  301. #endif /* DEBUG_H */