dl2k.c 45 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785
  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. #define DRV_NAME "DL2000/TC902x-based linux driver"
  12. #define DRV_VERSION "v1.19"
  13. #define DRV_RELDATE "2007/08/12"
  14. #include "dl2k.h"
  15. #include <linux/dma-mapping.h>
  16. #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
  17. #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
  18. #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
  19. #define dr32(reg) ioread32(ioaddr + (reg))
  20. #define dr16(reg) ioread16(ioaddr + (reg))
  21. #define dr8(reg) ioread8(ioaddr + (reg))
  22. static char version[] __devinitdata =
  23. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  24. #define MAX_UNITS 8
  25. static int mtu[MAX_UNITS];
  26. static int vlan[MAX_UNITS];
  27. static int jumbo[MAX_UNITS];
  28. static char *media[MAX_UNITS];
  29. static int tx_flow=-1;
  30. static int rx_flow=-1;
  31. static int copy_thresh;
  32. static int rx_coalesce=10; /* Rx frame count each interrupt */
  33. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  34. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  35. MODULE_AUTHOR ("Edward Peng");
  36. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  37. MODULE_LICENSE("GPL");
  38. module_param_array(mtu, int, NULL, 0);
  39. module_param_array(media, charp, NULL, 0);
  40. module_param_array(vlan, int, NULL, 0);
  41. module_param_array(jumbo, int, NULL, 0);
  42. module_param(tx_flow, int, 0);
  43. module_param(rx_flow, int, 0);
  44. module_param(copy_thresh, int, 0);
  45. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  46. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  47. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  48. /* Enable the default interrupts */
  49. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  50. UpdateStats | LinkEvent)
  51. static void dl2k_enable_int(struct netdev_private *np)
  52. {
  53. void __iomem *ioaddr = np->ioaddr;
  54. dw16(IntEnable, DEFAULT_INTR);
  55. }
  56. static const int max_intrloop = 50;
  57. static const int multicast_filter_limit = 0x40;
  58. static int rio_open (struct net_device *dev);
  59. static void rio_timer (unsigned long data);
  60. static void rio_tx_timeout (struct net_device *dev);
  61. static void alloc_list (struct net_device *dev);
  62. static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
  63. static irqreturn_t rio_interrupt (int irq, void *dev_instance);
  64. static void rio_free_tx (struct net_device *dev, int irq);
  65. static void tx_error (struct net_device *dev, int tx_status);
  66. static int receive_packet (struct net_device *dev);
  67. static void rio_error (struct net_device *dev, int int_status);
  68. static int change_mtu (struct net_device *dev, int new_mtu);
  69. static void set_multicast (struct net_device *dev);
  70. static struct net_device_stats *get_stats (struct net_device *dev);
  71. static int clear_stats (struct net_device *dev);
  72. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  73. static int rio_close (struct net_device *dev);
  74. static int find_miiphy (struct net_device *dev);
  75. static int parse_eeprom (struct net_device *dev);
  76. static int read_eeprom (struct netdev_private *, int eep_addr);
  77. static int mii_wait_link (struct net_device *dev, int wait);
  78. static int mii_set_media (struct net_device *dev);
  79. static int mii_get_media (struct net_device *dev);
  80. static int mii_set_media_pcs (struct net_device *dev);
  81. static int mii_get_media_pcs (struct net_device *dev);
  82. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  83. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  84. u16 data);
  85. static const struct ethtool_ops ethtool_ops;
  86. static const struct net_device_ops netdev_ops = {
  87. .ndo_open = rio_open,
  88. .ndo_start_xmit = start_xmit,
  89. .ndo_stop = rio_close,
  90. .ndo_get_stats = get_stats,
  91. .ndo_validate_addr = eth_validate_addr,
  92. .ndo_set_mac_address = eth_mac_addr,
  93. .ndo_set_rx_mode = set_multicast,
  94. .ndo_do_ioctl = rio_ioctl,
  95. .ndo_tx_timeout = rio_tx_timeout,
  96. .ndo_change_mtu = change_mtu,
  97. };
  98. static int __devinit
  99. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  100. {
  101. struct net_device *dev;
  102. struct netdev_private *np;
  103. static int card_idx;
  104. int chip_idx = ent->driver_data;
  105. int err, irq;
  106. void __iomem *ioaddr;
  107. static int version_printed;
  108. void *ring_space;
  109. dma_addr_t ring_dma;
  110. if (!version_printed++)
  111. printk ("%s", version);
  112. err = pci_enable_device (pdev);
  113. if (err)
  114. return err;
  115. irq = pdev->irq;
  116. err = pci_request_regions (pdev, "dl2k");
  117. if (err)
  118. goto err_out_disable;
  119. pci_set_master (pdev);
  120. err = -ENOMEM;
  121. dev = alloc_etherdev (sizeof (*np));
  122. if (!dev)
  123. goto err_out_res;
  124. SET_NETDEV_DEV(dev, &pdev->dev);
  125. np = netdev_priv(dev);
  126. /* IO registers range. */
  127. ioaddr = pci_iomap(pdev, 0, 0);
  128. if (!ioaddr)
  129. goto err_out_dev;
  130. np->eeprom_addr = ioaddr;
  131. #ifdef MEM_MAPPING
  132. /* MM registers range. */
  133. ioaddr = pci_iomap(pdev, 1, 0);
  134. if (!ioaddr)
  135. goto err_out_iounmap;
  136. #endif
  137. np->ioaddr = ioaddr;
  138. np->chip_id = chip_idx;
  139. np->pdev = pdev;
  140. spin_lock_init (&np->tx_lock);
  141. spin_lock_init (&np->rx_lock);
  142. /* Parse manual configuration */
  143. np->an_enable = 1;
  144. np->tx_coalesce = 1;
  145. if (card_idx < MAX_UNITS) {
  146. if (media[card_idx] != NULL) {
  147. np->an_enable = 0;
  148. if (strcmp (media[card_idx], "auto") == 0 ||
  149. strcmp (media[card_idx], "autosense") == 0 ||
  150. strcmp (media[card_idx], "0") == 0 ) {
  151. np->an_enable = 2;
  152. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  153. strcmp (media[card_idx], "4") == 0) {
  154. np->speed = 100;
  155. np->full_duplex = 1;
  156. } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
  157. strcmp (media[card_idx], "3") == 0) {
  158. np->speed = 100;
  159. np->full_duplex = 0;
  160. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  161. strcmp (media[card_idx], "2") == 0) {
  162. np->speed = 10;
  163. np->full_duplex = 1;
  164. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  165. strcmp (media[card_idx], "1") == 0) {
  166. np->speed = 10;
  167. np->full_duplex = 0;
  168. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  169. strcmp (media[card_idx], "6") == 0) {
  170. np->speed=1000;
  171. np->full_duplex=1;
  172. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  173. strcmp (media[card_idx], "5") == 0) {
  174. np->speed = 1000;
  175. np->full_duplex = 0;
  176. } else {
  177. np->an_enable = 1;
  178. }
  179. }
  180. if (jumbo[card_idx] != 0) {
  181. np->jumbo = 1;
  182. dev->mtu = MAX_JUMBO;
  183. } else {
  184. np->jumbo = 0;
  185. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  186. dev->mtu = mtu[card_idx];
  187. }
  188. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  189. vlan[card_idx] : 0;
  190. if (rx_coalesce > 0 && rx_timeout > 0) {
  191. np->rx_coalesce = rx_coalesce;
  192. np->rx_timeout = rx_timeout;
  193. np->coalesce = 1;
  194. }
  195. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  196. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  197. if (tx_coalesce < 1)
  198. tx_coalesce = 1;
  199. else if (tx_coalesce > TX_RING_SIZE-1)
  200. tx_coalesce = TX_RING_SIZE - 1;
  201. }
  202. dev->netdev_ops = &netdev_ops;
  203. dev->watchdog_timeo = TX_TIMEOUT;
  204. SET_ETHTOOL_OPS(dev, &ethtool_ops);
  205. #if 0
  206. dev->features = NETIF_F_IP_CSUM;
  207. #endif
  208. pci_set_drvdata (pdev, dev);
  209. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  210. if (!ring_space)
  211. goto err_out_iounmap;
  212. np->tx_ring = ring_space;
  213. np->tx_ring_dma = ring_dma;
  214. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  215. if (!ring_space)
  216. goto err_out_unmap_tx;
  217. np->rx_ring = ring_space;
  218. np->rx_ring_dma = ring_dma;
  219. /* Parse eeprom data */
  220. parse_eeprom (dev);
  221. /* Find PHY address */
  222. err = find_miiphy (dev);
  223. if (err)
  224. goto err_out_unmap_rx;
  225. /* Fiber device? */
  226. np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
  227. np->link_status = 0;
  228. /* Set media and reset PHY */
  229. if (np->phy_media) {
  230. /* default Auto-Negotiation for fiber deivices */
  231. if (np->an_enable == 2) {
  232. np->an_enable = 1;
  233. }
  234. mii_set_media_pcs (dev);
  235. } else {
  236. /* Auto-Negotiation is mandatory for 1000BASE-T,
  237. IEEE 802.3ab Annex 28D page 14 */
  238. if (np->speed == 1000)
  239. np->an_enable = 1;
  240. mii_set_media (dev);
  241. }
  242. err = register_netdev (dev);
  243. if (err)
  244. goto err_out_unmap_rx;
  245. card_idx++;
  246. printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
  247. dev->name, np->name, dev->dev_addr, irq);
  248. if (tx_coalesce > 1)
  249. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  250. tx_coalesce);
  251. if (np->coalesce)
  252. printk(KERN_INFO
  253. "rx_coalesce:\t%d packets\n"
  254. "rx_timeout: \t%d ns\n",
  255. np->rx_coalesce, np->rx_timeout*640);
  256. if (np->vlan)
  257. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  258. return 0;
  259. err_out_unmap_rx:
  260. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  261. err_out_unmap_tx:
  262. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  263. err_out_iounmap:
  264. #ifdef MEM_MAPPING
  265. pci_iounmap(pdev, np->ioaddr);
  266. #endif
  267. pci_iounmap(pdev, np->eeprom_addr);
  268. err_out_dev:
  269. free_netdev (dev);
  270. err_out_res:
  271. pci_release_regions (pdev);
  272. err_out_disable:
  273. pci_disable_device (pdev);
  274. return err;
  275. }
  276. static int
  277. find_miiphy (struct net_device *dev)
  278. {
  279. struct netdev_private *np = netdev_priv(dev);
  280. int i, phy_found = 0;
  281. np = netdev_priv(dev);
  282. np->phy_addr = 1;
  283. for (i = 31; i >= 0; i--) {
  284. int mii_status = mii_read (dev, i, 1);
  285. if (mii_status != 0xffff && mii_status != 0x0000) {
  286. np->phy_addr = i;
  287. phy_found++;
  288. }
  289. }
  290. if (!phy_found) {
  291. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  292. return -ENODEV;
  293. }
  294. return 0;
  295. }
  296. static int
  297. parse_eeprom (struct net_device *dev)
  298. {
  299. struct netdev_private *np = netdev_priv(dev);
  300. void __iomem *ioaddr = np->ioaddr;
  301. int i, j;
  302. u8 sromdata[256];
  303. u8 *psib;
  304. u32 crc;
  305. PSROM_t psrom = (PSROM_t) sromdata;
  306. int cid, next;
  307. for (i = 0; i < 128; i++)
  308. ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
  309. if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
  310. /* Check CRC */
  311. crc = ~ether_crc_le (256 - 4, sromdata);
  312. if (psrom->crc != cpu_to_le32(crc)) {
  313. printk (KERN_ERR "%s: EEPROM data CRC error.\n",
  314. dev->name);
  315. return -1;
  316. }
  317. }
  318. /* Set MAC address */
  319. for (i = 0; i < 6; i++)
  320. dev->dev_addr[i] = psrom->mac_addr[i];
  321. if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
  322. return 0;
  323. }
  324. /* Parse Software Information Block */
  325. i = 0x30;
  326. psib = (u8 *) sromdata;
  327. do {
  328. cid = psib[i++];
  329. next = psib[i++];
  330. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  331. printk (KERN_ERR "Cell data error\n");
  332. return -1;
  333. }
  334. switch (cid) {
  335. case 0: /* Format version */
  336. break;
  337. case 1: /* End of cell */
  338. return 0;
  339. case 2: /* Duplex Polarity */
  340. np->duplex_polarity = psib[i];
  341. dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
  342. break;
  343. case 3: /* Wake Polarity */
  344. np->wake_polarity = psib[i];
  345. break;
  346. case 9: /* Adapter description */
  347. j = (next - i > 255) ? 255 : next - i;
  348. memcpy (np->name, &(psib[i]), j);
  349. break;
  350. case 4:
  351. case 5:
  352. case 6:
  353. case 7:
  354. case 8: /* Reversed */
  355. break;
  356. default: /* Unknown cell */
  357. return -1;
  358. }
  359. i = next;
  360. } while (1);
  361. return 0;
  362. }
  363. static int
  364. rio_open (struct net_device *dev)
  365. {
  366. struct netdev_private *np = netdev_priv(dev);
  367. void __iomem *ioaddr = np->ioaddr;
  368. const int irq = np->pdev->irq;
  369. int i;
  370. u16 macctrl;
  371. i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
  372. if (i)
  373. return i;
  374. /* Reset all logic functions */
  375. dw16(ASICCtrl + 2,
  376. GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
  377. mdelay(10);
  378. /* DebugCtrl bit 4, 5, 9 must set */
  379. dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
  380. /* Jumbo frame */
  381. if (np->jumbo != 0)
  382. dw16(MaxFrameSize, MAX_JUMBO+14);
  383. alloc_list (dev);
  384. /* Get station address */
  385. for (i = 0; i < 6; i++)
  386. dw8(StationAddr0 + i, dev->dev_addr[i]);
  387. set_multicast (dev);
  388. if (np->coalesce) {
  389. dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
  390. }
  391. /* Set RIO to poll every N*320nsec. */
  392. dw8(RxDMAPollPeriod, 0x20);
  393. dw8(TxDMAPollPeriod, 0xff);
  394. dw8(RxDMABurstThresh, 0x30);
  395. dw8(RxDMAUrgentThresh, 0x30);
  396. dw32(RmonStatMask, 0x0007ffff);
  397. /* clear statistics */
  398. clear_stats (dev);
  399. /* VLAN supported */
  400. if (np->vlan) {
  401. /* priority field in RxDMAIntCtrl */
  402. dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
  403. /* VLANId */
  404. dw16(VLANId, np->vlan);
  405. /* Length/Type should be 0x8100 */
  406. dw32(VLANTag, 0x8100 << 16 | np->vlan);
  407. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  408. VLAN information tagged by TFC' VID, CFI fields. */
  409. dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
  410. }
  411. init_timer (&np->timer);
  412. np->timer.expires = jiffies + 1*HZ;
  413. np->timer.data = (unsigned long) dev;
  414. np->timer.function = rio_timer;
  415. add_timer (&np->timer);
  416. /* Start Tx/Rx */
  417. dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
  418. macctrl = 0;
  419. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  420. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  421. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  422. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  423. dw16(MACCtrl, macctrl);
  424. netif_start_queue (dev);
  425. dl2k_enable_int(np);
  426. return 0;
  427. }
  428. static void
  429. rio_timer (unsigned long data)
  430. {
  431. struct net_device *dev = (struct net_device *)data;
  432. struct netdev_private *np = netdev_priv(dev);
  433. unsigned int entry;
  434. int next_tick = 1*HZ;
  435. unsigned long flags;
  436. spin_lock_irqsave(&np->rx_lock, flags);
  437. /* Recover rx ring exhausted error */
  438. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  439. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  440. /* Re-allocate skbuffs to fill the descriptor ring */
  441. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  442. struct sk_buff *skb;
  443. entry = np->old_rx % RX_RING_SIZE;
  444. /* Dropped packets don't need to re-allocate */
  445. if (np->rx_skbuff[entry] == NULL) {
  446. skb = netdev_alloc_skb_ip_align(dev,
  447. np->rx_buf_sz);
  448. if (skb == NULL) {
  449. np->rx_ring[entry].fraginfo = 0;
  450. printk (KERN_INFO
  451. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  452. dev->name, entry);
  453. break;
  454. }
  455. np->rx_skbuff[entry] = skb;
  456. np->rx_ring[entry].fraginfo =
  457. cpu_to_le64 (pci_map_single
  458. (np->pdev, skb->data, np->rx_buf_sz,
  459. PCI_DMA_FROMDEVICE));
  460. }
  461. np->rx_ring[entry].fraginfo |=
  462. cpu_to_le64((u64)np->rx_buf_sz << 48);
  463. np->rx_ring[entry].status = 0;
  464. } /* end for */
  465. } /* end if */
  466. spin_unlock_irqrestore (&np->rx_lock, flags);
  467. np->timer.expires = jiffies + next_tick;
  468. add_timer(&np->timer);
  469. }
  470. static void
  471. rio_tx_timeout (struct net_device *dev)
  472. {
  473. struct netdev_private *np = netdev_priv(dev);
  474. void __iomem *ioaddr = np->ioaddr;
  475. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  476. dev->name, dr32(TxStatus));
  477. rio_free_tx(dev, 0);
  478. dev->if_port = 0;
  479. dev->trans_start = jiffies; /* prevent tx timeout */
  480. }
  481. /* allocate and initialize Tx and Rx descriptors */
  482. static void
  483. alloc_list (struct net_device *dev)
  484. {
  485. struct netdev_private *np = netdev_priv(dev);
  486. void __iomem *ioaddr = np->ioaddr;
  487. int i;
  488. np->cur_rx = np->cur_tx = 0;
  489. np->old_rx = np->old_tx = 0;
  490. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  491. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  492. for (i = 0; i < TX_RING_SIZE; i++) {
  493. np->tx_skbuff[i] = NULL;
  494. np->tx_ring[i].status = cpu_to_le64 (TFDDone);
  495. np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
  496. ((i+1)%TX_RING_SIZE) *
  497. sizeof (struct netdev_desc));
  498. }
  499. /* Initialize Rx descriptors */
  500. for (i = 0; i < RX_RING_SIZE; i++) {
  501. np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
  502. ((i + 1) % RX_RING_SIZE) *
  503. sizeof (struct netdev_desc));
  504. np->rx_ring[i].status = 0;
  505. np->rx_ring[i].fraginfo = 0;
  506. np->rx_skbuff[i] = NULL;
  507. }
  508. /* Allocate the rx buffers */
  509. for (i = 0; i < RX_RING_SIZE; i++) {
  510. /* Allocated fixed size of skbuff */
  511. struct sk_buff *skb;
  512. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  513. np->rx_skbuff[i] = skb;
  514. if (skb == NULL) {
  515. printk (KERN_ERR
  516. "%s: alloc_list: allocate Rx buffer error! ",
  517. dev->name);
  518. break;
  519. }
  520. /* Rubicon now supports 40 bits of addressing space. */
  521. np->rx_ring[i].fraginfo =
  522. cpu_to_le64 ( pci_map_single (
  523. np->pdev, skb->data, np->rx_buf_sz,
  524. PCI_DMA_FROMDEVICE));
  525. np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
  526. }
  527. /* Set RFDListPtr */
  528. dw32(RFDListPtr0, np->rx_ring_dma);
  529. dw32(RFDListPtr1, 0);
  530. }
  531. static netdev_tx_t
  532. start_xmit (struct sk_buff *skb, struct net_device *dev)
  533. {
  534. struct netdev_private *np = netdev_priv(dev);
  535. void __iomem *ioaddr = np->ioaddr;
  536. struct netdev_desc *txdesc;
  537. unsigned entry;
  538. u64 tfc_vlan_tag = 0;
  539. if (np->link_status == 0) { /* Link Down */
  540. dev_kfree_skb(skb);
  541. return NETDEV_TX_OK;
  542. }
  543. entry = np->cur_tx % TX_RING_SIZE;
  544. np->tx_skbuff[entry] = skb;
  545. txdesc = &np->tx_ring[entry];
  546. #if 0
  547. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  548. txdesc->status |=
  549. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  550. IPChecksumEnable);
  551. }
  552. #endif
  553. if (np->vlan) {
  554. tfc_vlan_tag = VLANTagInsert |
  555. ((u64)np->vlan << 32) |
  556. ((u64)skb->priority << 45);
  557. }
  558. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  559. skb->len,
  560. PCI_DMA_TODEVICE));
  561. txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
  562. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  563. * Work around: Always use 1 descriptor in 10Mbps mode */
  564. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  565. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  566. WordAlignDisable |
  567. TxDMAIndicate |
  568. (1 << FragCountShift));
  569. else
  570. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  571. WordAlignDisable |
  572. (1 << FragCountShift));
  573. /* TxDMAPollNow */
  574. dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
  575. /* Schedule ISR */
  576. dw32(CountDown, 10000);
  577. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  578. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  579. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  580. /* do nothing */
  581. } else if (!netif_queue_stopped(dev)) {
  582. netif_stop_queue (dev);
  583. }
  584. /* The first TFDListPtr */
  585. if (!dr32(TFDListPtr0)) {
  586. dw32(TFDListPtr0, np->tx_ring_dma +
  587. entry * sizeof (struct netdev_desc));
  588. dw32(TFDListPtr1, 0);
  589. }
  590. return NETDEV_TX_OK;
  591. }
  592. static irqreturn_t
  593. rio_interrupt (int irq, void *dev_instance)
  594. {
  595. struct net_device *dev = dev_instance;
  596. struct netdev_private *np = netdev_priv(dev);
  597. void __iomem *ioaddr = np->ioaddr;
  598. unsigned int_status;
  599. int cnt = max_intrloop;
  600. int handled = 0;
  601. while (1) {
  602. int_status = dr16(IntStatus);
  603. dw16(IntStatus, int_status);
  604. int_status &= DEFAULT_INTR;
  605. if (int_status == 0 || --cnt < 0)
  606. break;
  607. handled = 1;
  608. /* Processing received packets */
  609. if (int_status & RxDMAComplete)
  610. receive_packet (dev);
  611. /* TxDMAComplete interrupt */
  612. if ((int_status & (TxDMAComplete|IntRequested))) {
  613. int tx_status;
  614. tx_status = dr32(TxStatus);
  615. if (tx_status & 0x01)
  616. tx_error (dev, tx_status);
  617. /* Free used tx skbuffs */
  618. rio_free_tx (dev, 1);
  619. }
  620. /* Handle uncommon events */
  621. if (int_status &
  622. (HostError | LinkEvent | UpdateStats))
  623. rio_error (dev, int_status);
  624. }
  625. if (np->cur_tx != np->old_tx)
  626. dw32(CountDown, 100);
  627. return IRQ_RETVAL(handled);
  628. }
  629. static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
  630. {
  631. return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
  632. }
  633. static void
  634. rio_free_tx (struct net_device *dev, int irq)
  635. {
  636. struct netdev_private *np = netdev_priv(dev);
  637. int entry = np->old_tx % TX_RING_SIZE;
  638. int tx_use = 0;
  639. unsigned long flag = 0;
  640. if (irq)
  641. spin_lock(&np->tx_lock);
  642. else
  643. spin_lock_irqsave(&np->tx_lock, flag);
  644. /* Free used tx skbuffs */
  645. while (entry != np->cur_tx) {
  646. struct sk_buff *skb;
  647. if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
  648. break;
  649. skb = np->tx_skbuff[entry];
  650. pci_unmap_single (np->pdev,
  651. desc_to_dma(&np->tx_ring[entry]),
  652. skb->len, PCI_DMA_TODEVICE);
  653. if (irq)
  654. dev_kfree_skb_irq (skb);
  655. else
  656. dev_kfree_skb (skb);
  657. np->tx_skbuff[entry] = NULL;
  658. entry = (entry + 1) % TX_RING_SIZE;
  659. tx_use++;
  660. }
  661. if (irq)
  662. spin_unlock(&np->tx_lock);
  663. else
  664. spin_unlock_irqrestore(&np->tx_lock, flag);
  665. np->old_tx = entry;
  666. /* If the ring is no longer full, clear tx_full and
  667. call netif_wake_queue() */
  668. if (netif_queue_stopped(dev) &&
  669. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  670. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  671. netif_wake_queue (dev);
  672. }
  673. }
  674. static void
  675. tx_error (struct net_device *dev, int tx_status)
  676. {
  677. struct netdev_private *np = netdev_priv(dev);
  678. void __iomem *ioaddr = np->ioaddr;
  679. int frame_id;
  680. int i;
  681. frame_id = (tx_status & 0xffff0000);
  682. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  683. dev->name, tx_status, frame_id);
  684. np->stats.tx_errors++;
  685. /* Ttransmit Underrun */
  686. if (tx_status & 0x10) {
  687. np->stats.tx_fifo_errors++;
  688. dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
  689. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  690. dw16(ASICCtrl + 2,
  691. TxReset | DMAReset | FIFOReset | NetworkReset);
  692. /* Wait for ResetBusy bit clear */
  693. for (i = 50; i > 0; i--) {
  694. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  695. break;
  696. mdelay (1);
  697. }
  698. rio_free_tx (dev, 1);
  699. /* Reset TFDListPtr */
  700. dw32(TFDListPtr0, np->tx_ring_dma +
  701. np->old_tx * sizeof (struct netdev_desc));
  702. dw32(TFDListPtr1, 0);
  703. /* Let TxStartThresh stay default value */
  704. }
  705. /* Late Collision */
  706. if (tx_status & 0x04) {
  707. np->stats.tx_fifo_errors++;
  708. /* TxReset and clear FIFO */
  709. dw16(ASICCtrl + 2, TxReset | FIFOReset);
  710. /* Wait reset done */
  711. for (i = 50; i > 0; i--) {
  712. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  713. break;
  714. mdelay (1);
  715. }
  716. /* Let TxStartThresh stay default value */
  717. }
  718. /* Maximum Collisions */
  719. #ifdef ETHER_STATS
  720. if (tx_status & 0x08)
  721. np->stats.collisions16++;
  722. #else
  723. if (tx_status & 0x08)
  724. np->stats.collisions++;
  725. #endif
  726. /* Restart the Tx */
  727. dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
  728. }
  729. static int
  730. receive_packet (struct net_device *dev)
  731. {
  732. struct netdev_private *np = netdev_priv(dev);
  733. int entry = np->cur_rx % RX_RING_SIZE;
  734. int cnt = 30;
  735. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  736. while (1) {
  737. struct netdev_desc *desc = &np->rx_ring[entry];
  738. int pkt_len;
  739. u64 frame_status;
  740. if (!(desc->status & cpu_to_le64(RFDDone)) ||
  741. !(desc->status & cpu_to_le64(FrameStart)) ||
  742. !(desc->status & cpu_to_le64(FrameEnd)))
  743. break;
  744. /* Chip omits the CRC. */
  745. frame_status = le64_to_cpu(desc->status);
  746. pkt_len = frame_status & 0xffff;
  747. if (--cnt < 0)
  748. break;
  749. /* Update rx error statistics, drop packet. */
  750. if (frame_status & RFS_Errors) {
  751. np->stats.rx_errors++;
  752. if (frame_status & (RxRuntFrame | RxLengthError))
  753. np->stats.rx_length_errors++;
  754. if (frame_status & RxFCSError)
  755. np->stats.rx_crc_errors++;
  756. if (frame_status & RxAlignmentError && np->speed != 1000)
  757. np->stats.rx_frame_errors++;
  758. if (frame_status & RxFIFOOverrun)
  759. np->stats.rx_fifo_errors++;
  760. } else {
  761. struct sk_buff *skb;
  762. /* Small skbuffs for short packets */
  763. if (pkt_len > copy_thresh) {
  764. pci_unmap_single (np->pdev,
  765. desc_to_dma(desc),
  766. np->rx_buf_sz,
  767. PCI_DMA_FROMDEVICE);
  768. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  769. np->rx_skbuff[entry] = NULL;
  770. } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
  771. pci_dma_sync_single_for_cpu(np->pdev,
  772. desc_to_dma(desc),
  773. np->rx_buf_sz,
  774. PCI_DMA_FROMDEVICE);
  775. skb_copy_to_linear_data (skb,
  776. np->rx_skbuff[entry]->data,
  777. pkt_len);
  778. skb_put (skb, pkt_len);
  779. pci_dma_sync_single_for_device(np->pdev,
  780. desc_to_dma(desc),
  781. np->rx_buf_sz,
  782. PCI_DMA_FROMDEVICE);
  783. }
  784. skb->protocol = eth_type_trans (skb, dev);
  785. #if 0
  786. /* Checksum done by hw, but csum value unavailable. */
  787. if (np->pdev->pci_rev_id >= 0x0c &&
  788. !(frame_status & (TCPError | UDPError | IPError))) {
  789. skb->ip_summed = CHECKSUM_UNNECESSARY;
  790. }
  791. #endif
  792. netif_rx (skb);
  793. }
  794. entry = (entry + 1) % RX_RING_SIZE;
  795. }
  796. spin_lock(&np->rx_lock);
  797. np->cur_rx = entry;
  798. /* Re-allocate skbuffs to fill the descriptor ring */
  799. entry = np->old_rx;
  800. while (entry != np->cur_rx) {
  801. struct sk_buff *skb;
  802. /* Dropped packets don't need to re-allocate */
  803. if (np->rx_skbuff[entry] == NULL) {
  804. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  805. if (skb == NULL) {
  806. np->rx_ring[entry].fraginfo = 0;
  807. printk (KERN_INFO
  808. "%s: receive_packet: "
  809. "Unable to re-allocate Rx skbuff.#%d\n",
  810. dev->name, entry);
  811. break;
  812. }
  813. np->rx_skbuff[entry] = skb;
  814. np->rx_ring[entry].fraginfo =
  815. cpu_to_le64 (pci_map_single
  816. (np->pdev, skb->data, np->rx_buf_sz,
  817. PCI_DMA_FROMDEVICE));
  818. }
  819. np->rx_ring[entry].fraginfo |=
  820. cpu_to_le64((u64)np->rx_buf_sz << 48);
  821. np->rx_ring[entry].status = 0;
  822. entry = (entry + 1) % RX_RING_SIZE;
  823. }
  824. np->old_rx = entry;
  825. spin_unlock(&np->rx_lock);
  826. return 0;
  827. }
  828. static void
  829. rio_error (struct net_device *dev, int int_status)
  830. {
  831. struct netdev_private *np = netdev_priv(dev);
  832. void __iomem *ioaddr = np->ioaddr;
  833. u16 macctrl;
  834. /* Link change event */
  835. if (int_status & LinkEvent) {
  836. if (mii_wait_link (dev, 10) == 0) {
  837. printk (KERN_INFO "%s: Link up\n", dev->name);
  838. if (np->phy_media)
  839. mii_get_media_pcs (dev);
  840. else
  841. mii_get_media (dev);
  842. if (np->speed == 1000)
  843. np->tx_coalesce = tx_coalesce;
  844. else
  845. np->tx_coalesce = 1;
  846. macctrl = 0;
  847. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  848. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  849. macctrl |= (np->tx_flow) ?
  850. TxFlowControlEnable : 0;
  851. macctrl |= (np->rx_flow) ?
  852. RxFlowControlEnable : 0;
  853. dw16(MACCtrl, macctrl);
  854. np->link_status = 1;
  855. netif_carrier_on(dev);
  856. } else {
  857. printk (KERN_INFO "%s: Link off\n", dev->name);
  858. np->link_status = 0;
  859. netif_carrier_off(dev);
  860. }
  861. }
  862. /* UpdateStats statistics registers */
  863. if (int_status & UpdateStats) {
  864. get_stats (dev);
  865. }
  866. /* PCI Error, a catastronphic error related to the bus interface
  867. occurs, set GlobalReset and HostReset to reset. */
  868. if (int_status & HostError) {
  869. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  870. dev->name, int_status);
  871. dw16(ASICCtrl + 2, GlobalReset | HostReset);
  872. mdelay (500);
  873. }
  874. }
  875. static struct net_device_stats *
  876. get_stats (struct net_device *dev)
  877. {
  878. struct netdev_private *np = netdev_priv(dev);
  879. void __iomem *ioaddr = np->ioaddr;
  880. #ifdef MEM_MAPPING
  881. int i;
  882. #endif
  883. unsigned int stat_reg;
  884. /* All statistics registers need to be acknowledged,
  885. else statistic overflow could cause problems */
  886. np->stats.rx_packets += dr32(FramesRcvOk);
  887. np->stats.tx_packets += dr32(FramesXmtOk);
  888. np->stats.rx_bytes += dr32(OctetRcvOk);
  889. np->stats.tx_bytes += dr32(OctetXmtOk);
  890. np->stats.multicast = dr32(McstFramesRcvdOk);
  891. np->stats.collisions += dr32(SingleColFrames)
  892. + dr32(MultiColFrames);
  893. /* detailed tx errors */
  894. stat_reg = dr16(FramesAbortXSColls);
  895. np->stats.tx_aborted_errors += stat_reg;
  896. np->stats.tx_errors += stat_reg;
  897. stat_reg = dr16(CarrierSenseErrors);
  898. np->stats.tx_carrier_errors += stat_reg;
  899. np->stats.tx_errors += stat_reg;
  900. /* Clear all other statistic register. */
  901. dr32(McstOctetXmtOk);
  902. dr16(BcstFramesXmtdOk);
  903. dr32(McstFramesXmtdOk);
  904. dr16(BcstFramesRcvdOk);
  905. dr16(MacControlFramesRcvd);
  906. dr16(FrameTooLongErrors);
  907. dr16(InRangeLengthErrors);
  908. dr16(FramesCheckSeqErrors);
  909. dr16(FramesLostRxErrors);
  910. dr32(McstOctetXmtOk);
  911. dr32(BcstOctetXmtOk);
  912. dr32(McstFramesXmtdOk);
  913. dr32(FramesWDeferredXmt);
  914. dr32(LateCollisions);
  915. dr16(BcstFramesXmtdOk);
  916. dr16(MacControlFramesXmtd);
  917. dr16(FramesWEXDeferal);
  918. #ifdef MEM_MAPPING
  919. for (i = 0x100; i <= 0x150; i += 4)
  920. dr32(i);
  921. #endif
  922. dr16(TxJumboFrames);
  923. dr16(RxJumboFrames);
  924. dr16(TCPCheckSumErrors);
  925. dr16(UDPCheckSumErrors);
  926. dr16(IPCheckSumErrors);
  927. return &np->stats;
  928. }
  929. static int
  930. clear_stats (struct net_device *dev)
  931. {
  932. struct netdev_private *np = netdev_priv(dev);
  933. void __iomem *ioaddr = np->ioaddr;
  934. #ifdef MEM_MAPPING
  935. int i;
  936. #endif
  937. /* All statistics registers need to be acknowledged,
  938. else statistic overflow could cause problems */
  939. dr32(FramesRcvOk);
  940. dr32(FramesXmtOk);
  941. dr32(OctetRcvOk);
  942. dr32(OctetXmtOk);
  943. dr32(McstFramesRcvdOk);
  944. dr32(SingleColFrames);
  945. dr32(MultiColFrames);
  946. dr32(LateCollisions);
  947. /* detailed rx errors */
  948. dr16(FrameTooLongErrors);
  949. dr16(InRangeLengthErrors);
  950. dr16(FramesCheckSeqErrors);
  951. dr16(FramesLostRxErrors);
  952. /* detailed tx errors */
  953. dr16(FramesAbortXSColls);
  954. dr16(CarrierSenseErrors);
  955. /* Clear all other statistic register. */
  956. dr32(McstOctetXmtOk);
  957. dr16(BcstFramesXmtdOk);
  958. dr32(McstFramesXmtdOk);
  959. dr16(BcstFramesRcvdOk);
  960. dr16(MacControlFramesRcvd);
  961. dr32(McstOctetXmtOk);
  962. dr32(BcstOctetXmtOk);
  963. dr32(McstFramesXmtdOk);
  964. dr32(FramesWDeferredXmt);
  965. dr16(BcstFramesXmtdOk);
  966. dr16(MacControlFramesXmtd);
  967. dr16(FramesWEXDeferal);
  968. #ifdef MEM_MAPPING
  969. for (i = 0x100; i <= 0x150; i += 4)
  970. dr32(i);
  971. #endif
  972. dr16(TxJumboFrames);
  973. dr16(RxJumboFrames);
  974. dr16(TCPCheckSumErrors);
  975. dr16(UDPCheckSumErrors);
  976. dr16(IPCheckSumErrors);
  977. return 0;
  978. }
  979. static int
  980. change_mtu (struct net_device *dev, int new_mtu)
  981. {
  982. struct netdev_private *np = netdev_priv(dev);
  983. int max = (np->jumbo) ? MAX_JUMBO : 1536;
  984. if ((new_mtu < 68) || (new_mtu > max)) {
  985. return -EINVAL;
  986. }
  987. dev->mtu = new_mtu;
  988. return 0;
  989. }
  990. static void
  991. set_multicast (struct net_device *dev)
  992. {
  993. struct netdev_private *np = netdev_priv(dev);
  994. void __iomem *ioaddr = np->ioaddr;
  995. u32 hash_table[2];
  996. u16 rx_mode = 0;
  997. hash_table[0] = hash_table[1] = 0;
  998. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  999. hash_table[1] |= 0x02000000;
  1000. if (dev->flags & IFF_PROMISC) {
  1001. /* Receive all frames promiscuously. */
  1002. rx_mode = ReceiveAllFrames;
  1003. } else if ((dev->flags & IFF_ALLMULTI) ||
  1004. (netdev_mc_count(dev) > multicast_filter_limit)) {
  1005. /* Receive broadcast and multicast frames */
  1006. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1007. } else if (!netdev_mc_empty(dev)) {
  1008. struct netdev_hw_addr *ha;
  1009. /* Receive broadcast frames and multicast frames filtering
  1010. by Hashtable */
  1011. rx_mode =
  1012. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1013. netdev_for_each_mc_addr(ha, dev) {
  1014. int bit, index = 0;
  1015. int crc = ether_crc_le(ETH_ALEN, ha->addr);
  1016. /* The inverted high significant 6 bits of CRC are
  1017. used as an index to hashtable */
  1018. for (bit = 0; bit < 6; bit++)
  1019. if (crc & (1 << (31 - bit)))
  1020. index |= (1 << bit);
  1021. hash_table[index / 32] |= (1 << (index % 32));
  1022. }
  1023. } else {
  1024. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1025. }
  1026. if (np->vlan) {
  1027. /* ReceiveVLANMatch field in ReceiveMode */
  1028. rx_mode |= ReceiveVLANMatch;
  1029. }
  1030. dw32(HashTable0, hash_table[0]);
  1031. dw32(HashTable1, hash_table[1]);
  1032. dw16(ReceiveMode, rx_mode);
  1033. }
  1034. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1035. {
  1036. struct netdev_private *np = netdev_priv(dev);
  1037. strcpy(info->driver, "dl2k");
  1038. strcpy(info->version, DRV_VERSION);
  1039. strcpy(info->bus_info, pci_name(np->pdev));
  1040. }
  1041. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1042. {
  1043. struct netdev_private *np = netdev_priv(dev);
  1044. if (np->phy_media) {
  1045. /* fiber device */
  1046. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1047. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1048. cmd->port = PORT_FIBRE;
  1049. cmd->transceiver = XCVR_INTERNAL;
  1050. } else {
  1051. /* copper device */
  1052. cmd->supported = SUPPORTED_10baseT_Half |
  1053. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1054. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1055. SUPPORTED_Autoneg | SUPPORTED_MII;
  1056. cmd->advertising = ADVERTISED_10baseT_Half |
  1057. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1058. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1059. ADVERTISED_Autoneg | ADVERTISED_MII;
  1060. cmd->port = PORT_MII;
  1061. cmd->transceiver = XCVR_INTERNAL;
  1062. }
  1063. if ( np->link_status ) {
  1064. ethtool_cmd_speed_set(cmd, np->speed);
  1065. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1066. } else {
  1067. ethtool_cmd_speed_set(cmd, -1);
  1068. cmd->duplex = -1;
  1069. }
  1070. if ( np->an_enable)
  1071. cmd->autoneg = AUTONEG_ENABLE;
  1072. else
  1073. cmd->autoneg = AUTONEG_DISABLE;
  1074. cmd->phy_address = np->phy_addr;
  1075. return 0;
  1076. }
  1077. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1078. {
  1079. struct netdev_private *np = netdev_priv(dev);
  1080. netif_carrier_off(dev);
  1081. if (cmd->autoneg == AUTONEG_ENABLE) {
  1082. if (np->an_enable)
  1083. return 0;
  1084. else {
  1085. np->an_enable = 1;
  1086. mii_set_media(dev);
  1087. return 0;
  1088. }
  1089. } else {
  1090. np->an_enable = 0;
  1091. if (np->speed == 1000) {
  1092. ethtool_cmd_speed_set(cmd, SPEED_100);
  1093. cmd->duplex = DUPLEX_FULL;
  1094. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1095. }
  1096. switch (ethtool_cmd_speed(cmd)) {
  1097. case SPEED_10:
  1098. np->speed = 10;
  1099. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1100. break;
  1101. case SPEED_100:
  1102. np->speed = 100;
  1103. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1104. break;
  1105. case SPEED_1000: /* not supported */
  1106. default:
  1107. return -EINVAL;
  1108. }
  1109. mii_set_media(dev);
  1110. }
  1111. return 0;
  1112. }
  1113. static u32 rio_get_link(struct net_device *dev)
  1114. {
  1115. struct netdev_private *np = netdev_priv(dev);
  1116. return np->link_status;
  1117. }
  1118. static const struct ethtool_ops ethtool_ops = {
  1119. .get_drvinfo = rio_get_drvinfo,
  1120. .get_settings = rio_get_settings,
  1121. .set_settings = rio_set_settings,
  1122. .get_link = rio_get_link,
  1123. };
  1124. static int
  1125. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1126. {
  1127. int phy_addr;
  1128. struct netdev_private *np = netdev_priv(dev);
  1129. struct mii_ioctl_data *miidata = if_mii(rq);
  1130. phy_addr = np->phy_addr;
  1131. switch (cmd) {
  1132. case SIOCGMIIPHY:
  1133. miidata->phy_id = phy_addr;
  1134. break;
  1135. case SIOCGMIIREG:
  1136. miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
  1137. break;
  1138. case SIOCSMIIREG:
  1139. if (!capable(CAP_NET_ADMIN))
  1140. return -EPERM;
  1141. mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
  1142. break;
  1143. default:
  1144. return -EOPNOTSUPP;
  1145. }
  1146. return 0;
  1147. }
  1148. #define EEP_READ 0x0200
  1149. #define EEP_BUSY 0x8000
  1150. /* Read the EEPROM word */
  1151. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1152. static int read_eeprom(struct netdev_private *np, int eep_addr)
  1153. {
  1154. void __iomem *ioaddr = np->eeprom_addr;
  1155. int i = 1000;
  1156. dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
  1157. while (i-- > 0) {
  1158. if (!(dr16(EepromCtrl) & EEP_BUSY))
  1159. return dr16(EepromData);
  1160. }
  1161. return 0;
  1162. }
  1163. enum phy_ctrl_bits {
  1164. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1165. MII_DUPLEX = 0x08,
  1166. };
  1167. #define mii_delay() dr8(PhyCtrl)
  1168. static void
  1169. mii_sendbit (struct net_device *dev, u32 data)
  1170. {
  1171. struct netdev_private *np = netdev_priv(dev);
  1172. void __iomem *ioaddr = np->ioaddr;
  1173. data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
  1174. dw8(PhyCtrl, data);
  1175. mii_delay ();
  1176. dw8(PhyCtrl, data | MII_CLK);
  1177. mii_delay ();
  1178. }
  1179. static int
  1180. mii_getbit (struct net_device *dev)
  1181. {
  1182. struct netdev_private *np = netdev_priv(dev);
  1183. void __iomem *ioaddr = np->ioaddr;
  1184. u8 data;
  1185. data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
  1186. dw8(PhyCtrl, data);
  1187. mii_delay ();
  1188. dw8(PhyCtrl, data | MII_CLK);
  1189. mii_delay ();
  1190. return (dr8(PhyCtrl) >> 1) & 1;
  1191. }
  1192. static void
  1193. mii_send_bits (struct net_device *dev, u32 data, int len)
  1194. {
  1195. int i;
  1196. for (i = len - 1; i >= 0; i--) {
  1197. mii_sendbit (dev, data & (1 << i));
  1198. }
  1199. }
  1200. static int
  1201. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1202. {
  1203. u32 cmd;
  1204. int i;
  1205. u32 retval = 0;
  1206. /* Preamble */
  1207. mii_send_bits (dev, 0xffffffff, 32);
  1208. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1209. /* ST,OP = 0110'b for read operation */
  1210. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1211. mii_send_bits (dev, cmd, 14);
  1212. /* Turnaround */
  1213. if (mii_getbit (dev))
  1214. goto err_out;
  1215. /* Read data */
  1216. for (i = 0; i < 16; i++) {
  1217. retval |= mii_getbit (dev);
  1218. retval <<= 1;
  1219. }
  1220. /* End cycle */
  1221. mii_getbit (dev);
  1222. return (retval >> 1) & 0xffff;
  1223. err_out:
  1224. return 0;
  1225. }
  1226. static int
  1227. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1228. {
  1229. u32 cmd;
  1230. /* Preamble */
  1231. mii_send_bits (dev, 0xffffffff, 32);
  1232. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1233. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1234. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1235. mii_send_bits (dev, cmd, 32);
  1236. /* End cycle */
  1237. mii_getbit (dev);
  1238. return 0;
  1239. }
  1240. static int
  1241. mii_wait_link (struct net_device *dev, int wait)
  1242. {
  1243. __u16 bmsr;
  1244. int phy_addr;
  1245. struct netdev_private *np;
  1246. np = netdev_priv(dev);
  1247. phy_addr = np->phy_addr;
  1248. do {
  1249. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1250. if (bmsr & BMSR_LSTATUS)
  1251. return 0;
  1252. mdelay (1);
  1253. } while (--wait > 0);
  1254. return -1;
  1255. }
  1256. static int
  1257. mii_get_media (struct net_device *dev)
  1258. {
  1259. __u16 negotiate;
  1260. __u16 bmsr;
  1261. __u16 mscr;
  1262. __u16 mssr;
  1263. int phy_addr;
  1264. struct netdev_private *np;
  1265. np = netdev_priv(dev);
  1266. phy_addr = np->phy_addr;
  1267. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1268. if (np->an_enable) {
  1269. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1270. /* Auto-Negotiation not completed */
  1271. return -1;
  1272. }
  1273. negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1274. mii_read (dev, phy_addr, MII_LPA);
  1275. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1276. mssr = mii_read (dev, phy_addr, MII_STAT1000);
  1277. if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
  1278. np->speed = 1000;
  1279. np->full_duplex = 1;
  1280. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1281. } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
  1282. np->speed = 1000;
  1283. np->full_duplex = 0;
  1284. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1285. } else if (negotiate & ADVERTISE_100FULL) {
  1286. np->speed = 100;
  1287. np->full_duplex = 1;
  1288. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1289. } else if (negotiate & ADVERTISE_100HALF) {
  1290. np->speed = 100;
  1291. np->full_duplex = 0;
  1292. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1293. } else if (negotiate & ADVERTISE_10FULL) {
  1294. np->speed = 10;
  1295. np->full_duplex = 1;
  1296. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1297. } else if (negotiate & ADVERTISE_10HALF) {
  1298. np->speed = 10;
  1299. np->full_duplex = 0;
  1300. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1301. }
  1302. if (negotiate & ADVERTISE_PAUSE_CAP) {
  1303. np->tx_flow &= 1;
  1304. np->rx_flow &= 1;
  1305. } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
  1306. np->tx_flow = 0;
  1307. np->rx_flow &= 1;
  1308. }
  1309. /* else tx_flow, rx_flow = user select */
  1310. } else {
  1311. __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1312. switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
  1313. case BMCR_SPEED1000:
  1314. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1315. break;
  1316. case BMCR_SPEED100:
  1317. printk (KERN_INFO "Operating at 100 Mbps, ");
  1318. break;
  1319. case 0:
  1320. printk (KERN_INFO "Operating at 10 Mbps, ");
  1321. }
  1322. if (bmcr & BMCR_FULLDPLX) {
  1323. printk (KERN_CONT "Full duplex\n");
  1324. } else {
  1325. printk (KERN_CONT "Half duplex\n");
  1326. }
  1327. }
  1328. if (np->tx_flow)
  1329. printk(KERN_INFO "Enable Tx Flow Control\n");
  1330. else
  1331. printk(KERN_INFO "Disable Tx Flow Control\n");
  1332. if (np->rx_flow)
  1333. printk(KERN_INFO "Enable Rx Flow Control\n");
  1334. else
  1335. printk(KERN_INFO "Disable Rx Flow Control\n");
  1336. return 0;
  1337. }
  1338. static int
  1339. mii_set_media (struct net_device *dev)
  1340. {
  1341. __u16 pscr;
  1342. __u16 bmcr;
  1343. __u16 bmsr;
  1344. __u16 anar;
  1345. int phy_addr;
  1346. struct netdev_private *np;
  1347. np = netdev_priv(dev);
  1348. phy_addr = np->phy_addr;
  1349. /* Does user set speed? */
  1350. if (np->an_enable) {
  1351. /* Advertise capabilities */
  1352. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1353. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1354. ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
  1355. ADVERTISE_100HALF | ADVERTISE_10HALF |
  1356. ADVERTISE_100BASE4);
  1357. if (bmsr & BMSR_100FULL)
  1358. anar |= ADVERTISE_100FULL;
  1359. if (bmsr & BMSR_100HALF)
  1360. anar |= ADVERTISE_100HALF;
  1361. if (bmsr & BMSR_100BASE4)
  1362. anar |= ADVERTISE_100BASE4;
  1363. if (bmsr & BMSR_10FULL)
  1364. anar |= ADVERTISE_10FULL;
  1365. if (bmsr & BMSR_10HALF)
  1366. anar |= ADVERTISE_10HALF;
  1367. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1368. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1369. /* Enable Auto crossover */
  1370. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1371. pscr |= 3 << 5; /* 11'b */
  1372. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1373. /* Soft reset PHY */
  1374. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1375. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1376. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1377. mdelay(1);
  1378. } else {
  1379. /* Force speed setting */
  1380. /* 1) Disable Auto crossover */
  1381. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1382. pscr &= ~(3 << 5);
  1383. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1384. /* 2) PHY Reset */
  1385. bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1386. bmcr |= BMCR_RESET;
  1387. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1388. /* 3) Power Down */
  1389. bmcr = 0x1940; /* must be 0x1940 */
  1390. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1391. mdelay (100); /* wait a certain time */
  1392. /* 4) Advertise nothing */
  1393. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1394. /* 5) Set media and Power Up */
  1395. bmcr = BMCR_PDOWN;
  1396. if (np->speed == 100) {
  1397. bmcr |= BMCR_SPEED100;
  1398. printk (KERN_INFO "Manual 100 Mbps, ");
  1399. } else if (np->speed == 10) {
  1400. printk (KERN_INFO "Manual 10 Mbps, ");
  1401. }
  1402. if (np->full_duplex) {
  1403. bmcr |= BMCR_FULLDPLX;
  1404. printk (KERN_CONT "Full duplex\n");
  1405. } else {
  1406. printk (KERN_CONT "Half duplex\n");
  1407. }
  1408. #if 0
  1409. /* Set 1000BaseT Master/Slave setting */
  1410. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1411. mscr |= MII_MSCR_CFG_ENABLE;
  1412. mscr &= ~MII_MSCR_CFG_VALUE = 0;
  1413. #endif
  1414. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1415. mdelay(10);
  1416. }
  1417. return 0;
  1418. }
  1419. static int
  1420. mii_get_media_pcs (struct net_device *dev)
  1421. {
  1422. __u16 negotiate;
  1423. __u16 bmsr;
  1424. int phy_addr;
  1425. struct netdev_private *np;
  1426. np = netdev_priv(dev);
  1427. phy_addr = np->phy_addr;
  1428. bmsr = mii_read (dev, phy_addr, PCS_BMSR);
  1429. if (np->an_enable) {
  1430. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1431. /* Auto-Negotiation not completed */
  1432. return -1;
  1433. }
  1434. negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
  1435. mii_read (dev, phy_addr, PCS_ANLPAR);
  1436. np->speed = 1000;
  1437. if (negotiate & PCS_ANAR_FULL_DUPLEX) {
  1438. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1439. np->full_duplex = 1;
  1440. } else {
  1441. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1442. np->full_duplex = 0;
  1443. }
  1444. if (negotiate & PCS_ANAR_PAUSE) {
  1445. np->tx_flow &= 1;
  1446. np->rx_flow &= 1;
  1447. } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
  1448. np->tx_flow = 0;
  1449. np->rx_flow &= 1;
  1450. }
  1451. /* else tx_flow, rx_flow = user select */
  1452. } else {
  1453. __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
  1454. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1455. if (bmcr & BMCR_FULLDPLX) {
  1456. printk (KERN_CONT "Full duplex\n");
  1457. } else {
  1458. printk (KERN_CONT "Half duplex\n");
  1459. }
  1460. }
  1461. if (np->tx_flow)
  1462. printk(KERN_INFO "Enable Tx Flow Control\n");
  1463. else
  1464. printk(KERN_INFO "Disable Tx Flow Control\n");
  1465. if (np->rx_flow)
  1466. printk(KERN_INFO "Enable Rx Flow Control\n");
  1467. else
  1468. printk(KERN_INFO "Disable Rx Flow Control\n");
  1469. return 0;
  1470. }
  1471. static int
  1472. mii_set_media_pcs (struct net_device *dev)
  1473. {
  1474. __u16 bmcr;
  1475. __u16 esr;
  1476. __u16 anar;
  1477. int phy_addr;
  1478. struct netdev_private *np;
  1479. np = netdev_priv(dev);
  1480. phy_addr = np->phy_addr;
  1481. /* Auto-Negotiation? */
  1482. if (np->an_enable) {
  1483. /* Advertise capabilities */
  1484. esr = mii_read (dev, phy_addr, PCS_ESR);
  1485. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1486. ~PCS_ANAR_HALF_DUPLEX &
  1487. ~PCS_ANAR_FULL_DUPLEX;
  1488. if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
  1489. anar |= PCS_ANAR_HALF_DUPLEX;
  1490. if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
  1491. anar |= PCS_ANAR_FULL_DUPLEX;
  1492. anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
  1493. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1494. /* Soft reset PHY */
  1495. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1496. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1497. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1498. mdelay(1);
  1499. } else {
  1500. /* Force speed setting */
  1501. /* PHY Reset */
  1502. bmcr = BMCR_RESET;
  1503. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1504. mdelay(10);
  1505. if (np->full_duplex) {
  1506. bmcr = BMCR_FULLDPLX;
  1507. printk (KERN_INFO "Manual full duplex\n");
  1508. } else {
  1509. bmcr = 0;
  1510. printk (KERN_INFO "Manual half duplex\n");
  1511. }
  1512. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1513. mdelay(10);
  1514. /* Advertise nothing */
  1515. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1516. }
  1517. return 0;
  1518. }
  1519. static int
  1520. rio_close (struct net_device *dev)
  1521. {
  1522. struct netdev_private *np = netdev_priv(dev);
  1523. void __iomem *ioaddr = np->ioaddr;
  1524. struct pci_dev *pdev = np->pdev;
  1525. struct sk_buff *skb;
  1526. int i;
  1527. netif_stop_queue (dev);
  1528. /* Disable interrupts */
  1529. dw16(IntEnable, 0);
  1530. /* Stop Tx and Rx logics */
  1531. dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
  1532. free_irq(pdev->irq, dev);
  1533. del_timer_sync (&np->timer);
  1534. /* Free all the skbuffs in the queue. */
  1535. for (i = 0; i < RX_RING_SIZE; i++) {
  1536. skb = np->rx_skbuff[i];
  1537. if (skb) {
  1538. pci_unmap_single(pdev, desc_to_dma(&np->rx_ring[i]),
  1539. skb->len, PCI_DMA_FROMDEVICE);
  1540. dev_kfree_skb (skb);
  1541. np->rx_skbuff[i] = NULL;
  1542. }
  1543. np->rx_ring[i].status = 0;
  1544. np->rx_ring[i].fraginfo = 0;
  1545. }
  1546. for (i = 0; i < TX_RING_SIZE; i++) {
  1547. skb = np->tx_skbuff[i];
  1548. if (skb) {
  1549. pci_unmap_single(pdev, desc_to_dma(&np->tx_ring[i]),
  1550. skb->len, PCI_DMA_TODEVICE);
  1551. dev_kfree_skb (skb);
  1552. np->tx_skbuff[i] = NULL;
  1553. }
  1554. }
  1555. return 0;
  1556. }
  1557. static void __devexit
  1558. rio_remove1 (struct pci_dev *pdev)
  1559. {
  1560. struct net_device *dev = pci_get_drvdata (pdev);
  1561. if (dev) {
  1562. struct netdev_private *np = netdev_priv(dev);
  1563. unregister_netdev (dev);
  1564. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1565. np->rx_ring_dma);
  1566. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1567. np->tx_ring_dma);
  1568. #ifdef MEM_MAPPING
  1569. pci_iounmap(pdev, np->ioaddr);
  1570. #endif
  1571. pci_iounmap(pdev, np->eeprom_addr);
  1572. free_netdev (dev);
  1573. pci_release_regions (pdev);
  1574. pci_disable_device (pdev);
  1575. }
  1576. pci_set_drvdata (pdev, NULL);
  1577. }
  1578. static struct pci_driver rio_driver = {
  1579. .name = "dl2k",
  1580. .id_table = rio_pci_tbl,
  1581. .probe = rio_probe1,
  1582. .remove = __devexit_p(rio_remove1),
  1583. };
  1584. static int __init
  1585. rio_init (void)
  1586. {
  1587. return pci_register_driver(&rio_driver);
  1588. }
  1589. static void __exit
  1590. rio_exit (void)
  1591. {
  1592. pci_unregister_driver (&rio_driver);
  1593. }
  1594. module_init (rio_init);
  1595. module_exit (rio_exit);
  1596. /*
  1597. Compile command:
  1598. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1599. Read Documentation/networking/dl2k.txt for details.
  1600. */