cnic.c 144 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  47. #include "cnic.h"
  48. #include "cnic_defs.h"
  49. #define DRV_MODULE_NAME "cnic"
  50. static char version[] __devinitdata =
  51. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  52. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  53. "Chen (zongxi@broadcom.com");
  54. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  55. MODULE_LICENSE("GPL");
  56. MODULE_VERSION(CNIC_MODULE_VERSION);
  57. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  58. static LIST_HEAD(cnic_dev_list);
  59. static LIST_HEAD(cnic_udev_list);
  60. static DEFINE_RWLOCK(cnic_dev_lock);
  61. static DEFINE_MUTEX(cnic_lock);
  62. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  63. /* helper function, assuming cnic_lock is held */
  64. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  65. {
  66. return rcu_dereference_protected(cnic_ulp_tbl[type],
  67. lockdep_is_held(&cnic_lock));
  68. }
  69. static int cnic_service_bnx2(void *, void *);
  70. static int cnic_service_bnx2x(void *, void *);
  71. static int cnic_ctl(void *, struct cnic_ctl_info *);
  72. static struct cnic_ops cnic_bnx2_ops = {
  73. .cnic_owner = THIS_MODULE,
  74. .cnic_handler = cnic_service_bnx2,
  75. .cnic_ctl = cnic_ctl,
  76. };
  77. static struct cnic_ops cnic_bnx2x_ops = {
  78. .cnic_owner = THIS_MODULE,
  79. .cnic_handler = cnic_service_bnx2x,
  80. .cnic_ctl = cnic_ctl,
  81. };
  82. static struct workqueue_struct *cnic_wq;
  83. static void cnic_shutdown_rings(struct cnic_dev *);
  84. static void cnic_init_rings(struct cnic_dev *);
  85. static int cnic_cm_set_pg(struct cnic_sock *);
  86. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  87. {
  88. struct cnic_uio_dev *udev = uinfo->priv;
  89. struct cnic_dev *dev;
  90. if (!capable(CAP_NET_ADMIN))
  91. return -EPERM;
  92. if (udev->uio_dev != -1)
  93. return -EBUSY;
  94. rtnl_lock();
  95. dev = udev->dev;
  96. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  97. rtnl_unlock();
  98. return -ENODEV;
  99. }
  100. udev->uio_dev = iminor(inode);
  101. cnic_shutdown_rings(dev);
  102. cnic_init_rings(dev);
  103. rtnl_unlock();
  104. return 0;
  105. }
  106. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  107. {
  108. struct cnic_uio_dev *udev = uinfo->priv;
  109. udev->uio_dev = -1;
  110. return 0;
  111. }
  112. static inline void cnic_hold(struct cnic_dev *dev)
  113. {
  114. atomic_inc(&dev->ref_count);
  115. }
  116. static inline void cnic_put(struct cnic_dev *dev)
  117. {
  118. atomic_dec(&dev->ref_count);
  119. }
  120. static inline void csk_hold(struct cnic_sock *csk)
  121. {
  122. atomic_inc(&csk->ref_count);
  123. }
  124. static inline void csk_put(struct cnic_sock *csk)
  125. {
  126. atomic_dec(&csk->ref_count);
  127. }
  128. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  129. {
  130. struct cnic_dev *cdev;
  131. read_lock(&cnic_dev_lock);
  132. list_for_each_entry(cdev, &cnic_dev_list, list) {
  133. if (netdev == cdev->netdev) {
  134. cnic_hold(cdev);
  135. read_unlock(&cnic_dev_lock);
  136. return cdev;
  137. }
  138. }
  139. read_unlock(&cnic_dev_lock);
  140. return NULL;
  141. }
  142. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  143. {
  144. atomic_inc(&ulp_ops->ref_count);
  145. }
  146. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_dec(&ulp_ops->ref_count);
  149. }
  150. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTX_WR_CMD;
  157. io->cid_addr = cid_addr;
  158. io->offset = off;
  159. io->data = val;
  160. ethdev->drv_ctl(dev->netdev, &info);
  161. }
  162. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  163. {
  164. struct cnic_local *cp = dev->cnic_priv;
  165. struct cnic_eth_dev *ethdev = cp->ethdev;
  166. struct drv_ctl_info info;
  167. struct drv_ctl_io *io = &info.data.io;
  168. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  169. io->offset = off;
  170. io->dma_addr = addr;
  171. ethdev->drv_ctl(dev->netdev, &info);
  172. }
  173. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  174. {
  175. struct cnic_local *cp = dev->cnic_priv;
  176. struct cnic_eth_dev *ethdev = cp->ethdev;
  177. struct drv_ctl_info info;
  178. struct drv_ctl_l2_ring *ring = &info.data.ring;
  179. if (start)
  180. info.cmd = DRV_CTL_START_L2_CMD;
  181. else
  182. info.cmd = DRV_CTL_STOP_L2_CMD;
  183. ring->cid = cid;
  184. ring->client_id = cl_id;
  185. ethdev->drv_ctl(dev->netdev, &info);
  186. }
  187. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  188. {
  189. struct cnic_local *cp = dev->cnic_priv;
  190. struct cnic_eth_dev *ethdev = cp->ethdev;
  191. struct drv_ctl_info info;
  192. struct drv_ctl_io *io = &info.data.io;
  193. info.cmd = DRV_CTL_IO_WR_CMD;
  194. io->offset = off;
  195. io->data = val;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. }
  198. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  199. {
  200. struct cnic_local *cp = dev->cnic_priv;
  201. struct cnic_eth_dev *ethdev = cp->ethdev;
  202. struct drv_ctl_info info;
  203. struct drv_ctl_io *io = &info.data.io;
  204. info.cmd = DRV_CTL_IO_RD_CMD;
  205. io->offset = off;
  206. ethdev->drv_ctl(dev->netdev, &info);
  207. return io->data;
  208. }
  209. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  210. {
  211. struct cnic_local *cp = dev->cnic_priv;
  212. struct cnic_eth_dev *ethdev = cp->ethdev;
  213. struct drv_ctl_info info;
  214. if (reg)
  215. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  216. else
  217. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  218. info.data.ulp_type = ulp_type;
  219. ethdev->drv_ctl(dev->netdev, &info);
  220. }
  221. static int cnic_in_use(struct cnic_sock *csk)
  222. {
  223. return test_bit(SK_F_INUSE, &csk->flags);
  224. }
  225. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  226. {
  227. struct cnic_local *cp = dev->cnic_priv;
  228. struct cnic_eth_dev *ethdev = cp->ethdev;
  229. struct drv_ctl_info info;
  230. info.cmd = cmd;
  231. info.data.credit.credit_count = count;
  232. ethdev->drv_ctl(dev->netdev, &info);
  233. }
  234. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  235. {
  236. u32 i;
  237. for (i = 0; i < cp->max_cid_space; i++) {
  238. if (cp->ctx_tbl[i].cid == cid) {
  239. *l5_cid = i;
  240. return 0;
  241. }
  242. }
  243. return -EINVAL;
  244. }
  245. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  246. struct cnic_sock *csk)
  247. {
  248. struct iscsi_path path_req;
  249. char *buf = NULL;
  250. u16 len = 0;
  251. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  252. struct cnic_ulp_ops *ulp_ops;
  253. struct cnic_uio_dev *udev = cp->udev;
  254. int rc = 0, retry = 0;
  255. if (!udev || udev->uio_dev == -1)
  256. return -ENODEV;
  257. if (csk) {
  258. len = sizeof(path_req);
  259. buf = (char *) &path_req;
  260. memset(&path_req, 0, len);
  261. msg_type = ISCSI_KEVENT_PATH_REQ;
  262. path_req.handle = (u64) csk->l5_cid;
  263. if (test_bit(SK_F_IPV6, &csk->flags)) {
  264. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  265. sizeof(struct in6_addr));
  266. path_req.ip_addr_len = 16;
  267. } else {
  268. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  269. sizeof(struct in_addr));
  270. path_req.ip_addr_len = 4;
  271. }
  272. path_req.vlan_id = csk->vlan_id;
  273. path_req.pmtu = csk->mtu;
  274. }
  275. while (retry < 3) {
  276. rc = 0;
  277. rcu_read_lock();
  278. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  279. if (ulp_ops)
  280. rc = ulp_ops->iscsi_nl_send_msg(
  281. cp->ulp_handle[CNIC_ULP_ISCSI],
  282. msg_type, buf, len);
  283. rcu_read_unlock();
  284. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  285. break;
  286. msleep(100);
  287. retry++;
  288. }
  289. return rc;
  290. }
  291. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  292. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  293. char *buf, u16 len)
  294. {
  295. int rc = -EINVAL;
  296. switch (msg_type) {
  297. case ISCSI_UEVENT_PATH_UPDATE: {
  298. struct cnic_local *cp;
  299. u32 l5_cid;
  300. struct cnic_sock *csk;
  301. struct iscsi_path *path_resp;
  302. if (len < sizeof(*path_resp))
  303. break;
  304. path_resp = (struct iscsi_path *) buf;
  305. cp = dev->cnic_priv;
  306. l5_cid = (u32) path_resp->handle;
  307. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  308. break;
  309. rcu_read_lock();
  310. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  311. rc = -ENODEV;
  312. rcu_read_unlock();
  313. break;
  314. }
  315. csk = &cp->csk_tbl[l5_cid];
  316. csk_hold(csk);
  317. if (cnic_in_use(csk) &&
  318. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  319. csk->vlan_id = path_resp->vlan_id;
  320. memcpy(csk->ha, path_resp->mac_addr, 6);
  321. if (test_bit(SK_F_IPV6, &csk->flags))
  322. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  323. sizeof(struct in6_addr));
  324. else
  325. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  326. sizeof(struct in_addr));
  327. if (is_valid_ether_addr(csk->ha)) {
  328. cnic_cm_set_pg(csk);
  329. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  330. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  331. cnic_cm_upcall(cp, csk,
  332. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  333. clear_bit(SK_F_CONNECT_START, &csk->flags);
  334. }
  335. }
  336. csk_put(csk);
  337. rcu_read_unlock();
  338. rc = 0;
  339. }
  340. }
  341. return rc;
  342. }
  343. static int cnic_offld_prep(struct cnic_sock *csk)
  344. {
  345. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  346. return 0;
  347. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  348. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  349. return 0;
  350. }
  351. return 1;
  352. }
  353. static int cnic_close_prep(struct cnic_sock *csk)
  354. {
  355. clear_bit(SK_F_CONNECT_START, &csk->flags);
  356. smp_mb__after_clear_bit();
  357. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  358. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  359. msleep(1);
  360. return 1;
  361. }
  362. return 0;
  363. }
  364. static int cnic_abort_prep(struct cnic_sock *csk)
  365. {
  366. clear_bit(SK_F_CONNECT_START, &csk->flags);
  367. smp_mb__after_clear_bit();
  368. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  369. msleep(1);
  370. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  371. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  372. return 1;
  373. }
  374. return 0;
  375. }
  376. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  377. {
  378. struct cnic_dev *dev;
  379. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  380. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  381. return -EINVAL;
  382. }
  383. mutex_lock(&cnic_lock);
  384. if (cnic_ulp_tbl_prot(ulp_type)) {
  385. pr_err("%s: Type %d has already been registered\n",
  386. __func__, ulp_type);
  387. mutex_unlock(&cnic_lock);
  388. return -EBUSY;
  389. }
  390. read_lock(&cnic_dev_lock);
  391. list_for_each_entry(dev, &cnic_dev_list, list) {
  392. struct cnic_local *cp = dev->cnic_priv;
  393. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  394. }
  395. read_unlock(&cnic_dev_lock);
  396. atomic_set(&ulp_ops->ref_count, 0);
  397. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  398. mutex_unlock(&cnic_lock);
  399. /* Prevent race conditions with netdev_event */
  400. rtnl_lock();
  401. list_for_each_entry(dev, &cnic_dev_list, list) {
  402. struct cnic_local *cp = dev->cnic_priv;
  403. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  404. ulp_ops->cnic_init(dev);
  405. }
  406. rtnl_unlock();
  407. return 0;
  408. }
  409. int cnic_unregister_driver(int ulp_type)
  410. {
  411. struct cnic_dev *dev;
  412. struct cnic_ulp_ops *ulp_ops;
  413. int i = 0;
  414. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  415. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  416. return -EINVAL;
  417. }
  418. mutex_lock(&cnic_lock);
  419. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  420. if (!ulp_ops) {
  421. pr_err("%s: Type %d has not been registered\n",
  422. __func__, ulp_type);
  423. goto out_unlock;
  424. }
  425. read_lock(&cnic_dev_lock);
  426. list_for_each_entry(dev, &cnic_dev_list, list) {
  427. struct cnic_local *cp = dev->cnic_priv;
  428. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  429. pr_err("%s: Type %d still has devices registered\n",
  430. __func__, ulp_type);
  431. read_unlock(&cnic_dev_lock);
  432. goto out_unlock;
  433. }
  434. }
  435. read_unlock(&cnic_dev_lock);
  436. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  437. mutex_unlock(&cnic_lock);
  438. synchronize_rcu();
  439. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  440. msleep(100);
  441. i++;
  442. }
  443. if (atomic_read(&ulp_ops->ref_count) != 0)
  444. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  445. return 0;
  446. out_unlock:
  447. mutex_unlock(&cnic_lock);
  448. return -EINVAL;
  449. }
  450. static int cnic_start_hw(struct cnic_dev *);
  451. static void cnic_stop_hw(struct cnic_dev *);
  452. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  453. void *ulp_ctx)
  454. {
  455. struct cnic_local *cp = dev->cnic_priv;
  456. struct cnic_ulp_ops *ulp_ops;
  457. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  458. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  459. return -EINVAL;
  460. }
  461. mutex_lock(&cnic_lock);
  462. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  463. pr_err("%s: Driver with type %d has not been registered\n",
  464. __func__, ulp_type);
  465. mutex_unlock(&cnic_lock);
  466. return -EAGAIN;
  467. }
  468. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  469. pr_err("%s: Type %d has already been registered to this device\n",
  470. __func__, ulp_type);
  471. mutex_unlock(&cnic_lock);
  472. return -EBUSY;
  473. }
  474. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  475. cp->ulp_handle[ulp_type] = ulp_ctx;
  476. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  477. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  478. cnic_hold(dev);
  479. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  480. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  481. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  482. mutex_unlock(&cnic_lock);
  483. cnic_ulp_ctl(dev, ulp_type, true);
  484. return 0;
  485. }
  486. EXPORT_SYMBOL(cnic_register_driver);
  487. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  488. {
  489. struct cnic_local *cp = dev->cnic_priv;
  490. int i = 0;
  491. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  492. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  493. return -EINVAL;
  494. }
  495. mutex_lock(&cnic_lock);
  496. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  497. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  498. cnic_put(dev);
  499. } else {
  500. pr_err("%s: device not registered to this ulp type %d\n",
  501. __func__, ulp_type);
  502. mutex_unlock(&cnic_lock);
  503. return -EINVAL;
  504. }
  505. mutex_unlock(&cnic_lock);
  506. if (ulp_type == CNIC_ULP_ISCSI)
  507. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  508. synchronize_rcu();
  509. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  510. i < 20) {
  511. msleep(100);
  512. i++;
  513. }
  514. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  515. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  516. cnic_ulp_ctl(dev, ulp_type, false);
  517. return 0;
  518. }
  519. EXPORT_SYMBOL(cnic_unregister_driver);
  520. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  521. u32 next)
  522. {
  523. id_tbl->start = start_id;
  524. id_tbl->max = size;
  525. id_tbl->next = next;
  526. spin_lock_init(&id_tbl->lock);
  527. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  528. if (!id_tbl->table)
  529. return -ENOMEM;
  530. return 0;
  531. }
  532. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  533. {
  534. kfree(id_tbl->table);
  535. id_tbl->table = NULL;
  536. }
  537. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  538. {
  539. int ret = -1;
  540. id -= id_tbl->start;
  541. if (id >= id_tbl->max)
  542. return ret;
  543. spin_lock(&id_tbl->lock);
  544. if (!test_bit(id, id_tbl->table)) {
  545. set_bit(id, id_tbl->table);
  546. ret = 0;
  547. }
  548. spin_unlock(&id_tbl->lock);
  549. return ret;
  550. }
  551. /* Returns -1 if not successful */
  552. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  553. {
  554. u32 id;
  555. spin_lock(&id_tbl->lock);
  556. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  557. if (id >= id_tbl->max) {
  558. id = -1;
  559. if (id_tbl->next != 0) {
  560. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  561. if (id >= id_tbl->next)
  562. id = -1;
  563. }
  564. }
  565. if (id < id_tbl->max) {
  566. set_bit(id, id_tbl->table);
  567. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  568. id += id_tbl->start;
  569. }
  570. spin_unlock(&id_tbl->lock);
  571. return id;
  572. }
  573. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  574. {
  575. if (id == -1)
  576. return;
  577. id -= id_tbl->start;
  578. if (id >= id_tbl->max)
  579. return;
  580. clear_bit(id, id_tbl->table);
  581. }
  582. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  583. {
  584. int i;
  585. if (!dma->pg_arr)
  586. return;
  587. for (i = 0; i < dma->num_pages; i++) {
  588. if (dma->pg_arr[i]) {
  589. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  590. dma->pg_arr[i], dma->pg_map_arr[i]);
  591. dma->pg_arr[i] = NULL;
  592. }
  593. }
  594. if (dma->pgtbl) {
  595. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  596. dma->pgtbl, dma->pgtbl_map);
  597. dma->pgtbl = NULL;
  598. }
  599. kfree(dma->pg_arr);
  600. dma->pg_arr = NULL;
  601. dma->num_pages = 0;
  602. }
  603. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  604. {
  605. int i;
  606. __le32 *page_table = (__le32 *) dma->pgtbl;
  607. for (i = 0; i < dma->num_pages; i++) {
  608. /* Each entry needs to be in big endian format. */
  609. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  610. page_table++;
  611. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  612. page_table++;
  613. }
  614. }
  615. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  616. {
  617. int i;
  618. __le32 *page_table = (__le32 *) dma->pgtbl;
  619. for (i = 0; i < dma->num_pages; i++) {
  620. /* Each entry needs to be in little endian format. */
  621. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  622. page_table++;
  623. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  624. page_table++;
  625. }
  626. }
  627. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  628. int pages, int use_pg_tbl)
  629. {
  630. int i, size;
  631. struct cnic_local *cp = dev->cnic_priv;
  632. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  633. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  634. if (dma->pg_arr == NULL)
  635. return -ENOMEM;
  636. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  637. dma->num_pages = pages;
  638. for (i = 0; i < pages; i++) {
  639. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  640. BCM_PAGE_SIZE,
  641. &dma->pg_map_arr[i],
  642. GFP_ATOMIC);
  643. if (dma->pg_arr[i] == NULL)
  644. goto error;
  645. }
  646. if (!use_pg_tbl)
  647. return 0;
  648. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  649. ~(BCM_PAGE_SIZE - 1);
  650. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  651. &dma->pgtbl_map, GFP_ATOMIC);
  652. if (dma->pgtbl == NULL)
  653. goto error;
  654. cp->setup_pgtbl(dev, dma);
  655. return 0;
  656. error:
  657. cnic_free_dma(dev, dma);
  658. return -ENOMEM;
  659. }
  660. static void cnic_free_context(struct cnic_dev *dev)
  661. {
  662. struct cnic_local *cp = dev->cnic_priv;
  663. int i;
  664. for (i = 0; i < cp->ctx_blks; i++) {
  665. if (cp->ctx_arr[i].ctx) {
  666. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  667. cp->ctx_arr[i].ctx,
  668. cp->ctx_arr[i].mapping);
  669. cp->ctx_arr[i].ctx = NULL;
  670. }
  671. }
  672. }
  673. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  674. {
  675. uio_unregister_device(&udev->cnic_uinfo);
  676. if (udev->l2_buf) {
  677. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  678. udev->l2_buf, udev->l2_buf_map);
  679. udev->l2_buf = NULL;
  680. }
  681. if (udev->l2_ring) {
  682. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  683. udev->l2_ring, udev->l2_ring_map);
  684. udev->l2_ring = NULL;
  685. }
  686. pci_dev_put(udev->pdev);
  687. kfree(udev);
  688. }
  689. static void cnic_free_uio(struct cnic_uio_dev *udev)
  690. {
  691. if (!udev)
  692. return;
  693. write_lock(&cnic_dev_lock);
  694. list_del_init(&udev->list);
  695. write_unlock(&cnic_dev_lock);
  696. __cnic_free_uio(udev);
  697. }
  698. static void cnic_free_resc(struct cnic_dev *dev)
  699. {
  700. struct cnic_local *cp = dev->cnic_priv;
  701. struct cnic_uio_dev *udev = cp->udev;
  702. if (udev) {
  703. udev->dev = NULL;
  704. cp->udev = NULL;
  705. }
  706. cnic_free_context(dev);
  707. kfree(cp->ctx_arr);
  708. cp->ctx_arr = NULL;
  709. cp->ctx_blks = 0;
  710. cnic_free_dma(dev, &cp->gbl_buf_info);
  711. cnic_free_dma(dev, &cp->kwq_info);
  712. cnic_free_dma(dev, &cp->kwq_16_data_info);
  713. cnic_free_dma(dev, &cp->kcq2.dma);
  714. cnic_free_dma(dev, &cp->kcq1.dma);
  715. kfree(cp->iscsi_tbl);
  716. cp->iscsi_tbl = NULL;
  717. kfree(cp->ctx_tbl);
  718. cp->ctx_tbl = NULL;
  719. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  720. cnic_free_id_tbl(&cp->cid_tbl);
  721. }
  722. static int cnic_alloc_context(struct cnic_dev *dev)
  723. {
  724. struct cnic_local *cp = dev->cnic_priv;
  725. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  726. int i, k, arr_size;
  727. cp->ctx_blk_size = BCM_PAGE_SIZE;
  728. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  729. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  730. sizeof(struct cnic_ctx);
  731. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  732. if (cp->ctx_arr == NULL)
  733. return -ENOMEM;
  734. k = 0;
  735. for (i = 0; i < 2; i++) {
  736. u32 j, reg, off, lo, hi;
  737. if (i == 0)
  738. off = BNX2_PG_CTX_MAP;
  739. else
  740. off = BNX2_ISCSI_CTX_MAP;
  741. reg = cnic_reg_rd_ind(dev, off);
  742. lo = reg >> 16;
  743. hi = reg & 0xffff;
  744. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  745. cp->ctx_arr[k].cid = j;
  746. }
  747. cp->ctx_blks = k;
  748. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  749. cp->ctx_blks = 0;
  750. return -ENOMEM;
  751. }
  752. for (i = 0; i < cp->ctx_blks; i++) {
  753. cp->ctx_arr[i].ctx =
  754. dma_alloc_coherent(&dev->pcidev->dev,
  755. BCM_PAGE_SIZE,
  756. &cp->ctx_arr[i].mapping,
  757. GFP_KERNEL);
  758. if (cp->ctx_arr[i].ctx == NULL)
  759. return -ENOMEM;
  760. }
  761. }
  762. return 0;
  763. }
  764. static u16 cnic_bnx2_next_idx(u16 idx)
  765. {
  766. return idx + 1;
  767. }
  768. static u16 cnic_bnx2_hw_idx(u16 idx)
  769. {
  770. return idx;
  771. }
  772. static u16 cnic_bnx2x_next_idx(u16 idx)
  773. {
  774. idx++;
  775. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  776. idx++;
  777. return idx;
  778. }
  779. static u16 cnic_bnx2x_hw_idx(u16 idx)
  780. {
  781. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  782. idx++;
  783. return idx;
  784. }
  785. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  786. bool use_pg_tbl)
  787. {
  788. int err, i, use_page_tbl = 0;
  789. struct kcqe **kcq;
  790. if (use_pg_tbl)
  791. use_page_tbl = 1;
  792. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  793. if (err)
  794. return err;
  795. kcq = (struct kcqe **) info->dma.pg_arr;
  796. info->kcq = kcq;
  797. info->next_idx = cnic_bnx2_next_idx;
  798. info->hw_idx = cnic_bnx2_hw_idx;
  799. if (use_pg_tbl)
  800. return 0;
  801. info->next_idx = cnic_bnx2x_next_idx;
  802. info->hw_idx = cnic_bnx2x_hw_idx;
  803. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  804. struct bnx2x_bd_chain_next *next =
  805. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  806. int j = i + 1;
  807. if (j >= KCQ_PAGE_CNT)
  808. j = 0;
  809. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  810. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  811. }
  812. return 0;
  813. }
  814. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  815. {
  816. struct cnic_local *cp = dev->cnic_priv;
  817. struct cnic_uio_dev *udev;
  818. read_lock(&cnic_dev_lock);
  819. list_for_each_entry(udev, &cnic_udev_list, list) {
  820. if (udev->pdev == dev->pcidev) {
  821. udev->dev = dev;
  822. cp->udev = udev;
  823. read_unlock(&cnic_dev_lock);
  824. return 0;
  825. }
  826. }
  827. read_unlock(&cnic_dev_lock);
  828. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  829. if (!udev)
  830. return -ENOMEM;
  831. udev->uio_dev = -1;
  832. udev->dev = dev;
  833. udev->pdev = dev->pcidev;
  834. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  835. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  836. &udev->l2_ring_map,
  837. GFP_KERNEL | __GFP_COMP);
  838. if (!udev->l2_ring)
  839. goto err_udev;
  840. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  841. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  842. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  843. &udev->l2_buf_map,
  844. GFP_KERNEL | __GFP_COMP);
  845. if (!udev->l2_buf)
  846. goto err_dma;
  847. write_lock(&cnic_dev_lock);
  848. list_add(&udev->list, &cnic_udev_list);
  849. write_unlock(&cnic_dev_lock);
  850. pci_dev_get(udev->pdev);
  851. cp->udev = udev;
  852. return 0;
  853. err_dma:
  854. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  855. udev->l2_ring, udev->l2_ring_map);
  856. err_udev:
  857. kfree(udev);
  858. return -ENOMEM;
  859. }
  860. static int cnic_init_uio(struct cnic_dev *dev)
  861. {
  862. struct cnic_local *cp = dev->cnic_priv;
  863. struct cnic_uio_dev *udev = cp->udev;
  864. struct uio_info *uinfo;
  865. int ret = 0;
  866. if (!udev)
  867. return -ENOMEM;
  868. uinfo = &udev->cnic_uinfo;
  869. uinfo->mem[0].addr = dev->netdev->base_addr;
  870. uinfo->mem[0].internal_addr = dev->regview;
  871. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  872. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  873. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  874. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  875. PAGE_MASK;
  876. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  877. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  878. else
  879. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  880. uinfo->name = "bnx2_cnic";
  881. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  882. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  883. PAGE_MASK;
  884. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  885. uinfo->name = "bnx2x_cnic";
  886. }
  887. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  888. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  889. uinfo->mem[2].size = udev->l2_ring_size;
  890. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  891. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  892. uinfo->mem[3].size = udev->l2_buf_size;
  893. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  894. uinfo->version = CNIC_MODULE_VERSION;
  895. uinfo->irq = UIO_IRQ_CUSTOM;
  896. uinfo->open = cnic_uio_open;
  897. uinfo->release = cnic_uio_close;
  898. if (udev->uio_dev == -1) {
  899. if (!uinfo->priv) {
  900. uinfo->priv = udev;
  901. ret = uio_register_device(&udev->pdev->dev, uinfo);
  902. }
  903. } else {
  904. cnic_init_rings(dev);
  905. }
  906. return ret;
  907. }
  908. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  909. {
  910. struct cnic_local *cp = dev->cnic_priv;
  911. int ret;
  912. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  913. if (ret)
  914. goto error;
  915. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  916. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  917. if (ret)
  918. goto error;
  919. ret = cnic_alloc_context(dev);
  920. if (ret)
  921. goto error;
  922. ret = cnic_alloc_uio_rings(dev, 2);
  923. if (ret)
  924. goto error;
  925. ret = cnic_init_uio(dev);
  926. if (ret)
  927. goto error;
  928. return 0;
  929. error:
  930. cnic_free_resc(dev);
  931. return ret;
  932. }
  933. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  934. {
  935. struct cnic_local *cp = dev->cnic_priv;
  936. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  937. int total_mem, blks, i;
  938. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  939. blks = total_mem / ctx_blk_size;
  940. if (total_mem % ctx_blk_size)
  941. blks++;
  942. if (blks > cp->ethdev->ctx_tbl_len)
  943. return -ENOMEM;
  944. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  945. if (cp->ctx_arr == NULL)
  946. return -ENOMEM;
  947. cp->ctx_blks = blks;
  948. cp->ctx_blk_size = ctx_blk_size;
  949. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  950. cp->ctx_align = 0;
  951. else
  952. cp->ctx_align = ctx_blk_size;
  953. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  954. for (i = 0; i < blks; i++) {
  955. cp->ctx_arr[i].ctx =
  956. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  957. &cp->ctx_arr[i].mapping,
  958. GFP_KERNEL);
  959. if (cp->ctx_arr[i].ctx == NULL)
  960. return -ENOMEM;
  961. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  962. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  963. cnic_free_context(dev);
  964. cp->ctx_blk_size += cp->ctx_align;
  965. i = -1;
  966. continue;
  967. }
  968. }
  969. }
  970. return 0;
  971. }
  972. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  973. {
  974. struct cnic_local *cp = dev->cnic_priv;
  975. struct cnic_eth_dev *ethdev = cp->ethdev;
  976. u32 start_cid = ethdev->starting_cid;
  977. int i, j, n, ret, pages;
  978. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  979. cp->iro_arr = ethdev->iro_arr;
  980. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  981. cp->iscsi_start_cid = start_cid;
  982. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  983. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  984. cp->max_cid_space += dev->max_fcoe_conn;
  985. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  986. if (!cp->fcoe_init_cid)
  987. cp->fcoe_init_cid = 0x10;
  988. }
  989. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  990. GFP_KERNEL);
  991. if (!cp->iscsi_tbl)
  992. goto error;
  993. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  994. cp->max_cid_space, GFP_KERNEL);
  995. if (!cp->ctx_tbl)
  996. goto error;
  997. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  998. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  999. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1000. }
  1001. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1002. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1003. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1004. PAGE_SIZE;
  1005. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1006. if (ret)
  1007. return -ENOMEM;
  1008. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1009. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1010. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1011. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1012. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1013. off;
  1014. if ((i % n) == (n - 1))
  1015. j++;
  1016. }
  1017. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1018. if (ret)
  1019. goto error;
  1020. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1021. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1022. if (ret)
  1023. goto error;
  1024. }
  1025. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1026. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1027. if (ret)
  1028. goto error;
  1029. ret = cnic_alloc_bnx2x_context(dev);
  1030. if (ret)
  1031. goto error;
  1032. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1033. cp->l2_rx_ring_size = 15;
  1034. ret = cnic_alloc_uio_rings(dev, 4);
  1035. if (ret)
  1036. goto error;
  1037. ret = cnic_init_uio(dev);
  1038. if (ret)
  1039. goto error;
  1040. return 0;
  1041. error:
  1042. cnic_free_resc(dev);
  1043. return -ENOMEM;
  1044. }
  1045. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1046. {
  1047. return cp->max_kwq_idx -
  1048. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1049. }
  1050. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1051. u32 num_wqes)
  1052. {
  1053. struct cnic_local *cp = dev->cnic_priv;
  1054. struct kwqe *prod_qe;
  1055. u16 prod, sw_prod, i;
  1056. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1057. return -EAGAIN; /* bnx2 is down */
  1058. spin_lock_bh(&cp->cnic_ulp_lock);
  1059. if (num_wqes > cnic_kwq_avail(cp) &&
  1060. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1061. spin_unlock_bh(&cp->cnic_ulp_lock);
  1062. return -EAGAIN;
  1063. }
  1064. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1065. prod = cp->kwq_prod_idx;
  1066. sw_prod = prod & MAX_KWQ_IDX;
  1067. for (i = 0; i < num_wqes; i++) {
  1068. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1069. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1070. prod++;
  1071. sw_prod = prod & MAX_KWQ_IDX;
  1072. }
  1073. cp->kwq_prod_idx = prod;
  1074. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1075. spin_unlock_bh(&cp->cnic_ulp_lock);
  1076. return 0;
  1077. }
  1078. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1079. union l5cm_specific_data *l5_data)
  1080. {
  1081. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1082. dma_addr_t map;
  1083. map = ctx->kwqe_data_mapping;
  1084. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1085. l5_data->phy_address.hi = (u64) map >> 32;
  1086. return ctx->kwqe_data;
  1087. }
  1088. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1089. u32 type, union l5cm_specific_data *l5_data)
  1090. {
  1091. struct cnic_local *cp = dev->cnic_priv;
  1092. struct l5cm_spe kwqe;
  1093. struct kwqe_16 *kwq[1];
  1094. u16 type_16;
  1095. int ret;
  1096. kwqe.hdr.conn_and_cmd_data =
  1097. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1098. BNX2X_HW_CID(cp, cid)));
  1099. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1100. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1101. SPE_HDR_FUNCTION_ID;
  1102. kwqe.hdr.type = cpu_to_le16(type_16);
  1103. kwqe.hdr.reserved1 = 0;
  1104. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1105. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1106. kwq[0] = (struct kwqe_16 *) &kwqe;
  1107. spin_lock_bh(&cp->cnic_ulp_lock);
  1108. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1109. spin_unlock_bh(&cp->cnic_ulp_lock);
  1110. if (ret == 1)
  1111. return 0;
  1112. return ret;
  1113. }
  1114. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1115. struct kcqe *cqes[], u32 num_cqes)
  1116. {
  1117. struct cnic_local *cp = dev->cnic_priv;
  1118. struct cnic_ulp_ops *ulp_ops;
  1119. rcu_read_lock();
  1120. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1121. if (likely(ulp_ops)) {
  1122. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1123. cqes, num_cqes);
  1124. }
  1125. rcu_read_unlock();
  1126. }
  1127. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1128. {
  1129. struct cnic_local *cp = dev->cnic_priv;
  1130. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1131. int hq_bds, pages;
  1132. u32 pfid = cp->pfid;
  1133. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1134. cp->num_ccells = req1->num_ccells_per_conn;
  1135. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1136. cp->num_iscsi_tasks;
  1137. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1138. BNX2X_ISCSI_R2TQE_SIZE;
  1139. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1140. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1141. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1142. cp->num_cqs = req1->num_cqs;
  1143. if (!dev->max_iscsi_conn)
  1144. return 0;
  1145. /* init Tstorm RAM */
  1146. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1147. req1->rq_num_wqes);
  1148. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1149. PAGE_SIZE);
  1150. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1151. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1152. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1153. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1154. req1->num_tasks_per_conn);
  1155. /* init Ustorm RAM */
  1156. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1157. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1158. req1->rq_buffer_size);
  1159. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1160. PAGE_SIZE);
  1161. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1162. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1163. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1164. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1165. req1->num_tasks_per_conn);
  1166. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1167. req1->rq_num_wqes);
  1168. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1169. req1->cq_num_wqes);
  1170. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1171. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1172. /* init Xstorm RAM */
  1173. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1174. PAGE_SIZE);
  1175. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1176. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1177. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1178. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1179. req1->num_tasks_per_conn);
  1180. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1181. hq_bds);
  1182. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1183. req1->num_tasks_per_conn);
  1184. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1185. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1186. /* init Cstorm RAM */
  1187. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1188. PAGE_SIZE);
  1189. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1190. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1191. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1192. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1193. req1->num_tasks_per_conn);
  1194. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1195. req1->cq_num_wqes);
  1196. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1197. hq_bds);
  1198. return 0;
  1199. }
  1200. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1201. {
  1202. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1203. struct cnic_local *cp = dev->cnic_priv;
  1204. u32 pfid = cp->pfid;
  1205. struct iscsi_kcqe kcqe;
  1206. struct kcqe *cqes[1];
  1207. memset(&kcqe, 0, sizeof(kcqe));
  1208. if (!dev->max_iscsi_conn) {
  1209. kcqe.completion_status =
  1210. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1211. goto done;
  1212. }
  1213. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1214. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1215. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1216. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1217. req2->error_bit_map[1]);
  1218. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1219. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1220. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1221. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1222. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1223. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1224. req2->error_bit_map[1]);
  1225. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1226. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1227. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1228. done:
  1229. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1230. cqes[0] = (struct kcqe *) &kcqe;
  1231. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1232. return 0;
  1233. }
  1234. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1235. {
  1236. struct cnic_local *cp = dev->cnic_priv;
  1237. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1238. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1239. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1240. cnic_free_dma(dev, &iscsi->hq_info);
  1241. cnic_free_dma(dev, &iscsi->r2tq_info);
  1242. cnic_free_dma(dev, &iscsi->task_array_info);
  1243. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1244. } else {
  1245. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1246. }
  1247. ctx->cid = 0;
  1248. }
  1249. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1250. {
  1251. u32 cid;
  1252. int ret, pages;
  1253. struct cnic_local *cp = dev->cnic_priv;
  1254. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1255. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1256. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1257. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1258. if (cid == -1) {
  1259. ret = -ENOMEM;
  1260. goto error;
  1261. }
  1262. ctx->cid = cid;
  1263. return 0;
  1264. }
  1265. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1266. if (cid == -1) {
  1267. ret = -ENOMEM;
  1268. goto error;
  1269. }
  1270. ctx->cid = cid;
  1271. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1272. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1273. if (ret)
  1274. goto error;
  1275. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1276. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1277. if (ret)
  1278. goto error;
  1279. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1280. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1281. if (ret)
  1282. goto error;
  1283. return 0;
  1284. error:
  1285. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1286. return ret;
  1287. }
  1288. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1289. struct regpair *ctx_addr)
  1290. {
  1291. struct cnic_local *cp = dev->cnic_priv;
  1292. struct cnic_eth_dev *ethdev = cp->ethdev;
  1293. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1294. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1295. unsigned long align_off = 0;
  1296. dma_addr_t ctx_map;
  1297. void *ctx;
  1298. if (cp->ctx_align) {
  1299. unsigned long mask = cp->ctx_align - 1;
  1300. if (cp->ctx_arr[blk].mapping & mask)
  1301. align_off = cp->ctx_align -
  1302. (cp->ctx_arr[blk].mapping & mask);
  1303. }
  1304. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1305. (off * BNX2X_CONTEXT_MEM_SIZE);
  1306. ctx = cp->ctx_arr[blk].ctx + align_off +
  1307. (off * BNX2X_CONTEXT_MEM_SIZE);
  1308. if (init)
  1309. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1310. ctx_addr->lo = ctx_map & 0xffffffff;
  1311. ctx_addr->hi = (u64) ctx_map >> 32;
  1312. return ctx;
  1313. }
  1314. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1315. u32 num)
  1316. {
  1317. struct cnic_local *cp = dev->cnic_priv;
  1318. struct iscsi_kwqe_conn_offload1 *req1 =
  1319. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1320. struct iscsi_kwqe_conn_offload2 *req2 =
  1321. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1322. struct iscsi_kwqe_conn_offload3 *req3;
  1323. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1324. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1325. u32 cid = ctx->cid;
  1326. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1327. struct iscsi_context *ictx;
  1328. struct regpair context_addr;
  1329. int i, j, n = 2, n_max;
  1330. u8 port = CNIC_PORT(cp);
  1331. ctx->ctx_flags = 0;
  1332. if (!req2->num_additional_wqes)
  1333. return -EINVAL;
  1334. n_max = req2->num_additional_wqes + 2;
  1335. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1336. if (ictx == NULL)
  1337. return -ENOMEM;
  1338. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1339. ictx->xstorm_ag_context.hq_prod = 1;
  1340. ictx->xstorm_st_context.iscsi.first_burst_length =
  1341. ISCSI_DEF_FIRST_BURST_LEN;
  1342. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1343. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1344. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1345. req1->sq_page_table_addr_lo;
  1346. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1347. req1->sq_page_table_addr_hi;
  1348. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1349. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1350. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1351. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1352. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1353. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1354. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1355. iscsi->hq_info.pgtbl[0];
  1356. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1357. iscsi->hq_info.pgtbl[1];
  1358. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1359. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1360. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1361. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1362. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1363. iscsi->r2tq_info.pgtbl[0];
  1364. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1365. iscsi->r2tq_info.pgtbl[1];
  1366. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1367. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1368. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1369. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1370. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1371. BNX2X_ISCSI_PBL_NOT_CACHED;
  1372. ictx->xstorm_st_context.iscsi.flags.flags |=
  1373. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1374. ictx->xstorm_st_context.iscsi.flags.flags |=
  1375. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1376. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1377. ETH_P_8021Q;
  1378. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1379. cp->port_mode == CHIP_2_PORT_MODE) {
  1380. port = 0;
  1381. }
  1382. ictx->xstorm_st_context.common.flags =
  1383. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1384. ictx->xstorm_st_context.common.flags =
  1385. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1386. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1387. /* TSTORM requires the base address of RQ DB & not PTE */
  1388. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1389. req2->rq_page_table_addr_lo & PAGE_MASK;
  1390. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1391. req2->rq_page_table_addr_hi;
  1392. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1393. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1394. ictx->tstorm_st_context.tcp.flags2 |=
  1395. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1396. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1397. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1398. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1399. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1400. req2->rq_page_table_addr_lo;
  1401. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1402. req2->rq_page_table_addr_hi;
  1403. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1404. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1405. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1406. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1407. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1408. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1409. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1410. iscsi->r2tq_info.pgtbl[0];
  1411. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1412. iscsi->r2tq_info.pgtbl[1];
  1413. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1414. req1->cq_page_table_addr_lo;
  1415. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1416. req1->cq_page_table_addr_hi;
  1417. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1418. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1419. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1420. ictx->ustorm_st_context.task_pbe_cache_index =
  1421. BNX2X_ISCSI_PBL_NOT_CACHED;
  1422. ictx->ustorm_st_context.task_pdu_cache_index =
  1423. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1424. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1425. if (j == 3) {
  1426. if (n >= n_max)
  1427. break;
  1428. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1429. j = 0;
  1430. }
  1431. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1432. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1433. req3->qp_first_pte[j].hi;
  1434. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1435. req3->qp_first_pte[j].lo;
  1436. }
  1437. ictx->ustorm_st_context.task_pbl_base.lo =
  1438. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1439. ictx->ustorm_st_context.task_pbl_base.hi =
  1440. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1441. ictx->ustorm_st_context.tce_phy_addr.lo =
  1442. iscsi->task_array_info.pgtbl[0];
  1443. ictx->ustorm_st_context.tce_phy_addr.hi =
  1444. iscsi->task_array_info.pgtbl[1];
  1445. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1446. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1447. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1448. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1449. ISCSI_DEF_MAX_BURST_LEN;
  1450. ictx->ustorm_st_context.negotiated_rx |=
  1451. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1452. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1453. ictx->cstorm_st_context.hq_pbl_base.lo =
  1454. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1455. ictx->cstorm_st_context.hq_pbl_base.hi =
  1456. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1457. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1458. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1459. ictx->cstorm_st_context.task_pbl_base.lo =
  1460. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1461. ictx->cstorm_st_context.task_pbl_base.hi =
  1462. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1463. /* CSTORM and USTORM initialization is different, CSTORM requires
  1464. * CQ DB base & not PTE addr */
  1465. ictx->cstorm_st_context.cq_db_base.lo =
  1466. req1->cq_page_table_addr_lo & PAGE_MASK;
  1467. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1468. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1469. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1470. for (i = 0; i < cp->num_cqs; i++) {
  1471. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1472. ISCSI_INITIAL_SN;
  1473. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1474. ISCSI_INITIAL_SN;
  1475. }
  1476. ictx->xstorm_ag_context.cdu_reserved =
  1477. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1478. ISCSI_CONNECTION_TYPE);
  1479. ictx->ustorm_ag_context.cdu_usage =
  1480. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1481. ISCSI_CONNECTION_TYPE);
  1482. return 0;
  1483. }
  1484. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1485. u32 num, int *work)
  1486. {
  1487. struct iscsi_kwqe_conn_offload1 *req1;
  1488. struct iscsi_kwqe_conn_offload2 *req2;
  1489. struct cnic_local *cp = dev->cnic_priv;
  1490. struct cnic_context *ctx;
  1491. struct iscsi_kcqe kcqe;
  1492. struct kcqe *cqes[1];
  1493. u32 l5_cid;
  1494. int ret = 0;
  1495. if (num < 2) {
  1496. *work = num;
  1497. return -EINVAL;
  1498. }
  1499. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1500. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1501. if ((num - 2) < req2->num_additional_wqes) {
  1502. *work = num;
  1503. return -EINVAL;
  1504. }
  1505. *work = 2 + req2->num_additional_wqes;
  1506. l5_cid = req1->iscsi_conn_id;
  1507. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1508. return -EINVAL;
  1509. memset(&kcqe, 0, sizeof(kcqe));
  1510. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1511. kcqe.iscsi_conn_id = l5_cid;
  1512. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1513. ctx = &cp->ctx_tbl[l5_cid];
  1514. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1515. kcqe.completion_status =
  1516. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1517. goto done;
  1518. }
  1519. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1520. atomic_dec(&cp->iscsi_conn);
  1521. goto done;
  1522. }
  1523. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1524. if (ret) {
  1525. atomic_dec(&cp->iscsi_conn);
  1526. ret = 0;
  1527. goto done;
  1528. }
  1529. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1530. if (ret < 0) {
  1531. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1532. atomic_dec(&cp->iscsi_conn);
  1533. goto done;
  1534. }
  1535. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1536. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1537. done:
  1538. cqes[0] = (struct kcqe *) &kcqe;
  1539. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1540. return 0;
  1541. }
  1542. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1543. {
  1544. struct cnic_local *cp = dev->cnic_priv;
  1545. struct iscsi_kwqe_conn_update *req =
  1546. (struct iscsi_kwqe_conn_update *) kwqe;
  1547. void *data;
  1548. union l5cm_specific_data l5_data;
  1549. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1550. int ret;
  1551. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1552. return -EINVAL;
  1553. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1554. if (!data)
  1555. return -ENOMEM;
  1556. memcpy(data, kwqe, sizeof(struct kwqe));
  1557. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1558. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1559. return ret;
  1560. }
  1561. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1562. {
  1563. struct cnic_local *cp = dev->cnic_priv;
  1564. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1565. union l5cm_specific_data l5_data;
  1566. int ret;
  1567. u32 hw_cid;
  1568. init_waitqueue_head(&ctx->waitq);
  1569. ctx->wait_cond = 0;
  1570. memset(&l5_data, 0, sizeof(l5_data));
  1571. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1572. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1573. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1574. if (ret == 0) {
  1575. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1576. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1577. return -EBUSY;
  1578. }
  1579. return 0;
  1580. }
  1581. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1582. {
  1583. struct cnic_local *cp = dev->cnic_priv;
  1584. struct iscsi_kwqe_conn_destroy *req =
  1585. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1586. u32 l5_cid = req->reserved0;
  1587. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1588. int ret = 0;
  1589. struct iscsi_kcqe kcqe;
  1590. struct kcqe *cqes[1];
  1591. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1592. goto skip_cfc_delete;
  1593. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1594. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1595. if (delta > (2 * HZ))
  1596. delta = 0;
  1597. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1598. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1599. goto destroy_reply;
  1600. }
  1601. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1602. skip_cfc_delete:
  1603. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1604. if (!ret) {
  1605. atomic_dec(&cp->iscsi_conn);
  1606. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1607. }
  1608. destroy_reply:
  1609. memset(&kcqe, 0, sizeof(kcqe));
  1610. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1611. kcqe.iscsi_conn_id = l5_cid;
  1612. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1613. kcqe.iscsi_conn_context_id = req->context_id;
  1614. cqes[0] = (struct kcqe *) &kcqe;
  1615. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1616. return 0;
  1617. }
  1618. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1619. struct l4_kwq_connect_req1 *kwqe1,
  1620. struct l4_kwq_connect_req3 *kwqe3,
  1621. struct l5cm_active_conn_buffer *conn_buf)
  1622. {
  1623. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1624. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1625. &conn_buf->xstorm_conn_buffer;
  1626. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1627. &conn_buf->tstorm_conn_buffer;
  1628. struct regpair context_addr;
  1629. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1630. struct in6_addr src_ip, dst_ip;
  1631. int i;
  1632. u32 *addrp;
  1633. addrp = (u32 *) &conn_addr->local_ip_addr;
  1634. for (i = 0; i < 4; i++, addrp++)
  1635. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1636. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1637. for (i = 0; i < 4; i++, addrp++)
  1638. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1639. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1640. xstorm_buf->context_addr.hi = context_addr.hi;
  1641. xstorm_buf->context_addr.lo = context_addr.lo;
  1642. xstorm_buf->mss = 0xffff;
  1643. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1644. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1645. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1646. xstorm_buf->pseudo_header_checksum =
  1647. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1648. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1649. tstorm_buf->params |=
  1650. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1651. if (kwqe3->ka_timeout) {
  1652. tstorm_buf->ka_enable = 1;
  1653. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1654. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1655. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1656. }
  1657. tstorm_buf->max_rt_time = 0xffffffff;
  1658. }
  1659. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1660. {
  1661. struct cnic_local *cp = dev->cnic_priv;
  1662. u32 pfid = cp->pfid;
  1663. u8 *mac = dev->mac_addr;
  1664. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1665. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1666. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1667. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1668. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1669. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1670. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1671. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1672. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1673. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1674. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1675. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1676. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1677. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1678. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1679. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1680. mac[4]);
  1681. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1682. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1683. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1684. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1685. mac[2]);
  1686. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1687. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1688. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1689. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1690. mac[0]);
  1691. }
  1692. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1693. {
  1694. struct cnic_local *cp = dev->cnic_priv;
  1695. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1696. u16 tstorm_flags = 0;
  1697. if (tcp_ts) {
  1698. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1699. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1700. }
  1701. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1702. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1703. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1704. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1705. }
  1706. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1707. u32 num, int *work)
  1708. {
  1709. struct cnic_local *cp = dev->cnic_priv;
  1710. struct l4_kwq_connect_req1 *kwqe1 =
  1711. (struct l4_kwq_connect_req1 *) wqes[0];
  1712. struct l4_kwq_connect_req3 *kwqe3;
  1713. struct l5cm_active_conn_buffer *conn_buf;
  1714. struct l5cm_conn_addr_params *conn_addr;
  1715. union l5cm_specific_data l5_data;
  1716. u32 l5_cid = kwqe1->pg_cid;
  1717. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1718. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1719. int ret;
  1720. if (num < 2) {
  1721. *work = num;
  1722. return -EINVAL;
  1723. }
  1724. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1725. *work = 3;
  1726. else
  1727. *work = 2;
  1728. if (num < *work) {
  1729. *work = num;
  1730. return -EINVAL;
  1731. }
  1732. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1733. netdev_err(dev->netdev, "conn_buf size too big\n");
  1734. return -ENOMEM;
  1735. }
  1736. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1737. if (!conn_buf)
  1738. return -ENOMEM;
  1739. memset(conn_buf, 0, sizeof(*conn_buf));
  1740. conn_addr = &conn_buf->conn_addr_buf;
  1741. conn_addr->remote_addr_0 = csk->ha[0];
  1742. conn_addr->remote_addr_1 = csk->ha[1];
  1743. conn_addr->remote_addr_2 = csk->ha[2];
  1744. conn_addr->remote_addr_3 = csk->ha[3];
  1745. conn_addr->remote_addr_4 = csk->ha[4];
  1746. conn_addr->remote_addr_5 = csk->ha[5];
  1747. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1748. struct l4_kwq_connect_req2 *kwqe2 =
  1749. (struct l4_kwq_connect_req2 *) wqes[1];
  1750. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1751. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1752. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1753. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1754. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1755. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1756. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1757. }
  1758. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1759. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1760. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1761. conn_addr->local_tcp_port = kwqe1->src_port;
  1762. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1763. conn_addr->pmtu = kwqe3->pmtu;
  1764. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1765. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1766. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1767. cnic_bnx2x_set_tcp_timestamp(dev,
  1768. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1769. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1770. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1771. if (!ret)
  1772. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1773. return ret;
  1774. }
  1775. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1776. {
  1777. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1778. union l5cm_specific_data l5_data;
  1779. int ret;
  1780. memset(&l5_data, 0, sizeof(l5_data));
  1781. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1782. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1783. return ret;
  1784. }
  1785. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1786. {
  1787. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1788. union l5cm_specific_data l5_data;
  1789. int ret;
  1790. memset(&l5_data, 0, sizeof(l5_data));
  1791. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1792. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1793. return ret;
  1794. }
  1795. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1796. {
  1797. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1798. struct l4_kcq kcqe;
  1799. struct kcqe *cqes[1];
  1800. memset(&kcqe, 0, sizeof(kcqe));
  1801. kcqe.pg_host_opaque = req->host_opaque;
  1802. kcqe.pg_cid = req->host_opaque;
  1803. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1804. cqes[0] = (struct kcqe *) &kcqe;
  1805. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1806. return 0;
  1807. }
  1808. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1809. {
  1810. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1811. struct l4_kcq kcqe;
  1812. struct kcqe *cqes[1];
  1813. memset(&kcqe, 0, sizeof(kcqe));
  1814. kcqe.pg_host_opaque = req->pg_host_opaque;
  1815. kcqe.pg_cid = req->pg_cid;
  1816. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1817. cqes[0] = (struct kcqe *) &kcqe;
  1818. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1819. return 0;
  1820. }
  1821. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1822. {
  1823. struct fcoe_kwqe_stat *req;
  1824. struct fcoe_stat_ramrod_params *fcoe_stat;
  1825. union l5cm_specific_data l5_data;
  1826. struct cnic_local *cp = dev->cnic_priv;
  1827. int ret;
  1828. u32 cid;
  1829. req = (struct fcoe_kwqe_stat *) kwqe;
  1830. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1831. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1832. if (!fcoe_stat)
  1833. return -ENOMEM;
  1834. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1835. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1836. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1837. FCOE_CONNECTION_TYPE, &l5_data);
  1838. return ret;
  1839. }
  1840. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1841. u32 num, int *work)
  1842. {
  1843. int ret;
  1844. struct cnic_local *cp = dev->cnic_priv;
  1845. u32 cid;
  1846. struct fcoe_init_ramrod_params *fcoe_init;
  1847. struct fcoe_kwqe_init1 *req1;
  1848. struct fcoe_kwqe_init2 *req2;
  1849. struct fcoe_kwqe_init3 *req3;
  1850. union l5cm_specific_data l5_data;
  1851. if (num < 3) {
  1852. *work = num;
  1853. return -EINVAL;
  1854. }
  1855. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1856. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1857. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1858. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1859. *work = 1;
  1860. return -EINVAL;
  1861. }
  1862. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1863. *work = 2;
  1864. return -EINVAL;
  1865. }
  1866. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1867. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1868. return -ENOMEM;
  1869. }
  1870. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1871. if (!fcoe_init)
  1872. return -ENOMEM;
  1873. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1874. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1875. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1876. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1877. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1878. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1879. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1880. fcoe_init->sb_num = cp->status_blk_num;
  1881. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1882. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1883. cp->kcq2.sw_prod_idx = 0;
  1884. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1885. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1886. FCOE_CONNECTION_TYPE, &l5_data);
  1887. *work = 3;
  1888. return ret;
  1889. }
  1890. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1891. u32 num, int *work)
  1892. {
  1893. int ret = 0;
  1894. u32 cid = -1, l5_cid;
  1895. struct cnic_local *cp = dev->cnic_priv;
  1896. struct fcoe_kwqe_conn_offload1 *req1;
  1897. struct fcoe_kwqe_conn_offload2 *req2;
  1898. struct fcoe_kwqe_conn_offload3 *req3;
  1899. struct fcoe_kwqe_conn_offload4 *req4;
  1900. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1901. struct cnic_context *ctx;
  1902. struct fcoe_context *fctx;
  1903. struct regpair ctx_addr;
  1904. union l5cm_specific_data l5_data;
  1905. struct fcoe_kcqe kcqe;
  1906. struct kcqe *cqes[1];
  1907. if (num < 4) {
  1908. *work = num;
  1909. return -EINVAL;
  1910. }
  1911. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1912. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1913. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1914. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1915. *work = 4;
  1916. l5_cid = req1->fcoe_conn_id;
  1917. if (l5_cid >= dev->max_fcoe_conn)
  1918. goto err_reply;
  1919. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1920. ctx = &cp->ctx_tbl[l5_cid];
  1921. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1922. goto err_reply;
  1923. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1924. if (ret) {
  1925. ret = 0;
  1926. goto err_reply;
  1927. }
  1928. cid = ctx->cid;
  1929. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1930. if (fctx) {
  1931. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1932. u32 val;
  1933. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1934. FCOE_CONNECTION_TYPE);
  1935. fctx->xstorm_ag_context.cdu_reserved = val;
  1936. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1937. FCOE_CONNECTION_TYPE);
  1938. fctx->ustorm_ag_context.cdu_usage = val;
  1939. }
  1940. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1941. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1942. goto err_reply;
  1943. }
  1944. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1945. if (!fcoe_offload)
  1946. goto err_reply;
  1947. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1948. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1949. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1950. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1951. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1952. cid = BNX2X_HW_CID(cp, cid);
  1953. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1954. FCOE_CONNECTION_TYPE, &l5_data);
  1955. if (!ret)
  1956. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1957. return ret;
  1958. err_reply:
  1959. if (cid != -1)
  1960. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1961. memset(&kcqe, 0, sizeof(kcqe));
  1962. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1963. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1964. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1965. cqes[0] = (struct kcqe *) &kcqe;
  1966. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1967. return ret;
  1968. }
  1969. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1970. {
  1971. struct fcoe_kwqe_conn_enable_disable *req;
  1972. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1973. union l5cm_specific_data l5_data;
  1974. int ret;
  1975. u32 cid, l5_cid;
  1976. struct cnic_local *cp = dev->cnic_priv;
  1977. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1978. cid = req->context_id;
  1979. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1980. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1981. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1982. return -ENOMEM;
  1983. }
  1984. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1985. if (!fcoe_enable)
  1986. return -ENOMEM;
  1987. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1988. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1989. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1990. FCOE_CONNECTION_TYPE, &l5_data);
  1991. return ret;
  1992. }
  1993. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1994. {
  1995. struct fcoe_kwqe_conn_enable_disable *req;
  1996. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1997. union l5cm_specific_data l5_data;
  1998. int ret;
  1999. u32 cid, l5_cid;
  2000. struct cnic_local *cp = dev->cnic_priv;
  2001. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2002. cid = req->context_id;
  2003. l5_cid = req->conn_id;
  2004. if (l5_cid >= dev->max_fcoe_conn)
  2005. return -EINVAL;
  2006. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2007. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2008. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2009. return -ENOMEM;
  2010. }
  2011. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2012. if (!fcoe_disable)
  2013. return -ENOMEM;
  2014. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2015. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2016. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2017. FCOE_CONNECTION_TYPE, &l5_data);
  2018. return ret;
  2019. }
  2020. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2021. {
  2022. struct fcoe_kwqe_conn_destroy *req;
  2023. union l5cm_specific_data l5_data;
  2024. int ret;
  2025. u32 cid, l5_cid;
  2026. struct cnic_local *cp = dev->cnic_priv;
  2027. struct cnic_context *ctx;
  2028. struct fcoe_kcqe kcqe;
  2029. struct kcqe *cqes[1];
  2030. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2031. cid = req->context_id;
  2032. l5_cid = req->conn_id;
  2033. if (l5_cid >= dev->max_fcoe_conn)
  2034. return -EINVAL;
  2035. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2036. ctx = &cp->ctx_tbl[l5_cid];
  2037. init_waitqueue_head(&ctx->waitq);
  2038. ctx->wait_cond = 0;
  2039. memset(&kcqe, 0, sizeof(kcqe));
  2040. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2041. memset(&l5_data, 0, sizeof(l5_data));
  2042. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2043. FCOE_CONNECTION_TYPE, &l5_data);
  2044. if (ret == 0) {
  2045. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2046. if (ctx->wait_cond)
  2047. kcqe.completion_status = 0;
  2048. }
  2049. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2050. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2051. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2052. kcqe.fcoe_conn_id = req->conn_id;
  2053. kcqe.fcoe_conn_context_id = cid;
  2054. cqes[0] = (struct kcqe *) &kcqe;
  2055. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2056. return ret;
  2057. }
  2058. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2059. {
  2060. struct cnic_local *cp = dev->cnic_priv;
  2061. u32 i;
  2062. for (i = start_cid; i < cp->max_cid_space; i++) {
  2063. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2064. int j;
  2065. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2066. msleep(10);
  2067. for (j = 0; j < 5; j++) {
  2068. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2069. break;
  2070. msleep(20);
  2071. }
  2072. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2073. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2074. ctx->cid);
  2075. }
  2076. }
  2077. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2078. {
  2079. struct fcoe_kwqe_destroy *req;
  2080. union l5cm_specific_data l5_data;
  2081. struct cnic_local *cp = dev->cnic_priv;
  2082. int ret;
  2083. u32 cid;
  2084. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2085. req = (struct fcoe_kwqe_destroy *) kwqe;
  2086. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2087. memset(&l5_data, 0, sizeof(l5_data));
  2088. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2089. FCOE_CONNECTION_TYPE, &l5_data);
  2090. return ret;
  2091. }
  2092. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2093. {
  2094. struct cnic_local *cp = dev->cnic_priv;
  2095. struct kcqe kcqe;
  2096. struct kcqe *cqes[1];
  2097. u32 cid;
  2098. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2099. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2100. u32 kcqe_op;
  2101. int ulp_type;
  2102. cid = kwqe->kwqe_info0;
  2103. memset(&kcqe, 0, sizeof(kcqe));
  2104. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2105. u32 l5_cid = 0;
  2106. ulp_type = CNIC_ULP_FCOE;
  2107. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2108. struct fcoe_kwqe_conn_enable_disable *req;
  2109. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2110. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2111. cid = req->context_id;
  2112. l5_cid = req->conn_id;
  2113. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2114. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2115. } else {
  2116. return;
  2117. }
  2118. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2119. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2120. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2121. kcqe.kcqe_info2 = cid;
  2122. kcqe.kcqe_info0 = l5_cid;
  2123. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2124. ulp_type = CNIC_ULP_ISCSI;
  2125. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2126. cid = kwqe->kwqe_info1;
  2127. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2128. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2129. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2130. kcqe.kcqe_info2 = cid;
  2131. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2132. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2133. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2134. ulp_type = CNIC_ULP_L4;
  2135. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2136. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2137. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2138. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2139. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2140. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2141. else
  2142. return;
  2143. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2144. KCQE_FLAGS_LAYER_MASK_L4;
  2145. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2146. l4kcqe->cid = cid;
  2147. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2148. } else {
  2149. return;
  2150. }
  2151. cqes[0] = (struct kcqe *) &kcqe;
  2152. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2153. }
  2154. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2155. struct kwqe *wqes[], u32 num_wqes)
  2156. {
  2157. int i, work, ret;
  2158. u32 opcode;
  2159. struct kwqe *kwqe;
  2160. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2161. return -EAGAIN; /* bnx2 is down */
  2162. for (i = 0; i < num_wqes; ) {
  2163. kwqe = wqes[i];
  2164. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2165. work = 1;
  2166. switch (opcode) {
  2167. case ISCSI_KWQE_OPCODE_INIT1:
  2168. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2169. break;
  2170. case ISCSI_KWQE_OPCODE_INIT2:
  2171. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2172. break;
  2173. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2174. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2175. num_wqes - i, &work);
  2176. break;
  2177. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2178. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2179. break;
  2180. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2181. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2182. break;
  2183. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2184. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2185. &work);
  2186. break;
  2187. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2188. ret = cnic_bnx2x_close(dev, kwqe);
  2189. break;
  2190. case L4_KWQE_OPCODE_VALUE_RESET:
  2191. ret = cnic_bnx2x_reset(dev, kwqe);
  2192. break;
  2193. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2194. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2195. break;
  2196. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2197. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2198. break;
  2199. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2200. ret = 0;
  2201. break;
  2202. default:
  2203. ret = 0;
  2204. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2205. opcode);
  2206. break;
  2207. }
  2208. if (ret < 0) {
  2209. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2210. opcode);
  2211. /* Possibly bnx2x parity error, send completion
  2212. * to ulp drivers with error code to speed up
  2213. * cleanup and reset recovery.
  2214. */
  2215. if (ret == -EIO || ret == -EAGAIN)
  2216. cnic_bnx2x_kwqe_err(dev, kwqe);
  2217. }
  2218. i += work;
  2219. }
  2220. return 0;
  2221. }
  2222. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2223. struct kwqe *wqes[], u32 num_wqes)
  2224. {
  2225. struct cnic_local *cp = dev->cnic_priv;
  2226. int i, work, ret;
  2227. u32 opcode;
  2228. struct kwqe *kwqe;
  2229. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2230. return -EAGAIN; /* bnx2 is down */
  2231. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2232. return -EINVAL;
  2233. for (i = 0; i < num_wqes; ) {
  2234. kwqe = wqes[i];
  2235. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2236. work = 1;
  2237. switch (opcode) {
  2238. case FCOE_KWQE_OPCODE_INIT1:
  2239. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2240. num_wqes - i, &work);
  2241. break;
  2242. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2243. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2244. num_wqes - i, &work);
  2245. break;
  2246. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2247. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2248. break;
  2249. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2250. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2251. break;
  2252. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2253. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2254. break;
  2255. case FCOE_KWQE_OPCODE_DESTROY:
  2256. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2257. break;
  2258. case FCOE_KWQE_OPCODE_STAT:
  2259. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2260. break;
  2261. default:
  2262. ret = 0;
  2263. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2264. opcode);
  2265. break;
  2266. }
  2267. if (ret < 0) {
  2268. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2269. opcode);
  2270. /* Possibly bnx2x parity error, send completion
  2271. * to ulp drivers with error code to speed up
  2272. * cleanup and reset recovery.
  2273. */
  2274. if (ret == -EIO || ret == -EAGAIN)
  2275. cnic_bnx2x_kwqe_err(dev, kwqe);
  2276. }
  2277. i += work;
  2278. }
  2279. return 0;
  2280. }
  2281. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2282. u32 num_wqes)
  2283. {
  2284. int ret = -EINVAL;
  2285. u32 layer_code;
  2286. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2287. return -EAGAIN; /* bnx2x is down */
  2288. if (!num_wqes)
  2289. return 0;
  2290. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2291. switch (layer_code) {
  2292. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2293. case KWQE_FLAGS_LAYER_MASK_L4:
  2294. case KWQE_FLAGS_LAYER_MASK_L2:
  2295. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2296. break;
  2297. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2298. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2299. break;
  2300. }
  2301. return ret;
  2302. }
  2303. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2304. {
  2305. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2306. return KCQE_FLAGS_LAYER_MASK_L4;
  2307. return opflag & KCQE_FLAGS_LAYER_MASK;
  2308. }
  2309. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2310. {
  2311. struct cnic_local *cp = dev->cnic_priv;
  2312. int i, j, comp = 0;
  2313. i = 0;
  2314. j = 1;
  2315. while (num_cqes) {
  2316. struct cnic_ulp_ops *ulp_ops;
  2317. int ulp_type;
  2318. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2319. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2320. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2321. comp++;
  2322. while (j < num_cqes) {
  2323. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2324. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2325. break;
  2326. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2327. comp++;
  2328. j++;
  2329. }
  2330. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2331. ulp_type = CNIC_ULP_RDMA;
  2332. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2333. ulp_type = CNIC_ULP_ISCSI;
  2334. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2335. ulp_type = CNIC_ULP_FCOE;
  2336. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2337. ulp_type = CNIC_ULP_L4;
  2338. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2339. goto end;
  2340. else {
  2341. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2342. kcqe_op_flag);
  2343. goto end;
  2344. }
  2345. rcu_read_lock();
  2346. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2347. if (likely(ulp_ops)) {
  2348. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2349. cp->completed_kcq + i, j);
  2350. }
  2351. rcu_read_unlock();
  2352. end:
  2353. num_cqes -= j;
  2354. i += j;
  2355. j = 1;
  2356. }
  2357. if (unlikely(comp))
  2358. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2359. }
  2360. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2361. {
  2362. struct cnic_local *cp = dev->cnic_priv;
  2363. u16 i, ri, hw_prod, last;
  2364. struct kcqe *kcqe;
  2365. int kcqe_cnt = 0, last_cnt = 0;
  2366. i = ri = last = info->sw_prod_idx;
  2367. ri &= MAX_KCQ_IDX;
  2368. hw_prod = *info->hw_prod_idx_ptr;
  2369. hw_prod = info->hw_idx(hw_prod);
  2370. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2371. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2372. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2373. i = info->next_idx(i);
  2374. ri = i & MAX_KCQ_IDX;
  2375. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2376. last_cnt = kcqe_cnt;
  2377. last = i;
  2378. }
  2379. }
  2380. info->sw_prod_idx = last;
  2381. return last_cnt;
  2382. }
  2383. static int cnic_l2_completion(struct cnic_local *cp)
  2384. {
  2385. u16 hw_cons, sw_cons;
  2386. struct cnic_uio_dev *udev = cp->udev;
  2387. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2388. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2389. u32 cmd;
  2390. int comp = 0;
  2391. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2392. return 0;
  2393. hw_cons = *cp->rx_cons_ptr;
  2394. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2395. hw_cons++;
  2396. sw_cons = cp->rx_cons;
  2397. while (sw_cons != hw_cons) {
  2398. u8 cqe_fp_flags;
  2399. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2400. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2401. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2402. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2403. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2404. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2405. cmd == RAMROD_CMD_ID_ETH_HALT)
  2406. comp++;
  2407. }
  2408. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2409. }
  2410. return comp;
  2411. }
  2412. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2413. {
  2414. u16 rx_cons, tx_cons;
  2415. int comp = 0;
  2416. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2417. return;
  2418. rx_cons = *cp->rx_cons_ptr;
  2419. tx_cons = *cp->tx_cons_ptr;
  2420. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2421. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2422. comp = cnic_l2_completion(cp);
  2423. cp->tx_cons = tx_cons;
  2424. cp->rx_cons = rx_cons;
  2425. if (cp->udev)
  2426. uio_event_notify(&cp->udev->cnic_uinfo);
  2427. }
  2428. if (comp)
  2429. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2430. }
  2431. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2432. {
  2433. struct cnic_local *cp = dev->cnic_priv;
  2434. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2435. int kcqe_cnt;
  2436. /* status block index must be read before reading other fields */
  2437. rmb();
  2438. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2439. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2440. service_kcqes(dev, kcqe_cnt);
  2441. /* Tell compiler that status_blk fields can change. */
  2442. barrier();
  2443. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2444. /* status block index must be read first */
  2445. rmb();
  2446. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2447. }
  2448. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2449. cnic_chk_pkt_rings(cp);
  2450. return status_idx;
  2451. }
  2452. static int cnic_service_bnx2(void *data, void *status_blk)
  2453. {
  2454. struct cnic_dev *dev = data;
  2455. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2456. struct status_block *sblk = status_blk;
  2457. return sblk->status_idx;
  2458. }
  2459. return cnic_service_bnx2_queues(dev);
  2460. }
  2461. static void cnic_service_bnx2_msix(unsigned long data)
  2462. {
  2463. struct cnic_dev *dev = (struct cnic_dev *) data;
  2464. struct cnic_local *cp = dev->cnic_priv;
  2465. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2466. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2467. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2468. }
  2469. static void cnic_doirq(struct cnic_dev *dev)
  2470. {
  2471. struct cnic_local *cp = dev->cnic_priv;
  2472. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2473. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2474. prefetch(cp->status_blk.gen);
  2475. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2476. tasklet_schedule(&cp->cnic_irq_task);
  2477. }
  2478. }
  2479. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2480. {
  2481. struct cnic_dev *dev = dev_instance;
  2482. struct cnic_local *cp = dev->cnic_priv;
  2483. if (cp->ack_int)
  2484. cp->ack_int(dev);
  2485. cnic_doirq(dev);
  2486. return IRQ_HANDLED;
  2487. }
  2488. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2489. u16 index, u8 op, u8 update)
  2490. {
  2491. struct cnic_local *cp = dev->cnic_priv;
  2492. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2493. COMMAND_REG_INT_ACK);
  2494. struct igu_ack_register igu_ack;
  2495. igu_ack.status_block_index = index;
  2496. igu_ack.sb_id_and_flags =
  2497. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2498. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2499. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2500. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2501. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2502. }
  2503. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2504. u16 index, u8 op, u8 update)
  2505. {
  2506. struct igu_regular cmd_data;
  2507. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2508. cmd_data.sb_id_and_flags =
  2509. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2510. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2511. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2512. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2513. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2514. }
  2515. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2516. {
  2517. struct cnic_local *cp = dev->cnic_priv;
  2518. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2519. IGU_INT_DISABLE, 0);
  2520. }
  2521. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2522. {
  2523. struct cnic_local *cp = dev->cnic_priv;
  2524. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2525. IGU_INT_DISABLE, 0);
  2526. }
  2527. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2528. {
  2529. u32 last_status = *info->status_idx_ptr;
  2530. int kcqe_cnt;
  2531. /* status block index must be read before reading the KCQ */
  2532. rmb();
  2533. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2534. service_kcqes(dev, kcqe_cnt);
  2535. /* Tell compiler that sblk fields can change. */
  2536. barrier();
  2537. last_status = *info->status_idx_ptr;
  2538. /* status block index must be read before reading the KCQ */
  2539. rmb();
  2540. }
  2541. return last_status;
  2542. }
  2543. static void cnic_service_bnx2x_bh(unsigned long data)
  2544. {
  2545. struct cnic_dev *dev = (struct cnic_dev *) data;
  2546. struct cnic_local *cp = dev->cnic_priv;
  2547. u32 status_idx, new_status_idx;
  2548. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2549. return;
  2550. while (1) {
  2551. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2552. CNIC_WR16(dev, cp->kcq1.io_addr,
  2553. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2554. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2555. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2556. status_idx, IGU_INT_ENABLE, 1);
  2557. break;
  2558. }
  2559. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2560. if (new_status_idx != status_idx)
  2561. continue;
  2562. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2563. MAX_KCQ_IDX);
  2564. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2565. status_idx, IGU_INT_ENABLE, 1);
  2566. break;
  2567. }
  2568. }
  2569. static int cnic_service_bnx2x(void *data, void *status_blk)
  2570. {
  2571. struct cnic_dev *dev = data;
  2572. struct cnic_local *cp = dev->cnic_priv;
  2573. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2574. cnic_doirq(dev);
  2575. cnic_chk_pkt_rings(cp);
  2576. return 0;
  2577. }
  2578. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2579. {
  2580. struct cnic_ulp_ops *ulp_ops;
  2581. if (if_type == CNIC_ULP_ISCSI)
  2582. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2583. mutex_lock(&cnic_lock);
  2584. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2585. lockdep_is_held(&cnic_lock));
  2586. if (!ulp_ops) {
  2587. mutex_unlock(&cnic_lock);
  2588. return;
  2589. }
  2590. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2591. mutex_unlock(&cnic_lock);
  2592. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2593. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2594. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2595. }
  2596. static void cnic_ulp_stop(struct cnic_dev *dev)
  2597. {
  2598. struct cnic_local *cp = dev->cnic_priv;
  2599. int if_type;
  2600. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2601. cnic_ulp_stop_one(cp, if_type);
  2602. }
  2603. static void cnic_ulp_start(struct cnic_dev *dev)
  2604. {
  2605. struct cnic_local *cp = dev->cnic_priv;
  2606. int if_type;
  2607. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2608. struct cnic_ulp_ops *ulp_ops;
  2609. mutex_lock(&cnic_lock);
  2610. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2611. lockdep_is_held(&cnic_lock));
  2612. if (!ulp_ops || !ulp_ops->cnic_start) {
  2613. mutex_unlock(&cnic_lock);
  2614. continue;
  2615. }
  2616. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2617. mutex_unlock(&cnic_lock);
  2618. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2619. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2620. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2621. }
  2622. }
  2623. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2624. {
  2625. struct cnic_local *cp = dev->cnic_priv;
  2626. struct cnic_ulp_ops *ulp_ops;
  2627. int rc;
  2628. mutex_lock(&cnic_lock);
  2629. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2630. if (ulp_ops && ulp_ops->cnic_get_stats)
  2631. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2632. else
  2633. rc = -ENODEV;
  2634. mutex_unlock(&cnic_lock);
  2635. return rc;
  2636. }
  2637. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2638. {
  2639. struct cnic_dev *dev = data;
  2640. int ulp_type = CNIC_ULP_ISCSI;
  2641. switch (info->cmd) {
  2642. case CNIC_CTL_STOP_CMD:
  2643. cnic_hold(dev);
  2644. cnic_ulp_stop(dev);
  2645. cnic_stop_hw(dev);
  2646. cnic_put(dev);
  2647. break;
  2648. case CNIC_CTL_START_CMD:
  2649. cnic_hold(dev);
  2650. if (!cnic_start_hw(dev))
  2651. cnic_ulp_start(dev);
  2652. cnic_put(dev);
  2653. break;
  2654. case CNIC_CTL_STOP_ISCSI_CMD: {
  2655. struct cnic_local *cp = dev->cnic_priv;
  2656. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2657. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2658. break;
  2659. }
  2660. case CNIC_CTL_COMPLETION_CMD: {
  2661. struct cnic_ctl_completion *comp = &info->data.comp;
  2662. u32 cid = BNX2X_SW_CID(comp->cid);
  2663. u32 l5_cid;
  2664. struct cnic_local *cp = dev->cnic_priv;
  2665. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2666. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2667. if (unlikely(comp->error)) {
  2668. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2669. netdev_err(dev->netdev,
  2670. "CID %x CFC delete comp error %x\n",
  2671. cid, comp->error);
  2672. }
  2673. ctx->wait_cond = 1;
  2674. wake_up(&ctx->waitq);
  2675. }
  2676. break;
  2677. }
  2678. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2679. ulp_type = CNIC_ULP_FCOE;
  2680. /* fall through */
  2681. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2682. cnic_hold(dev);
  2683. cnic_copy_ulp_stats(dev, ulp_type);
  2684. cnic_put(dev);
  2685. break;
  2686. default:
  2687. return -EINVAL;
  2688. }
  2689. return 0;
  2690. }
  2691. static void cnic_ulp_init(struct cnic_dev *dev)
  2692. {
  2693. int i;
  2694. struct cnic_local *cp = dev->cnic_priv;
  2695. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2696. struct cnic_ulp_ops *ulp_ops;
  2697. mutex_lock(&cnic_lock);
  2698. ulp_ops = cnic_ulp_tbl_prot(i);
  2699. if (!ulp_ops || !ulp_ops->cnic_init) {
  2700. mutex_unlock(&cnic_lock);
  2701. continue;
  2702. }
  2703. ulp_get(ulp_ops);
  2704. mutex_unlock(&cnic_lock);
  2705. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2706. ulp_ops->cnic_init(dev);
  2707. ulp_put(ulp_ops);
  2708. }
  2709. }
  2710. static void cnic_ulp_exit(struct cnic_dev *dev)
  2711. {
  2712. int i;
  2713. struct cnic_local *cp = dev->cnic_priv;
  2714. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2715. struct cnic_ulp_ops *ulp_ops;
  2716. mutex_lock(&cnic_lock);
  2717. ulp_ops = cnic_ulp_tbl_prot(i);
  2718. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2719. mutex_unlock(&cnic_lock);
  2720. continue;
  2721. }
  2722. ulp_get(ulp_ops);
  2723. mutex_unlock(&cnic_lock);
  2724. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2725. ulp_ops->cnic_exit(dev);
  2726. ulp_put(ulp_ops);
  2727. }
  2728. }
  2729. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2730. {
  2731. struct cnic_dev *dev = csk->dev;
  2732. struct l4_kwq_offload_pg *l4kwqe;
  2733. struct kwqe *wqes[1];
  2734. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2735. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2736. wqes[0] = (struct kwqe *) l4kwqe;
  2737. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2738. l4kwqe->flags =
  2739. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2740. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2741. l4kwqe->da0 = csk->ha[0];
  2742. l4kwqe->da1 = csk->ha[1];
  2743. l4kwqe->da2 = csk->ha[2];
  2744. l4kwqe->da3 = csk->ha[3];
  2745. l4kwqe->da4 = csk->ha[4];
  2746. l4kwqe->da5 = csk->ha[5];
  2747. l4kwqe->sa0 = dev->mac_addr[0];
  2748. l4kwqe->sa1 = dev->mac_addr[1];
  2749. l4kwqe->sa2 = dev->mac_addr[2];
  2750. l4kwqe->sa3 = dev->mac_addr[3];
  2751. l4kwqe->sa4 = dev->mac_addr[4];
  2752. l4kwqe->sa5 = dev->mac_addr[5];
  2753. l4kwqe->etype = ETH_P_IP;
  2754. l4kwqe->ipid_start = DEF_IPID_START;
  2755. l4kwqe->host_opaque = csk->l5_cid;
  2756. if (csk->vlan_id) {
  2757. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2758. l4kwqe->vlan_tag = csk->vlan_id;
  2759. l4kwqe->l2hdr_nbytes += 4;
  2760. }
  2761. return dev->submit_kwqes(dev, wqes, 1);
  2762. }
  2763. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2764. {
  2765. struct cnic_dev *dev = csk->dev;
  2766. struct l4_kwq_update_pg *l4kwqe;
  2767. struct kwqe *wqes[1];
  2768. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2769. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2770. wqes[0] = (struct kwqe *) l4kwqe;
  2771. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2772. l4kwqe->flags =
  2773. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2774. l4kwqe->pg_cid = csk->pg_cid;
  2775. l4kwqe->da0 = csk->ha[0];
  2776. l4kwqe->da1 = csk->ha[1];
  2777. l4kwqe->da2 = csk->ha[2];
  2778. l4kwqe->da3 = csk->ha[3];
  2779. l4kwqe->da4 = csk->ha[4];
  2780. l4kwqe->da5 = csk->ha[5];
  2781. l4kwqe->pg_host_opaque = csk->l5_cid;
  2782. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2783. return dev->submit_kwqes(dev, wqes, 1);
  2784. }
  2785. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2786. {
  2787. struct cnic_dev *dev = csk->dev;
  2788. struct l4_kwq_upload *l4kwqe;
  2789. struct kwqe *wqes[1];
  2790. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2791. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2792. wqes[0] = (struct kwqe *) l4kwqe;
  2793. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2794. l4kwqe->flags =
  2795. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2796. l4kwqe->cid = csk->pg_cid;
  2797. return dev->submit_kwqes(dev, wqes, 1);
  2798. }
  2799. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2800. {
  2801. struct cnic_dev *dev = csk->dev;
  2802. struct l4_kwq_connect_req1 *l4kwqe1;
  2803. struct l4_kwq_connect_req2 *l4kwqe2;
  2804. struct l4_kwq_connect_req3 *l4kwqe3;
  2805. struct kwqe *wqes[3];
  2806. u8 tcp_flags = 0;
  2807. int num_wqes = 2;
  2808. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2809. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2810. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2811. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2812. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2813. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2814. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2815. l4kwqe3->flags =
  2816. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2817. l4kwqe3->ka_timeout = csk->ka_timeout;
  2818. l4kwqe3->ka_interval = csk->ka_interval;
  2819. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2820. l4kwqe3->tos = csk->tos;
  2821. l4kwqe3->ttl = csk->ttl;
  2822. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2823. l4kwqe3->pmtu = csk->mtu;
  2824. l4kwqe3->rcv_buf = csk->rcv_buf;
  2825. l4kwqe3->snd_buf = csk->snd_buf;
  2826. l4kwqe3->seed = csk->seed;
  2827. wqes[0] = (struct kwqe *) l4kwqe1;
  2828. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2829. wqes[1] = (struct kwqe *) l4kwqe2;
  2830. wqes[2] = (struct kwqe *) l4kwqe3;
  2831. num_wqes = 3;
  2832. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2833. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2834. l4kwqe2->flags =
  2835. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2836. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2837. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2838. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2839. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2840. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2841. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2842. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2843. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2844. sizeof(struct tcphdr);
  2845. } else {
  2846. wqes[1] = (struct kwqe *) l4kwqe3;
  2847. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2848. sizeof(struct tcphdr);
  2849. }
  2850. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2851. l4kwqe1->flags =
  2852. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2853. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2854. l4kwqe1->cid = csk->cid;
  2855. l4kwqe1->pg_cid = csk->pg_cid;
  2856. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2857. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2858. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2859. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2860. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2861. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2862. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2863. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2864. if (csk->tcp_flags & SK_TCP_NAGLE)
  2865. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2866. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2867. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2868. if (csk->tcp_flags & SK_TCP_SACK)
  2869. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2870. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2871. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2872. l4kwqe1->tcp_flags = tcp_flags;
  2873. return dev->submit_kwqes(dev, wqes, num_wqes);
  2874. }
  2875. static int cnic_cm_close_req(struct cnic_sock *csk)
  2876. {
  2877. struct cnic_dev *dev = csk->dev;
  2878. struct l4_kwq_close_req *l4kwqe;
  2879. struct kwqe *wqes[1];
  2880. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2881. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2882. wqes[0] = (struct kwqe *) l4kwqe;
  2883. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2884. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2885. l4kwqe->cid = csk->cid;
  2886. return dev->submit_kwqes(dev, wqes, 1);
  2887. }
  2888. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2889. {
  2890. struct cnic_dev *dev = csk->dev;
  2891. struct l4_kwq_reset_req *l4kwqe;
  2892. struct kwqe *wqes[1];
  2893. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2894. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2895. wqes[0] = (struct kwqe *) l4kwqe;
  2896. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2897. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2898. l4kwqe->cid = csk->cid;
  2899. return dev->submit_kwqes(dev, wqes, 1);
  2900. }
  2901. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2902. u32 l5_cid, struct cnic_sock **csk, void *context)
  2903. {
  2904. struct cnic_local *cp = dev->cnic_priv;
  2905. struct cnic_sock *csk1;
  2906. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2907. return -EINVAL;
  2908. if (cp->ctx_tbl) {
  2909. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2910. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2911. return -EAGAIN;
  2912. }
  2913. csk1 = &cp->csk_tbl[l5_cid];
  2914. if (atomic_read(&csk1->ref_count))
  2915. return -EAGAIN;
  2916. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2917. return -EBUSY;
  2918. csk1->dev = dev;
  2919. csk1->cid = cid;
  2920. csk1->l5_cid = l5_cid;
  2921. csk1->ulp_type = ulp_type;
  2922. csk1->context = context;
  2923. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2924. csk1->ka_interval = DEF_KA_INTERVAL;
  2925. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2926. csk1->tos = DEF_TOS;
  2927. csk1->ttl = DEF_TTL;
  2928. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2929. csk1->rcv_buf = DEF_RCV_BUF;
  2930. csk1->snd_buf = DEF_SND_BUF;
  2931. csk1->seed = DEF_SEED;
  2932. *csk = csk1;
  2933. return 0;
  2934. }
  2935. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2936. {
  2937. if (csk->src_port) {
  2938. struct cnic_dev *dev = csk->dev;
  2939. struct cnic_local *cp = dev->cnic_priv;
  2940. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2941. csk->src_port = 0;
  2942. }
  2943. }
  2944. static void cnic_close_conn(struct cnic_sock *csk)
  2945. {
  2946. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2947. cnic_cm_upload_pg(csk);
  2948. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2949. }
  2950. cnic_cm_cleanup(csk);
  2951. }
  2952. static int cnic_cm_destroy(struct cnic_sock *csk)
  2953. {
  2954. if (!cnic_in_use(csk))
  2955. return -EINVAL;
  2956. csk_hold(csk);
  2957. clear_bit(SK_F_INUSE, &csk->flags);
  2958. smp_mb__after_clear_bit();
  2959. while (atomic_read(&csk->ref_count) != 1)
  2960. msleep(1);
  2961. cnic_cm_cleanup(csk);
  2962. csk->flags = 0;
  2963. csk_put(csk);
  2964. return 0;
  2965. }
  2966. static inline u16 cnic_get_vlan(struct net_device *dev,
  2967. struct net_device **vlan_dev)
  2968. {
  2969. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2970. *vlan_dev = vlan_dev_real_dev(dev);
  2971. return vlan_dev_vlan_id(dev);
  2972. }
  2973. *vlan_dev = dev;
  2974. return 0;
  2975. }
  2976. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2977. struct dst_entry **dst)
  2978. {
  2979. #if defined(CONFIG_INET)
  2980. struct rtable *rt;
  2981. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2982. if (!IS_ERR(rt)) {
  2983. *dst = &rt->dst;
  2984. return 0;
  2985. }
  2986. return PTR_ERR(rt);
  2987. #else
  2988. return -ENETUNREACH;
  2989. #endif
  2990. }
  2991. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2992. struct dst_entry **dst)
  2993. {
  2994. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2995. struct flowi6 fl6;
  2996. memset(&fl6, 0, sizeof(fl6));
  2997. fl6.daddr = dst_addr->sin6_addr;
  2998. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2999. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3000. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3001. if ((*dst)->error) {
  3002. dst_release(*dst);
  3003. *dst = NULL;
  3004. return -ENETUNREACH;
  3005. } else
  3006. return 0;
  3007. #endif
  3008. return -ENETUNREACH;
  3009. }
  3010. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3011. int ulp_type)
  3012. {
  3013. struct cnic_dev *dev = NULL;
  3014. struct dst_entry *dst;
  3015. struct net_device *netdev = NULL;
  3016. int err = -ENETUNREACH;
  3017. if (dst_addr->sin_family == AF_INET)
  3018. err = cnic_get_v4_route(dst_addr, &dst);
  3019. else if (dst_addr->sin_family == AF_INET6) {
  3020. struct sockaddr_in6 *dst_addr6 =
  3021. (struct sockaddr_in6 *) dst_addr;
  3022. err = cnic_get_v6_route(dst_addr6, &dst);
  3023. } else
  3024. return NULL;
  3025. if (err)
  3026. return NULL;
  3027. if (!dst->dev)
  3028. goto done;
  3029. cnic_get_vlan(dst->dev, &netdev);
  3030. dev = cnic_from_netdev(netdev);
  3031. done:
  3032. dst_release(dst);
  3033. if (dev)
  3034. cnic_put(dev);
  3035. return dev;
  3036. }
  3037. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3038. {
  3039. struct cnic_dev *dev = csk->dev;
  3040. struct cnic_local *cp = dev->cnic_priv;
  3041. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3042. }
  3043. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3044. {
  3045. struct cnic_dev *dev = csk->dev;
  3046. struct cnic_local *cp = dev->cnic_priv;
  3047. int is_v6, rc = 0;
  3048. struct dst_entry *dst = NULL;
  3049. struct net_device *realdev;
  3050. __be16 local_port;
  3051. u32 port_id;
  3052. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3053. saddr->remote.v6.sin6_family == AF_INET6)
  3054. is_v6 = 1;
  3055. else if (saddr->local.v4.sin_family == AF_INET &&
  3056. saddr->remote.v4.sin_family == AF_INET)
  3057. is_v6 = 0;
  3058. else
  3059. return -EINVAL;
  3060. clear_bit(SK_F_IPV6, &csk->flags);
  3061. if (is_v6) {
  3062. set_bit(SK_F_IPV6, &csk->flags);
  3063. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3064. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3065. sizeof(struct in6_addr));
  3066. csk->dst_port = saddr->remote.v6.sin6_port;
  3067. local_port = saddr->local.v6.sin6_port;
  3068. } else {
  3069. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3070. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3071. csk->dst_port = saddr->remote.v4.sin_port;
  3072. local_port = saddr->local.v4.sin_port;
  3073. }
  3074. csk->vlan_id = 0;
  3075. csk->mtu = dev->netdev->mtu;
  3076. if (dst && dst->dev) {
  3077. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3078. if (realdev == dev->netdev) {
  3079. csk->vlan_id = vlan;
  3080. csk->mtu = dst_mtu(dst);
  3081. }
  3082. }
  3083. port_id = be16_to_cpu(local_port);
  3084. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3085. port_id < CNIC_LOCAL_PORT_MAX) {
  3086. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3087. port_id = 0;
  3088. } else
  3089. port_id = 0;
  3090. if (!port_id) {
  3091. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3092. if (port_id == -1) {
  3093. rc = -ENOMEM;
  3094. goto err_out;
  3095. }
  3096. local_port = cpu_to_be16(port_id);
  3097. }
  3098. csk->src_port = local_port;
  3099. err_out:
  3100. dst_release(dst);
  3101. return rc;
  3102. }
  3103. static void cnic_init_csk_state(struct cnic_sock *csk)
  3104. {
  3105. csk->state = 0;
  3106. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3107. clear_bit(SK_F_CLOSING, &csk->flags);
  3108. }
  3109. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3110. {
  3111. struct cnic_local *cp = csk->dev->cnic_priv;
  3112. int err = 0;
  3113. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3114. return -EOPNOTSUPP;
  3115. if (!cnic_in_use(csk))
  3116. return -EINVAL;
  3117. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3118. return -EINVAL;
  3119. cnic_init_csk_state(csk);
  3120. err = cnic_get_route(csk, saddr);
  3121. if (err)
  3122. goto err_out;
  3123. err = cnic_resolve_addr(csk, saddr);
  3124. if (!err)
  3125. return 0;
  3126. err_out:
  3127. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3128. return err;
  3129. }
  3130. static int cnic_cm_abort(struct cnic_sock *csk)
  3131. {
  3132. struct cnic_local *cp = csk->dev->cnic_priv;
  3133. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3134. if (!cnic_in_use(csk))
  3135. return -EINVAL;
  3136. if (cnic_abort_prep(csk))
  3137. return cnic_cm_abort_req(csk);
  3138. /* Getting here means that we haven't started connect, or
  3139. * connect was not successful.
  3140. */
  3141. cp->close_conn(csk, opcode);
  3142. if (csk->state != opcode)
  3143. return -EALREADY;
  3144. return 0;
  3145. }
  3146. static int cnic_cm_close(struct cnic_sock *csk)
  3147. {
  3148. if (!cnic_in_use(csk))
  3149. return -EINVAL;
  3150. if (cnic_close_prep(csk)) {
  3151. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3152. return cnic_cm_close_req(csk);
  3153. } else {
  3154. return -EALREADY;
  3155. }
  3156. return 0;
  3157. }
  3158. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3159. u8 opcode)
  3160. {
  3161. struct cnic_ulp_ops *ulp_ops;
  3162. int ulp_type = csk->ulp_type;
  3163. rcu_read_lock();
  3164. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3165. if (ulp_ops) {
  3166. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3167. ulp_ops->cm_connect_complete(csk);
  3168. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3169. ulp_ops->cm_close_complete(csk);
  3170. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3171. ulp_ops->cm_remote_abort(csk);
  3172. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3173. ulp_ops->cm_abort_complete(csk);
  3174. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3175. ulp_ops->cm_remote_close(csk);
  3176. }
  3177. rcu_read_unlock();
  3178. }
  3179. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3180. {
  3181. if (cnic_offld_prep(csk)) {
  3182. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3183. cnic_cm_update_pg(csk);
  3184. else
  3185. cnic_cm_offload_pg(csk);
  3186. }
  3187. return 0;
  3188. }
  3189. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3190. {
  3191. struct cnic_local *cp = dev->cnic_priv;
  3192. u32 l5_cid = kcqe->pg_host_opaque;
  3193. u8 opcode = kcqe->op_code;
  3194. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3195. csk_hold(csk);
  3196. if (!cnic_in_use(csk))
  3197. goto done;
  3198. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3199. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3200. goto done;
  3201. }
  3202. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3203. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3204. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3205. cnic_cm_upcall(cp, csk,
  3206. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3207. goto done;
  3208. }
  3209. csk->pg_cid = kcqe->pg_cid;
  3210. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3211. cnic_cm_conn_req(csk);
  3212. done:
  3213. csk_put(csk);
  3214. }
  3215. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3216. {
  3217. struct cnic_local *cp = dev->cnic_priv;
  3218. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3219. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3220. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3221. ctx->timestamp = jiffies;
  3222. ctx->wait_cond = 1;
  3223. wake_up(&ctx->waitq);
  3224. }
  3225. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3226. {
  3227. struct cnic_local *cp = dev->cnic_priv;
  3228. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3229. u8 opcode = l4kcqe->op_code;
  3230. u32 l5_cid;
  3231. struct cnic_sock *csk;
  3232. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3233. cnic_process_fcoe_term_conn(dev, kcqe);
  3234. return;
  3235. }
  3236. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3237. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3238. cnic_cm_process_offld_pg(dev, l4kcqe);
  3239. return;
  3240. }
  3241. l5_cid = l4kcqe->conn_id;
  3242. if (opcode & 0x80)
  3243. l5_cid = l4kcqe->cid;
  3244. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3245. return;
  3246. csk = &cp->csk_tbl[l5_cid];
  3247. csk_hold(csk);
  3248. if (!cnic_in_use(csk)) {
  3249. csk_put(csk);
  3250. return;
  3251. }
  3252. switch (opcode) {
  3253. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3254. if (l4kcqe->status != 0) {
  3255. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3256. cnic_cm_upcall(cp, csk,
  3257. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3258. }
  3259. break;
  3260. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3261. if (l4kcqe->status == 0)
  3262. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3263. else if (l4kcqe->status ==
  3264. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3265. set_bit(SK_F_HW_ERR, &csk->flags);
  3266. smp_mb__before_clear_bit();
  3267. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3268. cnic_cm_upcall(cp, csk, opcode);
  3269. break;
  3270. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3271. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3272. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3273. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3274. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3275. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3276. set_bit(SK_F_HW_ERR, &csk->flags);
  3277. cp->close_conn(csk, opcode);
  3278. break;
  3279. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3280. /* after we already sent CLOSE_REQ */
  3281. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3282. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3283. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3284. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3285. else
  3286. cnic_cm_upcall(cp, csk, opcode);
  3287. break;
  3288. }
  3289. csk_put(csk);
  3290. }
  3291. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3292. {
  3293. struct cnic_dev *dev = data;
  3294. int i;
  3295. for (i = 0; i < num; i++)
  3296. cnic_cm_process_kcqe(dev, kcqe[i]);
  3297. }
  3298. static struct cnic_ulp_ops cm_ulp_ops = {
  3299. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3300. };
  3301. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3302. {
  3303. struct cnic_local *cp = dev->cnic_priv;
  3304. kfree(cp->csk_tbl);
  3305. cp->csk_tbl = NULL;
  3306. cnic_free_id_tbl(&cp->csk_port_tbl);
  3307. }
  3308. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3309. {
  3310. struct cnic_local *cp = dev->cnic_priv;
  3311. u32 port_id;
  3312. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3313. GFP_KERNEL);
  3314. if (!cp->csk_tbl)
  3315. return -ENOMEM;
  3316. port_id = random32();
  3317. port_id %= CNIC_LOCAL_PORT_RANGE;
  3318. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3319. CNIC_LOCAL_PORT_MIN, port_id)) {
  3320. cnic_cm_free_mem(dev);
  3321. return -ENOMEM;
  3322. }
  3323. return 0;
  3324. }
  3325. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3326. {
  3327. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3328. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3329. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3330. csk->state = opcode;
  3331. }
  3332. /* 1. If event opcode matches the expected event in csk->state
  3333. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3334. * event
  3335. * 3. If the expected event is 0, meaning the connection was never
  3336. * never established, we accept the opcode from cm_abort.
  3337. */
  3338. if (opcode == csk->state || csk->state == 0 ||
  3339. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3340. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3341. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3342. if (csk->state == 0)
  3343. csk->state = opcode;
  3344. return 1;
  3345. }
  3346. }
  3347. return 0;
  3348. }
  3349. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3350. {
  3351. struct cnic_dev *dev = csk->dev;
  3352. struct cnic_local *cp = dev->cnic_priv;
  3353. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3354. cnic_cm_upcall(cp, csk, opcode);
  3355. return;
  3356. }
  3357. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3358. cnic_close_conn(csk);
  3359. csk->state = opcode;
  3360. cnic_cm_upcall(cp, csk, opcode);
  3361. }
  3362. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3363. {
  3364. }
  3365. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3366. {
  3367. u32 seed;
  3368. seed = random32();
  3369. cnic_ctx_wr(dev, 45, 0, seed);
  3370. return 0;
  3371. }
  3372. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3373. {
  3374. struct cnic_dev *dev = csk->dev;
  3375. struct cnic_local *cp = dev->cnic_priv;
  3376. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3377. union l5cm_specific_data l5_data;
  3378. u32 cmd = 0;
  3379. int close_complete = 0;
  3380. switch (opcode) {
  3381. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3382. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3383. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3384. if (cnic_ready_to_close(csk, opcode)) {
  3385. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3386. close_complete = 1;
  3387. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3388. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3389. else
  3390. close_complete = 1;
  3391. }
  3392. break;
  3393. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3394. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3395. break;
  3396. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3397. close_complete = 1;
  3398. break;
  3399. }
  3400. if (cmd) {
  3401. memset(&l5_data, 0, sizeof(l5_data));
  3402. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3403. &l5_data);
  3404. } else if (close_complete) {
  3405. ctx->timestamp = jiffies;
  3406. cnic_close_conn(csk);
  3407. cnic_cm_upcall(cp, csk, csk->state);
  3408. }
  3409. }
  3410. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3411. {
  3412. struct cnic_local *cp = dev->cnic_priv;
  3413. if (!cp->ctx_tbl)
  3414. return;
  3415. if (!netif_running(dev->netdev))
  3416. return;
  3417. cnic_bnx2x_delete_wait(dev, 0);
  3418. cancel_delayed_work(&cp->delete_task);
  3419. flush_workqueue(cnic_wq);
  3420. if (atomic_read(&cp->iscsi_conn) != 0)
  3421. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3422. atomic_read(&cp->iscsi_conn));
  3423. }
  3424. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3425. {
  3426. struct cnic_local *cp = dev->cnic_priv;
  3427. u32 pfid = cp->pfid;
  3428. u32 port = CNIC_PORT(cp);
  3429. cnic_init_bnx2x_mac(dev);
  3430. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3431. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3432. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3433. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3434. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3435. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3436. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3437. DEF_MAX_DA_COUNT);
  3438. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3439. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3440. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3441. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3442. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3443. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3444. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3445. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3446. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3447. DEF_MAX_CWND);
  3448. return 0;
  3449. }
  3450. static void cnic_delete_task(struct work_struct *work)
  3451. {
  3452. struct cnic_local *cp;
  3453. struct cnic_dev *dev;
  3454. u32 i;
  3455. int need_resched = 0;
  3456. cp = container_of(work, struct cnic_local, delete_task.work);
  3457. dev = cp->dev;
  3458. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3459. struct drv_ctl_info info;
  3460. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3461. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3462. cp->ethdev->drv_ctl(dev->netdev, &info);
  3463. }
  3464. for (i = 0; i < cp->max_cid_space; i++) {
  3465. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3466. int err;
  3467. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3468. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3469. continue;
  3470. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3471. need_resched = 1;
  3472. continue;
  3473. }
  3474. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3475. continue;
  3476. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3477. cnic_free_bnx2x_conn_resc(dev, i);
  3478. if (!err) {
  3479. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3480. atomic_dec(&cp->iscsi_conn);
  3481. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3482. }
  3483. }
  3484. if (need_resched)
  3485. queue_delayed_work(cnic_wq, &cp->delete_task,
  3486. msecs_to_jiffies(10));
  3487. }
  3488. static int cnic_cm_open(struct cnic_dev *dev)
  3489. {
  3490. struct cnic_local *cp = dev->cnic_priv;
  3491. int err;
  3492. err = cnic_cm_alloc_mem(dev);
  3493. if (err)
  3494. return err;
  3495. err = cp->start_cm(dev);
  3496. if (err)
  3497. goto err_out;
  3498. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3499. dev->cm_create = cnic_cm_create;
  3500. dev->cm_destroy = cnic_cm_destroy;
  3501. dev->cm_connect = cnic_cm_connect;
  3502. dev->cm_abort = cnic_cm_abort;
  3503. dev->cm_close = cnic_cm_close;
  3504. dev->cm_select_dev = cnic_cm_select_dev;
  3505. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3506. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3507. return 0;
  3508. err_out:
  3509. cnic_cm_free_mem(dev);
  3510. return err;
  3511. }
  3512. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3513. {
  3514. struct cnic_local *cp = dev->cnic_priv;
  3515. int i;
  3516. cp->stop_cm(dev);
  3517. if (!cp->csk_tbl)
  3518. return 0;
  3519. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3520. struct cnic_sock *csk = &cp->csk_tbl[i];
  3521. clear_bit(SK_F_INUSE, &csk->flags);
  3522. cnic_cm_cleanup(csk);
  3523. }
  3524. cnic_cm_free_mem(dev);
  3525. return 0;
  3526. }
  3527. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3528. {
  3529. u32 cid_addr;
  3530. int i;
  3531. cid_addr = GET_CID_ADDR(cid);
  3532. for (i = 0; i < CTX_SIZE; i += 4)
  3533. cnic_ctx_wr(dev, cid_addr, i, 0);
  3534. }
  3535. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3536. {
  3537. struct cnic_local *cp = dev->cnic_priv;
  3538. int ret = 0, i;
  3539. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3540. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3541. return 0;
  3542. for (i = 0; i < cp->ctx_blks; i++) {
  3543. int j;
  3544. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3545. u32 val;
  3546. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3547. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3548. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3549. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3550. (u64) cp->ctx_arr[i].mapping >> 32);
  3551. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3552. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3553. for (j = 0; j < 10; j++) {
  3554. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3555. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3556. break;
  3557. udelay(5);
  3558. }
  3559. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3560. ret = -EBUSY;
  3561. break;
  3562. }
  3563. }
  3564. return ret;
  3565. }
  3566. static void cnic_free_irq(struct cnic_dev *dev)
  3567. {
  3568. struct cnic_local *cp = dev->cnic_priv;
  3569. struct cnic_eth_dev *ethdev = cp->ethdev;
  3570. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3571. cp->disable_int_sync(dev);
  3572. tasklet_kill(&cp->cnic_irq_task);
  3573. free_irq(ethdev->irq_arr[0].vector, dev);
  3574. }
  3575. }
  3576. static int cnic_request_irq(struct cnic_dev *dev)
  3577. {
  3578. struct cnic_local *cp = dev->cnic_priv;
  3579. struct cnic_eth_dev *ethdev = cp->ethdev;
  3580. int err;
  3581. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3582. if (err)
  3583. tasklet_disable(&cp->cnic_irq_task);
  3584. return err;
  3585. }
  3586. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3587. {
  3588. struct cnic_local *cp = dev->cnic_priv;
  3589. struct cnic_eth_dev *ethdev = cp->ethdev;
  3590. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3591. int err, i = 0;
  3592. int sblk_num = cp->status_blk_num;
  3593. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3594. BNX2_HC_SB_CONFIG_1;
  3595. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3596. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3597. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3598. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3599. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3600. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3601. (unsigned long) dev);
  3602. err = cnic_request_irq(dev);
  3603. if (err)
  3604. return err;
  3605. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3606. i < 10) {
  3607. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3608. 1 << (11 + sblk_num));
  3609. udelay(10);
  3610. i++;
  3611. barrier();
  3612. }
  3613. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3614. cnic_free_irq(dev);
  3615. goto failed;
  3616. }
  3617. } else {
  3618. struct status_block *sblk = cp->status_blk.gen;
  3619. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3620. int i = 0;
  3621. while (sblk->status_completion_producer_index && i < 10) {
  3622. CNIC_WR(dev, BNX2_HC_COMMAND,
  3623. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3624. udelay(10);
  3625. i++;
  3626. barrier();
  3627. }
  3628. if (sblk->status_completion_producer_index)
  3629. goto failed;
  3630. }
  3631. return 0;
  3632. failed:
  3633. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3634. return -EBUSY;
  3635. }
  3636. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3637. {
  3638. struct cnic_local *cp = dev->cnic_priv;
  3639. struct cnic_eth_dev *ethdev = cp->ethdev;
  3640. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3641. return;
  3642. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3643. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3644. }
  3645. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3646. {
  3647. struct cnic_local *cp = dev->cnic_priv;
  3648. struct cnic_eth_dev *ethdev = cp->ethdev;
  3649. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3650. return;
  3651. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3652. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3653. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3654. synchronize_irq(ethdev->irq_arr[0].vector);
  3655. }
  3656. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3657. {
  3658. struct cnic_local *cp = dev->cnic_priv;
  3659. struct cnic_eth_dev *ethdev = cp->ethdev;
  3660. struct cnic_uio_dev *udev = cp->udev;
  3661. u32 cid_addr, tx_cid, sb_id;
  3662. u32 val, offset0, offset1, offset2, offset3;
  3663. int i;
  3664. struct tx_bd *txbd;
  3665. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3666. struct status_block *s_blk = cp->status_blk.gen;
  3667. sb_id = cp->status_blk_num;
  3668. tx_cid = 20;
  3669. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3670. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3671. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3672. tx_cid = TX_TSS_CID + sb_id - 1;
  3673. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3674. (TX_TSS_CID << 7));
  3675. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3676. }
  3677. cp->tx_cons = *cp->tx_cons_ptr;
  3678. cid_addr = GET_CID_ADDR(tx_cid);
  3679. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3680. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3681. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3682. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3683. offset0 = BNX2_L2CTX_TYPE_XI;
  3684. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3685. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3686. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3687. } else {
  3688. cnic_init_context(dev, tx_cid);
  3689. cnic_init_context(dev, tx_cid + 1);
  3690. offset0 = BNX2_L2CTX_TYPE;
  3691. offset1 = BNX2_L2CTX_CMD_TYPE;
  3692. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3693. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3694. }
  3695. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3696. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3697. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3698. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3699. txbd = udev->l2_ring;
  3700. buf_map = udev->l2_buf_map;
  3701. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3702. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3703. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3704. }
  3705. val = (u64) ring_map >> 32;
  3706. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3707. txbd->tx_bd_haddr_hi = val;
  3708. val = (u64) ring_map & 0xffffffff;
  3709. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3710. txbd->tx_bd_haddr_lo = val;
  3711. }
  3712. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3713. {
  3714. struct cnic_local *cp = dev->cnic_priv;
  3715. struct cnic_eth_dev *ethdev = cp->ethdev;
  3716. struct cnic_uio_dev *udev = cp->udev;
  3717. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3718. int i;
  3719. struct rx_bd *rxbd;
  3720. struct status_block *s_blk = cp->status_blk.gen;
  3721. dma_addr_t ring_map = udev->l2_ring_map;
  3722. sb_id = cp->status_blk_num;
  3723. cnic_init_context(dev, 2);
  3724. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3725. coal_reg = BNX2_HC_COMMAND;
  3726. coal_val = CNIC_RD(dev, coal_reg);
  3727. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3728. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3729. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3730. coal_reg = BNX2_HC_COALESCE_NOW;
  3731. coal_val = 1 << (11 + sb_id);
  3732. }
  3733. i = 0;
  3734. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3735. CNIC_WR(dev, coal_reg, coal_val);
  3736. udelay(10);
  3737. i++;
  3738. barrier();
  3739. }
  3740. cp->rx_cons = *cp->rx_cons_ptr;
  3741. cid_addr = GET_CID_ADDR(2);
  3742. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3743. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3744. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3745. if (sb_id == 0)
  3746. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3747. else
  3748. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3749. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3750. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3751. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3752. dma_addr_t buf_map;
  3753. int n = (i % cp->l2_rx_ring_size) + 1;
  3754. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3755. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3756. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3757. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3758. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3759. }
  3760. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3761. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3762. rxbd->rx_bd_haddr_hi = val;
  3763. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3764. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3765. rxbd->rx_bd_haddr_lo = val;
  3766. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3767. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3768. }
  3769. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3770. {
  3771. struct kwqe *wqes[1], l2kwqe;
  3772. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3773. wqes[0] = &l2kwqe;
  3774. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3775. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3776. KWQE_OPCODE_SHIFT) | 2;
  3777. dev->submit_kwqes(dev, wqes, 1);
  3778. }
  3779. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3780. {
  3781. struct cnic_local *cp = dev->cnic_priv;
  3782. u32 val;
  3783. val = cp->func << 2;
  3784. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3785. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3786. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3787. dev->mac_addr[0] = (u8) (val >> 8);
  3788. dev->mac_addr[1] = (u8) val;
  3789. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3790. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3791. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3792. dev->mac_addr[2] = (u8) (val >> 24);
  3793. dev->mac_addr[3] = (u8) (val >> 16);
  3794. dev->mac_addr[4] = (u8) (val >> 8);
  3795. dev->mac_addr[5] = (u8) val;
  3796. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3797. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3798. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3799. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3800. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3801. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3802. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3803. }
  3804. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3805. {
  3806. struct cnic_local *cp = dev->cnic_priv;
  3807. struct cnic_eth_dev *ethdev = cp->ethdev;
  3808. struct status_block *sblk = cp->status_blk.gen;
  3809. u32 val, kcq_cid_addr, kwq_cid_addr;
  3810. int err;
  3811. cnic_set_bnx2_mac(dev);
  3812. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3813. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3814. if (BCM_PAGE_BITS > 12)
  3815. val |= (12 - 8) << 4;
  3816. else
  3817. val |= (BCM_PAGE_BITS - 8) << 4;
  3818. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3819. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3820. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3821. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3822. err = cnic_setup_5709_context(dev, 1);
  3823. if (err)
  3824. return err;
  3825. cnic_init_context(dev, KWQ_CID);
  3826. cnic_init_context(dev, KCQ_CID);
  3827. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3828. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3829. cp->max_kwq_idx = MAX_KWQ_IDX;
  3830. cp->kwq_prod_idx = 0;
  3831. cp->kwq_con_idx = 0;
  3832. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3833. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3834. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3835. else
  3836. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3837. /* Initialize the kernel work queue context. */
  3838. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3839. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3840. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3841. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3842. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3843. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3844. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3845. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3846. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3847. val = (u32) cp->kwq_info.pgtbl_map;
  3848. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3849. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3850. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3851. cp->kcq1.sw_prod_idx = 0;
  3852. cp->kcq1.hw_prod_idx_ptr =
  3853. (u16 *) &sblk->status_completion_producer_index;
  3854. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3855. /* Initialize the kernel complete queue context. */
  3856. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3857. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3858. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3859. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3860. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3861. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3862. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3863. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3864. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3865. val = (u32) cp->kcq1.dma.pgtbl_map;
  3866. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3867. cp->int_num = 0;
  3868. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3869. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3870. u32 sb_id = cp->status_blk_num;
  3871. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3872. cp->kcq1.hw_prod_idx_ptr =
  3873. (u16 *) &msblk->status_completion_producer_index;
  3874. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3875. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3876. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3877. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3878. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3879. }
  3880. /* Enable Commnad Scheduler notification when we write to the
  3881. * host producer index of the kernel contexts. */
  3882. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3883. /* Enable Command Scheduler notification when we write to either
  3884. * the Send Queue or Receive Queue producer indexes of the kernel
  3885. * bypass contexts. */
  3886. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3887. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3888. /* Notify COM when the driver post an application buffer. */
  3889. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3890. /* Set the CP and COM doorbells. These two processors polls the
  3891. * doorbell for a non zero value before running. This must be done
  3892. * after setting up the kernel queue contexts. */
  3893. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3894. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3895. cnic_init_bnx2_tx_ring(dev);
  3896. cnic_init_bnx2_rx_ring(dev);
  3897. err = cnic_init_bnx2_irq(dev);
  3898. if (err) {
  3899. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3900. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3901. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3902. return err;
  3903. }
  3904. return 0;
  3905. }
  3906. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3907. {
  3908. struct cnic_local *cp = dev->cnic_priv;
  3909. struct cnic_eth_dev *ethdev = cp->ethdev;
  3910. u32 start_offset = ethdev->ctx_tbl_offset;
  3911. int i;
  3912. for (i = 0; i < cp->ctx_blks; i++) {
  3913. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3914. dma_addr_t map = ctx->mapping;
  3915. if (cp->ctx_align) {
  3916. unsigned long mask = cp->ctx_align - 1;
  3917. map = (map + mask) & ~mask;
  3918. }
  3919. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3920. }
  3921. }
  3922. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3923. {
  3924. struct cnic_local *cp = dev->cnic_priv;
  3925. struct cnic_eth_dev *ethdev = cp->ethdev;
  3926. int err = 0;
  3927. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3928. (unsigned long) dev);
  3929. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3930. err = cnic_request_irq(dev);
  3931. return err;
  3932. }
  3933. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3934. u16 sb_id, u8 sb_index,
  3935. u8 disable)
  3936. {
  3937. u32 addr = BAR_CSTRORM_INTMEM +
  3938. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3939. offsetof(struct hc_status_block_data_e1x, index_data) +
  3940. sizeof(struct hc_index_data)*sb_index +
  3941. offsetof(struct hc_index_data, flags);
  3942. u16 flags = CNIC_RD16(dev, addr);
  3943. /* clear and set */
  3944. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3945. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3946. HC_INDEX_DATA_HC_ENABLED);
  3947. CNIC_WR16(dev, addr, flags);
  3948. }
  3949. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3950. {
  3951. struct cnic_local *cp = dev->cnic_priv;
  3952. u8 sb_id = cp->status_blk_num;
  3953. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3954. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3955. offsetof(struct hc_status_block_data_e1x, index_data) +
  3956. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3957. offsetof(struct hc_index_data, timeout), 64 / 4);
  3958. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3959. }
  3960. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3961. {
  3962. }
  3963. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3964. struct client_init_ramrod_data *data)
  3965. {
  3966. struct cnic_local *cp = dev->cnic_priv;
  3967. struct cnic_uio_dev *udev = cp->udev;
  3968. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3969. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3970. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3971. int i;
  3972. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3973. u32 val;
  3974. memset(txbd, 0, BCM_PAGE_SIZE);
  3975. buf_map = udev->l2_buf_map;
  3976. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3977. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3978. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3979. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3980. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3981. reg_bd->addr_hi = start_bd->addr_hi;
  3982. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3983. start_bd->nbytes = cpu_to_le16(0x10);
  3984. start_bd->nbd = cpu_to_le16(3);
  3985. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3986. start_bd->general_data = (UNICAST_ADDRESS <<
  3987. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3988. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3989. }
  3990. val = (u64) ring_map >> 32;
  3991. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3992. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3993. val = (u64) ring_map & 0xffffffff;
  3994. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3995. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3996. /* Other ramrod params */
  3997. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3998. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3999. /* reset xstorm per client statistics */
  4000. if (cli < MAX_STAT_COUNTER_ID) {
  4001. data->general.statistics_zero_flg = 1;
  4002. data->general.statistics_en_flg = 1;
  4003. data->general.statistics_counter_id = cli;
  4004. }
  4005. cp->tx_cons_ptr =
  4006. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4007. }
  4008. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4009. struct client_init_ramrod_data *data)
  4010. {
  4011. struct cnic_local *cp = dev->cnic_priv;
  4012. struct cnic_uio_dev *udev = cp->udev;
  4013. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4014. BCM_PAGE_SIZE);
  4015. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4016. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  4017. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4018. int i;
  4019. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4020. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4021. u32 val;
  4022. dma_addr_t ring_map = udev->l2_ring_map;
  4023. /* General data */
  4024. data->general.client_id = cli;
  4025. data->general.activate_flg = 1;
  4026. data->general.sp_client_id = cli;
  4027. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4028. data->general.func_id = cp->pfid;
  4029. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4030. dma_addr_t buf_map;
  4031. int n = (i % cp->l2_rx_ring_size) + 1;
  4032. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4033. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4034. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4035. }
  4036. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  4037. rxbd->addr_hi = cpu_to_le32(val);
  4038. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4039. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  4040. rxbd->addr_lo = cpu_to_le32(val);
  4041. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4042. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4043. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  4044. rxcqe->addr_hi = cpu_to_le32(val);
  4045. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4046. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  4047. rxcqe->addr_lo = cpu_to_le32(val);
  4048. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4049. /* Other ramrod params */
  4050. data->rx.client_qzone_id = cl_qzone_id;
  4051. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4052. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4053. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4054. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4055. data->rx.outer_vlan_removal_enable_flg = 1;
  4056. data->rx.silent_vlan_removal_flg = 1;
  4057. data->rx.silent_vlan_value = 0;
  4058. data->rx.silent_vlan_mask = 0xffff;
  4059. cp->rx_cons_ptr =
  4060. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4061. cp->rx_cons = *cp->rx_cons_ptr;
  4062. }
  4063. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4064. {
  4065. struct cnic_local *cp = dev->cnic_priv;
  4066. u32 pfid = cp->pfid;
  4067. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4068. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4069. cp->kcq1.sw_prod_idx = 0;
  4070. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4071. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4072. cp->kcq1.hw_prod_idx_ptr =
  4073. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4074. cp->kcq1.status_idx_ptr =
  4075. &sb->sb.running_index[SM_RX_ID];
  4076. } else {
  4077. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4078. cp->kcq1.hw_prod_idx_ptr =
  4079. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4080. cp->kcq1.status_idx_ptr =
  4081. &sb->sb.running_index[SM_RX_ID];
  4082. }
  4083. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4084. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4085. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4086. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4087. cp->kcq2.sw_prod_idx = 0;
  4088. cp->kcq2.hw_prod_idx_ptr =
  4089. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4090. cp->kcq2.status_idx_ptr =
  4091. &sb->sb.running_index[SM_RX_ID];
  4092. }
  4093. }
  4094. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4095. {
  4096. struct cnic_local *cp = dev->cnic_priv;
  4097. struct cnic_eth_dev *ethdev = cp->ethdev;
  4098. int func = CNIC_FUNC(cp), ret;
  4099. u32 pfid;
  4100. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4101. cp->port_mode = CHIP_PORT_MODE_NONE;
  4102. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4103. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4104. if (!(val & 1))
  4105. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4106. else
  4107. val = (val >> 1) & 1;
  4108. if (val) {
  4109. cp->port_mode = CHIP_4_PORT_MODE;
  4110. cp->pfid = func >> 1;
  4111. } else {
  4112. cp->port_mode = CHIP_2_PORT_MODE;
  4113. cp->pfid = func & 0x6;
  4114. }
  4115. } else {
  4116. cp->pfid = func;
  4117. }
  4118. pfid = cp->pfid;
  4119. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4120. cp->iscsi_start_cid, 0);
  4121. if (ret)
  4122. return -ENOMEM;
  4123. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4124. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4125. cp->fcoe_start_cid, 0);
  4126. if (ret)
  4127. return -ENOMEM;
  4128. }
  4129. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4130. cnic_init_bnx2x_kcq(dev);
  4131. /* Only 1 EQ */
  4132. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4133. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4134. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4135. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4136. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4137. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4138. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4139. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4140. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4141. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4142. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4143. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4144. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4145. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4146. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4147. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4148. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4149. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4150. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4151. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4152. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4153. HC_INDEX_ISCSI_EQ_CONS);
  4154. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4155. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4156. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4157. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4158. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4159. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4160. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4161. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4162. cnic_setup_bnx2x_context(dev);
  4163. ret = cnic_init_bnx2x_irq(dev);
  4164. if (ret)
  4165. return ret;
  4166. return 0;
  4167. }
  4168. static void cnic_init_rings(struct cnic_dev *dev)
  4169. {
  4170. struct cnic_local *cp = dev->cnic_priv;
  4171. struct cnic_uio_dev *udev = cp->udev;
  4172. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4173. return;
  4174. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4175. cnic_init_bnx2_tx_ring(dev);
  4176. cnic_init_bnx2_rx_ring(dev);
  4177. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4178. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4179. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4180. u32 cid = cp->ethdev->iscsi_l2_cid;
  4181. u32 cl_qzone_id;
  4182. struct client_init_ramrod_data *data;
  4183. union l5cm_specific_data l5_data;
  4184. struct ustorm_eth_rx_producers rx_prods = {0};
  4185. u32 off, i, *cid_ptr;
  4186. rx_prods.bd_prod = 0;
  4187. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4188. barrier();
  4189. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4190. off = BAR_USTRORM_INTMEM +
  4191. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4192. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4193. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4194. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4195. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4196. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4197. data = udev->l2_buf;
  4198. cid_ptr = udev->l2_buf + 12;
  4199. memset(data, 0, sizeof(*data));
  4200. cnic_init_bnx2x_tx_ring(dev, data);
  4201. cnic_init_bnx2x_rx_ring(dev, data);
  4202. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4203. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4204. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4205. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4206. cid, ETH_CONNECTION_TYPE, &l5_data);
  4207. i = 0;
  4208. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4209. ++i < 10)
  4210. msleep(1);
  4211. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4212. netdev_err(dev->netdev,
  4213. "iSCSI CLIENT_SETUP did not complete\n");
  4214. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4215. cnic_ring_ctl(dev, cid, cli, 1);
  4216. *cid_ptr = cid;
  4217. }
  4218. }
  4219. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4220. {
  4221. struct cnic_local *cp = dev->cnic_priv;
  4222. struct cnic_uio_dev *udev = cp->udev;
  4223. void *rx_ring;
  4224. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4225. return;
  4226. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4227. cnic_shutdown_bnx2_rx_ring(dev);
  4228. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4229. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4230. u32 cid = cp->ethdev->iscsi_l2_cid;
  4231. union l5cm_specific_data l5_data;
  4232. int i;
  4233. cnic_ring_ctl(dev, cid, cli, 0);
  4234. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4235. l5_data.phy_address.lo = cli;
  4236. l5_data.phy_address.hi = 0;
  4237. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4238. cid, ETH_CONNECTION_TYPE, &l5_data);
  4239. i = 0;
  4240. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4241. ++i < 10)
  4242. msleep(1);
  4243. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4244. netdev_err(dev->netdev,
  4245. "iSCSI CLIENT_HALT did not complete\n");
  4246. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4247. memset(&l5_data, 0, sizeof(l5_data));
  4248. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4249. cid, NONE_CONNECTION_TYPE, &l5_data);
  4250. msleep(10);
  4251. }
  4252. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4253. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4254. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4255. }
  4256. static int cnic_register_netdev(struct cnic_dev *dev)
  4257. {
  4258. struct cnic_local *cp = dev->cnic_priv;
  4259. struct cnic_eth_dev *ethdev = cp->ethdev;
  4260. int err;
  4261. if (!ethdev)
  4262. return -ENODEV;
  4263. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4264. return 0;
  4265. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4266. if (err)
  4267. netdev_err(dev->netdev, "register_cnic failed\n");
  4268. return err;
  4269. }
  4270. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4271. {
  4272. struct cnic_local *cp = dev->cnic_priv;
  4273. struct cnic_eth_dev *ethdev = cp->ethdev;
  4274. if (!ethdev)
  4275. return;
  4276. ethdev->drv_unregister_cnic(dev->netdev);
  4277. }
  4278. static int cnic_start_hw(struct cnic_dev *dev)
  4279. {
  4280. struct cnic_local *cp = dev->cnic_priv;
  4281. struct cnic_eth_dev *ethdev = cp->ethdev;
  4282. int err;
  4283. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4284. return -EALREADY;
  4285. dev->regview = ethdev->io_base;
  4286. pci_dev_get(dev->pcidev);
  4287. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4288. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4289. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4290. err = cp->alloc_resc(dev);
  4291. if (err) {
  4292. netdev_err(dev->netdev, "allocate resource failure\n");
  4293. goto err1;
  4294. }
  4295. err = cp->start_hw(dev);
  4296. if (err)
  4297. goto err1;
  4298. err = cnic_cm_open(dev);
  4299. if (err)
  4300. goto err1;
  4301. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4302. cp->enable_int(dev);
  4303. return 0;
  4304. err1:
  4305. cp->free_resc(dev);
  4306. pci_dev_put(dev->pcidev);
  4307. return err;
  4308. }
  4309. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4310. {
  4311. cnic_disable_bnx2_int_sync(dev);
  4312. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4313. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4314. cnic_init_context(dev, KWQ_CID);
  4315. cnic_init_context(dev, KCQ_CID);
  4316. cnic_setup_5709_context(dev, 0);
  4317. cnic_free_irq(dev);
  4318. cnic_free_resc(dev);
  4319. }
  4320. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4321. {
  4322. struct cnic_local *cp = dev->cnic_priv;
  4323. cnic_free_irq(dev);
  4324. *cp->kcq1.hw_prod_idx_ptr = 0;
  4325. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4326. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4327. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4328. cnic_free_resc(dev);
  4329. }
  4330. static void cnic_stop_hw(struct cnic_dev *dev)
  4331. {
  4332. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4333. struct cnic_local *cp = dev->cnic_priv;
  4334. int i = 0;
  4335. /* Need to wait for the ring shutdown event to complete
  4336. * before clearing the CNIC_UP flag.
  4337. */
  4338. while (cp->udev->uio_dev != -1 && i < 15) {
  4339. msleep(100);
  4340. i++;
  4341. }
  4342. cnic_shutdown_rings(dev);
  4343. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4344. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4345. synchronize_rcu();
  4346. cnic_cm_shutdown(dev);
  4347. cp->stop_hw(dev);
  4348. pci_dev_put(dev->pcidev);
  4349. }
  4350. }
  4351. static void cnic_free_dev(struct cnic_dev *dev)
  4352. {
  4353. int i = 0;
  4354. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4355. msleep(100);
  4356. i++;
  4357. }
  4358. if (atomic_read(&dev->ref_count) != 0)
  4359. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4360. netdev_info(dev->netdev, "Removed CNIC device\n");
  4361. dev_put(dev->netdev);
  4362. kfree(dev);
  4363. }
  4364. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4365. struct pci_dev *pdev)
  4366. {
  4367. struct cnic_dev *cdev;
  4368. struct cnic_local *cp;
  4369. int alloc_size;
  4370. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4371. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4372. if (cdev == NULL) {
  4373. netdev_err(dev, "allocate dev struct failure\n");
  4374. return NULL;
  4375. }
  4376. cdev->netdev = dev;
  4377. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4378. cdev->register_device = cnic_register_device;
  4379. cdev->unregister_device = cnic_unregister_device;
  4380. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4381. cp = cdev->cnic_priv;
  4382. cp->dev = cdev;
  4383. cp->l2_single_buf_size = 0x400;
  4384. cp->l2_rx_ring_size = 3;
  4385. spin_lock_init(&cp->cnic_ulp_lock);
  4386. netdev_info(dev, "Added CNIC device\n");
  4387. return cdev;
  4388. }
  4389. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4390. {
  4391. struct pci_dev *pdev;
  4392. struct cnic_dev *cdev;
  4393. struct cnic_local *cp;
  4394. struct cnic_eth_dev *ethdev = NULL;
  4395. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4396. probe = symbol_get(bnx2_cnic_probe);
  4397. if (probe) {
  4398. ethdev = (*probe)(dev);
  4399. symbol_put(bnx2_cnic_probe);
  4400. }
  4401. if (!ethdev)
  4402. return NULL;
  4403. pdev = ethdev->pdev;
  4404. if (!pdev)
  4405. return NULL;
  4406. dev_hold(dev);
  4407. pci_dev_get(pdev);
  4408. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4409. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4410. (pdev->revision < 0x10)) {
  4411. pci_dev_put(pdev);
  4412. goto cnic_err;
  4413. }
  4414. pci_dev_put(pdev);
  4415. cdev = cnic_alloc_dev(dev, pdev);
  4416. if (cdev == NULL)
  4417. goto cnic_err;
  4418. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4419. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4420. cp = cdev->cnic_priv;
  4421. cp->ethdev = ethdev;
  4422. cdev->pcidev = pdev;
  4423. cp->chip_id = ethdev->chip_id;
  4424. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4425. cp->cnic_ops = &cnic_bnx2_ops;
  4426. cp->start_hw = cnic_start_bnx2_hw;
  4427. cp->stop_hw = cnic_stop_bnx2_hw;
  4428. cp->setup_pgtbl = cnic_setup_page_tbl;
  4429. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4430. cp->free_resc = cnic_free_resc;
  4431. cp->start_cm = cnic_cm_init_bnx2_hw;
  4432. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4433. cp->enable_int = cnic_enable_bnx2_int;
  4434. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4435. cp->close_conn = cnic_close_bnx2_conn;
  4436. return cdev;
  4437. cnic_err:
  4438. dev_put(dev);
  4439. return NULL;
  4440. }
  4441. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4442. {
  4443. struct pci_dev *pdev;
  4444. struct cnic_dev *cdev;
  4445. struct cnic_local *cp;
  4446. struct cnic_eth_dev *ethdev = NULL;
  4447. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4448. probe = symbol_get(bnx2x_cnic_probe);
  4449. if (probe) {
  4450. ethdev = (*probe)(dev);
  4451. symbol_put(bnx2x_cnic_probe);
  4452. }
  4453. if (!ethdev)
  4454. return NULL;
  4455. pdev = ethdev->pdev;
  4456. if (!pdev)
  4457. return NULL;
  4458. dev_hold(dev);
  4459. cdev = cnic_alloc_dev(dev, pdev);
  4460. if (cdev == NULL) {
  4461. dev_put(dev);
  4462. return NULL;
  4463. }
  4464. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4465. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4466. cp = cdev->cnic_priv;
  4467. cp->ethdev = ethdev;
  4468. cdev->pcidev = pdev;
  4469. cp->chip_id = ethdev->chip_id;
  4470. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4471. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4472. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4473. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4474. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4475. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4476. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4477. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4478. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4479. cp->cnic_ops = &cnic_bnx2x_ops;
  4480. cp->start_hw = cnic_start_bnx2x_hw;
  4481. cp->stop_hw = cnic_stop_bnx2x_hw;
  4482. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4483. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4484. cp->free_resc = cnic_free_resc;
  4485. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4486. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4487. cp->enable_int = cnic_enable_bnx2x_int;
  4488. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4489. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4490. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4491. else
  4492. cp->ack_int = cnic_ack_bnx2x_msix;
  4493. cp->close_conn = cnic_close_bnx2x_conn;
  4494. return cdev;
  4495. }
  4496. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4497. {
  4498. struct ethtool_drvinfo drvinfo;
  4499. struct cnic_dev *cdev = NULL;
  4500. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4501. memset(&drvinfo, 0, sizeof(drvinfo));
  4502. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4503. if (!strcmp(drvinfo.driver, "bnx2"))
  4504. cdev = init_bnx2_cnic(dev);
  4505. if (!strcmp(drvinfo.driver, "bnx2x"))
  4506. cdev = init_bnx2x_cnic(dev);
  4507. if (cdev) {
  4508. write_lock(&cnic_dev_lock);
  4509. list_add(&cdev->list, &cnic_dev_list);
  4510. write_unlock(&cnic_dev_lock);
  4511. }
  4512. }
  4513. return cdev;
  4514. }
  4515. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4516. u16 vlan_id)
  4517. {
  4518. int if_type;
  4519. rcu_read_lock();
  4520. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4521. struct cnic_ulp_ops *ulp_ops;
  4522. void *ctx;
  4523. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4524. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4525. continue;
  4526. ctx = cp->ulp_handle[if_type];
  4527. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4528. }
  4529. rcu_read_unlock();
  4530. }
  4531. /**
  4532. * netdev event handler
  4533. */
  4534. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4535. void *ptr)
  4536. {
  4537. struct net_device *netdev = ptr;
  4538. struct cnic_dev *dev;
  4539. int new_dev = 0;
  4540. dev = cnic_from_netdev(netdev);
  4541. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4542. /* Check for the hot-plug device */
  4543. dev = is_cnic_dev(netdev);
  4544. if (dev) {
  4545. new_dev = 1;
  4546. cnic_hold(dev);
  4547. }
  4548. }
  4549. if (dev) {
  4550. struct cnic_local *cp = dev->cnic_priv;
  4551. if (new_dev)
  4552. cnic_ulp_init(dev);
  4553. else if (event == NETDEV_UNREGISTER)
  4554. cnic_ulp_exit(dev);
  4555. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4556. if (cnic_register_netdev(dev) != 0) {
  4557. cnic_put(dev);
  4558. goto done;
  4559. }
  4560. if (!cnic_start_hw(dev))
  4561. cnic_ulp_start(dev);
  4562. }
  4563. cnic_rcv_netevent(cp, event, 0);
  4564. if (event == NETDEV_GOING_DOWN) {
  4565. cnic_ulp_stop(dev);
  4566. cnic_stop_hw(dev);
  4567. cnic_unregister_netdev(dev);
  4568. } else if (event == NETDEV_UNREGISTER) {
  4569. write_lock(&cnic_dev_lock);
  4570. list_del_init(&dev->list);
  4571. write_unlock(&cnic_dev_lock);
  4572. cnic_put(dev);
  4573. cnic_free_dev(dev);
  4574. goto done;
  4575. }
  4576. cnic_put(dev);
  4577. } else {
  4578. struct net_device *realdev;
  4579. u16 vid;
  4580. vid = cnic_get_vlan(netdev, &realdev);
  4581. if (realdev) {
  4582. dev = cnic_from_netdev(realdev);
  4583. if (dev) {
  4584. vid |= VLAN_TAG_PRESENT;
  4585. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4586. cnic_put(dev);
  4587. }
  4588. }
  4589. }
  4590. done:
  4591. return NOTIFY_DONE;
  4592. }
  4593. static struct notifier_block cnic_netdev_notifier = {
  4594. .notifier_call = cnic_netdev_event
  4595. };
  4596. static void cnic_release(void)
  4597. {
  4598. struct cnic_dev *dev;
  4599. struct cnic_uio_dev *udev;
  4600. while (!list_empty(&cnic_dev_list)) {
  4601. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4602. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4603. cnic_ulp_stop(dev);
  4604. cnic_stop_hw(dev);
  4605. }
  4606. cnic_ulp_exit(dev);
  4607. cnic_unregister_netdev(dev);
  4608. list_del_init(&dev->list);
  4609. cnic_free_dev(dev);
  4610. }
  4611. while (!list_empty(&cnic_udev_list)) {
  4612. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4613. list);
  4614. cnic_free_uio(udev);
  4615. }
  4616. }
  4617. static int __init cnic_init(void)
  4618. {
  4619. int rc = 0;
  4620. pr_info("%s", version);
  4621. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4622. if (rc) {
  4623. cnic_release();
  4624. return rc;
  4625. }
  4626. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4627. if (!cnic_wq) {
  4628. cnic_release();
  4629. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4630. return -ENOMEM;
  4631. }
  4632. return 0;
  4633. }
  4634. static void __exit cnic_exit(void)
  4635. {
  4636. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4637. cnic_release();
  4638. destroy_workqueue(cnic_wq);
  4639. }
  4640. module_init(cnic_init);
  4641. module_exit(cnic_exit);