exynos5250.dtsi 17 KB

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  1. /*
  2. * SAMSUNG EXYNOS5250 SoC device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
  8. * EXYNOS5250 based board files can include this file and provide
  9. * values for board specfic bindings.
  10. *
  11. * Note: This file does not include device nodes for all the controllers in
  12. * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13. * additional nodes can be added to this file.
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. /include/ "skeleton.dtsi"
  20. / {
  21. compatible = "samsung,exynos5250";
  22. interrupt-parent = <&gic>;
  23. aliases {
  24. spi0 = &spi_0;
  25. spi1 = &spi_1;
  26. spi2 = &spi_2;
  27. gsc0 = &gsc_0;
  28. gsc1 = &gsc_1;
  29. gsc2 = &gsc_2;
  30. gsc3 = &gsc_3;
  31. mshc0 = &dwmmc_0;
  32. mshc1 = &dwmmc_1;
  33. mshc2 = &dwmmc_2;
  34. mshc3 = &dwmmc_3;
  35. i2c0 = &i2c_0;
  36. i2c1 = &i2c_1;
  37. i2c2 = &i2c_2;
  38. i2c3 = &i2c_3;
  39. i2c4 = &i2c_4;
  40. i2c5 = &i2c_5;
  41. i2c6 = &i2c_6;
  42. i2c7 = &i2c_7;
  43. i2c8 = &i2c_8;
  44. };
  45. pd_gsc: gsc-power-domain@0x10044000 {
  46. compatible = "samsung,exynos4210-pd";
  47. reg = <0x10044000 0x20>;
  48. };
  49. pd_mfc: mfc-power-domain@0x10044040 {
  50. compatible = "samsung,exynos4210-pd";
  51. reg = <0x10044040 0x20>;
  52. };
  53. clock: clock-controller@0x10010000 {
  54. compatible = "samsung,exynos5250-clock";
  55. reg = <0x10010000 0x30000>;
  56. #clock-cells = <1>;
  57. };
  58. gic:interrupt-controller@10481000 {
  59. compatible = "arm,cortex-a9-gic";
  60. #interrupt-cells = <3>;
  61. interrupt-controller;
  62. reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
  63. };
  64. combiner:interrupt-controller@10440000 {
  65. compatible = "samsung,exynos4210-combiner";
  66. #interrupt-cells = <2>;
  67. interrupt-controller;
  68. samsung,combiner-nr = <32>;
  69. reg = <0x10440000 0x1000>;
  70. interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  71. <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  72. <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  73. <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  74. <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
  75. <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
  76. <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
  77. <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
  78. };
  79. mct@101C0000 {
  80. compatible = "samsung,exynos4210-mct";
  81. reg = <0x101C0000 0x800>;
  82. interrupt-controller;
  83. #interrups-cells = <2>;
  84. interrupt-parent = <&mct_map>;
  85. interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
  86. <4 0>, <5 0>;
  87. clocks = <&clock 1>, <&clock 335>;
  88. clock-names = "fin_pll", "mct";
  89. mct_map: mct-map {
  90. #interrupt-cells = <2>;
  91. #address-cells = <0>;
  92. #size-cells = <0>;
  93. interrupt-map = <0x0 0 &combiner 23 3>,
  94. <0x1 0 &combiner 23 4>,
  95. <0x2 0 &combiner 25 2>,
  96. <0x3 0 &combiner 25 3>,
  97. <0x4 0 &gic 0 120 0>,
  98. <0x5 0 &gic 0 121 0>;
  99. };
  100. };
  101. watchdog {
  102. compatible = "samsung,s3c2410-wdt";
  103. reg = <0x101D0000 0x100>;
  104. interrupts = <0 42 0>;
  105. clocks = <&clock 336>;
  106. clock-names = "watchdog";
  107. };
  108. codec@11000000 {
  109. compatible = "samsung,mfc-v6";
  110. reg = <0x11000000 0x10000>;
  111. interrupts = <0 96 0>;
  112. samsung,power-domain = <&pd_mfc>;
  113. };
  114. rtc {
  115. compatible = "samsung,s3c6410-rtc";
  116. reg = <0x101E0000 0x100>;
  117. interrupts = <0 43 0>, <0 44 0>;
  118. clocks = <&clock 337>;
  119. clock-names = "rtc";
  120. };
  121. tmu@10060000 {
  122. compatible = "samsung,exynos5250-tmu";
  123. reg = <0x10060000 0x100>;
  124. interrupts = <0 65 0>;
  125. clocks = <&clock 338>;
  126. clock-names = "tmu_apbif";
  127. };
  128. serial@12C00000 {
  129. compatible = "samsung,exynos4210-uart";
  130. reg = <0x12C00000 0x100>;
  131. interrupts = <0 51 0>;
  132. clocks = <&clock 289>, <&clock 146>;
  133. clock-names = "uart", "clk_uart_baud0";
  134. };
  135. serial@12C10000 {
  136. compatible = "samsung,exynos4210-uart";
  137. reg = <0x12C10000 0x100>;
  138. interrupts = <0 52 0>;
  139. clocks = <&clock 290>, <&clock 147>;
  140. clock-names = "uart", "clk_uart_baud0";
  141. };
  142. serial@12C20000 {
  143. compatible = "samsung,exynos4210-uart";
  144. reg = <0x12C20000 0x100>;
  145. interrupts = <0 53 0>;
  146. clocks = <&clock 291>, <&clock 148>;
  147. clock-names = "uart", "clk_uart_baud0";
  148. };
  149. serial@12C30000 {
  150. compatible = "samsung,exynos4210-uart";
  151. reg = <0x12C30000 0x100>;
  152. interrupts = <0 54 0>;
  153. clocks = <&clock 292>, <&clock 149>;
  154. clock-names = "uart", "clk_uart_baud0";
  155. };
  156. sata@122F0000 {
  157. compatible = "samsung,exynos5-sata-ahci";
  158. reg = <0x122F0000 0x1ff>;
  159. interrupts = <0 115 0>;
  160. clocks = <&clock 277>, <&clock 143>;
  161. clock-names = "sata", "sclk_sata";
  162. };
  163. sata-phy@12170000 {
  164. compatible = "samsung,exynos5-sata-phy";
  165. reg = <0x12170000 0x1ff>;
  166. };
  167. i2c_0: i2c@12C60000 {
  168. compatible = "samsung,s3c2440-i2c";
  169. reg = <0x12C60000 0x100>;
  170. interrupts = <0 56 0>;
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. clocks = <&clock 294>;
  174. clock-names = "i2c";
  175. };
  176. i2c_1: i2c@12C70000 {
  177. compatible = "samsung,s3c2440-i2c";
  178. reg = <0x12C70000 0x100>;
  179. interrupts = <0 57 0>;
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182. clocks = <&clock 295>;
  183. clock-names = "i2c";
  184. };
  185. i2c_2: i2c@12C80000 {
  186. compatible = "samsung,s3c2440-i2c";
  187. reg = <0x12C80000 0x100>;
  188. interrupts = <0 58 0>;
  189. #address-cells = <1>;
  190. #size-cells = <0>;
  191. clocks = <&clock 296>;
  192. clock-names = "i2c";
  193. };
  194. i2c_3: i2c@12C90000 {
  195. compatible = "samsung,s3c2440-i2c";
  196. reg = <0x12C90000 0x100>;
  197. interrupts = <0 59 0>;
  198. #address-cells = <1>;
  199. #size-cells = <0>;
  200. clocks = <&clock 297>;
  201. clock-names = "i2c";
  202. };
  203. i2c_4: i2c@12CA0000 {
  204. compatible = "samsung,s3c2440-i2c";
  205. reg = <0x12CA0000 0x100>;
  206. interrupts = <0 60 0>;
  207. #address-cells = <1>;
  208. #size-cells = <0>;
  209. clocks = <&clock 298>;
  210. clock-names = "i2c";
  211. };
  212. i2c_5: i2c@12CB0000 {
  213. compatible = "samsung,s3c2440-i2c";
  214. reg = <0x12CB0000 0x100>;
  215. interrupts = <0 61 0>;
  216. #address-cells = <1>;
  217. #size-cells = <0>;
  218. clocks = <&clock 299>;
  219. clock-names = "i2c";
  220. };
  221. i2c_6: i2c@12CC0000 {
  222. compatible = "samsung,s3c2440-i2c";
  223. reg = <0x12CC0000 0x100>;
  224. interrupts = <0 62 0>;
  225. #address-cells = <1>;
  226. #size-cells = <0>;
  227. clocks = <&clock 300>;
  228. clock-names = "i2c";
  229. };
  230. i2c_7: i2c@12CD0000 {
  231. compatible = "samsung,s3c2440-i2c";
  232. reg = <0x12CD0000 0x100>;
  233. interrupts = <0 63 0>;
  234. #address-cells = <1>;
  235. #size-cells = <0>;
  236. clocks = <&clock 301>;
  237. clock-names = "i2c";
  238. };
  239. i2c_8: i2c@12CE0000 {
  240. compatible = "samsung,s3c2440-hdmiphy-i2c";
  241. reg = <0x12CE0000 0x1000>;
  242. interrupts = <0 64 0>;
  243. #address-cells = <1>;
  244. #size-cells = <0>;
  245. clocks = <&clock 302>;
  246. clock-names = "i2c";
  247. };
  248. i2c@121D0000 {
  249. compatible = "samsung,exynos5-sata-phy-i2c";
  250. reg = <0x121D0000 0x100>;
  251. #address-cells = <1>;
  252. #size-cells = <0>;
  253. clocks = <&clock 288>;
  254. clock-names = "i2c";
  255. };
  256. spi_0: spi@12d20000 {
  257. compatible = "samsung,exynos4210-spi";
  258. reg = <0x12d20000 0x100>;
  259. interrupts = <0 66 0>;
  260. dmas = <&pdma0 5
  261. &pdma0 4>;
  262. dma-names = "tx", "rx";
  263. #address-cells = <1>;
  264. #size-cells = <0>;
  265. clocks = <&clock 304>, <&clock 154>;
  266. clock-names = "spi", "spi_busclk0";
  267. };
  268. spi_1: spi@12d30000 {
  269. compatible = "samsung,exynos4210-spi";
  270. reg = <0x12d30000 0x100>;
  271. interrupts = <0 67 0>;
  272. dmas = <&pdma1 5
  273. &pdma1 4>;
  274. dma-names = "tx", "rx";
  275. #address-cells = <1>;
  276. #size-cells = <0>;
  277. clocks = <&clock 305>, <&clock 155>;
  278. clock-names = "spi", "spi_busclk0";
  279. };
  280. spi_2: spi@12d40000 {
  281. compatible = "samsung,exynos4210-spi";
  282. reg = <0x12d40000 0x100>;
  283. interrupts = <0 68 0>;
  284. dmas = <&pdma0 7
  285. &pdma0 6>;
  286. dma-names = "tx", "rx";
  287. #address-cells = <1>;
  288. #size-cells = <0>;
  289. clocks = <&clock 306>, <&clock 156>;
  290. clock-names = "spi", "spi_busclk0";
  291. };
  292. dwmmc_0: dwmmc0@12200000 {
  293. compatible = "samsung,exynos5250-dw-mshc";
  294. reg = <0x12200000 0x1000>;
  295. interrupts = <0 75 0>;
  296. #address-cells = <1>;
  297. #size-cells = <0>;
  298. clocks = <&clock 280>, <&clock 139>;
  299. clock-names = "biu", "ciu";
  300. };
  301. dwmmc_1: dwmmc1@12210000 {
  302. compatible = "samsung,exynos5250-dw-mshc";
  303. reg = <0x12210000 0x1000>;
  304. interrupts = <0 76 0>;
  305. #address-cells = <1>;
  306. #size-cells = <0>;
  307. clocks = <&clock 281>, <&clock 140>;
  308. clock-names = "biu", "ciu";
  309. };
  310. dwmmc_2: dwmmc2@12220000 {
  311. compatible = "samsung,exynos5250-dw-mshc";
  312. reg = <0x12220000 0x1000>;
  313. interrupts = <0 77 0>;
  314. #address-cells = <1>;
  315. #size-cells = <0>;
  316. clocks = <&clock 282>, <&clock 141>;
  317. clock-names = "biu", "ciu";
  318. };
  319. dwmmc_3: dwmmc3@12230000 {
  320. compatible = "samsung,exynos5250-dw-mshc";
  321. reg = <0x12230000 0x1000>;
  322. interrupts = <0 78 0>;
  323. #address-cells = <1>;
  324. #size-cells = <0>;
  325. clocks = <&clock 283>, <&clock 142>;
  326. clock-names = "biu", "ciu";
  327. };
  328. i2s0: i2s@03830000 {
  329. compatible = "samsung,i2s-v5";
  330. reg = <0x03830000 0x100>;
  331. dmas = <&pdma0 10
  332. &pdma0 9
  333. &pdma0 8>;
  334. dma-names = "tx", "rx", "tx-sec";
  335. samsung,supports-6ch;
  336. samsung,supports-rstclr;
  337. samsung,supports-secdai;
  338. samsung,idma-addr = <0x03000000>;
  339. };
  340. i2s1: i2s@12D60000 {
  341. compatible = "samsung,i2s-v5";
  342. reg = <0x12D60000 0x100>;
  343. dmas = <&pdma1 12
  344. &pdma1 11>;
  345. dma-names = "tx", "rx";
  346. };
  347. i2s2: i2s@12D70000 {
  348. compatible = "samsung,i2s-v5";
  349. reg = <0x12D70000 0x100>;
  350. dmas = <&pdma0 12
  351. &pdma0 11>;
  352. dma-names = "tx", "rx";
  353. };
  354. usb@12110000 {
  355. compatible = "samsung,exynos4210-ehci";
  356. reg = <0x12110000 0x100>;
  357. interrupts = <0 71 0>;
  358. };
  359. usb@12120000 {
  360. compatible = "samsung,exynos4210-ohci";
  361. reg = <0x12120000 0x100>;
  362. interrupts = <0 71 0>;
  363. };
  364. amba {
  365. #address-cells = <1>;
  366. #size-cells = <1>;
  367. compatible = "arm,amba-bus";
  368. interrupt-parent = <&gic>;
  369. ranges;
  370. pdma0: pdma@121A0000 {
  371. compatible = "arm,pl330", "arm,primecell";
  372. reg = <0x121A0000 0x1000>;
  373. interrupts = <0 34 0>;
  374. clocks = <&clock 275>;
  375. clock-names = "apb_pclk";
  376. #dma-cells = <1>;
  377. #dma-channels = <8>;
  378. #dma-requests = <32>;
  379. };
  380. pdma1: pdma@121B0000 {
  381. compatible = "arm,pl330", "arm,primecell";
  382. reg = <0x121B0000 0x1000>;
  383. interrupts = <0 35 0>;
  384. clocks = <&clock 276>;
  385. clock-names = "apb_pclk";
  386. #dma-cells = <1>;
  387. #dma-channels = <8>;
  388. #dma-requests = <32>;
  389. };
  390. mdma0: mdma@10800000 {
  391. compatible = "arm,pl330", "arm,primecell";
  392. reg = <0x10800000 0x1000>;
  393. interrupts = <0 33 0>;
  394. clocks = <&clock 271>;
  395. clock-names = "apb_pclk";
  396. #dma-cells = <1>;
  397. #dma-channels = <8>;
  398. #dma-requests = <1>;
  399. };
  400. mdma1: mdma@11C10000 {
  401. compatible = "arm,pl330", "arm,primecell";
  402. reg = <0x11C10000 0x1000>;
  403. interrupts = <0 124 0>;
  404. clocks = <&clock 271>;
  405. clock-names = "apb_pclk";
  406. #dma-cells = <1>;
  407. #dma-channels = <8>;
  408. #dma-requests = <1>;
  409. };
  410. };
  411. gpio-controllers {
  412. #address-cells = <1>;
  413. #size-cells = <1>;
  414. gpio-controller;
  415. ranges;
  416. gpa0: gpio-controller@11400000 {
  417. compatible = "samsung,exynos4-gpio";
  418. reg = <0x11400000 0x20>;
  419. #gpio-cells = <4>;
  420. };
  421. gpa1: gpio-controller@11400020 {
  422. compatible = "samsung,exynos4-gpio";
  423. reg = <0x11400020 0x20>;
  424. #gpio-cells = <4>;
  425. };
  426. gpa2: gpio-controller@11400040 {
  427. compatible = "samsung,exynos4-gpio";
  428. reg = <0x11400040 0x20>;
  429. #gpio-cells = <4>;
  430. };
  431. gpb0: gpio-controller@11400060 {
  432. compatible = "samsung,exynos4-gpio";
  433. reg = <0x11400060 0x20>;
  434. #gpio-cells = <4>;
  435. };
  436. gpb1: gpio-controller@11400080 {
  437. compatible = "samsung,exynos4-gpio";
  438. reg = <0x11400080 0x20>;
  439. #gpio-cells = <4>;
  440. };
  441. gpb2: gpio-controller@114000A0 {
  442. compatible = "samsung,exynos4-gpio";
  443. reg = <0x114000A0 0x20>;
  444. #gpio-cells = <4>;
  445. };
  446. gpb3: gpio-controller@114000C0 {
  447. compatible = "samsung,exynos4-gpio";
  448. reg = <0x114000C0 0x20>;
  449. #gpio-cells = <4>;
  450. };
  451. gpc0: gpio-controller@114000E0 {
  452. compatible = "samsung,exynos4-gpio";
  453. reg = <0x114000E0 0x20>;
  454. #gpio-cells = <4>;
  455. };
  456. gpc1: gpio-controller@11400100 {
  457. compatible = "samsung,exynos4-gpio";
  458. reg = <0x11400100 0x20>;
  459. #gpio-cells = <4>;
  460. };
  461. gpc2: gpio-controller@11400120 {
  462. compatible = "samsung,exynos4-gpio";
  463. reg = <0x11400120 0x20>;
  464. #gpio-cells = <4>;
  465. };
  466. gpc3: gpio-controller@11400140 {
  467. compatible = "samsung,exynos4-gpio";
  468. reg = <0x11400140 0x20>;
  469. #gpio-cells = <4>;
  470. };
  471. gpc4: gpio-controller@114002E0 {
  472. compatible = "samsung,exynos4-gpio";
  473. reg = <0x114002E0 0x20>;
  474. #gpio-cells = <4>;
  475. };
  476. gpd0: gpio-controller@11400160 {
  477. compatible = "samsung,exynos4-gpio";
  478. reg = <0x11400160 0x20>;
  479. #gpio-cells = <4>;
  480. };
  481. gpd1: gpio-controller@11400180 {
  482. compatible = "samsung,exynos4-gpio";
  483. reg = <0x11400180 0x20>;
  484. #gpio-cells = <4>;
  485. };
  486. gpy0: gpio-controller@114001A0 {
  487. compatible = "samsung,exynos4-gpio";
  488. reg = <0x114001A0 0x20>;
  489. #gpio-cells = <4>;
  490. };
  491. gpy1: gpio-controller@114001C0 {
  492. compatible = "samsung,exynos4-gpio";
  493. reg = <0x114001C0 0x20>;
  494. #gpio-cells = <4>;
  495. };
  496. gpy2: gpio-controller@114001E0 {
  497. compatible = "samsung,exynos4-gpio";
  498. reg = <0x114001E0 0x20>;
  499. #gpio-cells = <4>;
  500. };
  501. gpy3: gpio-controller@11400200 {
  502. compatible = "samsung,exynos4-gpio";
  503. reg = <0x11400200 0x20>;
  504. #gpio-cells = <4>;
  505. };
  506. gpy4: gpio-controller@11400220 {
  507. compatible = "samsung,exynos4-gpio";
  508. reg = <0x11400220 0x20>;
  509. #gpio-cells = <4>;
  510. };
  511. gpy5: gpio-controller@11400240 {
  512. compatible = "samsung,exynos4-gpio";
  513. reg = <0x11400240 0x20>;
  514. #gpio-cells = <4>;
  515. };
  516. gpy6: gpio-controller@11400260 {
  517. compatible = "samsung,exynos4-gpio";
  518. reg = <0x11400260 0x20>;
  519. #gpio-cells = <4>;
  520. };
  521. gpx0: gpio-controller@11400C00 {
  522. compatible = "samsung,exynos4-gpio";
  523. reg = <0x11400C00 0x20>;
  524. #gpio-cells = <4>;
  525. };
  526. gpx1: gpio-controller@11400C20 {
  527. compatible = "samsung,exynos4-gpio";
  528. reg = <0x11400C20 0x20>;
  529. #gpio-cells = <4>;
  530. };
  531. gpx2: gpio-controller@11400C40 {
  532. compatible = "samsung,exynos4-gpio";
  533. reg = <0x11400C40 0x20>;
  534. #gpio-cells = <4>;
  535. };
  536. gpx3: gpio-controller@11400C60 {
  537. compatible = "samsung,exynos4-gpio";
  538. reg = <0x11400C60 0x20>;
  539. #gpio-cells = <4>;
  540. };
  541. gpe0: gpio-controller@13400000 {
  542. compatible = "samsung,exynos4-gpio";
  543. reg = <0x13400000 0x20>;
  544. #gpio-cells = <4>;
  545. };
  546. gpe1: gpio-controller@13400020 {
  547. compatible = "samsung,exynos4-gpio";
  548. reg = <0x13400020 0x20>;
  549. #gpio-cells = <4>;
  550. };
  551. gpf0: gpio-controller@13400040 {
  552. compatible = "samsung,exynos4-gpio";
  553. reg = <0x13400040 0x20>;
  554. #gpio-cells = <4>;
  555. };
  556. gpf1: gpio-controller@13400060 {
  557. compatible = "samsung,exynos4-gpio";
  558. reg = <0x13400060 0x20>;
  559. #gpio-cells = <4>;
  560. };
  561. gpg0: gpio-controller@13400080 {
  562. compatible = "samsung,exynos4-gpio";
  563. reg = <0x13400080 0x20>;
  564. #gpio-cells = <4>;
  565. };
  566. gpg1: gpio-controller@134000A0 {
  567. compatible = "samsung,exynos4-gpio";
  568. reg = <0x134000A0 0x20>;
  569. #gpio-cells = <4>;
  570. };
  571. gpg2: gpio-controller@134000C0 {
  572. compatible = "samsung,exynos4-gpio";
  573. reg = <0x134000C0 0x20>;
  574. #gpio-cells = <4>;
  575. };
  576. gph0: gpio-controller@134000E0 {
  577. compatible = "samsung,exynos4-gpio";
  578. reg = <0x134000E0 0x20>;
  579. #gpio-cells = <4>;
  580. };
  581. gph1: gpio-controller@13400100 {
  582. compatible = "samsung,exynos4-gpio";
  583. reg = <0x13400100 0x20>;
  584. #gpio-cells = <4>;
  585. };
  586. gpv0: gpio-controller@10D10000 {
  587. compatible = "samsung,exynos4-gpio";
  588. reg = <0x10D10000 0x20>;
  589. #gpio-cells = <4>;
  590. };
  591. gpv1: gpio-controller@10D10020 {
  592. compatible = "samsung,exynos4-gpio";
  593. reg = <0x10D10020 0x20>;
  594. #gpio-cells = <4>;
  595. };
  596. gpv2: gpio-controller@10D10040 {
  597. compatible = "samsung,exynos4-gpio";
  598. reg = <0x10D10060 0x20>;
  599. #gpio-cells = <4>;
  600. };
  601. gpv3: gpio-controller@10D10060 {
  602. compatible = "samsung,exynos4-gpio";
  603. reg = <0x10D10080 0x20>;
  604. #gpio-cells = <4>;
  605. };
  606. gpv4: gpio-controller@10D10080 {
  607. compatible = "samsung,exynos4-gpio";
  608. reg = <0x10D100C0 0x20>;
  609. #gpio-cells = <4>;
  610. };
  611. gpz: gpio-controller@03860000 {
  612. compatible = "samsung,exynos4-gpio";
  613. reg = <0x03860000 0x20>;
  614. #gpio-cells = <4>;
  615. };
  616. };
  617. gsc_0: gsc@0x13e00000 {
  618. compatible = "samsung,exynos5-gsc";
  619. reg = <0x13e00000 0x1000>;
  620. interrupts = <0 85 0>;
  621. samsung,power-domain = <&pd_gsc>;
  622. clocks = <&clock 256>;
  623. clock-names = "gscl";
  624. };
  625. gsc_1: gsc@0x13e10000 {
  626. compatible = "samsung,exynos5-gsc";
  627. reg = <0x13e10000 0x1000>;
  628. interrupts = <0 86 0>;
  629. samsung,power-domain = <&pd_gsc>;
  630. clocks = <&clock 257>;
  631. clock-names = "gscl";
  632. };
  633. gsc_2: gsc@0x13e20000 {
  634. compatible = "samsung,exynos5-gsc";
  635. reg = <0x13e20000 0x1000>;
  636. interrupts = <0 87 0>;
  637. samsung,power-domain = <&pd_gsc>;
  638. clocks = <&clock 258>;
  639. clock-names = "gscl";
  640. };
  641. gsc_3: gsc@0x13e30000 {
  642. compatible = "samsung,exynos5-gsc";
  643. reg = <0x13e30000 0x1000>;
  644. interrupts = <0 88 0>;
  645. samsung,power-domain = <&pd_gsc>;
  646. clocks = <&clock 259>;
  647. clock-names = "gscl";
  648. };
  649. hdmi {
  650. compatible = "samsung,exynos5-hdmi";
  651. reg = <0x14530000 0x70000>;
  652. interrupts = <0 95 0>;
  653. clocks = <&clock 333>, <&clock 136>, <&clock 137>,
  654. <&clock 333>, <&clock 333>;
  655. clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
  656. "sclk_hdmiphy", "hdmiphy";
  657. };
  658. mixer {
  659. compatible = "samsung,exynos5-mixer";
  660. reg = <0x14450000 0x10000>;
  661. interrupts = <0 94 0>;
  662. };
  663. dp-controller {
  664. compatible = "samsung,exynos5-dp";
  665. reg = <0x145b0000 0x1000>;
  666. interrupts = <10 3>;
  667. interrupt-parent = <&combiner>;
  668. #address-cells = <1>;
  669. #size-cells = <0>;
  670. dptx-phy {
  671. reg = <0x10040720>;
  672. samsung,enable-mask = <1>;
  673. };
  674. };
  675. };