i915_dma.c 50 KB

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  1. /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
  2. */
  3. /*
  4. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a
  8. * copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation the rights to use, copy, modify, merge, publish,
  11. * distribute, sub license, and/or sell copies of the Software, and to
  12. * permit persons to whom the Software is furnished to do so, subject to
  13. * the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial portions
  17. * of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26. *
  27. */
  28. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29. #include <drm/drmP.h>
  30. #include <drm/drm_crtc_helper.h>
  31. #include <drm/drm_fb_helper.h>
  32. #include "intel_drv.h"
  33. #include <drm/i915_drm.h>
  34. #include "i915_drv.h"
  35. #include "i915_trace.h"
  36. #include <linux/pci.h>
  37. #include <linux/vgaarb.h>
  38. #include <linux/acpi.h>
  39. #include <linux/pnp.h>
  40. #include <linux/vga_switcheroo.h>
  41. #include <linux/slab.h>
  42. #include <acpi/video.h>
  43. #include <asm/pat.h>
  44. #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  45. #define BEGIN_LP_RING(n) \
  46. intel_ring_begin(LP_RING(dev_priv), (n))
  47. #define OUT_RING(x) \
  48. intel_ring_emit(LP_RING(dev_priv), x)
  49. #define ADVANCE_LP_RING() \
  50. intel_ring_advance(LP_RING(dev_priv))
  51. /**
  52. * Lock test for when it's just for synchronization of ring access.
  53. *
  54. * In that case, we don't need to do it when GEM is initialized as nobody else
  55. * has access to the ring.
  56. */
  57. #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
  58. if (LP_RING(dev->dev_private)->obj == NULL) \
  59. LOCK_TEST_WITH_RETURN(dev, file); \
  60. } while (0)
  61. static inline u32
  62. intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  63. {
  64. if (I915_NEED_GFX_HWS(dev_priv->dev))
  65. return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  66. else
  67. return intel_read_status_page(LP_RING(dev_priv), reg);
  68. }
  69. #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  70. #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  71. #define I915_BREADCRUMB_INDEX 0x21
  72. void i915_update_dri1_breadcrumb(struct drm_device *dev)
  73. {
  74. drm_i915_private_t *dev_priv = dev->dev_private;
  75. struct drm_i915_master_private *master_priv;
  76. if (dev->primary->master) {
  77. master_priv = dev->primary->master->driver_priv;
  78. if (master_priv->sarea_priv)
  79. master_priv->sarea_priv->last_dispatch =
  80. READ_BREADCRUMB(dev_priv);
  81. }
  82. }
  83. static void i915_write_hws_pga(struct drm_device *dev)
  84. {
  85. drm_i915_private_t *dev_priv = dev->dev_private;
  86. u32 addr;
  87. addr = dev_priv->status_page_dmah->busaddr;
  88. if (INTEL_INFO(dev)->gen >= 4)
  89. addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  90. I915_WRITE(HWS_PGA, addr);
  91. }
  92. /**
  93. * Frees the hardware status page, whether it's a physical address or a virtual
  94. * address set up by the X Server.
  95. */
  96. static void i915_free_hws(struct drm_device *dev)
  97. {
  98. drm_i915_private_t *dev_priv = dev->dev_private;
  99. struct intel_ring_buffer *ring = LP_RING(dev_priv);
  100. if (dev_priv->status_page_dmah) {
  101. drm_pci_free(dev, dev_priv->status_page_dmah);
  102. dev_priv->status_page_dmah = NULL;
  103. }
  104. if (ring->status_page.gfx_addr) {
  105. ring->status_page.gfx_addr = 0;
  106. iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
  107. }
  108. /* Need to rewrite hardware status page */
  109. I915_WRITE(HWS_PGA, 0x1ffff000);
  110. }
  111. void i915_kernel_lost_context(struct drm_device * dev)
  112. {
  113. drm_i915_private_t *dev_priv = dev->dev_private;
  114. struct drm_i915_master_private *master_priv;
  115. struct intel_ring_buffer *ring = LP_RING(dev_priv);
  116. /*
  117. * We should never lose context on the ring with modesetting
  118. * as we don't expose it to userspace
  119. */
  120. if (drm_core_check_feature(dev, DRIVER_MODESET))
  121. return;
  122. ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
  123. ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
  124. ring->space = ring->head - (ring->tail + 8);
  125. if (ring->space < 0)
  126. ring->space += ring->size;
  127. if (!dev->primary->master)
  128. return;
  129. master_priv = dev->primary->master->driver_priv;
  130. if (ring->head == ring->tail && master_priv->sarea_priv)
  131. master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
  132. }
  133. static int i915_dma_cleanup(struct drm_device * dev)
  134. {
  135. drm_i915_private_t *dev_priv = dev->dev_private;
  136. int i;
  137. /* Make sure interrupts are disabled here because the uninstall ioctl
  138. * may not have been called from userspace and after dev_private
  139. * is freed, it's too late.
  140. */
  141. if (dev->irq_enabled)
  142. drm_irq_uninstall(dev);
  143. mutex_lock(&dev->struct_mutex);
  144. for (i = 0; i < I915_NUM_RINGS; i++)
  145. intel_cleanup_ring_buffer(&dev_priv->ring[i]);
  146. mutex_unlock(&dev->struct_mutex);
  147. /* Clear the HWS virtual address at teardown */
  148. if (I915_NEED_GFX_HWS(dev))
  149. i915_free_hws(dev);
  150. return 0;
  151. }
  152. static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
  153. {
  154. drm_i915_private_t *dev_priv = dev->dev_private;
  155. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  156. int ret;
  157. master_priv->sarea = drm_getsarea(dev);
  158. if (master_priv->sarea) {
  159. master_priv->sarea_priv = (drm_i915_sarea_t *)
  160. ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
  161. } else {
  162. DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
  163. }
  164. if (init->ring_size != 0) {
  165. if (LP_RING(dev_priv)->obj != NULL) {
  166. i915_dma_cleanup(dev);
  167. DRM_ERROR("Client tried to initialize ringbuffer in "
  168. "GEM mode\n");
  169. return -EINVAL;
  170. }
  171. ret = intel_render_ring_init_dri(dev,
  172. init->ring_start,
  173. init->ring_size);
  174. if (ret) {
  175. i915_dma_cleanup(dev);
  176. return ret;
  177. }
  178. }
  179. dev_priv->dri1.cpp = init->cpp;
  180. dev_priv->dri1.back_offset = init->back_offset;
  181. dev_priv->dri1.front_offset = init->front_offset;
  182. dev_priv->dri1.current_page = 0;
  183. if (master_priv->sarea_priv)
  184. master_priv->sarea_priv->pf_current_page = 0;
  185. /* Allow hardware batchbuffers unless told otherwise.
  186. */
  187. dev_priv->dri1.allow_batchbuffer = 1;
  188. return 0;
  189. }
  190. static int i915_dma_resume(struct drm_device * dev)
  191. {
  192. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  193. struct intel_ring_buffer *ring = LP_RING(dev_priv);
  194. DRM_DEBUG_DRIVER("%s\n", __func__);
  195. if (ring->virtual_start == NULL) {
  196. DRM_ERROR("can not ioremap virtual address for"
  197. " ring buffer\n");
  198. return -ENOMEM;
  199. }
  200. /* Program Hardware Status Page */
  201. if (!ring->status_page.page_addr) {
  202. DRM_ERROR("Can not find hardware status page\n");
  203. return -EINVAL;
  204. }
  205. DRM_DEBUG_DRIVER("hw status page @ %p\n",
  206. ring->status_page.page_addr);
  207. if (ring->status_page.gfx_addr != 0)
  208. intel_ring_setup_status_page(ring);
  209. else
  210. i915_write_hws_pga(dev);
  211. DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  212. return 0;
  213. }
  214. static int i915_dma_init(struct drm_device *dev, void *data,
  215. struct drm_file *file_priv)
  216. {
  217. drm_i915_init_t *init = data;
  218. int retcode = 0;
  219. if (drm_core_check_feature(dev, DRIVER_MODESET))
  220. return -ENODEV;
  221. switch (init->func) {
  222. case I915_INIT_DMA:
  223. retcode = i915_initialize(dev, init);
  224. break;
  225. case I915_CLEANUP_DMA:
  226. retcode = i915_dma_cleanup(dev);
  227. break;
  228. case I915_RESUME_DMA:
  229. retcode = i915_dma_resume(dev);
  230. break;
  231. default:
  232. retcode = -EINVAL;
  233. break;
  234. }
  235. return retcode;
  236. }
  237. /* Implement basically the same security restrictions as hardware does
  238. * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
  239. *
  240. * Most of the calculations below involve calculating the size of a
  241. * particular instruction. It's important to get the size right as
  242. * that tells us where the next instruction to check is. Any illegal
  243. * instruction detected will be given a size of zero, which is a
  244. * signal to abort the rest of the buffer.
  245. */
  246. static int validate_cmd(int cmd)
  247. {
  248. switch (((cmd >> 29) & 0x7)) {
  249. case 0x0:
  250. switch ((cmd >> 23) & 0x3f) {
  251. case 0x0:
  252. return 1; /* MI_NOOP */
  253. case 0x4:
  254. return 1; /* MI_FLUSH */
  255. default:
  256. return 0; /* disallow everything else */
  257. }
  258. break;
  259. case 0x1:
  260. return 0; /* reserved */
  261. case 0x2:
  262. return (cmd & 0xff) + 2; /* 2d commands */
  263. case 0x3:
  264. if (((cmd >> 24) & 0x1f) <= 0x18)
  265. return 1;
  266. switch ((cmd >> 24) & 0x1f) {
  267. case 0x1c:
  268. return 1;
  269. case 0x1d:
  270. switch ((cmd >> 16) & 0xff) {
  271. case 0x3:
  272. return (cmd & 0x1f) + 2;
  273. case 0x4:
  274. return (cmd & 0xf) + 2;
  275. default:
  276. return (cmd & 0xffff) + 2;
  277. }
  278. case 0x1e:
  279. if (cmd & (1 << 23))
  280. return (cmd & 0xffff) + 1;
  281. else
  282. return 1;
  283. case 0x1f:
  284. if ((cmd & (1 << 23)) == 0) /* inline vertices */
  285. return (cmd & 0x1ffff) + 2;
  286. else if (cmd & (1 << 17)) /* indirect random */
  287. if ((cmd & 0xffff) == 0)
  288. return 0; /* unknown length, too hard */
  289. else
  290. return (((cmd & 0xffff) + 1) / 2) + 1;
  291. else
  292. return 2; /* indirect sequential */
  293. default:
  294. return 0;
  295. }
  296. default:
  297. return 0;
  298. }
  299. return 0;
  300. }
  301. static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
  302. {
  303. drm_i915_private_t *dev_priv = dev->dev_private;
  304. int i, ret;
  305. if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
  306. return -EINVAL;
  307. for (i = 0; i < dwords;) {
  308. int sz = validate_cmd(buffer[i]);
  309. if (sz == 0 || i + sz > dwords)
  310. return -EINVAL;
  311. i += sz;
  312. }
  313. ret = BEGIN_LP_RING((dwords+1)&~1);
  314. if (ret)
  315. return ret;
  316. for (i = 0; i < dwords; i++)
  317. OUT_RING(buffer[i]);
  318. if (dwords & 1)
  319. OUT_RING(0);
  320. ADVANCE_LP_RING();
  321. return 0;
  322. }
  323. int
  324. i915_emit_box(struct drm_device *dev,
  325. struct drm_clip_rect *box,
  326. int DR1, int DR4)
  327. {
  328. struct drm_i915_private *dev_priv = dev->dev_private;
  329. int ret;
  330. if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
  331. box->y2 <= 0 || box->x2 <= 0) {
  332. DRM_ERROR("Bad box %d,%d..%d,%d\n",
  333. box->x1, box->y1, box->x2, box->y2);
  334. return -EINVAL;
  335. }
  336. if (INTEL_INFO(dev)->gen >= 4) {
  337. ret = BEGIN_LP_RING(4);
  338. if (ret)
  339. return ret;
  340. OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
  341. OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
  342. OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
  343. OUT_RING(DR4);
  344. } else {
  345. ret = BEGIN_LP_RING(6);
  346. if (ret)
  347. return ret;
  348. OUT_RING(GFX_OP_DRAWRECT_INFO);
  349. OUT_RING(DR1);
  350. OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
  351. OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
  352. OUT_RING(DR4);
  353. OUT_RING(0);
  354. }
  355. ADVANCE_LP_RING();
  356. return 0;
  357. }
  358. /* XXX: Emitting the counter should really be moved to part of the IRQ
  359. * emit. For now, do it in both places:
  360. */
  361. static void i915_emit_breadcrumb(struct drm_device *dev)
  362. {
  363. drm_i915_private_t *dev_priv = dev->dev_private;
  364. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  365. dev_priv->dri1.counter++;
  366. if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
  367. dev_priv->dri1.counter = 0;
  368. if (master_priv->sarea_priv)
  369. master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
  370. if (BEGIN_LP_RING(4) == 0) {
  371. OUT_RING(MI_STORE_DWORD_INDEX);
  372. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  373. OUT_RING(dev_priv->dri1.counter);
  374. OUT_RING(0);
  375. ADVANCE_LP_RING();
  376. }
  377. }
  378. static int i915_dispatch_cmdbuffer(struct drm_device * dev,
  379. drm_i915_cmdbuffer_t *cmd,
  380. struct drm_clip_rect *cliprects,
  381. void *cmdbuf)
  382. {
  383. int nbox = cmd->num_cliprects;
  384. int i = 0, count, ret;
  385. if (cmd->sz & 0x3) {
  386. DRM_ERROR("alignment");
  387. return -EINVAL;
  388. }
  389. i915_kernel_lost_context(dev);
  390. count = nbox ? nbox : 1;
  391. for (i = 0; i < count; i++) {
  392. if (i < nbox) {
  393. ret = i915_emit_box(dev, &cliprects[i],
  394. cmd->DR1, cmd->DR4);
  395. if (ret)
  396. return ret;
  397. }
  398. ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
  399. if (ret)
  400. return ret;
  401. }
  402. i915_emit_breadcrumb(dev);
  403. return 0;
  404. }
  405. static int i915_dispatch_batchbuffer(struct drm_device * dev,
  406. drm_i915_batchbuffer_t * batch,
  407. struct drm_clip_rect *cliprects)
  408. {
  409. struct drm_i915_private *dev_priv = dev->dev_private;
  410. int nbox = batch->num_cliprects;
  411. int i, count, ret;
  412. if ((batch->start | batch->used) & 0x7) {
  413. DRM_ERROR("alignment");
  414. return -EINVAL;
  415. }
  416. i915_kernel_lost_context(dev);
  417. count = nbox ? nbox : 1;
  418. for (i = 0; i < count; i++) {
  419. if (i < nbox) {
  420. ret = i915_emit_box(dev, &cliprects[i],
  421. batch->DR1, batch->DR4);
  422. if (ret)
  423. return ret;
  424. }
  425. if (!IS_I830(dev) && !IS_845G(dev)) {
  426. ret = BEGIN_LP_RING(2);
  427. if (ret)
  428. return ret;
  429. if (INTEL_INFO(dev)->gen >= 4) {
  430. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
  431. OUT_RING(batch->start);
  432. } else {
  433. OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
  434. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  435. }
  436. } else {
  437. ret = BEGIN_LP_RING(4);
  438. if (ret)
  439. return ret;
  440. OUT_RING(MI_BATCH_BUFFER);
  441. OUT_RING(batch->start | MI_BATCH_NON_SECURE);
  442. OUT_RING(batch->start + batch->used - 4);
  443. OUT_RING(0);
  444. }
  445. ADVANCE_LP_RING();
  446. }
  447. if (IS_G4X(dev) || IS_GEN5(dev)) {
  448. if (BEGIN_LP_RING(2) == 0) {
  449. OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
  450. OUT_RING(MI_NOOP);
  451. ADVANCE_LP_RING();
  452. }
  453. }
  454. i915_emit_breadcrumb(dev);
  455. return 0;
  456. }
  457. static int i915_dispatch_flip(struct drm_device * dev)
  458. {
  459. drm_i915_private_t *dev_priv = dev->dev_private;
  460. struct drm_i915_master_private *master_priv =
  461. dev->primary->master->driver_priv;
  462. int ret;
  463. if (!master_priv->sarea_priv)
  464. return -EINVAL;
  465. DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
  466. __func__,
  467. dev_priv->dri1.current_page,
  468. master_priv->sarea_priv->pf_current_page);
  469. i915_kernel_lost_context(dev);
  470. ret = BEGIN_LP_RING(10);
  471. if (ret)
  472. return ret;
  473. OUT_RING(MI_FLUSH | MI_READ_FLUSH);
  474. OUT_RING(0);
  475. OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
  476. OUT_RING(0);
  477. if (dev_priv->dri1.current_page == 0) {
  478. OUT_RING(dev_priv->dri1.back_offset);
  479. dev_priv->dri1.current_page = 1;
  480. } else {
  481. OUT_RING(dev_priv->dri1.front_offset);
  482. dev_priv->dri1.current_page = 0;
  483. }
  484. OUT_RING(0);
  485. OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
  486. OUT_RING(0);
  487. ADVANCE_LP_RING();
  488. master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
  489. if (BEGIN_LP_RING(4) == 0) {
  490. OUT_RING(MI_STORE_DWORD_INDEX);
  491. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  492. OUT_RING(dev_priv->dri1.counter);
  493. OUT_RING(0);
  494. ADVANCE_LP_RING();
  495. }
  496. master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
  497. return 0;
  498. }
  499. static int i915_quiescent(struct drm_device *dev)
  500. {
  501. struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
  502. i915_kernel_lost_context(dev);
  503. return intel_wait_ring_idle(ring);
  504. }
  505. static int i915_flush_ioctl(struct drm_device *dev, void *data,
  506. struct drm_file *file_priv)
  507. {
  508. int ret;
  509. if (drm_core_check_feature(dev, DRIVER_MODESET))
  510. return -ENODEV;
  511. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  512. mutex_lock(&dev->struct_mutex);
  513. ret = i915_quiescent(dev);
  514. mutex_unlock(&dev->struct_mutex);
  515. return ret;
  516. }
  517. static int i915_batchbuffer(struct drm_device *dev, void *data,
  518. struct drm_file *file_priv)
  519. {
  520. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  521. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  522. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  523. master_priv->sarea_priv;
  524. drm_i915_batchbuffer_t *batch = data;
  525. int ret;
  526. struct drm_clip_rect *cliprects = NULL;
  527. if (drm_core_check_feature(dev, DRIVER_MODESET))
  528. return -ENODEV;
  529. if (!dev_priv->dri1.allow_batchbuffer) {
  530. DRM_ERROR("Batchbuffer ioctl disabled\n");
  531. return -EINVAL;
  532. }
  533. DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
  534. batch->start, batch->used, batch->num_cliprects);
  535. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  536. if (batch->num_cliprects < 0)
  537. return -EINVAL;
  538. if (batch->num_cliprects) {
  539. cliprects = kcalloc(batch->num_cliprects,
  540. sizeof(struct drm_clip_rect),
  541. GFP_KERNEL);
  542. if (cliprects == NULL)
  543. return -ENOMEM;
  544. ret = copy_from_user(cliprects, batch->cliprects,
  545. batch->num_cliprects *
  546. sizeof(struct drm_clip_rect));
  547. if (ret != 0) {
  548. ret = -EFAULT;
  549. goto fail_free;
  550. }
  551. }
  552. mutex_lock(&dev->struct_mutex);
  553. ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
  554. mutex_unlock(&dev->struct_mutex);
  555. if (sarea_priv)
  556. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  557. fail_free:
  558. kfree(cliprects);
  559. return ret;
  560. }
  561. static int i915_cmdbuffer(struct drm_device *dev, void *data,
  562. struct drm_file *file_priv)
  563. {
  564. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  565. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  566. drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
  567. master_priv->sarea_priv;
  568. drm_i915_cmdbuffer_t *cmdbuf = data;
  569. struct drm_clip_rect *cliprects = NULL;
  570. void *batch_data;
  571. int ret;
  572. DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
  573. cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
  574. if (drm_core_check_feature(dev, DRIVER_MODESET))
  575. return -ENODEV;
  576. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  577. if (cmdbuf->num_cliprects < 0)
  578. return -EINVAL;
  579. batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
  580. if (batch_data == NULL)
  581. return -ENOMEM;
  582. ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
  583. if (ret != 0) {
  584. ret = -EFAULT;
  585. goto fail_batch_free;
  586. }
  587. if (cmdbuf->num_cliprects) {
  588. cliprects = kcalloc(cmdbuf->num_cliprects,
  589. sizeof(struct drm_clip_rect), GFP_KERNEL);
  590. if (cliprects == NULL) {
  591. ret = -ENOMEM;
  592. goto fail_batch_free;
  593. }
  594. ret = copy_from_user(cliprects, cmdbuf->cliprects,
  595. cmdbuf->num_cliprects *
  596. sizeof(struct drm_clip_rect));
  597. if (ret != 0) {
  598. ret = -EFAULT;
  599. goto fail_clip_free;
  600. }
  601. }
  602. mutex_lock(&dev->struct_mutex);
  603. ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
  604. mutex_unlock(&dev->struct_mutex);
  605. if (ret) {
  606. DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
  607. goto fail_clip_free;
  608. }
  609. if (sarea_priv)
  610. sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  611. fail_clip_free:
  612. kfree(cliprects);
  613. fail_batch_free:
  614. kfree(batch_data);
  615. return ret;
  616. }
  617. static int i915_emit_irq(struct drm_device * dev)
  618. {
  619. drm_i915_private_t *dev_priv = dev->dev_private;
  620. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  621. i915_kernel_lost_context(dev);
  622. DRM_DEBUG_DRIVER("\n");
  623. dev_priv->dri1.counter++;
  624. if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
  625. dev_priv->dri1.counter = 1;
  626. if (master_priv->sarea_priv)
  627. master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
  628. if (BEGIN_LP_RING(4) == 0) {
  629. OUT_RING(MI_STORE_DWORD_INDEX);
  630. OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
  631. OUT_RING(dev_priv->dri1.counter);
  632. OUT_RING(MI_USER_INTERRUPT);
  633. ADVANCE_LP_RING();
  634. }
  635. return dev_priv->dri1.counter;
  636. }
  637. static int i915_wait_irq(struct drm_device * dev, int irq_nr)
  638. {
  639. drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  640. struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
  641. int ret = 0;
  642. struct intel_ring_buffer *ring = LP_RING(dev_priv);
  643. DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
  644. READ_BREADCRUMB(dev_priv));
  645. if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
  646. if (master_priv->sarea_priv)
  647. master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
  648. return 0;
  649. }
  650. if (master_priv->sarea_priv)
  651. master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
  652. if (ring->irq_get(ring)) {
  653. DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
  654. READ_BREADCRUMB(dev_priv) >= irq_nr);
  655. ring->irq_put(ring);
  656. } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
  657. ret = -EBUSY;
  658. if (ret == -EBUSY) {
  659. DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
  660. READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
  661. }
  662. return ret;
  663. }
  664. /* Needs the lock as it touches the ring.
  665. */
  666. static int i915_irq_emit(struct drm_device *dev, void *data,
  667. struct drm_file *file_priv)
  668. {
  669. drm_i915_private_t *dev_priv = dev->dev_private;
  670. drm_i915_irq_emit_t *emit = data;
  671. int result;
  672. if (drm_core_check_feature(dev, DRIVER_MODESET))
  673. return -ENODEV;
  674. if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
  675. DRM_ERROR("called with no initialization\n");
  676. return -EINVAL;
  677. }
  678. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  679. mutex_lock(&dev->struct_mutex);
  680. result = i915_emit_irq(dev);
  681. mutex_unlock(&dev->struct_mutex);
  682. if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
  683. DRM_ERROR("copy_to_user\n");
  684. return -EFAULT;
  685. }
  686. return 0;
  687. }
  688. /* Doesn't need the hardware lock.
  689. */
  690. static int i915_irq_wait(struct drm_device *dev, void *data,
  691. struct drm_file *file_priv)
  692. {
  693. drm_i915_private_t *dev_priv = dev->dev_private;
  694. drm_i915_irq_wait_t *irqwait = data;
  695. if (drm_core_check_feature(dev, DRIVER_MODESET))
  696. return -ENODEV;
  697. if (!dev_priv) {
  698. DRM_ERROR("called with no initialization\n");
  699. return -EINVAL;
  700. }
  701. return i915_wait_irq(dev, irqwait->irq_seq);
  702. }
  703. static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  704. struct drm_file *file_priv)
  705. {
  706. drm_i915_private_t *dev_priv = dev->dev_private;
  707. drm_i915_vblank_pipe_t *pipe = data;
  708. if (drm_core_check_feature(dev, DRIVER_MODESET))
  709. return -ENODEV;
  710. if (!dev_priv) {
  711. DRM_ERROR("called with no initialization\n");
  712. return -EINVAL;
  713. }
  714. pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
  715. return 0;
  716. }
  717. /**
  718. * Schedule buffer swap at given vertical blank.
  719. */
  720. static int i915_vblank_swap(struct drm_device *dev, void *data,
  721. struct drm_file *file_priv)
  722. {
  723. /* The delayed swap mechanism was fundamentally racy, and has been
  724. * removed. The model was that the client requested a delayed flip/swap
  725. * from the kernel, then waited for vblank before continuing to perform
  726. * rendering. The problem was that the kernel might wake the client
  727. * up before it dispatched the vblank swap (since the lock has to be
  728. * held while touching the ringbuffer), in which case the client would
  729. * clear and start the next frame before the swap occurred, and
  730. * flicker would occur in addition to likely missing the vblank.
  731. *
  732. * In the absence of this ioctl, userland falls back to a correct path
  733. * of waiting for a vblank, then dispatching the swap on its own.
  734. * Context switching to userland and back is plenty fast enough for
  735. * meeting the requirements of vblank swapping.
  736. */
  737. return -EINVAL;
  738. }
  739. static int i915_flip_bufs(struct drm_device *dev, void *data,
  740. struct drm_file *file_priv)
  741. {
  742. int ret;
  743. if (drm_core_check_feature(dev, DRIVER_MODESET))
  744. return -ENODEV;
  745. DRM_DEBUG_DRIVER("%s\n", __func__);
  746. RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
  747. mutex_lock(&dev->struct_mutex);
  748. ret = i915_dispatch_flip(dev);
  749. mutex_unlock(&dev->struct_mutex);
  750. return ret;
  751. }
  752. static int i915_getparam(struct drm_device *dev, void *data,
  753. struct drm_file *file_priv)
  754. {
  755. drm_i915_private_t *dev_priv = dev->dev_private;
  756. drm_i915_getparam_t *param = data;
  757. int value;
  758. if (!dev_priv) {
  759. DRM_ERROR("called with no initialization\n");
  760. return -EINVAL;
  761. }
  762. switch (param->param) {
  763. case I915_PARAM_IRQ_ACTIVE:
  764. value = dev->pdev->irq ? 1 : 0;
  765. break;
  766. case I915_PARAM_ALLOW_BATCHBUFFER:
  767. value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
  768. break;
  769. case I915_PARAM_LAST_DISPATCH:
  770. value = READ_BREADCRUMB(dev_priv);
  771. break;
  772. case I915_PARAM_CHIPSET_ID:
  773. value = dev->pci_device;
  774. break;
  775. case I915_PARAM_HAS_GEM:
  776. value = 1;
  777. break;
  778. case I915_PARAM_NUM_FENCES_AVAIL:
  779. value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  780. break;
  781. case I915_PARAM_HAS_OVERLAY:
  782. value = dev_priv->overlay ? 1 : 0;
  783. break;
  784. case I915_PARAM_HAS_PAGEFLIPPING:
  785. value = 1;
  786. break;
  787. case I915_PARAM_HAS_EXECBUF2:
  788. /* depends on GEM */
  789. value = 1;
  790. break;
  791. case I915_PARAM_HAS_BSD:
  792. value = intel_ring_initialized(&dev_priv->ring[VCS]);
  793. break;
  794. case I915_PARAM_HAS_BLT:
  795. value = intel_ring_initialized(&dev_priv->ring[BCS]);
  796. break;
  797. case I915_PARAM_HAS_RELAXED_FENCING:
  798. value = 1;
  799. break;
  800. case I915_PARAM_HAS_COHERENT_RINGS:
  801. value = 1;
  802. break;
  803. case I915_PARAM_HAS_EXEC_CONSTANTS:
  804. value = INTEL_INFO(dev)->gen >= 4;
  805. break;
  806. case I915_PARAM_HAS_RELAXED_DELTA:
  807. value = 1;
  808. break;
  809. case I915_PARAM_HAS_GEN7_SOL_RESET:
  810. value = 1;
  811. break;
  812. case I915_PARAM_HAS_LLC:
  813. value = HAS_LLC(dev);
  814. break;
  815. case I915_PARAM_HAS_ALIASING_PPGTT:
  816. value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
  817. break;
  818. case I915_PARAM_HAS_WAIT_TIMEOUT:
  819. value = 1;
  820. break;
  821. case I915_PARAM_HAS_SEMAPHORES:
  822. value = i915_semaphore_is_enabled(dev);
  823. break;
  824. case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
  825. value = 1;
  826. break;
  827. case I915_PARAM_HAS_SECURE_BATCHES:
  828. value = capable(CAP_SYS_ADMIN);
  829. break;
  830. default:
  831. DRM_DEBUG_DRIVER("Unknown parameter %d\n",
  832. param->param);
  833. return -EINVAL;
  834. }
  835. if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
  836. DRM_ERROR("DRM_COPY_TO_USER failed\n");
  837. return -EFAULT;
  838. }
  839. return 0;
  840. }
  841. static int i915_setparam(struct drm_device *dev, void *data,
  842. struct drm_file *file_priv)
  843. {
  844. drm_i915_private_t *dev_priv = dev->dev_private;
  845. drm_i915_setparam_t *param = data;
  846. if (!dev_priv) {
  847. DRM_ERROR("called with no initialization\n");
  848. return -EINVAL;
  849. }
  850. switch (param->param) {
  851. case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
  852. break;
  853. case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
  854. break;
  855. case I915_SETPARAM_ALLOW_BATCHBUFFER:
  856. dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
  857. break;
  858. case I915_SETPARAM_NUM_USED_FENCES:
  859. if (param->value > dev_priv->num_fence_regs ||
  860. param->value < 0)
  861. return -EINVAL;
  862. /* Userspace can use first N regs */
  863. dev_priv->fence_reg_start = param->value;
  864. break;
  865. default:
  866. DRM_DEBUG_DRIVER("unknown parameter %d\n",
  867. param->param);
  868. return -EINVAL;
  869. }
  870. return 0;
  871. }
  872. static int i915_set_status_page(struct drm_device *dev, void *data,
  873. struct drm_file *file_priv)
  874. {
  875. drm_i915_private_t *dev_priv = dev->dev_private;
  876. drm_i915_hws_addr_t *hws = data;
  877. struct intel_ring_buffer *ring = LP_RING(dev_priv);
  878. if (drm_core_check_feature(dev, DRIVER_MODESET))
  879. return -ENODEV;
  880. if (!I915_NEED_GFX_HWS(dev))
  881. return -EINVAL;
  882. if (!dev_priv) {
  883. DRM_ERROR("called with no initialization\n");
  884. return -EINVAL;
  885. }
  886. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  887. WARN(1, "tried to set status page when mode setting active\n");
  888. return 0;
  889. }
  890. DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
  891. ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
  892. dev_priv->dri1.gfx_hws_cpu_addr =
  893. ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);
  894. if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
  895. i915_dma_cleanup(dev);
  896. ring->status_page.gfx_addr = 0;
  897. DRM_ERROR("can not ioremap virtual address for"
  898. " G33 hw status page\n");
  899. return -ENOMEM;
  900. }
  901. memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
  902. I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
  903. DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
  904. ring->status_page.gfx_addr);
  905. DRM_DEBUG_DRIVER("load hws at %p\n",
  906. ring->status_page.page_addr);
  907. return 0;
  908. }
  909. static int i915_get_bridge_dev(struct drm_device *dev)
  910. {
  911. struct drm_i915_private *dev_priv = dev->dev_private;
  912. dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
  913. if (!dev_priv->bridge_dev) {
  914. DRM_ERROR("bridge device not found\n");
  915. return -1;
  916. }
  917. return 0;
  918. }
  919. #define MCHBAR_I915 0x44
  920. #define MCHBAR_I965 0x48
  921. #define MCHBAR_SIZE (4*4096)
  922. #define DEVEN_REG 0x54
  923. #define DEVEN_MCHBAR_EN (1 << 28)
  924. /* Allocate space for the MCH regs if needed, return nonzero on error */
  925. static int
  926. intel_alloc_mchbar_resource(struct drm_device *dev)
  927. {
  928. drm_i915_private_t *dev_priv = dev->dev_private;
  929. int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
  930. u32 temp_lo, temp_hi = 0;
  931. u64 mchbar_addr;
  932. int ret;
  933. if (INTEL_INFO(dev)->gen >= 4)
  934. pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
  935. pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
  936. mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
  937. /* If ACPI doesn't have it, assume we need to allocate it ourselves */
  938. #ifdef CONFIG_PNP
  939. if (mchbar_addr &&
  940. pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
  941. return 0;
  942. #endif
  943. /* Get some space for it */
  944. dev_priv->mch_res.name = "i915 MCHBAR";
  945. dev_priv->mch_res.flags = IORESOURCE_MEM;
  946. ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
  947. &dev_priv->mch_res,
  948. MCHBAR_SIZE, MCHBAR_SIZE,
  949. PCIBIOS_MIN_MEM,
  950. 0, pcibios_align_resource,
  951. dev_priv->bridge_dev);
  952. if (ret) {
  953. DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
  954. dev_priv->mch_res.start = 0;
  955. return ret;
  956. }
  957. if (INTEL_INFO(dev)->gen >= 4)
  958. pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
  959. upper_32_bits(dev_priv->mch_res.start));
  960. pci_write_config_dword(dev_priv->bridge_dev, reg,
  961. lower_32_bits(dev_priv->mch_res.start));
  962. return 0;
  963. }
  964. /* Setup MCHBAR if possible, return true if we should disable it again */
  965. static void
  966. intel_setup_mchbar(struct drm_device *dev)
  967. {
  968. drm_i915_private_t *dev_priv = dev->dev_private;
  969. int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
  970. u32 temp;
  971. bool enabled;
  972. dev_priv->mchbar_need_disable = false;
  973. if (IS_I915G(dev) || IS_I915GM(dev)) {
  974. pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
  975. enabled = !!(temp & DEVEN_MCHBAR_EN);
  976. } else {
  977. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  978. enabled = temp & 1;
  979. }
  980. /* If it's already enabled, don't have to do anything */
  981. if (enabled)
  982. return;
  983. if (intel_alloc_mchbar_resource(dev))
  984. return;
  985. dev_priv->mchbar_need_disable = true;
  986. /* Space is allocated or reserved, so enable it. */
  987. if (IS_I915G(dev) || IS_I915GM(dev)) {
  988. pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
  989. temp | DEVEN_MCHBAR_EN);
  990. } else {
  991. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  992. pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
  993. }
  994. }
  995. static void
  996. intel_teardown_mchbar(struct drm_device *dev)
  997. {
  998. drm_i915_private_t *dev_priv = dev->dev_private;
  999. int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
  1000. u32 temp;
  1001. if (dev_priv->mchbar_need_disable) {
  1002. if (IS_I915G(dev) || IS_I915GM(dev)) {
  1003. pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
  1004. temp &= ~DEVEN_MCHBAR_EN;
  1005. pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
  1006. } else {
  1007. pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
  1008. temp &= ~1;
  1009. pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
  1010. }
  1011. }
  1012. if (dev_priv->mch_res.start)
  1013. release_resource(&dev_priv->mch_res);
  1014. }
  1015. /* true = enable decode, false = disable decoder */
  1016. static unsigned int i915_vga_set_decode(void *cookie, bool state)
  1017. {
  1018. struct drm_device *dev = cookie;
  1019. intel_modeset_vga_set_state(dev, state);
  1020. if (state)
  1021. return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  1022. VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  1023. else
  1024. return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  1025. }
  1026. static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
  1027. {
  1028. struct drm_device *dev = pci_get_drvdata(pdev);
  1029. pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
  1030. if (state == VGA_SWITCHEROO_ON) {
  1031. pr_info("switched on\n");
  1032. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  1033. /* i915 resume handler doesn't set to D0 */
  1034. pci_set_power_state(dev->pdev, PCI_D0);
  1035. i915_resume(dev);
  1036. dev->switch_power_state = DRM_SWITCH_POWER_ON;
  1037. } else {
  1038. pr_err("switched off\n");
  1039. dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  1040. i915_suspend(dev, pmm);
  1041. dev->switch_power_state = DRM_SWITCH_POWER_OFF;
  1042. }
  1043. }
  1044. static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
  1045. {
  1046. struct drm_device *dev = pci_get_drvdata(pdev);
  1047. bool can_switch;
  1048. spin_lock(&dev->count_lock);
  1049. can_switch = (dev->open_count == 0);
  1050. spin_unlock(&dev->count_lock);
  1051. return can_switch;
  1052. }
  1053. static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
  1054. .set_gpu_state = i915_switcheroo_set_state,
  1055. .reprobe = NULL,
  1056. .can_switch = i915_switcheroo_can_switch,
  1057. };
  1058. static int i915_load_modeset_init(struct drm_device *dev)
  1059. {
  1060. struct drm_i915_private *dev_priv = dev->dev_private;
  1061. int ret;
  1062. ret = intel_parse_bios(dev);
  1063. if (ret)
  1064. DRM_INFO("failed to find VBIOS tables\n");
  1065. /* If we have > 1 VGA cards, then we need to arbitrate access
  1066. * to the common VGA resources.
  1067. *
  1068. * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
  1069. * then we do not take part in VGA arbitration and the
  1070. * vga_client_register() fails with -ENODEV.
  1071. */
  1072. ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
  1073. if (ret && ret != -ENODEV)
  1074. goto out;
  1075. intel_register_dsm_handler();
  1076. ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
  1077. if (ret)
  1078. goto cleanup_vga_client;
  1079. /* Initialise stolen first so that we may reserve preallocated
  1080. * objects for the BIOS to KMS transition.
  1081. */
  1082. ret = i915_gem_init_stolen(dev);
  1083. if (ret)
  1084. goto cleanup_vga_switcheroo;
  1085. intel_modeset_init(dev);
  1086. ret = i915_gem_init(dev);
  1087. if (ret)
  1088. goto cleanup_gem_stolen;
  1089. intel_modeset_gem_init(dev);
  1090. INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
  1091. ret = drm_irq_install(dev);
  1092. if (ret)
  1093. goto cleanup_gem;
  1094. /* Always safe in the mode setting case. */
  1095. /* FIXME: do pre/post-mode set stuff in core KMS code */
  1096. dev->vblank_disable_allowed = 1;
  1097. ret = intel_fbdev_init(dev);
  1098. if (ret)
  1099. goto cleanup_irq;
  1100. drm_kms_helper_poll_init(dev);
  1101. /* We're off and running w/KMS */
  1102. dev_priv->mm.suspended = 0;
  1103. return 0;
  1104. cleanup_irq:
  1105. drm_irq_uninstall(dev);
  1106. cleanup_gem:
  1107. mutex_lock(&dev->struct_mutex);
  1108. i915_gem_cleanup_ringbuffer(dev);
  1109. mutex_unlock(&dev->struct_mutex);
  1110. i915_gem_cleanup_aliasing_ppgtt(dev);
  1111. cleanup_gem_stolen:
  1112. i915_gem_cleanup_stolen(dev);
  1113. cleanup_vga_switcheroo:
  1114. vga_switcheroo_unregister_client(dev->pdev);
  1115. cleanup_vga_client:
  1116. vga_client_register(dev->pdev, NULL, NULL, NULL);
  1117. out:
  1118. return ret;
  1119. }
  1120. int i915_master_create(struct drm_device *dev, struct drm_master *master)
  1121. {
  1122. struct drm_i915_master_private *master_priv;
  1123. master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
  1124. if (!master_priv)
  1125. return -ENOMEM;
  1126. master->driver_priv = master_priv;
  1127. return 0;
  1128. }
  1129. void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
  1130. {
  1131. struct drm_i915_master_private *master_priv = master->driver_priv;
  1132. if (!master_priv)
  1133. return;
  1134. kfree(master_priv);
  1135. master->driver_priv = NULL;
  1136. }
  1137. static void
  1138. i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
  1139. unsigned long size)
  1140. {
  1141. dev_priv->mm.gtt_mtrr = -1;
  1142. #if defined(CONFIG_X86_PAT)
  1143. if (cpu_has_pat)
  1144. return;
  1145. #endif
  1146. /* Set up a WC MTRR for non-PAT systems. This is more common than
  1147. * one would think, because the kernel disables PAT on first
  1148. * generation Core chips because WC PAT gets overridden by a UC
  1149. * MTRR if present. Even if a UC MTRR isn't present.
  1150. */
  1151. dev_priv->mm.gtt_mtrr = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
  1152. if (dev_priv->mm.gtt_mtrr < 0) {
  1153. DRM_INFO("MTRR allocation failed. Graphics "
  1154. "performance may suffer.\n");
  1155. }
  1156. }
  1157. static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
  1158. {
  1159. struct apertures_struct *ap;
  1160. struct pci_dev *pdev = dev_priv->dev->pdev;
  1161. bool primary;
  1162. ap = alloc_apertures(1);
  1163. if (!ap)
  1164. return;
  1165. ap->ranges[0].base = dev_priv->mm.gtt->gma_bus_addr;
  1166. ap->ranges[0].size =
  1167. dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
  1168. primary =
  1169. pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  1170. remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
  1171. kfree(ap);
  1172. }
  1173. static void i915_dump_device_info(struct drm_i915_private *dev_priv)
  1174. {
  1175. const struct intel_device_info *info = dev_priv->info;
  1176. #define DEV_INFO_FLAG(name) info->name ? #name "," : ""
  1177. #define DEV_INFO_SEP ,
  1178. DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x flags="
  1179. "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
  1180. info->gen,
  1181. dev_priv->dev->pdev->device,
  1182. DEV_INFO_FLAGS);
  1183. #undef DEV_INFO_FLAG
  1184. #undef DEV_INFO_SEP
  1185. }
  1186. /**
  1187. * i915_driver_load - setup chip and create an initial config
  1188. * @dev: DRM device
  1189. * @flags: startup flags
  1190. *
  1191. * The driver load routine has to do several things:
  1192. * - drive output discovery via intel_modeset_init()
  1193. * - initialize the memory manager
  1194. * - allocate initial config memory
  1195. * - setup the DRM framebuffer with the allocated memory
  1196. */
  1197. int i915_driver_load(struct drm_device *dev, unsigned long flags)
  1198. {
  1199. struct drm_i915_private *dev_priv;
  1200. struct intel_device_info *info;
  1201. int ret = 0, mmio_bar, mmio_size;
  1202. uint32_t aperture_size;
  1203. info = (struct intel_device_info *) flags;
  1204. /* Refuse to load on gen6+ without kms enabled. */
  1205. if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
  1206. return -ENODEV;
  1207. /* i915 has 4 more counters */
  1208. dev->counters += 4;
  1209. dev->types[6] = _DRM_STAT_IRQ;
  1210. dev->types[7] = _DRM_STAT_PRIMARY;
  1211. dev->types[8] = _DRM_STAT_SECONDARY;
  1212. dev->types[9] = _DRM_STAT_DMA;
  1213. dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
  1214. if (dev_priv == NULL)
  1215. return -ENOMEM;
  1216. dev->dev_private = (void *)dev_priv;
  1217. dev_priv->dev = dev;
  1218. dev_priv->info = info;
  1219. i915_dump_device_info(dev_priv);
  1220. if (i915_get_bridge_dev(dev)) {
  1221. ret = -EIO;
  1222. goto free_priv;
  1223. }
  1224. ret = i915_gem_gtt_init(dev);
  1225. if (ret)
  1226. goto put_bridge;
  1227. if (drm_core_check_feature(dev, DRIVER_MODESET))
  1228. i915_kick_out_firmware_fb(dev_priv);
  1229. pci_set_master(dev->pdev);
  1230. /* overlay on gen2 is broken and can't address above 1G */
  1231. if (IS_GEN2(dev))
  1232. dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
  1233. /* 965GM sometimes incorrectly writes to hardware status page (HWS)
  1234. * using 32bit addressing, overwriting memory if HWS is located
  1235. * above 4GB.
  1236. *
  1237. * The documentation also mentions an issue with undefined
  1238. * behaviour if any general state is accessed within a page above 4GB,
  1239. * which also needs to be handled carefully.
  1240. */
  1241. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1242. dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
  1243. mmio_bar = IS_GEN2(dev) ? 1 : 0;
  1244. /* Before gen4, the registers and the GTT are behind different BARs.
  1245. * However, from gen4 onwards, the registers and the GTT are shared
  1246. * in the same BAR, so we want to restrict this ioremap from
  1247. * clobbering the GTT which we want ioremap_wc instead. Fortunately,
  1248. * the register BAR remains the same size for all the earlier
  1249. * generations up to Ironlake.
  1250. */
  1251. if (info->gen < 5)
  1252. mmio_size = 512*1024;
  1253. else
  1254. mmio_size = 2*1024*1024;
  1255. dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
  1256. if (!dev_priv->regs) {
  1257. DRM_ERROR("failed to map registers\n");
  1258. ret = -EIO;
  1259. goto put_gmch;
  1260. }
  1261. aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
  1262. dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;
  1263. dev_priv->mm.gtt_mapping =
  1264. io_mapping_create_wc(dev_priv->mm.gtt_base_addr,
  1265. aperture_size);
  1266. if (dev_priv->mm.gtt_mapping == NULL) {
  1267. ret = -EIO;
  1268. goto out_rmmap;
  1269. }
  1270. i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,
  1271. aperture_size);
  1272. /* The i915 workqueue is primarily used for batched retirement of
  1273. * requests (and thus managing bo) once the task has been completed
  1274. * by the GPU. i915_gem_retire_requests() is called directly when we
  1275. * need high-priority retirement, such as waiting for an explicit
  1276. * bo.
  1277. *
  1278. * It is also used for periodic low-priority events, such as
  1279. * idle-timers and recording error state.
  1280. *
  1281. * All tasks on the workqueue are expected to acquire the dev mutex
  1282. * so there is no point in running more than one instance of the
  1283. * workqueue at any time. Use an ordered one.
  1284. */
  1285. dev_priv->wq = alloc_ordered_workqueue("i915", 0);
  1286. if (dev_priv->wq == NULL) {
  1287. DRM_ERROR("Failed to create our workqueue.\n");
  1288. ret = -ENOMEM;
  1289. goto out_mtrrfree;
  1290. }
  1291. /* This must be called before any calls to HAS_PCH_* */
  1292. intel_detect_pch(dev);
  1293. intel_irq_init(dev);
  1294. intel_gt_init(dev);
  1295. /* Try to make sure MCHBAR is enabled before poking at it */
  1296. intel_setup_mchbar(dev);
  1297. intel_setup_gmbus(dev);
  1298. intel_opregion_setup(dev);
  1299. intel_setup_bios(dev);
  1300. i915_gem_load(dev);
  1301. /* On the 945G/GM, the chipset reports the MSI capability on the
  1302. * integrated graphics even though the support isn't actually there
  1303. * according to the published specs. It doesn't appear to function
  1304. * correctly in testing on 945G.
  1305. * This may be a side effect of MSI having been made available for PEG
  1306. * and the registers being closely associated.
  1307. *
  1308. * According to chipset errata, on the 965GM, MSI interrupts may
  1309. * be lost or delayed, but we use them anyways to avoid
  1310. * stuck interrupts on some machines.
  1311. */
  1312. if (!IS_I945G(dev) && !IS_I945GM(dev))
  1313. pci_enable_msi(dev->pdev);
  1314. spin_lock_init(&dev_priv->irq_lock);
  1315. spin_lock_init(&dev_priv->error_lock);
  1316. spin_lock_init(&dev_priv->rps.lock);
  1317. spin_lock_init(&dev_priv->dpio_lock);
  1318. mutex_init(&dev_priv->rps.hw_lock);
  1319. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  1320. dev_priv->num_pipe = 3;
  1321. else if (IS_MOBILE(dev) || !IS_GEN2(dev))
  1322. dev_priv->num_pipe = 2;
  1323. else
  1324. dev_priv->num_pipe = 1;
  1325. ret = drm_vblank_init(dev, dev_priv->num_pipe);
  1326. if (ret)
  1327. goto out_gem_unload;
  1328. /* Start out suspended */
  1329. dev_priv->mm.suspended = 1;
  1330. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1331. ret = i915_load_modeset_init(dev);
  1332. if (ret < 0) {
  1333. DRM_ERROR("failed to init modeset\n");
  1334. goto out_gem_unload;
  1335. }
  1336. }
  1337. i915_setup_sysfs(dev);
  1338. /* Must be done after probing outputs */
  1339. intel_opregion_init(dev);
  1340. acpi_video_register();
  1341. setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
  1342. (unsigned long) dev);
  1343. if (IS_GEN5(dev))
  1344. intel_gpu_ips_init(dev_priv);
  1345. return 0;
  1346. out_gem_unload:
  1347. if (dev_priv->mm.inactive_shrinker.shrink)
  1348. unregister_shrinker(&dev_priv->mm.inactive_shrinker);
  1349. if (dev->pdev->msi_enabled)
  1350. pci_disable_msi(dev->pdev);
  1351. intel_teardown_gmbus(dev);
  1352. intel_teardown_mchbar(dev);
  1353. destroy_workqueue(dev_priv->wq);
  1354. out_mtrrfree:
  1355. if (dev_priv->mm.gtt_mtrr >= 0) {
  1356. mtrr_del(dev_priv->mm.gtt_mtrr,
  1357. dev_priv->mm.gtt_base_addr,
  1358. aperture_size);
  1359. dev_priv->mm.gtt_mtrr = -1;
  1360. }
  1361. io_mapping_free(dev_priv->mm.gtt_mapping);
  1362. out_rmmap:
  1363. pci_iounmap(dev->pdev, dev_priv->regs);
  1364. put_gmch:
  1365. i915_gem_gtt_fini(dev);
  1366. put_bridge:
  1367. pci_dev_put(dev_priv->bridge_dev);
  1368. free_priv:
  1369. kfree(dev_priv);
  1370. return ret;
  1371. }
  1372. int i915_driver_unload(struct drm_device *dev)
  1373. {
  1374. struct drm_i915_private *dev_priv = dev->dev_private;
  1375. int ret;
  1376. intel_gpu_ips_teardown();
  1377. i915_teardown_sysfs(dev);
  1378. if (dev_priv->mm.inactive_shrinker.shrink)
  1379. unregister_shrinker(&dev_priv->mm.inactive_shrinker);
  1380. mutex_lock(&dev->struct_mutex);
  1381. ret = i915_gpu_idle(dev);
  1382. if (ret)
  1383. DRM_ERROR("failed to idle hardware: %d\n", ret);
  1384. i915_gem_retire_requests(dev);
  1385. mutex_unlock(&dev->struct_mutex);
  1386. /* Cancel the retire work handler, which should be idle now. */
  1387. cancel_delayed_work_sync(&dev_priv->mm.retire_work);
  1388. io_mapping_free(dev_priv->mm.gtt_mapping);
  1389. if (dev_priv->mm.gtt_mtrr >= 0) {
  1390. mtrr_del(dev_priv->mm.gtt_mtrr,
  1391. dev_priv->mm.gtt_base_addr,
  1392. dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
  1393. dev_priv->mm.gtt_mtrr = -1;
  1394. }
  1395. acpi_video_unregister();
  1396. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1397. intel_fbdev_fini(dev);
  1398. intel_modeset_cleanup(dev);
  1399. cancel_work_sync(&dev_priv->console_resume_work);
  1400. /*
  1401. * free the memory space allocated for the child device
  1402. * config parsed from VBT
  1403. */
  1404. if (dev_priv->child_dev && dev_priv->child_dev_num) {
  1405. kfree(dev_priv->child_dev);
  1406. dev_priv->child_dev = NULL;
  1407. dev_priv->child_dev_num = 0;
  1408. }
  1409. vga_switcheroo_unregister_client(dev->pdev);
  1410. vga_client_register(dev->pdev, NULL, NULL, NULL);
  1411. }
  1412. /* Free error state after interrupts are fully disabled. */
  1413. del_timer_sync(&dev_priv->hangcheck_timer);
  1414. cancel_work_sync(&dev_priv->error_work);
  1415. i915_destroy_error_state(dev);
  1416. if (dev->pdev->msi_enabled)
  1417. pci_disable_msi(dev->pdev);
  1418. intel_opregion_fini(dev);
  1419. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1420. /* Flush any outstanding unpin_work. */
  1421. flush_workqueue(dev_priv->wq);
  1422. mutex_lock(&dev->struct_mutex);
  1423. i915_gem_free_all_phys_object(dev);
  1424. i915_gem_cleanup_ringbuffer(dev);
  1425. i915_gem_context_fini(dev);
  1426. mutex_unlock(&dev->struct_mutex);
  1427. i915_gem_cleanup_aliasing_ppgtt(dev);
  1428. i915_gem_cleanup_stolen(dev);
  1429. drm_mm_takedown(&dev_priv->mm.stolen);
  1430. intel_cleanup_overlay(dev);
  1431. if (!I915_NEED_GFX_HWS(dev))
  1432. i915_free_hws(dev);
  1433. }
  1434. if (dev_priv->regs != NULL)
  1435. pci_iounmap(dev->pdev, dev_priv->regs);
  1436. intel_teardown_gmbus(dev);
  1437. intel_teardown_mchbar(dev);
  1438. destroy_workqueue(dev_priv->wq);
  1439. pci_dev_put(dev_priv->bridge_dev);
  1440. kfree(dev->dev_private);
  1441. return 0;
  1442. }
  1443. int i915_driver_open(struct drm_device *dev, struct drm_file *file)
  1444. {
  1445. struct drm_i915_file_private *file_priv;
  1446. DRM_DEBUG_DRIVER("\n");
  1447. file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
  1448. if (!file_priv)
  1449. return -ENOMEM;
  1450. file->driver_priv = file_priv;
  1451. spin_lock_init(&file_priv->mm.lock);
  1452. INIT_LIST_HEAD(&file_priv->mm.request_list);
  1453. idr_init(&file_priv->context_idr);
  1454. return 0;
  1455. }
  1456. /**
  1457. * i915_driver_lastclose - clean up after all DRM clients have exited
  1458. * @dev: DRM device
  1459. *
  1460. * Take care of cleaning up after all DRM clients have exited. In the
  1461. * mode setting case, we want to restore the kernel's initial mode (just
  1462. * in case the last client left us in a bad state).
  1463. *
  1464. * Additionally, in the non-mode setting case, we'll tear down the GTT
  1465. * and DMA structures, since the kernel won't be using them, and clea
  1466. * up any GEM state.
  1467. */
  1468. void i915_driver_lastclose(struct drm_device * dev)
  1469. {
  1470. drm_i915_private_t *dev_priv = dev->dev_private;
  1471. /* On gen6+ we refuse to init without kms enabled, but then the drm core
  1472. * goes right around and calls lastclose. Check for this and don't clean
  1473. * up anything. */
  1474. if (!dev_priv)
  1475. return;
  1476. if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  1477. intel_fb_restore_mode(dev);
  1478. vga_switcheroo_process_delayed_switch();
  1479. return;
  1480. }
  1481. i915_gem_lastclose(dev);
  1482. i915_dma_cleanup(dev);
  1483. }
  1484. void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
  1485. {
  1486. i915_gem_context_close(dev, file_priv);
  1487. i915_gem_release(dev, file_priv);
  1488. }
  1489. void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
  1490. {
  1491. struct drm_i915_file_private *file_priv = file->driver_priv;
  1492. kfree(file_priv);
  1493. }
  1494. struct drm_ioctl_desc i915_ioctls[] = {
  1495. DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1496. DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
  1497. DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
  1498. DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
  1499. DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
  1500. DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
  1501. DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
  1502. DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1503. DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
  1504. DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
  1505. DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1506. DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
  1507. DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1508. DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1509. DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
  1510. DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
  1511. DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  1512. DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1513. DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
  1514. DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
  1515. DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1516. DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1517. DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1518. DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
  1519. DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
  1520. DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1521. DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1522. DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
  1523. DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
  1524. DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
  1525. DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
  1526. DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
  1527. DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
  1528. DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
  1529. DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
  1530. DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
  1531. DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
  1532. DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
  1533. DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
  1534. DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
  1535. DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
  1536. DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
  1537. DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
  1538. DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
  1539. DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
  1540. DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
  1541. DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
  1542. DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
  1543. };
  1544. int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
  1545. /*
  1546. * This is really ugly: Because old userspace abused the linux agp interface to
  1547. * manage the gtt, we need to claim that all intel devices are agp. For
  1548. * otherwise the drm core refuses to initialize the agp support code.
  1549. */
  1550. int i915_driver_device_is_agp(struct drm_device * dev)
  1551. {
  1552. return 1;
  1553. }