omap-dmic.c 12 KB

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  1. /*
  2. * omap-dmic.c -- OMAP ASoC DMIC DAI driver
  3. *
  4. * Copyright (C) 2010 - 2011 Texas Instruments
  5. *
  6. * Author: David Lambert <dlambert@ti.com>
  7. * Misael Lopez Cruz <misael.lopez@ti.com>
  8. * Liam Girdwood <lrg@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/err.h>
  30. #include <linux/clk.h>
  31. #include <linux/io.h>
  32. #include <linux/slab.h>
  33. #include <linux/pm_runtime.h>
  34. #include <plat/dma.h>
  35. #include <sound/core.h>
  36. #include <sound/pcm.h>
  37. #include <sound/pcm_params.h>
  38. #include <sound/initval.h>
  39. #include <sound/soc.h>
  40. #include "omap-pcm.h"
  41. #include "omap-dmic.h"
  42. struct omap_dmic {
  43. struct device *dev;
  44. void __iomem *io_base;
  45. struct clk *fclk;
  46. int fclk_freq;
  47. int out_freq;
  48. int clk_div;
  49. int sysclk;
  50. int threshold;
  51. u32 ch_enabled;
  52. bool active;
  53. struct mutex mutex;
  54. };
  55. /*
  56. * Stream DMA parameters
  57. */
  58. static struct omap_pcm_dma_data omap_dmic_dai_dma_params = {
  59. .name = "DMIC capture",
  60. .data_type = OMAP_DMA_DATA_TYPE_S32,
  61. .sync_mode = OMAP_DMA_SYNC_PACKET,
  62. };
  63. static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
  64. {
  65. __raw_writel(val, dmic->io_base + reg);
  66. }
  67. static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
  68. {
  69. return __raw_readl(dmic->io_base + reg);
  70. }
  71. static inline void omap_dmic_start(struct omap_dmic *dmic)
  72. {
  73. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  74. /* Configure DMA controller */
  75. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
  76. OMAP_DMIC_DMA_ENABLE);
  77. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
  78. }
  79. static inline void omap_dmic_stop(struct omap_dmic *dmic)
  80. {
  81. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  82. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  83. ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
  84. /* Disable DMA request generation */
  85. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
  86. OMAP_DMIC_DMA_ENABLE);
  87. }
  88. static inline int dmic_is_enabled(struct omap_dmic *dmic)
  89. {
  90. return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
  91. OMAP_DMIC_UP_ENABLE_MASK;
  92. }
  93. static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
  94. struct snd_soc_dai *dai)
  95. {
  96. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  97. int ret = 0;
  98. mutex_lock(&dmic->mutex);
  99. if (!dai->active) {
  100. snd_pcm_hw_constraint_msbits(substream->runtime, 0, 32, 24);
  101. dmic->active = 1;
  102. } else {
  103. ret = -EBUSY;
  104. }
  105. mutex_unlock(&dmic->mutex);
  106. return ret;
  107. }
  108. static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
  109. struct snd_soc_dai *dai)
  110. {
  111. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  112. mutex_lock(&dmic->mutex);
  113. if (!dai->active)
  114. dmic->active = 0;
  115. mutex_unlock(&dmic->mutex);
  116. }
  117. static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
  118. {
  119. int divider = -EINVAL;
  120. /*
  121. * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
  122. * configuration.
  123. */
  124. if (sample_rate == 192000) {
  125. if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
  126. divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
  127. else
  128. dev_err(dmic->dev,
  129. "invalid clock configuration for 192KHz\n");
  130. return divider;
  131. }
  132. switch (dmic->out_freq) {
  133. case 1536000:
  134. if (dmic->fclk_freq != 24576000)
  135. goto div_err;
  136. divider = 0x4; /* Divider: 16 */
  137. break;
  138. case 2400000:
  139. switch (dmic->fclk_freq) {
  140. case 12000000:
  141. divider = 0x5; /* Divider: 5 */
  142. break;
  143. case 19200000:
  144. divider = 0x0; /* Divider: 8 */
  145. break;
  146. case 24000000:
  147. divider = 0x2; /* Divider: 10 */
  148. break;
  149. default:
  150. goto div_err;
  151. }
  152. break;
  153. case 3072000:
  154. if (dmic->fclk_freq != 24576000)
  155. goto div_err;
  156. divider = 0x3; /* Divider: 8 */
  157. break;
  158. case 3840000:
  159. if (dmic->fclk_freq != 19200000)
  160. goto div_err;
  161. divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
  162. break;
  163. default:
  164. dev_err(dmic->dev, "invalid out frequency: %dHz\n",
  165. dmic->out_freq);
  166. break;
  167. }
  168. return divider;
  169. div_err:
  170. dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
  171. dmic->out_freq, dmic->fclk_freq);
  172. return -EINVAL;
  173. }
  174. static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
  175. struct snd_pcm_hw_params *params,
  176. struct snd_soc_dai *dai)
  177. {
  178. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  179. int channels;
  180. dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
  181. if (dmic->clk_div < 0) {
  182. dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
  183. dmic->out_freq, dmic->fclk_freq);
  184. return -EINVAL;
  185. }
  186. dmic->ch_enabled = 0;
  187. channels = params_channels(params);
  188. switch (channels) {
  189. case 6:
  190. dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
  191. case 4:
  192. dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
  193. case 2:
  194. dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
  195. break;
  196. default:
  197. dev_err(dmic->dev, "invalid number of legacy channels\n");
  198. return -EINVAL;
  199. }
  200. /* packet size is threshold * channels */
  201. omap_dmic_dai_dma_params.packet_size = dmic->threshold * channels;
  202. snd_soc_dai_set_dma_data(dai, substream, &omap_dmic_dai_dma_params);
  203. return 0;
  204. }
  205. static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
  206. struct snd_soc_dai *dai)
  207. {
  208. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  209. u32 ctrl;
  210. /* Configure uplink threshold */
  211. omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
  212. ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  213. /* Set dmic out format */
  214. ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
  215. ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  216. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  217. /* Configure dmic clock divider */
  218. ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
  219. ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
  220. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
  221. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  222. ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  223. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  224. return 0;
  225. }
  226. static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
  227. int cmd, struct snd_soc_dai *dai)
  228. {
  229. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  230. switch (cmd) {
  231. case SNDRV_PCM_TRIGGER_START:
  232. omap_dmic_start(dmic);
  233. break;
  234. case SNDRV_PCM_TRIGGER_STOP:
  235. omap_dmic_stop(dmic);
  236. break;
  237. default:
  238. break;
  239. }
  240. return 0;
  241. }
  242. static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
  243. unsigned int freq)
  244. {
  245. struct clk *parent_clk;
  246. char *parent_clk_name;
  247. int ret = 0;
  248. switch (freq) {
  249. case 12000000:
  250. case 19200000:
  251. case 24000000:
  252. case 24576000:
  253. break;
  254. default:
  255. dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
  256. dmic->fclk_freq = 0;
  257. return -EINVAL;
  258. }
  259. if (dmic->sysclk == clk_id) {
  260. dmic->fclk_freq = freq;
  261. return 0;
  262. }
  263. /* re-parent not allowed if a stream is ongoing */
  264. if (dmic->active && dmic_is_enabled(dmic)) {
  265. dev_err(dmic->dev, "can't re-parent when DMIC active\n");
  266. return -EBUSY;
  267. }
  268. switch (clk_id) {
  269. case OMAP_DMIC_SYSCLK_PAD_CLKS:
  270. parent_clk_name = "pad_clks_ck";
  271. break;
  272. case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
  273. parent_clk_name = "slimbus_clk";
  274. break;
  275. case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
  276. parent_clk_name = "dmic_sync_mux_ck";
  277. break;
  278. default:
  279. dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
  280. return -EINVAL;
  281. }
  282. parent_clk = clk_get(dmic->dev, parent_clk_name);
  283. if (IS_ERR(parent_clk)) {
  284. dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
  285. return -ENODEV;
  286. }
  287. mutex_lock(&dmic->mutex);
  288. if (dmic->active) {
  289. /* disable clock while reparenting */
  290. pm_runtime_put_sync(dmic->dev);
  291. ret = clk_set_parent(dmic->fclk, parent_clk);
  292. pm_runtime_get_sync(dmic->dev);
  293. } else {
  294. ret = clk_set_parent(dmic->fclk, parent_clk);
  295. }
  296. mutex_unlock(&dmic->mutex);
  297. if (ret < 0) {
  298. dev_err(dmic->dev, "re-parent failed\n");
  299. goto err_busy;
  300. }
  301. dmic->sysclk = clk_id;
  302. dmic->fclk_freq = freq;
  303. err_busy:
  304. clk_put(parent_clk);
  305. return ret;
  306. }
  307. static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
  308. unsigned int freq)
  309. {
  310. int ret = 0;
  311. if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
  312. dev_err(dmic->dev, "output clk_id (%d) not supported\n",
  313. clk_id);
  314. return -EINVAL;
  315. }
  316. switch (freq) {
  317. case 1536000:
  318. case 2400000:
  319. case 3072000:
  320. case 3840000:
  321. dmic->out_freq = freq;
  322. break;
  323. default:
  324. dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
  325. dmic->out_freq = 0;
  326. ret = -EINVAL;
  327. }
  328. return ret;
  329. }
  330. static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  331. unsigned int freq, int dir)
  332. {
  333. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  334. if (dir == SND_SOC_CLOCK_IN)
  335. return omap_dmic_select_fclk(dmic, clk_id, freq);
  336. else if (dir == SND_SOC_CLOCK_OUT)
  337. return omap_dmic_select_outclk(dmic, clk_id, freq);
  338. dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
  339. return -EINVAL;
  340. }
  341. static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
  342. .startup = omap_dmic_dai_startup,
  343. .shutdown = omap_dmic_dai_shutdown,
  344. .hw_params = omap_dmic_dai_hw_params,
  345. .prepare = omap_dmic_dai_prepare,
  346. .trigger = omap_dmic_dai_trigger,
  347. .set_sysclk = omap_dmic_set_dai_sysclk,
  348. };
  349. static int omap_dmic_probe(struct snd_soc_dai *dai)
  350. {
  351. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  352. pm_runtime_enable(dmic->dev);
  353. /* Disable lines while request is ongoing */
  354. pm_runtime_get_sync(dmic->dev);
  355. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
  356. pm_runtime_put_sync(dmic->dev);
  357. /* Configure DMIC threshold value */
  358. dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
  359. return 0;
  360. }
  361. static int omap_dmic_remove(struct snd_soc_dai *dai)
  362. {
  363. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  364. pm_runtime_disable(dmic->dev);
  365. return 0;
  366. }
  367. static struct snd_soc_dai_driver omap_dmic_dai = {
  368. .name = "omap-dmic",
  369. .probe = omap_dmic_probe,
  370. .remove = omap_dmic_remove,
  371. .capture = {
  372. .channels_min = 2,
  373. .channels_max = 6,
  374. .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
  375. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  376. },
  377. .ops = &omap_dmic_dai_ops,
  378. };
  379. static __devinit int asoc_dmic_probe(struct platform_device *pdev)
  380. {
  381. struct omap_dmic *dmic;
  382. struct resource *res;
  383. int ret;
  384. dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
  385. if (!dmic)
  386. return -ENOMEM;
  387. platform_set_drvdata(pdev, dmic);
  388. dmic->dev = &pdev->dev;
  389. dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
  390. mutex_init(&dmic->mutex);
  391. dmic->fclk = clk_get(dmic->dev, "dmic_fck");
  392. if (IS_ERR(dmic->fclk)) {
  393. dev_err(dmic->dev, "cant get dmic_fck\n");
  394. return -ENODEV;
  395. }
  396. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  397. if (!res) {
  398. dev_err(dmic->dev, "invalid dma memory resource\n");
  399. ret = -ENODEV;
  400. goto err_put_clk;
  401. }
  402. omap_dmic_dai_dma_params.port_addr = res->start + OMAP_DMIC_DATA_REG;
  403. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  404. if (!res) {
  405. dev_err(dmic->dev, "invalid dma resource\n");
  406. ret = -ENODEV;
  407. goto err_put_clk;
  408. }
  409. omap_dmic_dai_dma_params.dma_req = res->start;
  410. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  411. if (!res) {
  412. dev_err(dmic->dev, "invalid memory resource\n");
  413. ret = -ENODEV;
  414. goto err_put_clk;
  415. }
  416. if (!devm_request_mem_region(&pdev->dev, res->start,
  417. resource_size(res), pdev->name)) {
  418. dev_err(dmic->dev, "memory region already claimed\n");
  419. ret = -ENODEV;
  420. goto err_put_clk;
  421. }
  422. dmic->io_base = devm_ioremap(&pdev->dev, res->start,
  423. resource_size(res));
  424. if (!dmic->io_base) {
  425. ret = -ENOMEM;
  426. goto err_put_clk;
  427. }
  428. ret = snd_soc_register_dai(&pdev->dev, &omap_dmic_dai);
  429. if (ret)
  430. goto err_put_clk;
  431. return 0;
  432. err_put_clk:
  433. clk_put(dmic->fclk);
  434. return ret;
  435. }
  436. static int __devexit asoc_dmic_remove(struct platform_device *pdev)
  437. {
  438. struct omap_dmic *dmic = platform_get_drvdata(pdev);
  439. snd_soc_unregister_dai(&pdev->dev);
  440. clk_put(dmic->fclk);
  441. return 0;
  442. }
  443. static struct platform_driver asoc_dmic_driver = {
  444. .driver = {
  445. .name = "omap-dmic",
  446. .owner = THIS_MODULE,
  447. },
  448. .probe = asoc_dmic_probe,
  449. .remove = __devexit_p(asoc_dmic_remove),
  450. };
  451. module_platform_driver(asoc_dmic_driver);
  452. MODULE_ALIAS("platform:omap-dmic");
  453. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  454. MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
  455. MODULE_LICENSE("GPL");