wm8958-dsp2.c 27 KB

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  1. /*
  2. * wm8958-dsp2.c -- WM8958 DSP2 support
  3. *
  4. * Copyright 2011 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <sound/soc.h>
  21. #include <sound/initval.h>
  22. #include <sound/tlv.h>
  23. #include <trace/events/asoc.h>
  24. #include <linux/mfd/wm8994/core.h>
  25. #include <linux/mfd/wm8994/registers.h>
  26. #include <linux/mfd/wm8994/pdata.h>
  27. #include <linux/mfd/wm8994/gpio.h>
  28. #include "wm8994.h"
  29. #define WM_FW_BLOCK_INFO 0xff
  30. #define WM_FW_BLOCK_PM 0x00
  31. #define WM_FW_BLOCK_X 0x01
  32. #define WM_FW_BLOCK_Y 0x02
  33. #define WM_FW_BLOCK_Z 0x03
  34. #define WM_FW_BLOCK_I 0x06
  35. #define WM_FW_BLOCK_A 0x08
  36. #define WM_FW_BLOCK_C 0x0c
  37. static int wm8958_dsp2_fw(struct snd_soc_codec *codec, const char *name,
  38. const struct firmware *fw, bool check)
  39. {
  40. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  41. u64 data64;
  42. u32 data32;
  43. const u8 *data;
  44. char *str;
  45. size_t block_len, len;
  46. int ret = 0;
  47. /* Suppress unneeded downloads */
  48. if (wm8994->cur_fw == fw)
  49. return 0;
  50. if (fw->size < 32) {
  51. dev_err(codec->dev, "%s: firmware too short (%d bytes)\n",
  52. name, fw->size);
  53. goto err;
  54. }
  55. if (memcmp(fw->data, "WMFW", 4) != 0) {
  56. memcpy(&data32, fw->data, sizeof(data32));
  57. data32 = be32_to_cpu(data32);
  58. dev_err(codec->dev, "%s: firmware has bad file magic %08x\n",
  59. name, data32);
  60. goto err;
  61. }
  62. memcpy(&data32, fw->data + 4, sizeof(data32));
  63. len = be32_to_cpu(data32);
  64. memcpy(&data32, fw->data + 8, sizeof(data32));
  65. data32 = be32_to_cpu(data32);
  66. if ((data32 >> 24) & 0xff) {
  67. dev_err(codec->dev, "%s: unsupported firmware version %d\n",
  68. name, (data32 >> 24) & 0xff);
  69. goto err;
  70. }
  71. if ((data32 & 0xffff) != 8958) {
  72. dev_err(codec->dev, "%s: unsupported target device %d\n",
  73. name, data32 & 0xffff);
  74. goto err;
  75. }
  76. if (((data32 >> 16) & 0xff) != 0xc) {
  77. dev_err(codec->dev, "%s: unsupported target core %d\n",
  78. name, (data32 >> 16) & 0xff);
  79. goto err;
  80. }
  81. if (check) {
  82. memcpy(&data64, fw->data + 24, sizeof(u64));
  83. dev_info(codec->dev, "%s timestamp %llx\n",
  84. name, be64_to_cpu(data64));
  85. } else {
  86. snd_soc_write(codec, 0x102, 0x2);
  87. snd_soc_write(codec, 0x900, 0x2);
  88. }
  89. data = fw->data + len;
  90. len = fw->size - len;
  91. while (len) {
  92. if (len < 12) {
  93. dev_err(codec->dev, "%s short data block of %zd\n",
  94. name, len);
  95. goto err;
  96. }
  97. memcpy(&data32, data + 4, sizeof(data32));
  98. block_len = be32_to_cpu(data32);
  99. if (block_len + 8 > len) {
  100. dev_err(codec->dev, "%zd byte block longer than file\n",
  101. block_len);
  102. goto err;
  103. }
  104. if (block_len == 0) {
  105. dev_err(codec->dev, "Zero length block\n");
  106. goto err;
  107. }
  108. memcpy(&data32, data, sizeof(data32));
  109. data32 = be32_to_cpu(data32);
  110. switch ((data32 >> 24) & 0xff) {
  111. case WM_FW_BLOCK_INFO:
  112. /* Informational text */
  113. if (!check)
  114. break;
  115. str = kzalloc(block_len + 1, GFP_KERNEL);
  116. if (str) {
  117. memcpy(str, data + 8, block_len);
  118. dev_info(codec->dev, "%s: %s\n", name, str);
  119. kfree(str);
  120. } else {
  121. dev_err(codec->dev, "Out of memory\n");
  122. }
  123. break;
  124. case WM_FW_BLOCK_PM:
  125. case WM_FW_BLOCK_X:
  126. case WM_FW_BLOCK_Y:
  127. case WM_FW_BLOCK_Z:
  128. case WM_FW_BLOCK_I:
  129. case WM_FW_BLOCK_A:
  130. case WM_FW_BLOCK_C:
  131. dev_dbg(codec->dev, "%s: %zd bytes of %x@%x\n", name,
  132. block_len, (data32 >> 24) & 0xff,
  133. data32 & 0xffffff);
  134. if (check)
  135. break;
  136. data32 &= 0xffffff;
  137. wm8994_bulk_write(codec->control_data,
  138. data32 & 0xffffff,
  139. block_len / 2,
  140. (void *)(data + 8));
  141. break;
  142. default:
  143. dev_warn(codec->dev, "%s: unknown block type %d\n",
  144. name, (data32 >> 24) & 0xff);
  145. break;
  146. }
  147. /* Round up to the next 32 bit word */
  148. block_len += block_len % 4;
  149. data += block_len + 8;
  150. len -= block_len + 8;
  151. }
  152. if (!check) {
  153. dev_dbg(codec->dev, "%s: download done\n", name);
  154. wm8994->cur_fw = fw;
  155. } else {
  156. dev_info(codec->dev, "%s: got firmware\n", name);
  157. }
  158. goto ok;
  159. err:
  160. ret = -EINVAL;
  161. ok:
  162. if (!check) {
  163. snd_soc_write(codec, 0x900, 0x0);
  164. snd_soc_write(codec, 0x102, 0x0);
  165. }
  166. return ret;
  167. }
  168. static void wm8958_dsp_start_mbc(struct snd_soc_codec *codec, int path)
  169. {
  170. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  171. struct wm8994_pdata *pdata = wm8994->pdata;
  172. int i;
  173. /* If the DSP is already running then noop */
  174. if (snd_soc_read(codec, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
  175. return;
  176. /* If we have MBC firmware download it */
  177. if (wm8994->mbc)
  178. wm8958_dsp2_fw(codec, "MBC", wm8994->mbc, false);
  179. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  180. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  181. /* If we've got user supplied MBC settings use them */
  182. if (pdata && pdata->num_mbc_cfgs) {
  183. struct wm8958_mbc_cfg *cfg
  184. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  185. for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
  186. snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
  187. cfg->coeff_regs[i]);
  188. for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
  189. snd_soc_write(codec,
  190. i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
  191. cfg->cutoff_regs[i]);
  192. }
  193. /* Run the DSP */
  194. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  195. WM8958_DSP2_RUNR);
  196. /* And we're off! */
  197. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  198. WM8958_MBC_ENA |
  199. WM8958_MBC_SEL_MASK,
  200. path << WM8958_MBC_SEL_SHIFT |
  201. WM8958_MBC_ENA);
  202. }
  203. static void wm8958_dsp_start_vss(struct snd_soc_codec *codec, int path)
  204. {
  205. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  206. struct wm8994_pdata *pdata = wm8994->pdata;
  207. int i, ena;
  208. if (wm8994->mbc_vss)
  209. wm8958_dsp2_fw(codec, "MBC+VSS", wm8994->mbc_vss, false);
  210. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  211. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  212. /* If we've got user supplied settings use them */
  213. if (pdata && pdata->num_mbc_cfgs) {
  214. struct wm8958_mbc_cfg *cfg
  215. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  216. for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
  217. snd_soc_write(codec, i + 0x2800,
  218. cfg->combined_regs[i]);
  219. }
  220. if (pdata && pdata->num_vss_cfgs) {
  221. struct wm8958_vss_cfg *cfg
  222. = &pdata->vss_cfgs[wm8994->vss_cfg];
  223. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  224. snd_soc_write(codec, i + 0x2600, cfg->regs[i]);
  225. }
  226. if (pdata && pdata->num_vss_hpf_cfgs) {
  227. struct wm8958_vss_hpf_cfg *cfg
  228. = &pdata->vss_hpf_cfgs[wm8994->vss_hpf_cfg];
  229. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  230. snd_soc_write(codec, i + 0x2400, cfg->regs[i]);
  231. }
  232. /* Run the DSP */
  233. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  234. WM8958_DSP2_RUNR);
  235. /* Enable the algorithms we've selected */
  236. ena = 0;
  237. if (wm8994->mbc_ena[path])
  238. ena |= 0x8;
  239. if (wm8994->hpf2_ena[path])
  240. ena |= 0x4;
  241. if (wm8994->hpf1_ena[path])
  242. ena |= 0x2;
  243. if (wm8994->vss_ena[path])
  244. ena |= 0x1;
  245. snd_soc_write(codec, 0x2201, ena);
  246. /* Switch the DSP into the data path */
  247. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  248. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  249. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  250. }
  251. static void wm8958_dsp_start_enh_eq(struct snd_soc_codec *codec, int path)
  252. {
  253. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  254. struct wm8994_pdata *pdata = wm8994->pdata;
  255. int i;
  256. wm8958_dsp2_fw(codec, "ENH_EQ", wm8994->enh_eq, false);
  257. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  258. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  259. /* If we've got user supplied settings use them */
  260. if (pdata && pdata->num_enh_eq_cfgs) {
  261. struct wm8958_enh_eq_cfg *cfg
  262. = &pdata->enh_eq_cfgs[wm8994->enh_eq_cfg];
  263. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  264. snd_soc_write(codec, i + 0x2200,
  265. cfg->regs[i]);
  266. }
  267. /* Run the DSP */
  268. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  269. WM8958_DSP2_RUNR);
  270. /* Switch the DSP into the data path */
  271. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  272. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  273. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  274. }
  275. static void wm8958_dsp_apply(struct snd_soc_codec *codec, int path, int start)
  276. {
  277. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  278. int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
  279. int ena, reg, aif;
  280. switch (path) {
  281. case 0:
  282. pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
  283. aif = 0;
  284. break;
  285. case 1:
  286. pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
  287. aif = 0;
  288. break;
  289. case 2:
  290. pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
  291. aif = 1;
  292. break;
  293. default:
  294. BUG();
  295. return;
  296. }
  297. /* Do we have both an active AIF and an active algorithm? */
  298. ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
  299. wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
  300. wm8994->enh_eq_ena[path];
  301. if (!pwr_reg)
  302. ena = 0;
  303. reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
  304. dev_dbg(codec->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
  305. path, wm8994->dsp_active, start, pwr_reg, reg);
  306. if (start && ena) {
  307. /* If the DSP is already running then noop */
  308. if (reg & WM8958_DSP2_ENA)
  309. return;
  310. /* If either AIFnCLK is not yet enabled postpone */
  311. if (!(snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
  312. & WM8994_AIF1CLK_ENA_MASK) &&
  313. !(snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
  314. & WM8994_AIF2CLK_ENA_MASK))
  315. return;
  316. /* Switch the clock over to the appropriate AIF */
  317. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  318. WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
  319. aif << WM8958_DSP2CLK_SRC_SHIFT |
  320. WM8958_DSP2CLK_ENA);
  321. if (wm8994->enh_eq_ena[path])
  322. wm8958_dsp_start_enh_eq(codec, path);
  323. else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
  324. wm8994->hpf2_ena[path])
  325. wm8958_dsp_start_vss(codec, path);
  326. else if (wm8994->mbc_ena[path])
  327. wm8958_dsp_start_mbc(codec, path);
  328. wm8994->dsp_active = path;
  329. dev_dbg(codec->dev, "DSP running in path %d\n", path);
  330. }
  331. if (!start && wm8994->dsp_active == path) {
  332. /* If the DSP is already stopped then noop */
  333. if (!(reg & WM8958_DSP2_ENA))
  334. return;
  335. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  336. WM8958_MBC_ENA, 0);
  337. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  338. WM8958_DSP2_STOP);
  339. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  340. WM8958_DSP2_ENA, 0);
  341. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  342. WM8958_DSP2CLK_ENA, 0);
  343. wm8994->dsp_active = -1;
  344. dev_dbg(codec->dev, "DSP stopped\n");
  345. }
  346. }
  347. int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
  348. struct snd_kcontrol *kcontrol, int event)
  349. {
  350. struct snd_soc_codec *codec = w->codec;
  351. int i;
  352. switch (event) {
  353. case SND_SOC_DAPM_POST_PMU:
  354. case SND_SOC_DAPM_PRE_PMU:
  355. for (i = 0; i < 3; i++)
  356. wm8958_dsp_apply(codec, i, 1);
  357. break;
  358. case SND_SOC_DAPM_POST_PMD:
  359. case SND_SOC_DAPM_PRE_PMD:
  360. for (i = 0; i < 3; i++)
  361. wm8958_dsp_apply(codec, i, 0);
  362. break;
  363. }
  364. return 0;
  365. }
  366. /* Check if DSP2 is in use on another AIF */
  367. static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
  368. {
  369. int i;
  370. for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
  371. if (i == aif)
  372. continue;
  373. if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
  374. wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
  375. return 1;
  376. }
  377. return 0;
  378. }
  379. static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
  380. struct snd_ctl_elem_value *ucontrol)
  381. {
  382. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  383. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  384. struct wm8994_pdata *pdata = wm8994->pdata;
  385. int value = ucontrol->value.integer.value[0];
  386. int reg;
  387. /* Don't allow on the fly reconfiguration */
  388. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  389. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  390. return -EBUSY;
  391. if (value >= pdata->num_mbc_cfgs)
  392. return -EINVAL;
  393. wm8994->mbc_cfg = value;
  394. return 0;
  395. }
  396. static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
  397. struct snd_ctl_elem_value *ucontrol)
  398. {
  399. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  400. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  401. ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
  402. return 0;
  403. }
  404. static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
  405. struct snd_ctl_elem_info *uinfo)
  406. {
  407. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  408. uinfo->count = 1;
  409. uinfo->value.integer.min = 0;
  410. uinfo->value.integer.max = 1;
  411. return 0;
  412. }
  413. static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
  414. struct snd_ctl_elem_value *ucontrol)
  415. {
  416. int mbc = kcontrol->private_value;
  417. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  418. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  419. ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
  420. return 0;
  421. }
  422. static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
  423. struct snd_ctl_elem_value *ucontrol)
  424. {
  425. int mbc = kcontrol->private_value;
  426. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  427. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  428. if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
  429. return 0;
  430. if (ucontrol->value.integer.value[0] > 1)
  431. return -EINVAL;
  432. if (wm8958_dsp2_busy(wm8994, mbc)) {
  433. dev_dbg(codec->dev, "DSP2 active on %d already\n", mbc);
  434. return -EBUSY;
  435. }
  436. if (wm8994->enh_eq_ena[mbc])
  437. return -EBUSY;
  438. wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
  439. wm8958_dsp_apply(codec, mbc, wm8994->mbc_ena[mbc]);
  440. return 0;
  441. }
  442. #define WM8958_MBC_SWITCH(xname, xval) {\
  443. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  444. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  445. .info = wm8958_mbc_info, \
  446. .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
  447. .private_value = xval }
  448. static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
  449. struct snd_ctl_elem_value *ucontrol)
  450. {
  451. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  452. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  453. struct wm8994_pdata *pdata = wm8994->pdata;
  454. int value = ucontrol->value.integer.value[0];
  455. int reg;
  456. /* Don't allow on the fly reconfiguration */
  457. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  458. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  459. return -EBUSY;
  460. if (value >= pdata->num_vss_cfgs)
  461. return -EINVAL;
  462. wm8994->vss_cfg = value;
  463. return 0;
  464. }
  465. static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
  466. struct snd_ctl_elem_value *ucontrol)
  467. {
  468. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  469. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  470. ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
  471. return 0;
  472. }
  473. static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  474. struct snd_ctl_elem_value *ucontrol)
  475. {
  476. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  477. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  478. struct wm8994_pdata *pdata = wm8994->pdata;
  479. int value = ucontrol->value.integer.value[0];
  480. int reg;
  481. /* Don't allow on the fly reconfiguration */
  482. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  483. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  484. return -EBUSY;
  485. if (value >= pdata->num_vss_hpf_cfgs)
  486. return -EINVAL;
  487. wm8994->vss_hpf_cfg = value;
  488. return 0;
  489. }
  490. static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  491. struct snd_ctl_elem_value *ucontrol)
  492. {
  493. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  494. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  495. ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
  496. return 0;
  497. }
  498. static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
  499. struct snd_ctl_elem_info *uinfo)
  500. {
  501. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  502. uinfo->count = 1;
  503. uinfo->value.integer.min = 0;
  504. uinfo->value.integer.max = 1;
  505. return 0;
  506. }
  507. static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
  508. struct snd_ctl_elem_value *ucontrol)
  509. {
  510. int vss = kcontrol->private_value;
  511. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  512. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  513. ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
  514. return 0;
  515. }
  516. static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
  517. struct snd_ctl_elem_value *ucontrol)
  518. {
  519. int vss = kcontrol->private_value;
  520. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  521. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  522. if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
  523. return 0;
  524. if (ucontrol->value.integer.value[0] > 1)
  525. return -EINVAL;
  526. if (!wm8994->mbc_vss)
  527. return -ENODEV;
  528. if (wm8958_dsp2_busy(wm8994, vss)) {
  529. dev_dbg(codec->dev, "DSP2 active on %d already\n", vss);
  530. return -EBUSY;
  531. }
  532. if (wm8994->enh_eq_ena[vss])
  533. return -EBUSY;
  534. wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
  535. wm8958_dsp_apply(codec, vss, wm8994->vss_ena[vss]);
  536. return 0;
  537. }
  538. #define WM8958_VSS_SWITCH(xname, xval) {\
  539. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  540. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  541. .info = wm8958_vss_info, \
  542. .get = wm8958_vss_get, .put = wm8958_vss_put, \
  543. .private_value = xval }
  544. static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
  545. struct snd_ctl_elem_info *uinfo)
  546. {
  547. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  548. uinfo->count = 1;
  549. uinfo->value.integer.min = 0;
  550. uinfo->value.integer.max = 1;
  551. return 0;
  552. }
  553. static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
  554. struct snd_ctl_elem_value *ucontrol)
  555. {
  556. int hpf = kcontrol->private_value;
  557. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  558. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  559. if (hpf < 3)
  560. ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
  561. else
  562. ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
  563. return 0;
  564. }
  565. static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
  566. struct snd_ctl_elem_value *ucontrol)
  567. {
  568. int hpf = kcontrol->private_value;
  569. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  570. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  571. if (hpf < 3) {
  572. if (wm8994->hpf1_ena[hpf % 3] ==
  573. ucontrol->value.integer.value[0])
  574. return 0;
  575. } else {
  576. if (wm8994->hpf2_ena[hpf % 3] ==
  577. ucontrol->value.integer.value[0])
  578. return 0;
  579. }
  580. if (ucontrol->value.integer.value[0] > 1)
  581. return -EINVAL;
  582. if (!wm8994->mbc_vss)
  583. return -ENODEV;
  584. if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
  585. dev_dbg(codec->dev, "DSP2 active on %d already\n", hpf);
  586. return -EBUSY;
  587. }
  588. if (wm8994->enh_eq_ena[hpf % 3])
  589. return -EBUSY;
  590. if (hpf < 3)
  591. wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
  592. else
  593. wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
  594. wm8958_dsp_apply(codec, hpf % 3, ucontrol->value.integer.value[0]);
  595. return 0;
  596. }
  597. #define WM8958_HPF_SWITCH(xname, xval) {\
  598. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  599. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  600. .info = wm8958_hpf_info, \
  601. .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
  602. .private_value = xval }
  603. static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
  604. struct snd_ctl_elem_value *ucontrol)
  605. {
  606. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  607. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  608. struct wm8994_pdata *pdata = wm8994->pdata;
  609. int value = ucontrol->value.integer.value[0];
  610. int reg;
  611. /* Don't allow on the fly reconfiguration */
  612. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  613. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  614. return -EBUSY;
  615. if (value >= pdata->num_enh_eq_cfgs)
  616. return -EINVAL;
  617. wm8994->enh_eq_cfg = value;
  618. return 0;
  619. }
  620. static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
  621. struct snd_ctl_elem_value *ucontrol)
  622. {
  623. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  624. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  625. ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
  626. return 0;
  627. }
  628. static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
  629. struct snd_ctl_elem_info *uinfo)
  630. {
  631. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  632. uinfo->count = 1;
  633. uinfo->value.integer.min = 0;
  634. uinfo->value.integer.max = 1;
  635. return 0;
  636. }
  637. static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
  638. struct snd_ctl_elem_value *ucontrol)
  639. {
  640. int eq = kcontrol->private_value;
  641. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  642. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  643. ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
  644. return 0;
  645. }
  646. static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
  647. struct snd_ctl_elem_value *ucontrol)
  648. {
  649. int eq = kcontrol->private_value;
  650. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  651. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  652. if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
  653. return 0;
  654. if (ucontrol->value.integer.value[0] > 1)
  655. return -EINVAL;
  656. if (!wm8994->enh_eq)
  657. return -ENODEV;
  658. if (wm8958_dsp2_busy(wm8994, eq)) {
  659. dev_dbg(codec->dev, "DSP2 active on %d already\n", eq);
  660. return -EBUSY;
  661. }
  662. if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
  663. wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
  664. return -EBUSY;
  665. wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
  666. wm8958_dsp_apply(codec, eq, ucontrol->value.integer.value[0]);
  667. return 0;
  668. }
  669. #define WM8958_ENH_EQ_SWITCH(xname, xval) {\
  670. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  671. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  672. .info = wm8958_enh_eq_info, \
  673. .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
  674. .private_value = xval }
  675. static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
  676. WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
  677. WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
  678. WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
  679. };
  680. static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
  681. WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
  682. WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
  683. WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
  684. WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
  685. WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
  686. WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
  687. WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
  688. WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
  689. WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
  690. };
  691. static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
  692. WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
  693. WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
  694. WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
  695. };
  696. static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
  697. {
  698. struct snd_soc_codec *codec = context;
  699. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  700. if (fw && (wm8958_dsp2_fw(codec, "ENH_EQ", fw, true) == 0)) {
  701. mutex_lock(&codec->mutex);
  702. wm8994->enh_eq = fw;
  703. mutex_unlock(&codec->mutex);
  704. }
  705. }
  706. static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
  707. {
  708. struct snd_soc_codec *codec = context;
  709. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  710. if (fw && (wm8958_dsp2_fw(codec, "MBC+VSS", fw, true) == 0)) {
  711. mutex_lock(&codec->mutex);
  712. wm8994->mbc_vss = fw;
  713. mutex_unlock(&codec->mutex);
  714. }
  715. /* We can't have more than one request outstanding at once so
  716. * we daisy chain.
  717. */
  718. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  719. "wm8958_enh_eq.wfw", codec->dev, GFP_KERNEL,
  720. codec, wm8958_enh_eq_loaded);
  721. }
  722. static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
  723. {
  724. struct snd_soc_codec *codec = context;
  725. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  726. if (wm8958_dsp2_fw(codec, "MBC", fw, true) != 0)
  727. return;
  728. mutex_lock(&codec->mutex);
  729. wm8994->mbc = fw;
  730. mutex_unlock(&codec->mutex);
  731. /* We can't have more than one request outstanding at once so
  732. * we daisy chain.
  733. */
  734. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  735. "wm8958_mbc_vss.wfw", codec->dev, GFP_KERNEL,
  736. codec, wm8958_mbc_vss_loaded);
  737. }
  738. void wm8958_dsp2_init(struct snd_soc_codec *codec)
  739. {
  740. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  741. struct wm8994_pdata *pdata = wm8994->pdata;
  742. int ret, i;
  743. wm8994->dsp_active = -1;
  744. snd_soc_add_controls(codec, wm8958_mbc_snd_controls,
  745. ARRAY_SIZE(wm8958_mbc_snd_controls));
  746. snd_soc_add_controls(codec, wm8958_vss_snd_controls,
  747. ARRAY_SIZE(wm8958_vss_snd_controls));
  748. snd_soc_add_controls(codec, wm8958_enh_eq_snd_controls,
  749. ARRAY_SIZE(wm8958_enh_eq_snd_controls));
  750. /* We don't *require* firmware and don't want to delay boot */
  751. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  752. "wm8958_mbc.wfw", codec->dev, GFP_KERNEL,
  753. codec, wm8958_mbc_loaded);
  754. if (!pdata)
  755. return;
  756. if (pdata->num_mbc_cfgs) {
  757. struct snd_kcontrol_new control[] = {
  758. SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
  759. wm8958_get_mbc_enum, wm8958_put_mbc_enum),
  760. };
  761. /* We need an array of texts for the enum API */
  762. wm8994->mbc_texts = kmalloc(sizeof(char *)
  763. * pdata->num_mbc_cfgs, GFP_KERNEL);
  764. if (!wm8994->mbc_texts) {
  765. dev_err(wm8994->codec->dev,
  766. "Failed to allocate %d MBC config texts\n",
  767. pdata->num_mbc_cfgs);
  768. return;
  769. }
  770. for (i = 0; i < pdata->num_mbc_cfgs; i++)
  771. wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
  772. wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
  773. wm8994->mbc_enum.texts = wm8994->mbc_texts;
  774. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  775. if (ret != 0)
  776. dev_err(wm8994->codec->dev,
  777. "Failed to add MBC mode controls: %d\n", ret);
  778. }
  779. if (pdata->num_vss_cfgs) {
  780. struct snd_kcontrol_new control[] = {
  781. SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
  782. wm8958_get_vss_enum, wm8958_put_vss_enum),
  783. };
  784. /* We need an array of texts for the enum API */
  785. wm8994->vss_texts = kmalloc(sizeof(char *)
  786. * pdata->num_vss_cfgs, GFP_KERNEL);
  787. if (!wm8994->vss_texts) {
  788. dev_err(wm8994->codec->dev,
  789. "Failed to allocate %d VSS config texts\n",
  790. pdata->num_vss_cfgs);
  791. return;
  792. }
  793. for (i = 0; i < pdata->num_vss_cfgs; i++)
  794. wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
  795. wm8994->vss_enum.max = pdata->num_vss_cfgs;
  796. wm8994->vss_enum.texts = wm8994->vss_texts;
  797. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  798. if (ret != 0)
  799. dev_err(wm8994->codec->dev,
  800. "Failed to add VSS mode controls: %d\n", ret);
  801. }
  802. if (pdata->num_vss_hpf_cfgs) {
  803. struct snd_kcontrol_new control[] = {
  804. SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
  805. wm8958_get_vss_hpf_enum,
  806. wm8958_put_vss_hpf_enum),
  807. };
  808. /* We need an array of texts for the enum API */
  809. wm8994->vss_hpf_texts = kmalloc(sizeof(char *)
  810. * pdata->num_vss_hpf_cfgs, GFP_KERNEL);
  811. if (!wm8994->vss_hpf_texts) {
  812. dev_err(wm8994->codec->dev,
  813. "Failed to allocate %d VSS HPF config texts\n",
  814. pdata->num_vss_hpf_cfgs);
  815. return;
  816. }
  817. for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
  818. wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
  819. wm8994->vss_hpf_enum.max = pdata->num_vss_hpf_cfgs;
  820. wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
  821. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  822. if (ret != 0)
  823. dev_err(wm8994->codec->dev,
  824. "Failed to add VSS HPFmode controls: %d\n",
  825. ret);
  826. }
  827. if (pdata->num_enh_eq_cfgs) {
  828. struct snd_kcontrol_new control[] = {
  829. SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
  830. wm8958_get_enh_eq_enum,
  831. wm8958_put_enh_eq_enum),
  832. };
  833. /* We need an array of texts for the enum API */
  834. wm8994->enh_eq_texts = kmalloc(sizeof(char *)
  835. * pdata->num_enh_eq_cfgs, GFP_KERNEL);
  836. if (!wm8994->enh_eq_texts) {
  837. dev_err(wm8994->codec->dev,
  838. "Failed to allocate %d enhanced EQ config texts\n",
  839. pdata->num_enh_eq_cfgs);
  840. return;
  841. }
  842. for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
  843. wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
  844. wm8994->enh_eq_enum.max = pdata->num_enh_eq_cfgs;
  845. wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
  846. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  847. if (ret != 0)
  848. dev_err(wm8994->codec->dev,
  849. "Failed to add enhanced EQ controls: %d\n",
  850. ret);
  851. }
  852. }